m5op_alpha.S revision 12160
110008Snilay@cs.wisc.edu/* 210008Snilay@cs.wisc.edu * Copyright (c) 2003-2006 The Regents of The University of Michigan 310008Snilay@cs.wisc.edu * All rights reserved. 410008Snilay@cs.wisc.edu * 510008Snilay@cs.wisc.edu * Redistribution and use in source and binary forms, with or without 610008Snilay@cs.wisc.edu * modification, are permitted provided that the following conditions are 710008Snilay@cs.wisc.edu * met: redistributions of source code must retain the above copyright 810008Snilay@cs.wisc.edu * notice, this list of conditions and the following disclaimer; 910008Snilay@cs.wisc.edu * redistributions in binary form must reproduce the above copyright 1010008Snilay@cs.wisc.edu * notice, this list of conditions and the following disclaimer in the 1110008Snilay@cs.wisc.edu * documentation and/or other materials provided with the distribution; 1210008Snilay@cs.wisc.edu * neither the name of the copyright holders nor the names of its 1310008Snilay@cs.wisc.edu * contributors may be used to endorse or promote products derived from 1410008Snilay@cs.wisc.edu * this software without specific prior written permission. 1510008Snilay@cs.wisc.edu * 1610008Snilay@cs.wisc.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1710008Snilay@cs.wisc.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1810008Snilay@cs.wisc.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1910008Snilay@cs.wisc.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2010008Snilay@cs.wisc.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2110008Snilay@cs.wisc.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2210008Snilay@cs.wisc.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2310008Snilay@cs.wisc.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2410008Snilay@cs.wisc.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2510008Snilay@cs.wisc.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2610008Snilay@cs.wisc.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2710008Snilay@cs.wisc.edu * 2810008Snilay@cs.wisc.edu * Authors: Nathan Binkert 2910008Snilay@cs.wisc.edu * Ali Saidi 3010008Snilay@cs.wisc.edu */ 3110008Snilay@cs.wisc.edu 3210008Snilay@cs.wisc.edu#define m5_op 0x01 3310008Snilay@cs.wisc.edu 3410008Snilay@cs.wisc.edu#include <gem5/asm/generic/m5ops.h> 3510008Snilay@cs.wisc.edu 3610008Snilay@cs.wisc.edu#define INST(op, ra, rb, func) \ 3710529Smorr@cs.wisc.edu .long (((op) << 26) | ((ra) << 21) | ((rb) << 16) | (func)) 3810008Snilay@cs.wisc.edu 3910008Snilay@cs.wisc.edu#define LEAF(func) \ 4010008Snilay@cs.wisc.edu .align 3; \ 4110008Snilay@cs.wisc.edu .globl func; \ 4210008Snilay@cs.wisc.edu .ent func; \ 4310008Snilay@cs.wisc.edufunc: 4410008Snilay@cs.wisc.edu 4510008Snilay@cs.wisc.edu#define RET \ 4610008Snilay@cs.wisc.edu ret ($26) 4710008Snilay@cs.wisc.edu 4810008Snilay@cs.wisc.edu#define END(func) \ 4910008Snilay@cs.wisc.edu .end func 5010008Snilay@cs.wisc.edu 5110008Snilay@cs.wisc.edu#define SIMPLE_OP(_f, _o) \ 5210008Snilay@cs.wisc.edu LEAF(_f) \ 5310008Snilay@cs.wisc.edu _o; \ 5410008Snilay@cs.wisc.edu RET; \ 5510008Snilay@cs.wisc.edu END(_f) 5610008Snilay@cs.wisc.edu 5710008Snilay@cs.wisc.edu#define ARM(reg) INST(m5_op, reg, 0, M5OP_ARM) 5810008Snilay@cs.wisc.edu#define QUIESCE INST(m5_op, 0, 0, M5OP_QUIESCE) 5910008Snilay@cs.wisc.edu#define QUIESCENS(r1) INST(m5_op, r1, 0, M5OP_QUIESCE_NS) 6010519Snilay@cs.wisc.edu#define QUIESCECYC(r1) INST(m5_op, r1, 0, M5OP_QUIESCE_CYCLE) 6110008Snilay@cs.wisc.edu#define QUIESCETIME INST(m5_op, 0, 0, M5OP_QUIESCE_TIME) 6210008Snilay@cs.wisc.edu#define RPNS INST(m5_op, 0, 0, M5OP_RPNS) 6310008Snilay@cs.wisc.edu#define WAKE_CPU(r1) INST(m5_op, r1, 0, M5OP_WAKE_CPU) 6410008Snilay@cs.wisc.edu#define M5EXIT(reg) INST(m5_op, reg, 0, M5OP_EXIT) 6510008Snilay@cs.wisc.edu#define INITPARAM(reg) INST(m5_op, reg, 0, M5OP_INIT_PARAM) 6610008Snilay@cs.wisc.edu#define LOADSYMBOL(reg) INST(m5_op, reg, 0, M5OP_LOAD_SYMBOL) 6710008Snilay@cs.wisc.edu#define RESET_STATS(r1, r2) INST(m5_op, r1, r2, M5OP_RESET_STATS) 6810008Snilay@cs.wisc.edu#define DUMP_STATS(r1, r2) INST(m5_op, r1, r2, M5OP_DUMP_STATS) 6910008Snilay@cs.wisc.edu#define DUMPRST_STATS(r1, r2) INST(m5_op, r1, r2, M5OP_DUMP_RESET_STATS) 7010008Snilay@cs.wisc.edu#define CHECKPOINT(r1, r2) INST(m5_op, r1, r2, M5OP_CHECKPOINT) 7110008Snilay@cs.wisc.edu#define READFILE INST(m5_op, 0, 0, M5OP_READ_FILE) 7210008Snilay@cs.wisc.edu#define DEBUGBREAK INST(m5_op, 0, 0, M5OP_DEBUG_BREAK) 7310008Snilay@cs.wisc.edu#define SWITCHCPU INST(m5_op, 0, 0, M5OP_SWITCH_CPU) 7410008Snilay@cs.wisc.edu#define ADDSYMBOL(r1,r2) INST(m5_op, r1, r2, M5OP_ADD_SYMBOL) 7510008Snilay@cs.wisc.edu#define PANIC INST(m5_op, 0, 0, M5OP_PANIC) 7610008Snilay@cs.wisc.edu 7710008Snilay@cs.wisc.edu#define AN_BSM INST(m5_op, M5OP_AN_BSM, 0, M5OP_ANNOTATE) 7810008Snilay@cs.wisc.edu#define AN_ESM INST(m5_op, M5OP_AN_ESM, 0, M5OP_ANNOTATE) 7910008Snilay@cs.wisc.edu#define AN_BEGIN INST(m5_op, M5OP_AN_BEGIN, 0, M5OP_ANNOTATE) 8010008Snilay@cs.wisc.edu#define AN_END INST(m5_op, M5OP_AN_END, 0, M5OP_ANNOTATE) 8110008Snilay@cs.wisc.edu#define AN_Q INST(m5_op, M5OP_AN_Q, 0, M5OP_ANNOTATE) 8210008Snilay@cs.wisc.edu#define AN_RQ INST(m5_op, M5OP_AN_RQ, 0, M5OP_ANNOTATE) 8310008Snilay@cs.wisc.edu#define AN_DQ INST(m5_op, M5OP_AN_DQ, 0, M5OP_ANNOTATE) 8410008Snilay@cs.wisc.edu#define AN_WF INST(m5_op, M5OP_AN_WF, 0, M5OP_ANNOTATE) 8510008Snilay@cs.wisc.edu#define AN_WE INST(m5_op, M5OP_AN_WE, 0, M5OP_ANNOTATE) 8610008Snilay@cs.wisc.edu#define AN_WS INST(m5_op, M5OP_AN_WS, 0, M5OP_ANNOTATE) 8710008Snilay@cs.wisc.edu#define AN_SQ INST(m5_op, M5OP_AN_SQ, 0, M5OP_ANNOTATE) 8810008Snilay@cs.wisc.edu#define AN_AQ INST(m5_op, M5OP_AN_AQ, 0, M5OP_ANNOTATE) 8910008Snilay@cs.wisc.edu#define AN_PQ INST(m5_op, M5OP_AN_PQ, 0, M5OP_ANNOTATE) 9010008Snilay@cs.wisc.edu#define AN_L INST(m5_op, M5OP_AN_L, 0, M5OP_ANNOTATE) 9110008Snilay@cs.wisc.edu#define AN_IDENTIFY INST(m5_op, M5OP_AN_IDENTIFY, 0, M5OP_ANNOTATE) 9210008Snilay@cs.wisc.edu#define AN_GETID INST(m5_op, M5OP_AN_GETID, 0, M5OP_ANNOTATE) 9310008Snilay@cs.wisc.edu 9410008Snilay@cs.wisc.edu 9510008Snilay@cs.wisc.edu .set noreorder 9610008Snilay@cs.wisc.edu 9710008Snilay@cs.wisc.eduSIMPLE_OP(m5_arm, ARM(16)) 9810008Snilay@cs.wisc.eduSIMPLE_OP(m5_quiesce, QUIESCE) 9910008Snilay@cs.wisc.eduSIMPLE_OP(m5_quiesce_ns, QUIESCENS(16)) 10010008Snilay@cs.wisc.eduSIMPLE_OP(m5_quiesce_cycle, QUIESCECYC(16)) 10110008Snilay@cs.wisc.eduSIMPLE_OP(m5_quiesce_time, QUIESCETIME) 10210008Snilay@cs.wisc.eduSIMPLE_OP(m5_rpns, RPNS) 10310008Snilay@cs.wisc.eduSIMPLE_OP(m5_wake_cpu, WAKE_CPU(16)) 10410008Snilay@cs.wisc.eduSIMPLE_OP(m5_exit, M5EXIT(16)) 10510529Smorr@cs.wisc.eduSIMPLE_OP(m5_init_param, INITPARAM(0)) 10610300Scastilloe@unican.esSIMPLE_OP(m5_load_symbol, LOADSYMBOL(0)) 10710008Snilay@cs.wisc.eduSIMPLE_OP(m5_reset_stats, RESET_STATS(16, 17)) 10810008Snilay@cs.wisc.eduSIMPLE_OP(m5_dump_stats, DUMP_STATS(16, 17)) 10910008Snilay@cs.wisc.eduSIMPLE_OP(m5_dump_reset_stats, DUMPRST_STATS(16, 17)) 11010300Scastilloe@unican.esSIMPLE_OP(m5_checkpoint, CHECKPOINT(16, 17)) 11110008Snilay@cs.wisc.eduSIMPLE_OP(m5_read_file, READFILE) 11210008Snilay@cs.wisc.eduSIMPLE_OP(m5_debug_break, DEBUGBREAK) 11310008Snilay@cs.wisc.eduSIMPLE_OP(m5_switch_cpu, SWITCHCPU) 11410008Snilay@cs.wisc.eduSIMPLE_OP(m5_add_symbol, ADDSYMBOL(16, 17)) 11510008Snilay@cs.wisc.eduSIMPLE_OP(m5_panic, PANIC) 11610008Snilay@cs.wisc.edu 11710008Snilay@cs.wisc.eduSIMPLE_OP(m5a_bsm, AN_BSM) 11810008Snilay@cs.wisc.eduSIMPLE_OP(m5a_esm, AN_ESM) 11910008Snilay@cs.wisc.eduSIMPLE_OP(m5a_begin, AN_BEGIN) 12010008Snilay@cs.wisc.eduSIMPLE_OP(m5a_end, AN_END) 12110008Snilay@cs.wisc.eduSIMPLE_OP(m5a_q, AN_Q) 12210008Snilay@cs.wisc.eduSIMPLE_OP(m5a_rq, AN_RQ) 12310008Snilay@cs.wisc.eduSIMPLE_OP(m5a_dq, AN_DQ) 12410008Snilay@cs.wisc.eduSIMPLE_OP(m5a_wf, AN_WF) 12510008Snilay@cs.wisc.eduSIMPLE_OP(m5a_we, AN_WE) 12610008Snilay@cs.wisc.eduSIMPLE_OP(m5a_ws, AN_WS) 12710008Snilay@cs.wisc.eduSIMPLE_OP(m5a_sq, AN_SQ) 12810008Snilay@cs.wisc.eduSIMPLE_OP(m5a_aq, AN_AQ) 12910008Snilay@cs.wisc.eduSIMPLE_OP(m5a_pq, AN_PQ) 13010008Snilay@cs.wisc.eduSIMPLE_OP(m5a_l, AN_L) 13110008Snilay@cs.wisc.eduSIMPLE_OP(m5a_identify, AN_IDENTIFY) 13210008Snilay@cs.wisc.eduSIMPLE_OP(m5a_getid, AN_GETID) 13310311Snilay@cs.wisc.edu 13410311Snilay@cs.wisc.edu