1278SN/A/* 22188SN/A * Copyright (c) 2003-2006 The Regents of The University of Michigan 3278SN/A * All rights reserved. 4278SN/A * 5278SN/A * Redistribution and use in source and binary forms, with or without 6278SN/A * modification, are permitted provided that the following conditions are 7278SN/A * met: redistributions of source code must retain the above copyright 8278SN/A * notice, this list of conditions and the following disclaimer; 9278SN/A * redistributions in binary form must reproduce the above copyright 10278SN/A * notice, this list of conditions and the following disclaimer in the 11278SN/A * documentation and/or other materials provided with the distribution; 12278SN/A * neither the name of the copyright holders nor the names of its 13278SN/A * contributors may be used to endorse or promote products derived from 14278SN/A * this software without specific prior written permission. 15278SN/A * 16278SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17278SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18278SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19278SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20278SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21278SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22278SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23278SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24278SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25278SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26278SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665SN/A * 282665SN/A * Authors: Nathan Binkert 292665SN/A * Ali Saidi 30278SN/A */ 31278SN/A 32275SN/A#define m5_op 0x01 33287SN/A 3412157Sandreas.sandberg@arm.com#include <gem5/asm/generic/m5ops.h> 352188SN/A 36275SN/A#define INST(op, ra, rb, func) \ 372188SN/A .long (((op) << 26) | ((ra) << 21) | ((rb) << 16) | (func)) 382188SN/A 392188SN/A#define LEAF(func) \ 402188SN/A .align 3; \ 412188SN/A .globl func; \ 422188SN/A .ent func; \ 432188SN/Afunc: 442188SN/A 452188SN/A#define RET \ 462188SN/A ret ($26) 472188SN/A 482188SN/A#define END(func) \ 492188SN/A .end func 502188SN/A 515543Ssaidi@eecs.umich.edu#define SIMPLE_OP(_f, _o) \ 525543Ssaidi@eecs.umich.edu LEAF(_f) \ 535543Ssaidi@eecs.umich.edu _o; \ 545543Ssaidi@eecs.umich.edu RET; \ 555505Snate@binkert.org END(_f) 565505Snate@binkert.org 5712157Sandreas.sandberg@arm.com#define ARM(reg) INST(m5_op, reg, 0, M5OP_ARM) 5812157Sandreas.sandberg@arm.com#define QUIESCE INST(m5_op, 0, 0, M5OP_QUIESCE) 5912157Sandreas.sandberg@arm.com#define QUIESCENS(r1) INST(m5_op, r1, 0, M5OP_QUIESCE_NS) 6012157Sandreas.sandberg@arm.com#define QUIESCECYC(r1) INST(m5_op, r1, 0, M5OP_QUIESCE_CYCLE) 6112157Sandreas.sandberg@arm.com#define QUIESCETIME INST(m5_op, 0, 0, M5OP_QUIESCE_TIME) 6212157Sandreas.sandberg@arm.com#define RPNS INST(m5_op, 0, 0, M5OP_RPNS) 6312157Sandreas.sandberg@arm.com#define WAKE_CPU(r1) INST(m5_op, r1, 0, M5OP_WAKE_CPU) 6412157Sandreas.sandberg@arm.com#define M5EXIT(reg) INST(m5_op, reg, 0, M5OP_EXIT) 6512157Sandreas.sandberg@arm.com#define INITPARAM(reg) INST(m5_op, reg, 0, M5OP_INIT_PARAM) 6612157Sandreas.sandberg@arm.com#define LOADSYMBOL(reg) INST(m5_op, reg, 0, M5OP_LOAD_SYMBOL) 6712157Sandreas.sandberg@arm.com#define RESET_STATS(r1, r2) INST(m5_op, r1, r2, M5OP_RESET_STATS) 6812157Sandreas.sandberg@arm.com#define DUMP_STATS(r1, r2) INST(m5_op, r1, r2, M5OP_DUMP_STATS) 6912157Sandreas.sandberg@arm.com#define DUMPRST_STATS(r1, r2) INST(m5_op, r1, r2, M5OP_DUMP_RESET_STATS) 7012157Sandreas.sandberg@arm.com#define CHECKPOINT(r1, r2) INST(m5_op, r1, r2, M5OP_CHECKPOINT) 7112157Sandreas.sandberg@arm.com#define READFILE INST(m5_op, 0, 0, M5OP_READ_FILE) 7212157Sandreas.sandberg@arm.com#define DEBUGBREAK INST(m5_op, 0, 0, M5OP_DEBUG_BREAK) 7312157Sandreas.sandberg@arm.com#define SWITCHCPU INST(m5_op, 0, 0, M5OP_SWITCH_CPU) 7412157Sandreas.sandberg@arm.com#define ADDSYMBOL(r1,r2) INST(m5_op, r1, r2, M5OP_ADD_SYMBOL) 7512157Sandreas.sandberg@arm.com#define PANIC INST(m5_op, 0, 0, M5OP_PANIC) 76275SN/A 7712157Sandreas.sandberg@arm.com#define AN_BSM INST(m5_op, M5OP_AN_BSM, 0, M5OP_ANNOTATE) 7812157Sandreas.sandberg@arm.com#define AN_ESM INST(m5_op, M5OP_AN_ESM, 0, M5OP_ANNOTATE) 7912157Sandreas.sandberg@arm.com#define AN_BEGIN INST(m5_op, M5OP_AN_BEGIN, 0, M5OP_ANNOTATE) 8012157Sandreas.sandberg@arm.com#define AN_END INST(m5_op, M5OP_AN_END, 0, M5OP_ANNOTATE) 8112157Sandreas.sandberg@arm.com#define AN_Q INST(m5_op, M5OP_AN_Q, 0, M5OP_ANNOTATE) 8212157Sandreas.sandberg@arm.com#define AN_RQ INST(m5_op, M5OP_AN_RQ, 0, M5OP_ANNOTATE) 8312157Sandreas.sandberg@arm.com#define AN_DQ INST(m5_op, M5OP_AN_DQ, 0, M5OP_ANNOTATE) 8412157Sandreas.sandberg@arm.com#define AN_WF INST(m5_op, M5OP_AN_WF, 0, M5OP_ANNOTATE) 8512157Sandreas.sandberg@arm.com#define AN_WE INST(m5_op, M5OP_AN_WE, 0, M5OP_ANNOTATE) 8612157Sandreas.sandberg@arm.com#define AN_WS INST(m5_op, M5OP_AN_WS, 0, M5OP_ANNOTATE) 8712157Sandreas.sandberg@arm.com#define AN_SQ INST(m5_op, M5OP_AN_SQ, 0, M5OP_ANNOTATE) 8812157Sandreas.sandberg@arm.com#define AN_AQ INST(m5_op, M5OP_AN_AQ, 0, M5OP_ANNOTATE) 8912157Sandreas.sandberg@arm.com#define AN_PQ INST(m5_op, M5OP_AN_PQ, 0, M5OP_ANNOTATE) 9012157Sandreas.sandberg@arm.com#define AN_L INST(m5_op, M5OP_AN_L, 0, M5OP_ANNOTATE) 9112157Sandreas.sandberg@arm.com#define AN_IDENTIFY INST(m5_op, M5OP_AN_IDENTIFY, 0, M5OP_ANNOTATE) 9212157Sandreas.sandberg@arm.com#define AN_GETID INST(m5_op, M5OP_AN_GETID, 0, M5OP_ANNOTATE) 935951Ssaidi@eecs.umich.edu 945951Ssaidi@eecs.umich.edu 952188SN/A .set noreorder 96275SN/A 9712160Sandreas.sandberg@arm.comSIMPLE_OP(m5_arm, ARM(16)) 9812160Sandreas.sandberg@arm.comSIMPLE_OP(m5_quiesce, QUIESCE) 9912160Sandreas.sandberg@arm.comSIMPLE_OP(m5_quiesce_ns, QUIESCENS(16)) 10012160Sandreas.sandberg@arm.comSIMPLE_OP(m5_quiesce_cycle, QUIESCECYC(16)) 10112160Sandreas.sandberg@arm.comSIMPLE_OP(m5_quiesce_time, QUIESCETIME) 10212160Sandreas.sandberg@arm.comSIMPLE_OP(m5_rpns, RPNS) 10312160Sandreas.sandberg@arm.comSIMPLE_OP(m5_wake_cpu, WAKE_CPU(16)) 1045505Snate@binkert.orgSIMPLE_OP(m5_exit, M5EXIT(16)) 10512160Sandreas.sandberg@arm.comSIMPLE_OP(m5_init_param, INITPARAM(0)) 10612160Sandreas.sandberg@arm.comSIMPLE_OP(m5_load_symbol, LOADSYMBOL(0)) 1075505Snate@binkert.orgSIMPLE_OP(m5_reset_stats, RESET_STATS(16, 17)) 1085505Snate@binkert.orgSIMPLE_OP(m5_dump_stats, DUMP_STATS(16, 17)) 10912160Sandreas.sandberg@arm.comSIMPLE_OP(m5_dump_reset_stats, DUMPRST_STATS(16, 17)) 1105505Snate@binkert.orgSIMPLE_OP(m5_checkpoint, CHECKPOINT(16, 17)) 11112160Sandreas.sandberg@arm.comSIMPLE_OP(m5_read_file, READFILE) 11212160Sandreas.sandberg@arm.comSIMPLE_OP(m5_debug_break, DEBUGBREAK) 11312160Sandreas.sandberg@arm.comSIMPLE_OP(m5_switch_cpu, SWITCHCPU) 11412160Sandreas.sandberg@arm.comSIMPLE_OP(m5_add_symbol, ADDSYMBOL(16, 17)) 1155505Snate@binkert.orgSIMPLE_OP(m5_panic, PANIC) 116275SN/A 1175951Ssaidi@eecs.umich.eduSIMPLE_OP(m5a_bsm, AN_BSM) 1185951Ssaidi@eecs.umich.eduSIMPLE_OP(m5a_esm, AN_ESM) 1195951Ssaidi@eecs.umich.eduSIMPLE_OP(m5a_begin, AN_BEGIN) 1205951Ssaidi@eecs.umich.eduSIMPLE_OP(m5a_end, AN_END) 1215951Ssaidi@eecs.umich.eduSIMPLE_OP(m5a_q, AN_Q) 1225951Ssaidi@eecs.umich.eduSIMPLE_OP(m5a_rq, AN_RQ) 1235951Ssaidi@eecs.umich.eduSIMPLE_OP(m5a_dq, AN_DQ) 1245951Ssaidi@eecs.umich.eduSIMPLE_OP(m5a_wf, AN_WF) 1255951Ssaidi@eecs.umich.eduSIMPLE_OP(m5a_we, AN_WE) 1265951Ssaidi@eecs.umich.eduSIMPLE_OP(m5a_ws, AN_WS) 1275951Ssaidi@eecs.umich.eduSIMPLE_OP(m5a_sq, AN_SQ) 1285951Ssaidi@eecs.umich.eduSIMPLE_OP(m5a_aq, AN_AQ) 1295951Ssaidi@eecs.umich.eduSIMPLE_OP(m5a_pq, AN_PQ) 1305951Ssaidi@eecs.umich.eduSIMPLE_OP(m5a_l, AN_L) 1315951Ssaidi@eecs.umich.eduSIMPLE_OP(m5a_identify, AN_IDENTIFY) 1325951Ssaidi@eecs.umich.eduSIMPLE_OP(m5a_getid, AN_GETID) 1335951Ssaidi@eecs.umich.edu 134