isa-is-simobject.py revision 11077
111077SCurtis.Dunham@arm.com# The ISA is now a separate SimObject, which means that we serialize 211077SCurtis.Dunham@arm.com# it in a separate section instead of as a part of the ThreadContext. 311077SCurtis.Dunham@arm.comdef upgrader(cpt): 411077SCurtis.Dunham@arm.com isa = cpt.get('root','isa') 511077SCurtis.Dunham@arm.com isa_fields = { 611077SCurtis.Dunham@arm.com "alpha" : ( "fpcr", "uniq", "lock_flag", "lock_addr", "ipr" ), 711077SCurtis.Dunham@arm.com "arm" : ( "miscRegs" ), 811077SCurtis.Dunham@arm.com "sparc" : ( "asi", "tick", "fprs", "gsr", "softint", "tick_cmpr", 911077SCurtis.Dunham@arm.com "stick", "stick_cmpr", "tpc", "tnpc", "tstate", "tt", 1011077SCurtis.Dunham@arm.com "tba", "pstate", "tl", "pil", "cwp", "gl", "hpstate", 1111077SCurtis.Dunham@arm.com "htstate", "hintp", "htba", "hstick_cmpr", 1211077SCurtis.Dunham@arm.com "strandStatusReg", "fsr", "priContext", "secContext", 1311077SCurtis.Dunham@arm.com "partId", "lsuCtrlReg", "scratchPad", 1411077SCurtis.Dunham@arm.com "cpu_mondo_head", "cpu_mondo_tail", 1511077SCurtis.Dunham@arm.com "dev_mondo_head", "dev_mondo_tail", 1611077SCurtis.Dunham@arm.com "res_error_head", "res_error_tail", 1711077SCurtis.Dunham@arm.com "nres_error_head", "nres_error_tail", 1811077SCurtis.Dunham@arm.com "tick_intr_sched", 1911077SCurtis.Dunham@arm.com "cpu", "tc_num", "tick_cmp", "stick_cmp", "hstick_cmp"), 2011077SCurtis.Dunham@arm.com "x86" : ( "regVal" ), 2111077SCurtis.Dunham@arm.com } 2211077SCurtis.Dunham@arm.com 2311077SCurtis.Dunham@arm.com isa_fields = isa_fields.get(isa, []) 2411077SCurtis.Dunham@arm.com isa_sections = [] 2511077SCurtis.Dunham@arm.com for sec in cpt.sections(): 2611077SCurtis.Dunham@arm.com import re 2711077SCurtis.Dunham@arm.com 2811077SCurtis.Dunham@arm.com re_cpu_match = re.match('^(.*sys.*\.cpu[^.]*)\.xc\.(.+)$', sec) 2911077SCurtis.Dunham@arm.com # Search for all the execution contexts 3011077SCurtis.Dunham@arm.com if not re_cpu_match: 3111077SCurtis.Dunham@arm.com continue 3211077SCurtis.Dunham@arm.com 3311077SCurtis.Dunham@arm.com if re_cpu_match.group(2) != "0": 3411077SCurtis.Dunham@arm.com # This shouldn't happen as we didn't support checkpointing 3511077SCurtis.Dunham@arm.com # of in-order and O3 CPUs. 3611077SCurtis.Dunham@arm.com raise ValueError("Don't know how to migrate multi-threaded CPUs " 3711077SCurtis.Dunham@arm.com "from version 1") 3811077SCurtis.Dunham@arm.com 3911077SCurtis.Dunham@arm.com isa_section = [] 4011077SCurtis.Dunham@arm.com for fspec in isa_fields: 4111077SCurtis.Dunham@arm.com for (key, value) in cpt.items(sec, raw=True): 4211077SCurtis.Dunham@arm.com if key in isa_fields: 4311077SCurtis.Dunham@arm.com isa_section.append((key, value)) 4411077SCurtis.Dunham@arm.com 4511077SCurtis.Dunham@arm.com name = "%s.isa" % re_cpu_match.group(1) 4611077SCurtis.Dunham@arm.com isa_sections.append((name, isa_section)) 4711077SCurtis.Dunham@arm.com 4811077SCurtis.Dunham@arm.com for (key, value) in isa_section: 4911077SCurtis.Dunham@arm.com cpt.remove_option(sec, key) 5011077SCurtis.Dunham@arm.com 5111077SCurtis.Dunham@arm.com for (sec, options) in isa_sections: 5211077SCurtis.Dunham@arm.com # Some intermediate versions of gem5 have empty ISA sections 5311077SCurtis.Dunham@arm.com # (after we made the ISA a SimObject, but before we started to 5411077SCurtis.Dunham@arm.com # serialize into a separate ISA section). 5511077SCurtis.Dunham@arm.com if not cpt.has_section(sec): 5611077SCurtis.Dunham@arm.com cpt.add_section(sec) 5711077SCurtis.Dunham@arm.com else: 5811077SCurtis.Dunham@arm.com if cpt.items(sec): 5911077SCurtis.Dunham@arm.com raise ValueError("Unexpected populated ISA section in old " 6011077SCurtis.Dunham@arm.com "checkpoint") 6111077SCurtis.Dunham@arm.com 6211077SCurtis.Dunham@arm.com for (key, value) in options: 6311077SCurtis.Dunham@arm.com cpt.set(sec, key, value) 6411077SCurtis.Dunham@arm.com 6511077SCurtis.Dunham@arm.comlegacy_version = 4 66