arm-ccregs.py revision 11077:fae097742b7e
111374Ssteve.reinhardt@amd.com# Use condition code registers for the ARM architecture. 211374Ssteve.reinhardt@amd.com# Previously the integer register file was used for these registers. 38464SN/Adef upgrader(cpt): 48464SN/A if cpt.get('root','isa') == 'arm': 58150SN/A for sec in cpt.sections(): 611374Ssteve.reinhardt@amd.com import re 711374Ssteve.reinhardt@amd.com 811374Ssteve.reinhardt@amd.com re_cpu_match = re.match('^(.*sys.*\.cpu[^.]*)\.xc\.(.+)$', sec) 911374Ssteve.reinhardt@amd.com # Search for all the execution contexts 1010798Ssteve.reinhardt@amd.com if not re_cpu_match: 118150SN/A continue 1211374Ssteve.reinhardt@amd.com 1310513SAli.Saidi@ARM.com items = [] 1410513SAli.Saidi@ARM.com for (item,value) in cpt.items(sec): 1511374Ssteve.reinhardt@amd.com items.append(item) 168150SN/A if 'ccRegs' not in items: 1710513SAli.Saidi@ARM.com intRegs = cpt.get(sec, 'intRegs').split() 1810513SAli.Saidi@ARM.com 1910513SAli.Saidi@ARM.com # Move those 5 integer registers to the ccRegs register file 2010513SAli.Saidi@ARM.com ccRegs = intRegs[38:43] 2110513SAli.Saidi@ARM.com del intRegs[38:43] 2210513SAli.Saidi@ARM.com 2310513SAli.Saidi@ARM.com ccRegs.append('0') # CCREG_ZERO 2410513SAli.Saidi@ARM.com 2510513SAli.Saidi@ARM.com cpt.set(sec, 'intRegs', ' '.join(intRegs)) 2610513SAli.Saidi@ARM.com cpt.set(sec, 'ccRegs', ' '.join(ccRegs)) 2710513SAli.Saidi@ARM.com 2810513SAli.Saidi@ARM.comlegacy_version = 13 2910513SAli.Saidi@ARM.com