cpt_upgrader.py revision 10250:9f5e9bdc2f27
1360SN/A#!/usr/bin/env python 210850SGiacomo.Gabrielli@arm.com 310796Sbrandon.potter@amd.com# Copyright (c) 2012-2013 ARM Limited 410027SChris.Adeniyi-Jones@arm.com# All rights reserved 510027SChris.Adeniyi-Jones@arm.com# 610027SChris.Adeniyi-Jones@arm.com# The license below extends only to copyright in the software and shall 710027SChris.Adeniyi-Jones@arm.com# not be construed as granting a license to any other intellectual 810027SChris.Adeniyi-Jones@arm.com# property including but not limited to intellectual property relating 910027SChris.Adeniyi-Jones@arm.com# to a hardware implementation of the functionality of the software 1010027SChris.Adeniyi-Jones@arm.com# licensed hereunder. You may use the software subject to the license 1110027SChris.Adeniyi-Jones@arm.com# terms below provided that you ensure that this notice is replicated 1210027SChris.Adeniyi-Jones@arm.com# unmodified and in its entirety in all distributions of the software, 1310027SChris.Adeniyi-Jones@arm.com# modified or unmodified, in source code or in binary form. 1410027SChris.Adeniyi-Jones@arm.com# 151458SN/A# Redistribution and use in source and binary forms, with or without 16360SN/A# modification, are permitted provided that the following conditions are 17360SN/A# met: redistributions of source code must retain the above copyright 18360SN/A# notice, this list of conditions and the following disclaimer; 19360SN/A# redistributions in binary form must reproduce the above copyright 20360SN/A# notice, this list of conditions and the following disclaimer in the 21360SN/A# documentation and/or other materials provided with the distribution; 22360SN/A# neither the name of the copyright holders nor the names of its 23360SN/A# contributors may be used to endorse or promote products derived from 24360SN/A# this software without specific prior written permission. 25360SN/A# 26360SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 27360SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 28360SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 29360SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 30360SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 31360SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 32360SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 33360SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 34360SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 35360SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 36360SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 37360SN/A# 38360SN/A# Authors: Ali Saidi 39360SN/A# 402665Ssaidi@eecs.umich.edu 412665Ssaidi@eecs.umich.edu# This python code is used to migrate checkpoints that were created in one 422665Ssaidi@eecs.umich.edu# version of the simulator to newer version. As features are added or bugs are 43360SN/A# fixed some of the state that needs to be checkpointed can change. If you have 44360SN/A# many historic checkpoints that you use, manually editing them to fix them is 451354SN/A# both time consuming and error-prone. 461354SN/A 47360SN/A# This script provides a way to migrate checkpoints to the newer repository in 4812018Sandreas.sandberg@arm.com# a programatic way. It can be imported into another script or used on the 4912018Sandreas.sandberg@arm.com# command line. From the command line the script will either migrate every 5012018Sandreas.sandberg@arm.com# checkpoint it finds recursively (-r option) or a single checkpoint. When a 5112018Sandreas.sandberg@arm.com# change is made to the gem5 repository that breaks previous checkpoints a 5212018Sandreas.sandberg@arm.com# from_N() method should be implemented here and the gem5CheckpointVersion 5312018Sandreas.sandberg@arm.com# variable in src/sim/serialize.hh should be incremented. For each version 5412018Sandreas.sandberg@arm.com# between the checkpoints current version and the new version the from_N() 552064SN/A# method will be run, passing in a ConfigParser object which contains the open 5612018Sandreas.sandberg@arm.com# file. As these operations can be isa specific the method can verify the isa 5712018Sandreas.sandberg@arm.com# and use regexes to find the correct sections that need to be updated. 5812018Sandreas.sandberg@arm.com 5912018Sandreas.sandberg@arm.com 6012018Sandreas.sandberg@arm.comimport ConfigParser 6112018Sandreas.sandberg@arm.comimport sys, os 6211799Sbrandon.potter@amd.comimport os.path as osp 6312018Sandreas.sandberg@arm.com 6412018Sandreas.sandberg@arm.com# An example of a translator 6512018Sandreas.sandberg@arm.comdef from_0(cpt): 6612018Sandreas.sandberg@arm.com if cpt.get('root','isa') == 'arm': 6712018Sandreas.sandberg@arm.com for sec in cpt.sections(): 6812018Sandreas.sandberg@arm.com import re 6911799Sbrandon.potter@amd.com # Search for all the execution contexts 70360SN/A if re.search('.*sys.*\.cpu.*\.x.\..*', sec): 71360SN/A # Update each one 72360SN/A mr = cpt.get(sec, 'miscRegs').split() 73360SN/A #mr.insert(21,0) 74360SN/A #mr.insert(26,0) 75360SN/A cpt.set(sec, 'miscRegs', ' '.join(str(x) for x in mr)) 761809SN/A 7711800Sbrandon.potter@amd.com# The backing store supporting the memories in the system has changed 7811392Sbrandon.potter@amd.com# in that it is now stored globally per address range. As a result the 791809SN/A# actual storage is separate from the memory controllers themselves. 8011392Sbrandon.potter@amd.comdef from_1(cpt): 8111383Sbrandon.potter@amd.com for sec in cpt.sections(): 823113Sgblack@eecs.umich.edu import re 8311799Sbrandon.potter@amd.com # Search for a physical memory 8411759Sbrandon.potter@amd.com if re.search('.*sys.*\.physmem$', sec): 8511812Sbaz21@cam.ac.uk # Add the number of stores attribute to the global physmem 8611812Sbaz21@cam.ac.uk cpt.set(sec, 'nbr_of_stores', '1') 8711799Sbrandon.potter@amd.com 888229Snate@binkert.org # Get the filename and size as this is moving to the 898229Snate@binkert.org # specific backing store 9011594Santhony.gutierrez@amd.com mem_filename = cpt.get(sec, 'filename') 917075Snate@binkert.org mem_size = cpt.get(sec, '_size') 928229Snate@binkert.org cpt.remove_option(sec, 'filename') 9311856Sbrandon.potter@amd.com cpt.remove_option(sec, '_size') 947075Snate@binkert.org 95360SN/A # Get the name so that we can create the new section 9611886Sbrandon.potter@amd.com system_name = str(sec).split('.')[0] 9711800Sbrandon.potter@amd.com section_name = system_name + '.physmem.store0' 9811392Sbrandon.potter@amd.com cpt.add_section(section_name) 9912334Sgabeblack@google.com cpt.set(section_name, 'store_id', '0') 1001354SN/A cpt.set(section_name, 'range_size', mem_size) 1016216Snate@binkert.org cpt.set(section_name, 'filename', mem_filename) 1026658Snate@binkert.org elif re.search('.*sys.*\.\w*mem$', sec): 1032474SN/A # Due to the lack of information about a start address, 1042680Sktlim@umich.edu # this migration only works if there is a single memory in 1058229Snate@binkert.org # the system, thus starting at 0 10611886Sbrandon.potter@amd.com raise ValueError("more than one memory detected (" + sec + ")") 10710496Ssteve.reinhardt@amd.com 10811911SBrandon.Potter@amd.comdef from_2(cpt): 1098229Snate@binkert.org for sec in cpt.sections(): 11011794Sbrandon.potter@amd.com import re 11111886Sbrandon.potter@amd.com # Search for a CPUs 11210497Ssteve.reinhardt@amd.com if re.search('.*sys.*cpu', sec): 11311794Sbrandon.potter@amd.com try: 114360SN/A junk = cpt.get(sec, 'instCnt') 115360SN/A cpt.set(sec, '_pid', '0') 116360SN/A except ConfigParser.NoOptionError: 117360SN/A pass 118360SN/A 119360SN/A# The ISA is now a separate SimObject, which means that we serialize 120360SN/A# it in a separate section instead of as a part of the ThreadContext. 121360SN/Adef from_3(cpt): 122360SN/A isa = cpt.get('root','isa') 123360SN/A isa_fields = { 124378SN/A "alpha" : ( "fpcr", "uniq", "lock_flag", "lock_addr", "ipr" ), 1251706SN/A "arm" : ( "miscRegs" ), 12611851Sbrandon.potter@amd.com "sparc" : ( "asi", "tick", "fprs", "gsr", "softint", "tick_cmpr", 127378SN/A "stick", "stick_cmpr", "tpc", "tnpc", "tstate", "tt", 128378SN/A "tba", "pstate", "tl", "pil", "cwp", "gl", "hpstate", 129378SN/A "htstate", "hintp", "htba", "hstick_cmpr", 130378SN/A "strandStatusReg", "fsr", "priContext", "secContext", 131378SN/A "partId", "lsuCtrlReg", "scratchPad", 1321706SN/A "cpu_mondo_head", "cpu_mondo_tail", 13311851Sbrandon.potter@amd.com "dev_mondo_head", "dev_mondo_tail", 134360SN/A "res_error_head", "res_error_tail", 13511760Sbrandon.potter@amd.com "nres_error_head", "nres_error_tail", 13611760Sbrandon.potter@amd.com "tick_intr_sched", 13711851Sbrandon.potter@amd.com "cpu", "tc_num", "tick_cmp", "stick_cmp", "hstick_cmp"), 13811760Sbrandon.potter@amd.com "x86" : ( "regVal" ), 1396109Ssanchezd@stanford.edu } 1401706SN/A 14111851Sbrandon.potter@amd.com isa_fields = isa_fields.get(isa, []) 142378SN/A isa_sections = [] 1436109Ssanchezd@stanford.edu for sec in cpt.sections(): 1446109Ssanchezd@stanford.edu import re 14511851Sbrandon.potter@amd.com 1466109Ssanchezd@stanford.edu re_cpu_match = re.match('^(.*sys.*\.cpu[^.]*)\.xc\.(.+)$', sec) 14711886Sbrandon.potter@amd.com # Search for all the execution contexts 14811886Sbrandon.potter@amd.com if not re_cpu_match: 14911886Sbrandon.potter@amd.com continue 15011886Sbrandon.potter@amd.com 151378SN/A if re_cpu_match.group(2) != "0": 1521706SN/A # This shouldn't happen as we didn't support checkpointing 15311851Sbrandon.potter@amd.com # of in-order and O3 CPUs. 154378SN/A raise ValueError("Don't know how to migrate multi-threaded CPUs " 1555748SSteve.Reinhardt@amd.com "from version 1") 1565748SSteve.Reinhardt@amd.com 15711851Sbrandon.potter@amd.com isa_section = [] 158378SN/A for fspec in isa_fields: 159378SN/A for (key, value) in cpt.items(sec, raw=True): 1601706SN/A if key in isa_fields: 16111851Sbrandon.potter@amd.com isa_section.append((key, value)) 162378SN/A 16311886Sbrandon.potter@amd.com name = "%s.isa" % re_cpu_match.group(1) 1641706SN/A isa_sections.append((name, isa_section)) 16511851Sbrandon.potter@amd.com 166378SN/A for (key, value) in isa_section: 167378SN/A cpt.remove_option(sec, key) 1681706SN/A 16911851Sbrandon.potter@amd.com for (sec, options) in isa_sections: 170378SN/A # Some intermediate versions of gem5 have empty ISA sections 171378SN/A # (after we made the ISA a SimObject, but before we started to 1721706SN/A # serialize into a separate ISA section). 17311851Sbrandon.potter@amd.com if not cpt.has_section(sec): 174378SN/A cpt.add_section(sec) 1754118Sgblack@eecs.umich.edu else: 1764118Sgblack@eecs.umich.edu if cpt.items(sec): 17711851Sbrandon.potter@amd.com raise ValueError("Unexpected populated ISA section in old " 1784118Sgblack@eecs.umich.edu "checkpoint") 179378SN/A 1801706SN/A for (key, value) in options: 18111851Sbrandon.potter@amd.com cpt.set(sec, key, value) 182378SN/A 183378SN/A# Version 5 of the checkpoint format removes the MISCREG_CPSR_MODE 1841706SN/A# register from the ARM register file. 18511851Sbrandon.potter@amd.comdef from_4(cpt): 186360SN/A if cpt.get('root','isa') == 'arm': 1875513SMichael.Adler@intel.com for sec in cpt.sections(): 1885513SMichael.Adler@intel.com import re 18911851Sbrandon.potter@amd.com # Search for all ISA sections 1905513SMichael.Adler@intel.com if re.search('.*sys.*\.cpu.*\.isa', sec): 19110203SAli.Saidi@ARM.com mr = cpt.get(sec, 'miscRegs').split() 19210203SAli.Saidi@ARM.com # Remove MISCREG_CPSR_MODE 19311851Sbrandon.potter@amd.com del mr[137] 19410203SAli.Saidi@ARM.com cpt.set(sec, 'miscRegs', ' '.join(str(x) for x in mr)) 1955513SMichael.Adler@intel.com 19611851Sbrandon.potter@amd.com# Version 6 of the checkpoint format adds tlb to x86 checkpoints 1975513SMichael.Adler@intel.comdef from_5(cpt): 198511SN/A if cpt.get('root','isa') == 'x86': 19910633Smichaelupton@gmail.com for sec in cpt.sections(): 20011851Sbrandon.potter@amd.com import re 20110633Smichaelupton@gmail.com # Search for all ISA sections 2021706SN/A if re.search('.*sys.*\.cpu.*\.dtb$', sec): 20311851Sbrandon.potter@amd.com cpt.set(sec, '_size', '0') 204511SN/A cpt.set(sec, 'lruSeq', '0') 2055513SMichael.Adler@intel.com 2065513SMichael.Adler@intel.com if re.search('.*sys.*\.cpu.*\.itb$', sec): 20711851Sbrandon.potter@amd.com cpt.set(sec, '_size', '0') 2085513SMichael.Adler@intel.com cpt.set(sec, 'lruSeq', '0') 209511SN/A else: 2101706SN/A print "ISA is not x86" 21111851Sbrandon.potter@amd.com 2121706SN/A# Version 7 of the checkpoint adds support for the IDE dmaAbort flag 2131706SN/Adef from_6(cpt): 2141706SN/A # Update IDE disk devices with dmaAborted 2151706SN/A for sec in cpt.sections(): 21611851Sbrandon.potter@amd.com # curSector only exists in IDE devices, so key on that attribute 2171706SN/A if cpt.has_option(sec, "curSector"): 2181706SN/A cpt.set(sec, "dmaAborted", "false") 2191706SN/A 2201706SN/A# Version 8 of the checkpoint adds an ARM MISCREG 22111851Sbrandon.potter@amd.comdef from_7(cpt): 2221706SN/A if cpt.get('root','isa') == 'arm': 223511SN/A for sec in cpt.sections(): 2246703Svince@csl.cornell.edu import re 2256703Svince@csl.cornell.edu # Search for all ISA sections 22611851Sbrandon.potter@amd.com if re.search('.*sys.*\.cpu.*\.isa', sec): 2276703Svince@csl.cornell.edu mr = cpt.get(sec, 'miscRegs').split() 2286685Stjones1@inf.ed.ac.uk if len(mr) == 161: 2296685Stjones1@inf.ed.ac.uk print "MISCREG_TEEHBR already seems to be inserted." 23011851Sbrandon.potter@amd.com else: 2316685Stjones1@inf.ed.ac.uk # Add dummy value for MISCREG_TEEHBR 2326685Stjones1@inf.ed.ac.uk mr.insert(51,0); 2335513SMichael.Adler@intel.com cpt.set(sec, 'miscRegs', ' '.join(str(x) for x in mr)) 2345513SMichael.Adler@intel.com 23511851Sbrandon.potter@amd.com# Version 9 of the checkpoint adds an all ARMv8 state 2365513SMichael.Adler@intel.comdef from_8(cpt): 23711885Sbrandon.potter@amd.com if cpt.get('root','isa') != 'arm': 23811885Sbrandon.potter@amd.com return 23911885Sbrandon.potter@amd.com import re 2405513SMichael.Adler@intel.com print "Warning: The size of the FP register file has changed. "\ 2411999SN/A "To get similar results you need to adjust the number of "\ 2421999SN/A "physical registers in the CPU you're restoring into by "\ 24311851Sbrandon.potter@amd.com "NNNN." 2441999SN/A # Find the CPU context's and upgrade their registers 24511885Sbrandon.potter@amd.com for sec in cpt.sections(): 24611885Sbrandon.potter@amd.com re_xc_match = re.match('^.*?sys.*?\.cpu(\d+)*\.xc\.*', sec) 24711885Sbrandon.potter@amd.com if not re_xc_match: 2481999SN/A continue 2491999SN/A 2501999SN/A # Update floating point regs 25111851Sbrandon.potter@amd.com fpr = cpt.get(sec, 'floatRegs.i').split() 2521999SN/A # v8 has 128 normal fp and 32 special fp regs compared 2533079Sstever@eecs.umich.edu # to v7's 64 normal fp and 8 special fp regs. 2543079Sstever@eecs.umich.edu # Insert the extra normal fp registers at end of v7 normal fp regs 25511851Sbrandon.potter@amd.com for x in xrange(64): 2563079Sstever@eecs.umich.edu fpr.insert(64, "0") 25711908SBrandon.Potter@amd.com # Append the extra special registers 25811908SBrandon.Potter@amd.com for x in xrange(24): 25911908SBrandon.Potter@amd.com fpr.append("0") 26011908SBrandon.Potter@amd.com cpt.set(sec, 'floatRegs.i', ' '.join(str(x) for x in fpr)) 26111875Sbrandon.potter@amd.com 2622093SN/A ir = cpt.get(sec, 'intRegs').split() 26311851Sbrandon.potter@amd.com # Add in v8 int reg state 2642093SN/A # Splice in R13_HYP 2652687Sksewell@umich.edu ir.insert(20, "0") 2662687Sksewell@umich.edu # Splice in INTREG_DUMMY and SP0 - SP3 26711851Sbrandon.potter@amd.com ir.extend(["0", "0", "0", "0", "0"]) 2682687Sksewell@umich.edu cpt.set(sec, 'intRegs', ' '.join(str(x) for x in ir)) 2692238SN/A 2702238SN/A # Update the cpu interrupt field 27111851Sbrandon.potter@amd.com for sec in cpt.sections(): 2722238SN/A re_int_match = re.match("^.*?sys.*?\.cpu(\d+)*$", sec) 27311908SBrandon.Potter@amd.com if not re_int_match: 27411908SBrandon.Potter@amd.com continue 27511908SBrandon.Potter@amd.com 27611908SBrandon.Potter@amd.com irqs = cpt.get(sec, "interrupts").split() 27711908SBrandon.Potter@amd.com irqs.append("false") 27811908SBrandon.Potter@amd.com irqs.append("false") 27911908SBrandon.Potter@amd.com cpt.set(sec, "interrupts", ' '.join(str(x) for x in irqs)) 28011908SBrandon.Potter@amd.com 2812238SN/A # Update the per cpu interrupt structure 2822238SN/A for sec in cpt.sections(): 28311851Sbrandon.potter@amd.com re_int_match = re.match("^.*?sys.*?\.cpu(\d+)*\.interrupts$", sec) 2842238SN/A if not re_int_match: 2852238SN/A continue 2862238SN/A 28711851Sbrandon.potter@amd.com irqs = cpt.get(sec, "interrupts").split() 2882238SN/A irqs.append("false") 2892238SN/A irqs.append("false") 2902238SN/A cpt.set(sec, "interrupts", ' '.join(str(x) for x in irqs)) 29111851Sbrandon.potter@amd.com 2922238SN/A # Update the misc regs and add in new isa specific fields 2932238SN/A for sec in cpt.sections(): 2942238SN/A re_isa_match = re.match("^.*?sys.*?\.cpu(\d+)*\.isa$", sec) 29511851Sbrandon.potter@amd.com if not re_isa_match: 2962238SN/A continue 2972238SN/A 2982238SN/A cpt.set(sec, 'haveSecurity', 'false') 29911851Sbrandon.potter@amd.com cpt.set(sec, 'haveLPAE', 'false') 3002238SN/A cpt.set(sec, 'haveVirtualization', 'false') 3012238SN/A cpt.set(sec, 'haveLargeAsid64', 'false') 3022238SN/A cpt.set(sec, 'physAddrRange64', '40') 30311851Sbrandon.potter@amd.com 3042238SN/A # splice in the new misc registers, ~200 -> 605 registers, 3059455Smitch.hayenga+gem5@gmail.com # ordering does not remain consistent 3069455Smitch.hayenga+gem5@gmail.com mr_old = cpt.get(sec, 'miscRegs').split() 30711851Sbrandon.potter@amd.com mr_new = [ '0' for x in xrange(605) ] 30810203SAli.Saidi@ARM.com 30911851Sbrandon.potter@amd.com # map old v7 miscRegs to new v8 miscRegs 31011851Sbrandon.potter@amd.com mr_new[0] = mr_old[0] # CPSR 3119455Smitch.hayenga+gem5@gmail.com mr_new[16] = mr_old[1] # CPSR_Q 3129112Smarc.orr@gmail.com mr_new[1] = mr_old[2] # SPSR 31311906SBrandon.Potter@amd.com mr_new[2] = mr_old[3] # SPSR_FIQ 31411906SBrandon.Potter@amd.com mr_new[3] = mr_old[4] # SPSR_IRQ 3159112Smarc.orr@gmail.com mr_new[4] = mr_old[5] # SPSR_SVC 3169112Smarc.orr@gmail.com mr_new[5] = mr_old[6] # SPSR_MON 31711851Sbrandon.potter@amd.com mr_new[8] = mr_old[7] # SPSR_UND 3189112Smarc.orr@gmail.com mr_new[6] = mr_old[8] # SPSR_ABT 3199112Smarc.orr@gmail.com mr_new[432] = mr_old[9] # FPSR 32011911SBrandon.Potter@amd.com mr_new[10] = mr_old[10] # FPSID 3219112Smarc.orr@gmail.com mr_new[11] = mr_old[11] # FPSCR 32211911SBrandon.Potter@amd.com mr_new[18] = mr_old[12] # FPSCR_QC 32311911SBrandon.Potter@amd.com mr_new[17] = mr_old[13] # FPSCR_EXC 32411911SBrandon.Potter@amd.com mr_new[14] = mr_old[14] # FPEXC 32511911SBrandon.Potter@amd.com mr_new[13] = mr_old[15] # MVFR0 3269112Smarc.orr@gmail.com mr_new[12] = mr_old[16] # MVFR1 32711911SBrandon.Potter@amd.com mr_new[28] = mr_old[17] # SCTLR_RST, 32811911SBrandon.Potter@amd.com mr_new[29] = mr_old[18] # SEV_MAILBOX, 32911911SBrandon.Potter@amd.com mr_new[30] = mr_old[19] # DBGDIDR 33011911SBrandon.Potter@amd.com mr_new[31] = mr_old[20] # DBGDSCR_INT, 3319238Slluc.alvarez@bsc.es mr_new[33] = mr_old[21] # DBGDTRRX_INT, 3329112Smarc.orr@gmail.com mr_new[34] = mr_old[22] # DBGTRTX_INT, 33311911SBrandon.Potter@amd.com mr_new[35] = mr_old[23] # DBGWFAR, 3349112Smarc.orr@gmail.com mr_new[36] = mr_old[24] # DBGVCR, 33511911SBrandon.Potter@amd.com #mr_new[] = mr_old[25] # DBGECR -> UNUSED, 33611911SBrandon.Potter@amd.com #mr_new[] = mr_old[26] # DBGDSCCR -> UNUSED, 33711911SBrandon.Potter@amd.com #mr_new[] = mr_old[27] # DBGSMCR -> UNUSED, 33811911SBrandon.Potter@amd.com mr_new[37] = mr_old[28] # DBGDTRRX_EXT, 33911911SBrandon.Potter@amd.com mr_new[38] = mr_old[29] # DBGDSCR_EXT, 3409112Smarc.orr@gmail.com mr_new[39] = mr_old[30] # DBGDTRTX_EXT, 34111911SBrandon.Potter@amd.com #mr_new[] = mr_old[31] # DBGDRCR -> UNUSED, 34211911SBrandon.Potter@amd.com mr_new[41] = mr_old[32] # DBGBVR, 34311911SBrandon.Potter@amd.com mr_new[47] = mr_old[33] # DBGBCR, 34411911SBrandon.Potter@amd.com #mr_new[] = mr_old[34] # DBGBVR_M -> UNUSED, 34511911SBrandon.Potter@amd.com #mr_new[] = mr_old[35] # DBGBCR_M -> UNUSED, 34611911SBrandon.Potter@amd.com mr_new[61] = mr_old[36] # DBGDRAR, 3479112Smarc.orr@gmail.com #mr_new[] = mr_old[37] # DBGBXVR_M -> UNUSED, 3489112Smarc.orr@gmail.com mr_new[64] = mr_old[38] # DBGOSLAR, 34911911SBrandon.Potter@amd.com #mr_new[] = mr_old[39] # DBGOSSRR -> UNUSED, 35011911SBrandon.Potter@amd.com mr_new[66] = mr_old[40] # DBGOSDLR, 3519112Smarc.orr@gmail.com mr_new[67] = mr_old[41] # DBGPRCR, 35211911SBrandon.Potter@amd.com #mr_new[] = mr_old[42] # DBGPRSR -> UNUSED, 35311911SBrandon.Potter@amd.com mr_new[68] = mr_old[43] # DBGDSAR, 3549112Smarc.orr@gmail.com #mr_new[] = mr_old[44] # DBGITCTRL -> UNUSED, 3559112Smarc.orr@gmail.com mr_new[69] = mr_old[45] # DBGCLAIMSET, 35611911SBrandon.Potter@amd.com mr_new[70] = mr_old[46] # DBGCLAIMCLR, 35711911SBrandon.Potter@amd.com mr_new[71] = mr_old[47] # DBGAUTHSTATUS, 3589112Smarc.orr@gmail.com mr_new[72] = mr_old[48] # DBGDEVID2, 3599112Smarc.orr@gmail.com mr_new[73] = mr_old[49] # DBGDEVID1, 3602238SN/A mr_new[74] = mr_old[50] # DBGDEVID, 3612238SN/A mr_new[77] = mr_old[51] # TEEHBR, 3622238SN/A mr_new[109] = mr_old[52] # v7 SCTLR -> aarc32 SCTLR_NS 3632238SN/A mr_new[189] = mr_old[53] # DCCISW, 36411851Sbrandon.potter@amd.com mr_new[188] = mr_old[54] # DCCIMVAC, 3652238SN/A mr_new[183] = mr_old[55] # DCCMVAC, 3662238SN/A mr_new[271] = mr_old[56] # v7 CONTEXTIDR -> aarch32 CONTEXTIDR_NS, 3672238SN/A mr_new[274] = mr_old[57] # v7 TPIDRURW -> aarch32 TPIDRURW_NS, 36811851Sbrandon.potter@amd.com mr_new[277] = mr_old[58] # v7 TPIDRURO -> aarch32 TPIDRURO_NS, 3692238SN/A mr_new[280] = mr_old[59] # v7 TPIDRPRW -> aarch32 TPIDRPRW_NS, 3702238SN/A mr_new[170] = mr_old[60] # CP15ISB, 3712238SN/A mr_new[185] = mr_old[61] # CP15DSB, 37211851Sbrandon.potter@amd.com mr_new[186] = mr_old[62] # CP15DMB, 3732238SN/A mr_new[114] = mr_old[63] # CPACR, 3742238SN/A mr_new[101] = mr_old[64] # CLIDR, 3752238SN/A mr_new[100] = mr_old[65] # CCSIDR, 37611851Sbrandon.potter@amd.com mr_new[104] = mr_old[66] # v7 CSSELR -> aarch32 CSSELR_NS, 3772238SN/A mr_new[163] = mr_old[67] # ICIALLUIS, 3782238SN/A mr_new[168] = mr_old[68] # ICIALLU, 3791354SN/A mr_new[169] = mr_old[69] # ICIMVAU, 3801354SN/A mr_new[172] = mr_old[70] # BPIMVA, 38110796Sbrandon.potter@amd.com mr_new[164] = mr_old[71] # BPIALLIS, 38210796Sbrandon.potter@amd.com mr_new[171] = mr_old[72] # BPIALL, 3831354SN/A mr_new[80] = mr_old[73] # MIDR, 3841354SN/A mr_new[126] = mr_old[74] # v7 TTBR0 -> aarch32 TTBR0_NS, 3851354SN/A mr_new[129] = mr_old[75] # v7 TTBR1 -> aarch32 TTBR1_NS, 3861354SN/A mr_new[83] = mr_old[76] # TLBTR, 3871354SN/A mr_new[137] = mr_old[77] # v7 DACR -> aarch32 DACR_NS, 3881354SN/A mr_new[192] = mr_old[78] # TLBIALLIS, 3891354SN/A mr_new[193] = mr_old[79] # TLBIMVAIS, 3901354SN/A mr_new[194] = mr_old[80] # TLBIASIDIS, 3911354SN/A mr_new[195] = mr_old[81] # TLBIMVAAIS, 3921354SN/A mr_new[198] = mr_old[82] # ITLBIALL, 39310796Sbrandon.potter@amd.com mr_new[199] = mr_old[83] # ITLBIMVA, 3941354SN/A mr_new[200] = mr_old[84] # ITLBIASID, 39510796Sbrandon.potter@amd.com mr_new[201] = mr_old[85] # DTLBIALL, 3961354SN/A mr_new[202] = mr_old[86] # DTLBIMVA, 3971354SN/A mr_new[203] = mr_old[87] # DTLBIASID, 3981354SN/A mr_new[204] = mr_old[88] # TLBIALL, 3991354SN/A mr_new[205] = mr_old[89] # TLBIMVA, 40010796Sbrandon.potter@amd.com mr_new[206] = mr_old[90] # TLBIASID, 40110796Sbrandon.potter@amd.com mr_new[207] = mr_old[91] # TLBIMVAA, 40210796Sbrandon.potter@amd.com mr_new[140] = mr_old[92] # v7 DFSR -> aarch32 DFSR_NS, 40310796Sbrandon.potter@amd.com mr_new[143] = mr_old[93] # v7 IFSR -> aarch32 IFSR_NS, 40410796Sbrandon.potter@amd.com mr_new[155] = mr_old[94] # v7 DFAR -> aarch32 DFAR_NS, 40510796Sbrandon.potter@amd.com mr_new[158] = mr_old[95] # v7 IFAR -> aarch32 IFAR_NS, 40610796Sbrandon.potter@amd.com mr_new[84] = mr_old[96] # MPIDR, 40710796Sbrandon.potter@amd.com mr_new[241] = mr_old[97] # v7 PRRR -> aarch32 PRRR_NS, 40810796Sbrandon.potter@amd.com mr_new[247] = mr_old[98] # v7 NMRR -> aarch32 NMRR_NS, 40910796Sbrandon.potter@amd.com mr_new[131] = mr_old[99] # TTBCR, 41010796Sbrandon.potter@amd.com mr_new[86] = mr_old[100] # ID_PFR0, 411360SN/A mr_new[81] = mr_old[101] # CTR, 412360SN/A mr_new[115] = mr_old[102] # SCR, 413360SN/A # Set the non-secure bit 414360SN/A scr = int(mr_new[115]) 415360SN/A scr = scr | 0x1 416360SN/A mr_new[115] = str(scr) 417360SN/A ### 41811759Sbrandon.potter@amd.com mr_new[116] = mr_old[103] # SDER, 4193113Sgblack@eecs.umich.edu mr_new[165] = mr_old[104] # PAR, 4203113Sgblack@eecs.umich.edu mr_new[175] = mr_old[105] # V2PCWPR -> ATS1CPR, 4213113Sgblack@eecs.umich.edu mr_new[176] = mr_old[106] # V2PCWPW -> ATS1CPW, 4223113Sgblack@eecs.umich.edu mr_new[177] = mr_old[107] # V2PCWUR -> ATS1CUR, 4233113Sgblack@eecs.umich.edu mr_new[178] = mr_old[108] # V2PCWUW -> ATS1CUW, 4243113Sgblack@eecs.umich.edu mr_new[179] = mr_old[109] # V2POWPR -> ATS12NSOPR, 4253113Sgblack@eecs.umich.edu mr_new[180] = mr_old[110] # V2POWPW -> ATS12NSOPW, 4263113Sgblack@eecs.umich.edu mr_new[181] = mr_old[111] # V2POWUR -> ATS12NSOUR, 4273113Sgblack@eecs.umich.edu mr_new[182] = mr_old[112] # V2POWUW -> ATS12NWOUW, 4283113Sgblack@eecs.umich.edu mr_new[90] = mr_old[113] # ID_MMFR0, 4293113Sgblack@eecs.umich.edu mr_new[92] = mr_old[114] # ID_MMFR2, 4303113Sgblack@eecs.umich.edu mr_new[93] = mr_old[115] # ID_MMFR3, 4313113Sgblack@eecs.umich.edu mr_new[112] = mr_old[116] # v7 ACTLR -> aarch32 ACTLR_NS 43212032Sandreas.sandberg@arm.com mr_new[222] = mr_old[117] # PMCR, 4333113Sgblack@eecs.umich.edu mr_new[230] = mr_old[118] # PMCCNTR, 4343113Sgblack@eecs.umich.edu mr_new[223] = mr_old[119] # PMCNTENSET, 4354189Sgblack@eecs.umich.edu mr_new[224] = mr_old[120] # PMCNTENCLR, 4364189Sgblack@eecs.umich.edu mr_new[225] = mr_old[121] # PMOVSR, 4373113Sgblack@eecs.umich.edu mr_new[226] = mr_old[122] # PMSWINC, 4383113Sgblack@eecs.umich.edu mr_new[227] = mr_old[123] # PMSELR, 4393113Sgblack@eecs.umich.edu mr_new[228] = mr_old[124] # PMCEID0, 4403113Sgblack@eecs.umich.edu mr_new[229] = mr_old[125] # PMCEID1, 4418737Skoansin.tan@gmail.com mr_new[231] = mr_old[126] # PMXEVTYPER, 4423113Sgblack@eecs.umich.edu mr_new[233] = mr_old[127] # PMXEVCNTR, 4438737Skoansin.tan@gmail.com mr_new[234] = mr_old[128] # PMUSERENR, 4443277Sgblack@eecs.umich.edu mr_new[235] = mr_old[129] # PMINTENSET, 4455515SMichael.Adler@intel.com mr_new[236] = mr_old[130] # PMINTENCLR, 4465515SMichael.Adler@intel.com mr_new[94] = mr_old[131] # ID_ISAR0, 4475515SMichael.Adler@intel.com mr_new[95] = mr_old[132] # ID_ISAR1, 4485515SMichael.Adler@intel.com mr_new[96] = mr_old[133] # ID_ISAR2, 4495515SMichael.Adler@intel.com mr_new[97] = mr_old[134] # ID_ISAR3, 4508737Skoansin.tan@gmail.com mr_new[98] = mr_old[135] # ID_ISAR4, 4513277Sgblack@eecs.umich.edu mr_new[99] = mr_old[136] # ID_ISAR5, 4528737Skoansin.tan@gmail.com mr_new[20] = mr_old[137] # LOCKFLAG, 4533277Sgblack@eecs.umich.edu mr_new[19] = mr_old[138] # LOCKADDR, 4548737Skoansin.tan@gmail.com mr_new[87] = mr_old[139] # ID_PFR1, 4553277Sgblack@eecs.umich.edu # Set up the processor features register 4568737Skoansin.tan@gmail.com pfr = int(mr_new[87]) 4573113Sgblack@eecs.umich.edu pfr = pfr | 0x1011 4583113Sgblack@eecs.umich.edu mr_new[87] = str(pfr) 4593113Sgblack@eecs.umich.edu ### 4603113Sgblack@eecs.umich.edu mr_new[238] = mr_old[140] # L2CTLR, 4618737Skoansin.tan@gmail.com mr_new[82] = mr_old[141] # TCMTR 4623113Sgblack@eecs.umich.edu mr_new[88] = mr_old[142] # ID_DFR0, 4638737Skoansin.tan@gmail.com mr_new[89] = mr_old[143] # ID_AFR0, 4643114Sgblack@eecs.umich.edu mr_new[91] = mr_old[144] # ID_MMFR1, 4658737Skoansin.tan@gmail.com mr_new[102] = mr_old[145] # AIDR, 4663114Sgblack@eecs.umich.edu mr_new[146] = mr_old[146] # v7 ADFSR -> aarch32 ADFSR_NS, 4678737Skoansin.tan@gmail.com mr_new[148] = mr_old[147] # AIFSR, 4683114Sgblack@eecs.umich.edu mr_new[173] = mr_old[148] # DCIMVAC, 4698737Skoansin.tan@gmail.com mr_new[174] = mr_old[149] # DCISW, 47011906SBrandon.Potter@amd.com mr_new[184] = mr_old[150] # MCCSW -> DCCSW, 4714061Sgblack@eecs.umich.edu mr_new[187] = mr_old[151] # DCCMVAU, 4724061Sgblack@eecs.umich.edu mr_new[117] = mr_old[152] # NSACR, 4738737Skoansin.tan@gmail.com mr_new[262] = mr_old[153] # VBAR, 4743113Sgblack@eecs.umich.edu mr_new[265] = mr_old[154] # MVBAR, 4758737Skoansin.tan@gmail.com mr_new[267] = mr_old[155] # ISR, 4763113Sgblack@eecs.umich.edu mr_new[269] = mr_old[156] # FCEIDR -> FCSEIDR, 4773113Sgblack@eecs.umich.edu #mr_new[] = mr_old[157] # L2LATENCY -> UNUSED, 4783113Sgblack@eecs.umich.edu #mr_new[] = mr_old[158] # CRN15 -> UNUSED, 4793113Sgblack@eecs.umich.edu mr_new[599] = mr_old[159] # NOP 4803113Sgblack@eecs.umich.edu mr_new[600] = mr_old[160] # RAZ, 48112032Sandreas.sandberg@arm.com 4823113Sgblack@eecs.umich.edu # Set the new miscRegs structure 4833113Sgblack@eecs.umich.edu cpt.set(sec, 'miscRegs', ' '.join(str(x) for x in mr_new)) 4844189Sgblack@eecs.umich.edu 4854189Sgblack@eecs.umich.edu cpu_prefix = {} 4863113Sgblack@eecs.umich.edu # Add in state for ITB/DTB 4873113Sgblack@eecs.umich.edu for sec in cpt.sections(): 4883113Sgblack@eecs.umich.edu re_tlb_match = re.match('(^.*?sys.*?\.cpu(\d+)*)\.(dtb|itb)$', sec) 4898737Skoansin.tan@gmail.com if not re_tlb_match: 4903113Sgblack@eecs.umich.edu continue 4918737Skoansin.tan@gmail.com 4923113Sgblack@eecs.umich.edu cpu_prefix[re_tlb_match.group(1)] = True # Save off prefix to add 4938737Skoansin.tan@gmail.com # Set the non-secure bit (bit 9) to 1 for attributes 4943113Sgblack@eecs.umich.edu attr = int(cpt.get(sec, '_attr')) 4953113Sgblack@eecs.umich.edu attr = attr | 0x200 4963113Sgblack@eecs.umich.edu cpt.set(sec, '_attr', str(attr)) 4973113Sgblack@eecs.umich.edu cpt.set(sec, 'haveLPAE', 'false') 4983113Sgblack@eecs.umich.edu cpt.set(sec, 'directToStage2', 'false') 4993113Sgblack@eecs.umich.edu cpt.set(sec, 'stage2Req', 'false') 5003113Sgblack@eecs.umich.edu cpt.set(sec, 'bootUncacheability', 'true') 50111906SBrandon.Potter@amd.com 5023113Sgblack@eecs.umich.edu # Add in extra state for the new TLB Entries 50312032Sandreas.sandberg@arm.com for sec in cpt.sections(): 5048852Sandreas.hansson@arm.com re_tlbentry_match = re.match('(^.*?sys.*?\.cpu(\d+)*)\.(dtb|itb).TlbEntry\d+$', sec) 50511906SBrandon.Potter@amd.com if not re_tlbentry_match: 5063113Sgblack@eecs.umich.edu continue 5073113Sgblack@eecs.umich.edu 5083113Sgblack@eecs.umich.edu # Add in the new entries 5093113Sgblack@eecs.umich.edu cpt.set(sec, 'longDescFormat', 'false') 5103113Sgblack@eecs.umich.edu cpt.set(sec, 'vmid', '0') 5113113Sgblack@eecs.umich.edu cpt.set(sec, 'isHyp', 'false') 5123113Sgblack@eecs.umich.edu valid = cpt.get(sec, 'valid') 5133113Sgblack@eecs.umich.edu if valid == 'true': 51412032Sandreas.sandberg@arm.com cpt.set(sec, 'ns', 'true') 5158852Sandreas.hansson@arm.com cpt.set(sec, 'nstid', 'true') 51611906SBrandon.Potter@amd.com cpt.set(sec, 'pxn', 'true') 5173113Sgblack@eecs.umich.edu cpt.set(sec, 'hap', '3') 5183113Sgblack@eecs.umich.edu # All v7 code used 2 level page tables 5193113Sgblack@eecs.umich.edu cpt.set(sec, 'lookupLevel', '2') 5206686Stjones1@inf.ed.ac.uk attr = int(cpt.get(sec, 'attributes')) 5213113Sgblack@eecs.umich.edu # set the non-secure bit (bit 9) to 1 5223113Sgblack@eecs.umich.edu # as no previous v7 code used secure code 5233113Sgblack@eecs.umich.edu attr = attr | 0x200 52411759Sbrandon.potter@amd.com cpt.set(sec, 'attributes', str(attr)) 52512032Sandreas.sandberg@arm.com else: 52611759Sbrandon.potter@amd.com cpt.set(sec, 'ns', 'false') 52711759Sbrandon.potter@amd.com cpt.set(sec, 'nstid', 'false') 52811759Sbrandon.potter@amd.com cpt.set(sec, 'pxn', 'false') 52911759Sbrandon.potter@amd.com cpt.set(sec, 'hap', '0') 53011759Sbrandon.potter@amd.com cpt.set(sec, 'lookupLevel', '0') 53111812Sbaz21@cam.ac.uk cpt.set(sec, 'outerShareable', 'false') 53211812Sbaz21@cam.ac.uk 53311812Sbaz21@cam.ac.uk # Add d/istage2_mmu and d/istage2_mmu.stage2_tlb 53411759Sbrandon.potter@amd.com for key in cpu_prefix: 53511812Sbaz21@cam.ac.uk for suffix in ['.istage2_mmu', '.dstage2_mmu']: 53611759Sbrandon.potter@amd.com new_sec = key + suffix 53711759Sbrandon.potter@amd.com cpt.add_section(new_sec) 53811759Sbrandon.potter@amd.com new_sec = key + suffix + ".stage2_tlb" 53911759Sbrandon.potter@amd.com cpt.add_section(new_sec) 54011759Sbrandon.potter@amd.com # Fill in tlb info with some defaults 54111759Sbrandon.potter@amd.com cpt.set(new_sec, '_attr', '0') 54211759Sbrandon.potter@amd.com cpt.set(new_sec, 'haveLPAE', 'false') 54311812Sbaz21@cam.ac.uk cpt.set(new_sec, 'directToStage2', 'false') 54411812Sbaz21@cam.ac.uk cpt.set(new_sec, 'stage2Req', 'false') 54511812Sbaz21@cam.ac.uk cpt.set(new_sec, 'bootUncacheability', 'false') 54611812Sbaz21@cam.ac.uk cpt.set(new_sec, 'num_entries', '0') 54711812Sbaz21@cam.ac.uk 54811812Sbaz21@cam.ac.uk# Version 10 adds block_size_bytes to system.ruby 54911812Sbaz21@cam.ac.ukdef from_9(cpt): 55011759Sbrandon.potter@amd.com for sec in cpt.sections(): 55111759Sbrandon.potter@amd.com if sec == 'system.ruby': 55211812Sbaz21@cam.ac.uk # Use Gem5's default of 64; this should be changed if the to be 55311812Sbaz21@cam.ac.uk # upgraded checkpoints were not taken with block-size 64! 55411759Sbrandon.potter@amd.com cpt.set(sec, 'block_size_bytes', '64') 55511812Sbaz21@cam.ac.uk 55611812Sbaz21@cam.ac.uk# Checkpoint version 11 (0xB) adds the perfLevel variable in the clock domain 55711812Sbaz21@cam.ac.uk# and voltage domain simObjects used for DVFS and is serialized and 55811812Sbaz21@cam.ac.uk# unserialized. 55911812Sbaz21@cam.ac.ukdef from_A(cpt): 56011812Sbaz21@cam.ac.uk for sec in cpt.sections(): 56111812Sbaz21@cam.ac.uk import re 56211759Sbrandon.potter@amd.com 56311759Sbrandon.potter@amd.com if re.match('^.*sys.*[._]clk_domain$', sec): 56411759Sbrandon.potter@amd.com # Make _perfLevel equal to 0 which means best performance 56511759Sbrandon.potter@amd.com cpt.set(sec, '_perfLevel', ' '.join('0')) 566378SN/A elif re.match('^.*sys.*[._]voltage_domain$', sec): 567378SN/A # Make _perfLevel equal to 0 which means best performance 5689141Smarc.orr@gmail.com cpt.set(sec, '_perfLevel', ' '.join('0')) 5699141Smarc.orr@gmail.com else: 570360SN/A continue 5711450SN/A 57211856Sbrandon.potter@amd.commigrations = [] 573360SN/Amigrations.append(from_0) 5746701Sgblack@eecs.umich.edumigrations.append(from_1) 57511856Sbrandon.potter@amd.commigrations.append(from_2) 57611856Sbrandon.potter@amd.commigrations.append(from_3) 577360SN/Amigrations.append(from_4) 57810930Sbrandon.potter@amd.commigrations.append(from_5) 579360SN/Amigrations.append(from_6) 58011856Sbrandon.potter@amd.commigrations.append(from_7) 58111856Sbrandon.potter@amd.commigrations.append(from_8) 58210496Ssteve.reinhardt@amd.commigrations.append(from_9) 58311856Sbrandon.potter@amd.commigrations.append(from_A) 58411856Sbrandon.potter@amd.com 5851458SN/Averbose_print = False 586360SN/A 58711856Sbrandon.potter@amd.comdef verboseprint(*args): 58811856Sbrandon.potter@amd.com if not verbose_print: 58911856Sbrandon.potter@amd.com return 59011856Sbrandon.potter@amd.com for arg in args: 59111856Sbrandon.potter@amd.com print arg, 59211856Sbrandon.potter@amd.com print 59311856Sbrandon.potter@amd.com 59411856Sbrandon.potter@amd.comdef process_file(path, **kwargs): 59510496Ssteve.reinhardt@amd.com if not osp.isfile(path): 59611856Sbrandon.potter@amd.com import errno 59711856Sbrandon.potter@amd.com raise IOError(ennro.ENOENT, "No such file", path) 59811856Sbrandon.potter@amd.com 59911856Sbrandon.potter@amd.com verboseprint("Processing file %s...." % path) 60011856Sbrandon.potter@amd.com 60110930Sbrandon.potter@amd.com if kwargs.get('backup', True): 6029141Smarc.orr@gmail.com import shutil 603360SN/A shutil.copyfile(path, path + '.bak') 604360SN/A 605360SN/A cpt = ConfigParser.SafeConfigParser() 60611907SBrandon.Potter@amd.com 60711907SBrandon.Potter@amd.com # gem5 is case sensitive with paramaters 60811907SBrandon.Potter@amd.com cpt.optionxform = str 609360SN/A 61011907SBrandon.Potter@amd.com # Read the current data 61111907SBrandon.Potter@amd.com cpt_file = file(path, 'r') 61211907SBrandon.Potter@amd.com cpt.readfp(cpt_file) 61311907SBrandon.Potter@amd.com cpt_file.close() 61411907SBrandon.Potter@amd.com 61511907SBrandon.Potter@amd.com # Make sure we know what we're starting from 61611907SBrandon.Potter@amd.com if not cpt.has_option('root','cpt_ver'): 61711907SBrandon.Potter@amd.com raise LookupError("cannot determine version of checkpoint") 61811907SBrandon.Potter@amd.com 61911907SBrandon.Potter@amd.com cpt_ver = cpt.getint('root','cpt_ver') 62011907SBrandon.Potter@amd.com 62111907SBrandon.Potter@amd.com # If the current checkpoint is longer than the migrations list, we have a problem 62211907SBrandon.Potter@amd.com # and someone didn't update this file 62311907SBrandon.Potter@amd.com if cpt_ver > len(migrations): 624360SN/A raise ValueError("upgrade script is too old and needs updating") 62511907SBrandon.Potter@amd.com 6261458SN/A verboseprint("\t...file is at version %#x" % cpt_ver) 627360SN/A 62811907SBrandon.Potter@amd.com if cpt_ver == len(migrations): 62911907SBrandon.Potter@amd.com verboseprint("\t...nothing to do") 63011907SBrandon.Potter@amd.com return 63111907SBrandon.Potter@amd.com 63211907SBrandon.Potter@amd.com # Walk through every function from now until the end fixing the checkpoint 63311907SBrandon.Potter@amd.com for v in xrange(cpt_ver,len(migrations)): 63411907SBrandon.Potter@amd.com verboseprint("\t...migrating to version %#x" % (v + 1)) 63511907SBrandon.Potter@amd.com migrations[v](cpt) 63611907SBrandon.Potter@amd.com cpt.set('root','cpt_ver', str(v + 1)) 63711907SBrandon.Potter@amd.com 638360SN/A # Write the old data back 63911907SBrandon.Potter@amd.com verboseprint("\t...completed") 64011907SBrandon.Potter@amd.com cpt.write(file(path, 'w')) 64111907SBrandon.Potter@amd.com 642360SN/Aif __name__ == '__main__': 643360SN/A from optparse import OptionParser 64411907SBrandon.Potter@amd.com parser = OptionParser("usage: %prog [options] <filename or directory>") 64511907SBrandon.Potter@amd.com parser.add_option("-r", "--recurse", action="store_true", 64611907SBrandon.Potter@amd.com help="Recurse through all subdirectories modifying "\ 64711907SBrandon.Potter@amd.com "each checkpoint that is found") 648360SN/A parser.add_option("-N", "--no-backup", action="store_false", 64911907SBrandon.Potter@amd.com dest="backup", default=True, 650360SN/A help="Do no backup each checkpoint before modifying it") 651360SN/A parser.add_option("-v", "--verbose", action="store_true", 65211907SBrandon.Potter@amd.com help="Print out debugging information as") 6533669Sbinkertn@umich.edu 65411907SBrandon.Potter@amd.com (options, args) = parser.parse_args() 65511907SBrandon.Potter@amd.com if len(args) != 1: 65611907SBrandon.Potter@amd.com parser.error("You must specify a checkpoint file to modify or a "\ 65711907SBrandon.Potter@amd.com "directory of checkpoints to recursively update") 65811907SBrandon.Potter@amd.com 65911907SBrandon.Potter@amd.com verbose_print = options.verbose 66011907SBrandon.Potter@amd.com 66111907SBrandon.Potter@amd.com # Deal with shell variables and ~ 66211907SBrandon.Potter@amd.com path = osp.expandvars(osp.expanduser(args[0])) 66311907SBrandon.Potter@amd.com 66411907SBrandon.Potter@amd.com # Process a single file if we have it 66511907SBrandon.Potter@amd.com if osp.isfile(path): 66611907SBrandon.Potter@amd.com process_file(path, **vars(options)) 66711907SBrandon.Potter@amd.com # Process an entire directory 66811907SBrandon.Potter@amd.com elif osp.isdir(path): 66911907SBrandon.Potter@amd.com cpt_file = osp.join(path, 'm5.cpt') 67011907SBrandon.Potter@amd.com if options.recurse: 67111907SBrandon.Potter@amd.com # Visit very file and see if it matches 67211907SBrandon.Potter@amd.com for root,dirs,files in os.walk(path): 67311907SBrandon.Potter@amd.com for name in files: 67411907SBrandon.Potter@amd.com if name == 'm5.cpt': 6751706SN/A process_file(osp.join(root,name), **vars(options)) 67611907SBrandon.Potter@amd.com for dir in dirs: 67711907SBrandon.Potter@amd.com pass 67811907SBrandon.Potter@amd.com # Maybe someone passed a cpt.XXXXXXX directory and not m5.cpt 67911907SBrandon.Potter@amd.com elif osp.isfile(cpt_file): 68011907SBrandon.Potter@amd.com process_file(cpt_file, **vars(options)) 68111907SBrandon.Potter@amd.com else: 68210496Ssteve.reinhardt@amd.com print "Error: checkpoint file not found at in %s " % path, 68310496Ssteve.reinhardt@amd.com print "and recurse not specified" 68411907SBrandon.Potter@amd.com sys.exit(1) 68511907SBrandon.Potter@amd.com sys.exit(0) 68611907SBrandon.Potter@amd.com 68711907SBrandon.Potter@amd.com