lrsc.S revision 12771:75508af5d8dc 
1# See LICENSE for license details.
2
3#*****************************************************************************
4# lrsr.S
5#-----------------------------------------------------------------------------
6#
7# Test LR/SC instructions.
8#
9
10#include "riscv_test.h"
11#include "test_macros.h"
12
13RVTEST_RV64U
14RVTEST_CODE_BEGIN
15
16# get a unique core id
17la a0, coreid
18li a1, 1
19amoadd.w a2, a1, (a0)
20
21# for now, only run this on core 0
221:li a3, 1
23bgeu a2, a3, 1b
24
251: lw a1, (a0)
26bltu a1, a3, 1b
27
28# make sure that sc without a reservation fails.
29TEST_CASE( 2, a4, 1, \
30  la a0, foo; \
31  sc.w a4, x0, (a0); \
32)
33
34# make sure that sc with the wrong reservation fails.
35# TODO is this actually mandatory behavior?
36TEST_CASE( 3, a4, 1, \
37  la a0, foo; \
38  add a1, a0, 1024; \
39  lr.w a1, (a1); \
40  sc.w a4, a1, (a0); \
41)
42
43#define LOG_ITERATIONS 10
44
45# have each core add its coreid+1 to foo 1024 times
46la a0, foo
47li a1, 1<<LOG_ITERATIONS
48addi a2, a2, 1
491: lr.w a4, (a0)
50add a4, a4, a2
51sc.w a4, a4, (a0)
52bnez a4, 1b
53add a1, a1, -1
54bnez a1, 1b
55
56# wait for all cores to finish
57la a0, barrier
58li a1, 1
59amoadd.w x0, a1, (a0)
601: lw a1, (a0)
61blt a1, a3, 1b
62fence
63
64# expected result is 512*ncores*(ncores+1)
65TEST_CASE( 4, a0, 0, \
66  lw a0, foo; \
67  slli a1, a3, LOG_ITERATIONS-1; \
681:sub a0, a0, a1; \
69  addi a3, a3, -1; \
70  bgez a3, 1b
71)
72
73TEST_PASSFAIL
74
75RVTEST_CODE_END
76
77  .data
78RVTEST_DATA_BEGIN
79
80  TEST_DATA
81
82coreid: .word 0
83barrier: .word 0
84foo: .word 0
85RVTEST_DATA_END
86