dirty.S revision 12771
16019Shines@cs.fsu.edu# See LICENSE for license details. 26019Shines@cs.fsu.edu 36019Shines@cs.fsu.edu#***************************************************************************** 46019Shines@cs.fsu.edu# dirty.S 56019Shines@cs.fsu.edu#----------------------------------------------------------------------------- 66019Shines@cs.fsu.edu# 76019Shines@cs.fsu.edu# Test VM referenced and dirty bits. 86019Shines@cs.fsu.edu# 96019Shines@cs.fsu.edu 106019Shines@cs.fsu.edu#include "riscv_test.h" 116019Shines@cs.fsu.edu#include "test_macros.h" 126019Shines@cs.fsu.edu 136019Shines@cs.fsu.eduRVTEST_RV64M 146019Shines@cs.fsu.eduRVTEST_CODE_BEGIN 156019Shines@cs.fsu.edu 166019Shines@cs.fsu.edu # Turn on VM 176019Shines@cs.fsu.edu li a0, (SATP_MODE & ~(SATP_MODE<<1)) * SATP_MODE_SV39 186019Shines@cs.fsu.edu la a1, page_table_1 196019Shines@cs.fsu.edu srl a1, a1, RISCV_PGSHIFT 206019Shines@cs.fsu.edu or a1, a1, a0 216019Shines@cs.fsu.edu csrw sptbr, a1 226019Shines@cs.fsu.edu sfence.vma 236019Shines@cs.fsu.edu 246019Shines@cs.fsu.edu # Set up MPRV with MPP=S, so loads and stores use S-mode 256019Shines@cs.fsu.edu li a1, ((MSTATUS_MPP & ~(MSTATUS_MPP<<1)) * PRV_S) | MSTATUS_MPRV 266019Shines@cs.fsu.edu csrs mstatus, a1 276019Shines@cs.fsu.edu 286019Shines@cs.fsu.edu # Try a faulting store to make sure dirty bit is not set 296019Shines@cs.fsu.edu li TESTNUM, 2 306019Shines@cs.fsu.edu li t2, 1 316019Shines@cs.fsu.edu sw t2, dummy - DRAM_BASE, a0 326019Shines@cs.fsu.edu 336019Shines@cs.fsu.edu # Set SUM=1 so user memory access is permitted 346019Shines@cs.fsu.edu li TESTNUM, 3 356019Shines@cs.fsu.edu li a1, ((MSTATUS_MPP & ~(MSTATUS_MPP<<1)) * PRV_S) | MSTATUS_SUM 366019Shines@cs.fsu.edu csrs mstatus, a1 376268Sgblack@eecs.umich.edu 386251Sgblack@eecs.umich.edu # Make sure SUM=1 works 396269Sgblack@eecs.umich.edu lw t0, dummy - DRAM_BASE 406269Sgblack@eecs.umich.edu bnez t0, die 416749Sgblack@eecs.umich.edu 426251Sgblack@eecs.umich.edu # Try a non-faulting store to make sure dirty bit is set 436251Sgblack@eecs.umich.edu sw t2, dummy - DRAM_BASE, a0 446251Sgblack@eecs.umich.edu 456251Sgblack@eecs.umich.edu # Make sure it succeeded 466743Ssaidi@eecs.umich.edu lw t0, dummy - DRAM_BASE 476251Sgblack@eecs.umich.edu bne t0, t2, die 486741Sgblack@eecs.umich.edu 496251Sgblack@eecs.umich.edu # Leave MPRV 506251Sgblack@eecs.umich.edu li t0, MSTATUS_MPRV 516268Sgblack@eecs.umich.edu csrc mstatus, t0 526759SAli.Saidi@ARM.com 536251Sgblack@eecs.umich.edu # Make sure D bit is set 546251Sgblack@eecs.umich.edu lw t0, page_table_1 556019Shines@cs.fsu.edu li a0, PTE_A | PTE_D 566267Sgblack@eecs.umich.edu and t0, t0, a0 576267Sgblack@eecs.umich.edu bne t0, a0, die 586267Sgblack@eecs.umich.edu 596019Shines@cs.fsu.edu # Enter MPRV again 606251Sgblack@eecs.umich.edu li t0, MSTATUS_MPRV 616251Sgblack@eecs.umich.edu csrs mstatus, t0 626251Sgblack@eecs.umich.edu 636251Sgblack@eecs.umich.edu # Make sure that superpage entries trap when PPN LSBs are set. 646251Sgblack@eecs.umich.edu li TESTNUM, 4 656251Sgblack@eecs.umich.edu lw a0, page_table_1 - DRAM_BASE 666251Sgblack@eecs.umich.edu or a0, a0, 1 << PTE_PPN_SHIFT 676019Shines@cs.fsu.edu sw a0, page_table_1 - DRAM_BASE, t0 686251Sgblack@eecs.umich.edu sfence.vma 696019Shines@cs.fsu.edu sw a0, page_table_1 - DRAM_BASE, t0 706275Sgblack@eecs.umich.edu j die 716275Sgblack@eecs.umich.edu 726275Sgblack@eecs.umich.edu RVTEST_PASS 736275Sgblack@eecs.umich.edu 746275Sgblack@eecs.umich.edu TEST_PASSFAIL 756251Sgblack@eecs.umich.edu 766019Shines@cs.fsu.edu .align 2 776275Sgblack@eecs.umich.edu .global mtvec_handler 786019Shines@cs.fsu.edumtvec_handler: 796275Sgblack@eecs.umich.edu csrr t0, mcause 806019Shines@cs.fsu.edu add t0, t0, -CAUSE_STORE_PAGE_FAULT 816251Sgblack@eecs.umich.edu bnez t0, die 826019Shines@cs.fsu.edu 836251Sgblack@eecs.umich.edu li t1, 2 846251Sgblack@eecs.umich.edu bne TESTNUM, t1, 1f 856019Shines@cs.fsu.edu # Make sure D bit is clear 866251Sgblack@eecs.umich.edu lw t0, page_table_1 876019Shines@cs.fsu.edu and t1, t0, PTE_D 886251Sgblack@eecs.umich.edu bnez t1, die 896019Shines@cs.fsu.eduskip: 906251Sgblack@eecs.umich.edu csrr t0, mepc 916251Sgblack@eecs.umich.edu add t0, t0, 4 926251Sgblack@eecs.umich.edu csrw mepc, t0 936019Shines@cs.fsu.edu mret 946019Shines@cs.fsu.edu 956251Sgblack@eecs.umich.edu1: 966251Sgblack@eecs.umich.edu li t1, 3 976251Sgblack@eecs.umich.edu bne TESTNUM, t1, 1f 986019Shines@cs.fsu.edu # The implementation doesn't appear to set D bits in HW. 996019Shines@cs.fsu.edu # Make sure the D bit really is clear. 1006251Sgblack@eecs.umich.edu lw t0, page_table_1 1016019Shines@cs.fsu.edu and t1, t0, PTE_D 102 bnez t1, die 103 # Set the D bit. 104 or t0, t0, PTE_D 105 sw t0, page_table_1, t1 106 sfence.vma 107 mret 108 1091: 110 li t1, 4 111 bne TESTNUM, t1, 1f 112 j pass 113 1141: 115die: 116 RVTEST_FAIL 117 118RVTEST_CODE_END 119 120 .data 121RVTEST_DATA_BEGIN 122 123 TEST_DATA 124 125.align 12 126page_table_1: .dword (DRAM_BASE/RISCV_PGSIZE << PTE_PPN_SHIFT) | PTE_V | PTE_U | PTE_R | PTE_W | PTE_X | PTE_A 127dummy: .dword 0 128 129RVTEST_DATA_END 130