illegal.S revision 12771:75508af5d8dc 
1# See LICENSE for license details.
2
3#*****************************************************************************
4# illegal.S
5#-----------------------------------------------------------------------------
6#
7# Test illegal instruction trap.
8#
9
10#include "riscv_test.h"
11#include "test_macros.h"
12
13RVTEST_RV64M
14RVTEST_CODE_BEGIN
15
16  .align 2
17  .option norvc
18
19  li TESTNUM, 2
20bad2:
21  .word 0
22  j fail
23
24  # Skip the rest of the test if S-mode is not present.
25  li t0, MSTATUS_MPP
26  csrc mstatus, t0
27  li t1, (MSTATUS_MPP & -MSTATUS_MPP) * PRV_S
28  csrs mstatus, t1
29  csrr t2, mstatus
30  and t2, t2, t0
31  bne t1, t2, pass
32
33  # Test vectored interrupts if they are supported.
34test_vectored_interrupts:
35  csrwi mip, MIP_SSIP
36  csrwi mie, MIP_SSIP
37  la t0, mtvec_handler + 1
38  csrrw s0, mtvec, t0
39  csrr t0, mtvec
40  andi t0, t0, 1
41  beqz t0, msip
42  csrsi mstatus, MSTATUS_MIE
431:
44  j 1b
45msip:
46  csrw mtvec, s0
47
48  # Delegate supervisor software interrupts so WFI won't stall.
49  csrwi mideleg, MIP_SSIP
50  # Enter supervisor mode.
51  la t0, 1f
52  csrw mepc, t0
53  li t0, MSTATUS_MPP
54  csrc mstatus, t0
55  li t1, (MSTATUS_MPP & -MSTATUS_MPP) * PRV_S
56  csrs mstatus, t1
57  mret
58
591:
60  # Make sure WFI doesn't trap when TW=0.
61  wfi
62bad3:
63  .word 0
64  j fail
65
66bad4:
67  # Make sure WFI does trap when TW=1.
68  wfi
69  j fail
70
71  # Make sure SFENCE.VMA and sptbr don't trap when TVM=0.
72  sfence.vma
73  csrr t0, sptbr
74bad5:
75  .word 0
76  j fail
77
78bad6:
79  # Make sure SFENCE.VMA and sptbr do trap when TVM=1.
80  sfence.vma
81  j fail
82bad7:
83  csrr t0, sptbr
84  j fail
85
86  # Make sure SRET doesn't trap when TSR=0.
87  la t0, bad8
88  csrw sepc, t0
89  li t0, SSTATUS_SPP
90  csrs sstatus, t0
91  li t0, SSTATUS_SPIE
92  csrc sstatus, t0
93  sret
94bad8:
95  .word 0
96  j fail
97
98  # Make sure SRET does trap when TSR=1.
99  la t0, 1f
100  csrw sepc, t0
101bad9:
102  sret
1031:
104  j fail
105
106  TEST_PASSFAIL
107
108  .align 8
109  .global mtvec_handler
110mtvec_handler:
111  j synchronous_exception
112  j msip
113  j fail
114  j fail
115  j fail
116  j fail
117  j fail
118  j fail
119  j fail
120  j fail
121  j fail
122  j fail
123  j fail
124  j fail
125  j fail
126  j fail
127
128synchronous_exception:
129  li t1, CAUSE_ILLEGAL_INSTRUCTION
130  csrr t0, mcause
131  bne t0, t1, fail
132  csrr t0, mepc
133
134  # Make sure mtval contains either 0 or the instruction word.
135  csrr t2, mbadaddr
136  beqz t2, 1f
137  lhu t3, 0(t0)
138  lhu t4, 2(t0)
139  slli t4, t4, 16
140  or t3, t3, t4
141  bne t2, t3, fail
1421:
143
144  la t1, bad2
145  beq t0, t1, 2f
146  la t1, bad3
147  beq t0, t1, 3f
148  la t1, bad4
149  beq t0, t1, 4f
150  la t1, bad5
151  beq t0, t1, 5f
152  la t1, bad6
153  beq t0, t1, 6f
154  la t1, bad7
155  beq t0, t1, 7f
156  la t1, bad8
157  beq t0, t1, 8f
158  la t1, bad9
159  beq t0, t1, 9f
160  j fail
1612:
1624:
1636:
1647:
165  addi t0, t0, 8
166  csrw mepc, t0
167  mret
168
1693:
170  li t1, MSTATUS_TW
171  csrs mstatus, t1
172  j 2b
173
1745:
175  li t1, MSTATUS_TVM
176  csrs mstatus, t1
177  j 2b
178
1798:
180  li t1, MSTATUS_TSR
181  csrs mstatus, t1
182  j 2b
183
1849:
185  j 2b
186
187RVTEST_CODE_END
188
189  .data
190RVTEST_DATA_BEGIN
191
192  TEST_DATA
193
194RVTEST_DATA_END
195