illegal.S revision 12771 
16145Snate@binkert.org# See LICENSE for license details.
26145Snate@binkert.org
36145Snate@binkert.org#*****************************************************************************
46145Snate@binkert.org# illegal.S
56145Snate@binkert.org#-----------------------------------------------------------------------------
66145Snate@binkert.org#
76145Snate@binkert.org# Test illegal instruction trap.
86145Snate@binkert.org#
96145Snate@binkert.org
106145Snate@binkert.org#include "riscv_test.h"
116145Snate@binkert.org#include "test_macros.h"
126145Snate@binkert.org
136145Snate@binkert.orgRVTEST_RV64M
146145Snate@binkert.orgRVTEST_CODE_BEGIN
156145Snate@binkert.org
166145Snate@binkert.org  .align 2
176145Snate@binkert.org  .option norvc
186145Snate@binkert.org
196145Snate@binkert.org  li TESTNUM, 2
206145Snate@binkert.orgbad2:
216145Snate@binkert.org  .word 0
226145Snate@binkert.org  j fail
236145Snate@binkert.org
246145Snate@binkert.org  # Skip the rest of the test if S-mode is not present.
256145Snate@binkert.org  li t0, MSTATUS_MPP
266145Snate@binkert.org  csrc mstatus, t0
276145Snate@binkert.org  li t1, (MSTATUS_MPP & -MSTATUS_MPP) * PRV_S
286145Snate@binkert.org  csrs mstatus, t1
296145Snate@binkert.org  csrr t2, mstatus
307054Snate@binkert.org  and t2, t2, t0
317054Snate@binkert.org  bne t1, t2, pass
327054Snate@binkert.org
337054Snate@binkert.org  # Test vectored interrupts if they are supported.
347054Snate@binkert.orgtest_vectored_interrupts:
357054Snate@binkert.org  csrwi mip, MIP_SSIP
367054Snate@binkert.org  csrwi mie, MIP_SSIP
376145Snate@binkert.org  la t0, mtvec_handler + 1
386145Snate@binkert.org  csrrw s0, mtvec, t0
397054Snate@binkert.org  csrr t0, mtvec
407054Snate@binkert.org  andi t0, t0, 1
416145Snate@binkert.org  beqz t0, msip
427002Snate@binkert.org  csrsi mstatus, MSTATUS_MIE
437454Snate@binkert.org1:
447002Snate@binkert.org  j 1b
459389Sandreas.hansson@arm.commsip:
469866Sjthestness@gmail.com  csrw mtvec, s0
479389Sandreas.hansson@arm.com
489274Snilay@cs.wisc.edu  # Delegate supervisor software interrupts so WFI won't stall.
499274Snilay@cs.wisc.edu  csrwi mideleg, MIP_SSIP
509274Snilay@cs.wisc.edu  # Enter supervisor mode.
516145Snate@binkert.org  la t0, 1f
526145Snate@binkert.org  csrw mepc, t0
536145Snate@binkert.org  li t0, MSTATUS_MPP
546145Snate@binkert.org  csrc mstatus, t0
556145Snate@binkert.org  li t1, (MSTATUS_MPP & -MSTATUS_MPP) * PRV_S
566145Snate@binkert.org  csrs mstatus, t1
579274Snilay@cs.wisc.edu  mret
587054Snate@binkert.org
597054Snate@binkert.org1:
609274Snilay@cs.wisc.edu  # Make sure WFI doesn't trap when TW=0.
619274Snilay@cs.wisc.edu  wfi
627054Snate@binkert.orgbad3:
6310311Snilay@cs.wisc.edu  .word 0
646145Snate@binkert.org  j fail
6510311Snilay@cs.wisc.edu
6610311Snilay@cs.wisc.edubad4:
6710311Snilay@cs.wisc.edu  # Make sure WFI does trap when TW=1.
6810311Snilay@cs.wisc.edu  wfi
6910311Snilay@cs.wisc.edu  j fail
707054Snate@binkert.org
716145Snate@binkert.org  # Make sure SFENCE.VMA and sptbr don't trap when TVM=0.
729863Snilay@cs.wisc.edu  sfence.vma
739863Snilay@cs.wisc.edu  csrr t0, sptbr
749863Snilay@cs.wisc.edubad5:
759863Snilay@cs.wisc.edu  .word 0
769863Snilay@cs.wisc.edu  j fail
779863Snilay@cs.wisc.edu
787054Snate@binkert.orgbad6:
799274Snilay@cs.wisc.edu  # Make sure SFENCE.VMA and sptbr do trap when TVM=1.
806145Snate@binkert.org  sfence.vma
819302Snilay@cs.wisc.edu  j fail
829302Snilay@cs.wisc.edubad7:
839302Snilay@cs.wisc.edu  csrr t0, sptbr
847054Snate@binkert.org  j fail
857054Snate@binkert.org
867054Snate@binkert.org  # Make sure SRET doesn't trap when TSR=0.
877054Snate@binkert.org  la t0, bad8
886145Snate@binkert.org  csrw sepc, t0
899858Snilay@cs.wisc.edu  li t0, SSTATUS_SPP
908259SBrad.Beckmann@amd.com  csrs sstatus, t0
917454Snate@binkert.org  li t0, SSTATUS_SPIE
927454Snate@binkert.org  csrc sstatus, t0
939863Snilay@cs.wisc.edu  sret
949863Snilay@cs.wisc.edubad8:
959863Snilay@cs.wisc.edu  .word 0
969866Sjthestness@gmail.com  j fail
979866Sjthestness@gmail.com
986145Snate@binkert.org  # Make sure SRET does trap when TSR=1.
996145Snate@binkert.org  la t0, 1f
1007054Snate@binkert.org  csrw sepc, t0
1017054Snate@binkert.orgbad9:
1026145Snate@binkert.org  sret
1037054Snate@binkert.org1:
1047054Snate@binkert.org  j fail
1057054Snate@binkert.org
1066145Snate@binkert.org  TEST_PASSFAIL
1076145Snate@binkert.org
1087054Snate@binkert.org  .align 8
109  .global mtvec_handler
110mtvec_handler:
111  j synchronous_exception
112  j msip
113  j fail
114  j fail
115  j fail
116  j fail
117  j fail
118  j fail
119  j fail
120  j fail
121  j fail
122  j fail
123  j fail
124  j fail
125  j fail
126  j fail
127
128synchronous_exception:
129  li t1, CAUSE_ILLEGAL_INSTRUCTION
130  csrr t0, mcause
131  bne t0, t1, fail
132  csrr t0, mepc
133
134  # Make sure mtval contains either 0 or the instruction word.
135  csrr t2, mbadaddr
136  beqz t2, 1f
137  lhu t3, 0(t0)
138  lhu t4, 2(t0)
139  slli t4, t4, 16
140  or t3, t3, t4
141  bne t2, t3, fail
1421:
143
144  la t1, bad2
145  beq t0, t1, 2f
146  la t1, bad3
147  beq t0, t1, 3f
148  la t1, bad4
149  beq t0, t1, 4f
150  la t1, bad5
151  beq t0, t1, 5f
152  la t1, bad6
153  beq t0, t1, 6f
154  la t1, bad7
155  beq t0, t1, 7f
156  la t1, bad8
157  beq t0, t1, 8f
158  la t1, bad9
159  beq t0, t1, 9f
160  j fail
1612:
1624:
1636:
1647:
165  addi t0, t0, 8
166  csrw mepc, t0
167  mret
168
1693:
170  li t1, MSTATUS_TW
171  csrs mstatus, t1
172  j 2b
173
1745:
175  li t1, MSTATUS_TVM
176  csrs mstatus, t1
177  j 2b
178
1798:
180  li t1, MSTATUS_TSR
181  csrs mstatus, t1
182  j 2b
183
1849:
185  j 2b
186
187RVTEST_CODE_END
188
189  .data
190RVTEST_DATA_BEGIN
191
192  TEST_DATA
193
194RVTEST_DATA_END
195