breakpoint.S revision 12771:75508af5d8dc 
1# See LICENSE for license details.
2
3#*****************************************************************************
4# breakpoint.S
5#-----------------------------------------------------------------------------
6#
7# Test breakpoints, if they are implemented.
8#
9
10#include "riscv_test.h"
11#include "test_macros.h"
12
13RVTEST_RV64M
14RVTEST_CODE_BEGIN
15
16  # Set up breakpoint to trap on M-mode fetches.
17  li TESTNUM, 2
18
19  # Skip tselect if hard-wired.
20  csrw tselect, x0
21  csrr a1, tselect
22  bne x0, a1, pass
23
24  # Make sure there's a breakpoint there.
25  csrr a0, tdata1
26  srli a0, a0, __riscv_xlen - 4
27  li a1, 2
28  bne a0, a1, pass
29
30  la a2, 1f
31  csrw tdata2, a2
32  li a0, MCONTROL_M | MCONTROL_EXECUTE
33  csrw tdata1, a0
34  # Skip if breakpoint type is unsupported.
35  csrr a1, tdata1
36  andi a1, a1, 0x7ff
37  bne a0, a1, 2f
38  .align 2
391:
40  # Trap handler should skip this instruction.
41  beqz x0, fail
42
43  # Make sure reads don't trap.
44  li TESTNUM, 3
45  lw a0, (a2)
46
472:
48  # Set up breakpoint to trap on M-mode reads.
49  li TESTNUM, 4
50  li a0, MCONTROL_M | MCONTROL_LOAD
51  csrw tdata1, a0
52  # Skip if breakpoint type is unsupported.
53  csrr a1, tdata1
54  andi a1, a1, 0x7ff
55  bne a0, a1, 2f
56  la a2, data1
57  csrw tdata2, a2
58
59  # Trap handler should skip this instruction.
60  lw a2, (a2)
61  beqz a2, fail
62
63  # Make sure writes don't trap.
64  li TESTNUM, 5
65  sw x0, (a2)
66
672:
68  # Set up breakpoint to trap on M-mode stores.
69  li TESTNUM, 6
70  li a0, MCONTROL_M | MCONTROL_STORE
71  csrw tdata1, a0
72  # Skip if breakpoint type is unsupported.
73  csrr a1, tdata1
74  andi a1, a1, 0x7ff
75  bne a0, a1, 2f
76
77  # Trap handler should skip this instruction.
78  sw a2, (a2)
79
80  # Make sure store didn't succeed.
81  li TESTNUM, 7
82  lw a2, (a2)
83  bnez a2, fail
84
85  # Try to set up a second breakpoint.
86  li a0, 1
87  csrw tselect, a0
88  csrr a1, tselect
89  bne a0, a1, pass
90
91  # Make sure there's a breakpoint there.
92  csrr a0, tdata1
93  srli a0, a0, __riscv_xlen - 4
94  li a1, 2
95  bne a0, a1, pass
96
97  li a0, MCONTROL_M | MCONTROL_LOAD
98  csrw tdata1, a0
99  la a3, data2
100  csrw tdata2, a3
101
102  # Make sure the second breakpoint triggers.
103  li TESTNUM, 8
104  lw a3, (a3)
105  beqz a3, fail
106
107  # Make sure the first breakpoint still triggers.
108  li TESTNUM, 10
109  la a2, data1
110  sw a2, (a2)
111  li TESTNUM, 11
112  lw a2, (a2)
113  bnez a2, fail
114
1152:
116  TEST_PASSFAIL
117
118  .align 2
119  .global mtvec_handler
120mtvec_handler:
121  # Only even-numbered tests should trap.
122  andi t0, TESTNUM, 1
123  bnez t0, fail
124
125  li t0, CAUSE_BREAKPOINT
126  csrr t1, mcause
127  bne t0, t1, fail
128
129  csrr t0, mepc
130  addi t0, t0, 4
131  csrw mepc, t0
132  mret
133
134RVTEST_CODE_END
135
136  .data
137RVTEST_DATA_BEGIN
138
139  TEST_DATA
140
141data1: .word 0
142data2: .word 0
143
144RVTEST_DATA_END
145