stats.txt revision 10752:62b24818c8c6
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.230173 # Number of seconds simulated 4sim_ticks 230173357500 # Number of ticks simulated 5final_tick 230173357500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 1098511 # Simulator instruction rate (inst/s) 8host_op_rate 1158108 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1471393960 # Simulator tick rate (ticks/s) 10host_mem_usage 313104 # Number of bytes of host memory used 11host_seconds 156.43 # Real time elapsed on the host 12sim_insts 171842483 # Number of instructions simulated 13sim_ops 181165370 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 110656 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 110336 # Number of bytes read from this memory 18system.physmem.bytes_read::total 220992 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 110656 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 110656 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 1729 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 1724 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 3453 # Number of read requests responded to by this memory 24system.physmem.bw_read::cpu.inst 480751 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 479360 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 960111 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 480751 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 480751 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 480751 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 479360 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 960111 # Total bandwidth to/from this memory (bytes/s) 32system.cpu_clk_domain.clock 500 # Clock period in ticks 33system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 34system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 35system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 36system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 37system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 38system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 39system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 40system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 41system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 42system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 43system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 44system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 45system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 46system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 47system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 48system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 49system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 50system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 51system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 52system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 53system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 54system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 55system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 56system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 57system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 58system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 59system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 60system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 61system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 62system.cpu.dtb.walker.walks 0 # Table walker walks requested 63system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 64system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 65system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 66system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 67system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 68system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 69system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 70system.cpu.dtb.inst_hits 0 # ITB inst hits 71system.cpu.dtb.inst_misses 0 # ITB inst misses 72system.cpu.dtb.read_hits 0 # DTB read hits 73system.cpu.dtb.read_misses 0 # DTB read misses 74system.cpu.dtb.write_hits 0 # DTB write hits 75system.cpu.dtb.write_misses 0 # DTB write misses 76system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 77system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 78system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 79system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 80system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 81system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 82system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 83system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 84system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 85system.cpu.dtb.read_accesses 0 # DTB read accesses 86system.cpu.dtb.write_accesses 0 # DTB write accesses 87system.cpu.dtb.inst_accesses 0 # ITB inst accesses 88system.cpu.dtb.hits 0 # DTB hits 89system.cpu.dtb.misses 0 # DTB misses 90system.cpu.dtb.accesses 0 # DTB accesses 91system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 92system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 93system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 94system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 95system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 96system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 97system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 98system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 99system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 100system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 101system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 102system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 103system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 104system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 105system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 106system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 107system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 108system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 109system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 110system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 111system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 112system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 113system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 114system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 115system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 116system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 117system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 118system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 119system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 120system.cpu.itb.walker.walks 0 # Table walker walks requested 121system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 122system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 123system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 124system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 125system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 126system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 127system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 128system.cpu.itb.inst_hits 0 # ITB inst hits 129system.cpu.itb.inst_misses 0 # ITB inst misses 130system.cpu.itb.read_hits 0 # DTB read hits 131system.cpu.itb.read_misses 0 # DTB read misses 132system.cpu.itb.write_hits 0 # DTB write hits 133system.cpu.itb.write_misses 0 # DTB write misses 134system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 135system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 136system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 137system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 138system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 139system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 140system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 141system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 142system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 143system.cpu.itb.read_accesses 0 # DTB read accesses 144system.cpu.itb.write_accesses 0 # DTB write accesses 145system.cpu.itb.inst_accesses 0 # ITB inst accesses 146system.cpu.itb.hits 0 # DTB hits 147system.cpu.itb.misses 0 # DTB misses 148system.cpu.itb.accesses 0 # DTB accesses 149system.cpu.workload.num_syscalls 400 # Number of system calls 150system.cpu.numCycles 460346715 # number of cpu cycles simulated 151system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 152system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 153system.cpu.committedInsts 171842483 # Number of instructions committed 154system.cpu.committedOps 181165370 # Number of ops (including micro ops) committed 155system.cpu.num_int_alu_accesses 143085668 # Number of integer alu accesses 156system.cpu.num_fp_alu_accesses 1752310 # Number of float alu accesses 157system.cpu.num_func_calls 3545028 # number of times a function call or return occured 158system.cpu.num_conditional_control_insts 32201008 # number of instructions that are conditional controls 159system.cpu.num_int_insts 143085668 # number of integer instructions 160system.cpu.num_fp_insts 1752310 # number of float instructions 161system.cpu.num_int_register_reads 242291225 # number of times the integer registers were read 162system.cpu.num_int_register_writes 98192342 # number of times the integer registers were written 163system.cpu.num_fp_register_reads 2822225 # number of times the floating registers were read 164system.cpu.num_fp_register_writes 2378039 # number of times the floating registers were written 165system.cpu.num_cc_register_reads 626384527 # number of times the CC registers were read 166system.cpu.num_cc_register_writes 190815535 # number of times the CC registers were written 167system.cpu.num_mem_refs 40540779 # number of memory refs 168system.cpu.num_load_insts 27896144 # Number of load instructions 169system.cpu.num_store_insts 12644635 # Number of store instructions 170system.cpu.num_idle_cycles 0.002000 # Number of idle cycles 171system.cpu.num_busy_cycles 460346714.998000 # Number of busy cycles 172system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles 173system.cpu.idle_fraction 0.000000 # Percentage of idle cycles 174system.cpu.Branches 40300311 # Number of branches fetched 175system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction 176system.cpu.op_class::IntAlu 138988212 76.51% 76.51% # Class of executed instruction 177system.cpu.op_class::IntMult 908940 0.50% 77.01% # Class of executed instruction 178system.cpu.op_class::IntDiv 0 0.00% 77.01% # Class of executed instruction 179system.cpu.op_class::FloatAdd 0 0.00% 77.01% # Class of executed instruction 180system.cpu.op_class::FloatCmp 0 0.00% 77.01% # Class of executed instruction 181system.cpu.op_class::FloatCvt 0 0.00% 77.01% # Class of executed instruction 182system.cpu.op_class::FloatMult 0 0.00% 77.01% # Class of executed instruction 183system.cpu.op_class::FloatDiv 0 0.00% 77.01% # Class of executed instruction 184system.cpu.op_class::FloatSqrt 0 0.00% 77.01% # Class of executed instruction 185system.cpu.op_class::SimdAdd 0 0.00% 77.01% # Class of executed instruction 186system.cpu.op_class::SimdAddAcc 0 0.00% 77.01% # Class of executed instruction 187system.cpu.op_class::SimdAlu 0 0.00% 77.01% # Class of executed instruction 188system.cpu.op_class::SimdCmp 0 0.00% 77.01% # Class of executed instruction 189system.cpu.op_class::SimdCvt 0 0.00% 77.01% # Class of executed instruction 190system.cpu.op_class::SimdMisc 0 0.00% 77.01% # Class of executed instruction 191system.cpu.op_class::SimdMult 0 0.00% 77.01% # Class of executed instruction 192system.cpu.op_class::SimdMultAcc 0 0.00% 77.01% # Class of executed instruction 193system.cpu.op_class::SimdShift 0 0.00% 77.01% # Class of executed instruction 194system.cpu.op_class::SimdShiftAcc 0 0.00% 77.01% # Class of executed instruction 195system.cpu.op_class::SimdSqrt 0 0.00% 77.01% # Class of executed instruction 196system.cpu.op_class::SimdFloatAdd 32754 0.02% 77.03% # Class of executed instruction 197system.cpu.op_class::SimdFloatAlu 0 0.00% 77.03% # Class of executed instruction 198system.cpu.op_class::SimdFloatCmp 154829 0.09% 77.12% # Class of executed instruction 199system.cpu.op_class::SimdFloatCvt 238880 0.13% 77.25% # Class of executed instruction 200system.cpu.op_class::SimdFloatDiv 76016 0.04% 77.29% # Class of executed instruction 201system.cpu.op_class::SimdFloatMisc 437591 0.24% 77.53% # Class of executed instruction 202system.cpu.op_class::SimdFloatMult 200806 0.11% 77.64% # Class of executed instruction 203system.cpu.op_class::SimdFloatMultAcc 71617 0.04% 77.68% # Class of executed instruction 204system.cpu.op_class::SimdFloatSqrt 318 0.00% 77.68% # Class of executed instruction 205system.cpu.op_class::MemRead 27896144 15.36% 93.04% # Class of executed instruction 206system.cpu.op_class::MemWrite 12644635 6.96% 100.00% # Class of executed instruction 207system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 208system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 209system.cpu.op_class::total 181650742 # Class of executed instruction 210system.cpu.dcache.tags.replacements 40 # number of replacements 211system.cpu.dcache.tags.tagsinuse 1363.619277 # Cycle average of tags in use 212system.cpu.dcache.tags.total_refs 40162626 # Total number of references to valid blocks. 213system.cpu.dcache.tags.sampled_refs 1789 # Sample count of references to valid blocks. 214system.cpu.dcache.tags.avg_refs 22449.762996 # Average number of references to valid blocks. 215system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 216system.cpu.dcache.tags.occ_blocks::cpu.data 1363.619277 # Average occupied blocks per requestor 217system.cpu.dcache.tags.occ_percent::cpu.data 0.332915 # Average percentage of cache occupancy 218system.cpu.dcache.tags.occ_percent::total 0.332915 # Average percentage of cache occupancy 219system.cpu.dcache.tags.occ_task_id_blocks::1024 1749 # Occupied blocks per task id 220system.cpu.dcache.tags.age_task_id_blocks_1024::0 14 # Occupied blocks per task id 221system.cpu.dcache.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id 222system.cpu.dcache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id 223system.cpu.dcache.tags.age_task_id_blocks_1024::3 302 # Occupied blocks per task id 224system.cpu.dcache.tags.age_task_id_blocks_1024::4 1345 # Occupied blocks per task id 225system.cpu.dcache.tags.occ_task_id_percent::1024 0.427002 # Percentage of cache occupancy per task id 226system.cpu.dcache.tags.tag_accesses 80330619 # Number of tag accesses 227system.cpu.dcache.tags.data_accesses 80330619 # Number of data accesses 228system.cpu.dcache.ReadReq_hits::cpu.data 27754163 # number of ReadReq hits 229system.cpu.dcache.ReadReq_hits::total 27754163 # number of ReadReq hits 230system.cpu.dcache.WriteReq_hits::cpu.data 12363187 # number of WriteReq hits 231system.cpu.dcache.WriteReq_hits::total 12363187 # number of WriteReq hits 232system.cpu.dcache.SoftPFReq_hits::cpu.data 462 # number of SoftPFReq hits 233system.cpu.dcache.SoftPFReq_hits::total 462 # number of SoftPFReq hits 234system.cpu.dcache.LoadLockedReq_hits::cpu.data 22407 # number of LoadLockedReq hits 235system.cpu.dcache.LoadLockedReq_hits::total 22407 # number of LoadLockedReq hits 236system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits 237system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits 238system.cpu.dcache.demand_hits::cpu.data 40117350 # number of demand (read+write) hits 239system.cpu.dcache.demand_hits::total 40117350 # number of demand (read+write) hits 240system.cpu.dcache.overall_hits::cpu.data 40117812 # number of overall hits 241system.cpu.dcache.overall_hits::total 40117812 # number of overall hits 242system.cpu.dcache.ReadReq_misses::cpu.data 688 # number of ReadReq misses 243system.cpu.dcache.ReadReq_misses::total 688 # number of ReadReq misses 244system.cpu.dcache.WriteReq_misses::cpu.data 1100 # number of WriteReq misses 245system.cpu.dcache.WriteReq_misses::total 1100 # number of WriteReq misses 246system.cpu.dcache.SoftPFReq_misses::cpu.data 1 # number of SoftPFReq misses 247system.cpu.dcache.SoftPFReq_misses::total 1 # number of SoftPFReq misses 248system.cpu.dcache.demand_misses::cpu.data 1788 # number of demand (read+write) misses 249system.cpu.dcache.demand_misses::total 1788 # number of demand (read+write) misses 250system.cpu.dcache.overall_misses::cpu.data 1789 # number of overall misses 251system.cpu.dcache.overall_misses::total 1789 # number of overall misses 252system.cpu.dcache.ReadReq_miss_latency::cpu.data 35469000 # number of ReadReq miss cycles 253system.cpu.dcache.ReadReq_miss_latency::total 35469000 # number of ReadReq miss cycles 254system.cpu.dcache.WriteReq_miss_latency::cpu.data 60194500 # number of WriteReq miss cycles 255system.cpu.dcache.WriteReq_miss_latency::total 60194500 # number of WriteReq miss cycles 256system.cpu.dcache.demand_miss_latency::cpu.data 95663500 # number of demand (read+write) miss cycles 257system.cpu.dcache.demand_miss_latency::total 95663500 # number of demand (read+write) miss cycles 258system.cpu.dcache.overall_miss_latency::cpu.data 95663500 # number of overall miss cycles 259system.cpu.dcache.overall_miss_latency::total 95663500 # number of overall miss cycles 260system.cpu.dcache.ReadReq_accesses::cpu.data 27754851 # number of ReadReq accesses(hits+misses) 261system.cpu.dcache.ReadReq_accesses::total 27754851 # number of ReadReq accesses(hits+misses) 262system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) 263system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) 264system.cpu.dcache.SoftPFReq_accesses::cpu.data 463 # number of SoftPFReq accesses(hits+misses) 265system.cpu.dcache.SoftPFReq_accesses::total 463 # number of SoftPFReq accesses(hits+misses) 266system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22407 # number of LoadLockedReq accesses(hits+misses) 267system.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses) 268system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses) 269system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) 270system.cpu.dcache.demand_accesses::cpu.data 40119138 # number of demand (read+write) accesses 271system.cpu.dcache.demand_accesses::total 40119138 # number of demand (read+write) accesses 272system.cpu.dcache.overall_accesses::cpu.data 40119601 # number of overall (read+write) accesses 273system.cpu.dcache.overall_accesses::total 40119601 # number of overall (read+write) accesses 274system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000025 # miss rate for ReadReq accesses 275system.cpu.dcache.ReadReq_miss_rate::total 0.000025 # miss rate for ReadReq accesses 276system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000089 # miss rate for WriteReq accesses 277system.cpu.dcache.WriteReq_miss_rate::total 0.000089 # miss rate for WriteReq accesses 278system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.002160 # miss rate for SoftPFReq accesses 279system.cpu.dcache.SoftPFReq_miss_rate::total 0.002160 # miss rate for SoftPFReq accesses 280system.cpu.dcache.demand_miss_rate::cpu.data 0.000045 # miss rate for demand accesses 281system.cpu.dcache.demand_miss_rate::total 0.000045 # miss rate for demand accesses 282system.cpu.dcache.overall_miss_rate::cpu.data 0.000045 # miss rate for overall accesses 283system.cpu.dcache.overall_miss_rate::total 0.000045 # miss rate for overall accesses 284system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51553.779070 # average ReadReq miss latency 285system.cpu.dcache.ReadReq_avg_miss_latency::total 51553.779070 # average ReadReq miss latency 286system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54722.272727 # average WriteReq miss latency 287system.cpu.dcache.WriteReq_avg_miss_latency::total 54722.272727 # average WriteReq miss latency 288system.cpu.dcache.demand_avg_miss_latency::cpu.data 53503.076063 # average overall miss latency 289system.cpu.dcache.demand_avg_miss_latency::total 53503.076063 # average overall miss latency 290system.cpu.dcache.overall_avg_miss_latency::cpu.data 53473.169368 # average overall miss latency 291system.cpu.dcache.overall_avg_miss_latency::total 53473.169368 # average overall miss latency 292system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 293system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 294system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 295system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 296system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 297system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 298system.cpu.dcache.fast_writes 0 # number of fast writes performed 299system.cpu.dcache.cache_copies 0 # number of cache copies performed 300system.cpu.dcache.writebacks::writebacks 16 # number of writebacks 301system.cpu.dcache.writebacks::total 16 # number of writebacks 302system.cpu.dcache.ReadReq_mshr_misses::cpu.data 688 # number of ReadReq MSHR misses 303system.cpu.dcache.ReadReq_mshr_misses::total 688 # number of ReadReq MSHR misses 304system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1100 # number of WriteReq MSHR misses 305system.cpu.dcache.WriteReq_mshr_misses::total 1100 # number of WriteReq MSHR misses 306system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses 307system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses 308system.cpu.dcache.demand_mshr_misses::cpu.data 1788 # number of demand (read+write) MSHR misses 309system.cpu.dcache.demand_mshr_misses::total 1788 # number of demand (read+write) MSHR misses 310system.cpu.dcache.overall_mshr_misses::cpu.data 1789 # number of overall MSHR misses 311system.cpu.dcache.overall_mshr_misses::total 1789 # number of overall MSHR misses 312system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 34437000 # number of ReadReq MSHR miss cycles 313system.cpu.dcache.ReadReq_mshr_miss_latency::total 34437000 # number of ReadReq MSHR miss cycles 314system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 58544500 # number of WriteReq MSHR miss cycles 315system.cpu.dcache.WriteReq_mshr_miss_latency::total 58544500 # number of WriteReq MSHR miss cycles 316system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 53500 # number of SoftPFReq MSHR miss cycles 317system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 53500 # number of SoftPFReq MSHR miss cycles 318system.cpu.dcache.demand_mshr_miss_latency::cpu.data 92981500 # number of demand (read+write) MSHR miss cycles 319system.cpu.dcache.demand_mshr_miss_latency::total 92981500 # number of demand (read+write) MSHR miss cycles 320system.cpu.dcache.overall_mshr_miss_latency::cpu.data 93035000 # number of overall MSHR miss cycles 321system.cpu.dcache.overall_mshr_miss_latency::total 93035000 # number of overall MSHR miss cycles 322system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for ReadReq accesses 323system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000025 # mshr miss rate for ReadReq accesses 324system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000089 # mshr miss rate for WriteReq accesses 325system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000089 # mshr miss rate for WriteReq accesses 326system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.002160 # mshr miss rate for SoftPFReq accesses 327system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.002160 # mshr miss rate for SoftPFReq accesses 328system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000045 # mshr miss rate for demand accesses 329system.cpu.dcache.demand_mshr_miss_rate::total 0.000045 # mshr miss rate for demand accesses 330system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000045 # mshr miss rate for overall accesses 331system.cpu.dcache.overall_mshr_miss_rate::total 0.000045 # mshr miss rate for overall accesses 332system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 50053.779070 # average ReadReq mshr miss latency 333system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 50053.779070 # average ReadReq mshr miss latency 334system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53222.272727 # average WriteReq mshr miss latency 335system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53222.272727 # average WriteReq mshr miss latency 336system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53500 # average SoftPFReq mshr miss latency 337system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53500 # average SoftPFReq mshr miss latency 338system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52003.076063 # average overall mshr miss latency 339system.cpu.dcache.demand_avg_mshr_miss_latency::total 52003.076063 # average overall mshr miss latency 340system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52003.912800 # average overall mshr miss latency 341system.cpu.dcache.overall_avg_mshr_miss_latency::total 52003.912800 # average overall mshr miss latency 342system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 343system.cpu.icache.tags.replacements 1506 # number of replacements 344system.cpu.icache.tags.tagsinuse 1147.992598 # Cycle average of tags in use 345system.cpu.icache.tags.total_refs 189857001 # Total number of references to valid blocks. 346system.cpu.icache.tags.sampled_refs 3051 # Sample count of references to valid blocks. 347system.cpu.icache.tags.avg_refs 62227.794494 # Average number of references to valid blocks. 348system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 349system.cpu.icache.tags.occ_blocks::cpu.inst 1147.992598 # Average occupied blocks per requestor 350system.cpu.icache.tags.occ_percent::cpu.inst 0.560543 # Average percentage of cache occupancy 351system.cpu.icache.tags.occ_percent::total 0.560543 # Average percentage of cache occupancy 352system.cpu.icache.tags.occ_task_id_blocks::1024 1545 # Occupied blocks per task id 353system.cpu.icache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id 354system.cpu.icache.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id 355system.cpu.icache.tags.age_task_id_blocks_1024::2 288 # Occupied blocks per task id 356system.cpu.icache.tags.age_task_id_blocks_1024::3 270 # Occupied blocks per task id 357system.cpu.icache.tags.age_task_id_blocks_1024::4 942 # Occupied blocks per task id 358system.cpu.icache.tags.occ_task_id_percent::1024 0.754395 # Percentage of cache occupancy per task id 359system.cpu.icache.tags.tag_accesses 379723155 # Number of tag accesses 360system.cpu.icache.tags.data_accesses 379723155 # Number of data accesses 361system.cpu.icache.ReadReq_hits::cpu.inst 189857001 # number of ReadReq hits 362system.cpu.icache.ReadReq_hits::total 189857001 # number of ReadReq hits 363system.cpu.icache.demand_hits::cpu.inst 189857001 # number of demand (read+write) hits 364system.cpu.icache.demand_hits::total 189857001 # number of demand (read+write) hits 365system.cpu.icache.overall_hits::cpu.inst 189857001 # number of overall hits 366system.cpu.icache.overall_hits::total 189857001 # number of overall hits 367system.cpu.icache.ReadReq_misses::cpu.inst 3051 # number of ReadReq misses 368system.cpu.icache.ReadReq_misses::total 3051 # number of ReadReq misses 369system.cpu.icache.demand_misses::cpu.inst 3051 # number of demand (read+write) misses 370system.cpu.icache.demand_misses::total 3051 # number of demand (read+write) misses 371system.cpu.icache.overall_misses::cpu.inst 3051 # number of overall misses 372system.cpu.icache.overall_misses::total 3051 # number of overall misses 373system.cpu.icache.ReadReq_miss_latency::cpu.inst 112371000 # number of ReadReq miss cycles 374system.cpu.icache.ReadReq_miss_latency::total 112371000 # number of ReadReq miss cycles 375system.cpu.icache.demand_miss_latency::cpu.inst 112371000 # number of demand (read+write) miss cycles 376system.cpu.icache.demand_miss_latency::total 112371000 # number of demand (read+write) miss cycles 377system.cpu.icache.overall_miss_latency::cpu.inst 112371000 # number of overall miss cycles 378system.cpu.icache.overall_miss_latency::total 112371000 # number of overall miss cycles 379system.cpu.icache.ReadReq_accesses::cpu.inst 189860052 # number of ReadReq accesses(hits+misses) 380system.cpu.icache.ReadReq_accesses::total 189860052 # number of ReadReq accesses(hits+misses) 381system.cpu.icache.demand_accesses::cpu.inst 189860052 # number of demand (read+write) accesses 382system.cpu.icache.demand_accesses::total 189860052 # number of demand (read+write) accesses 383system.cpu.icache.overall_accesses::cpu.inst 189860052 # number of overall (read+write) accesses 384system.cpu.icache.overall_accesses::total 189860052 # number of overall (read+write) accesses 385system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000016 # miss rate for ReadReq accesses 386system.cpu.icache.ReadReq_miss_rate::total 0.000016 # miss rate for ReadReq accesses 387system.cpu.icache.demand_miss_rate::cpu.inst 0.000016 # miss rate for demand accesses 388system.cpu.icache.demand_miss_rate::total 0.000016 # miss rate for demand accesses 389system.cpu.icache.overall_miss_rate::cpu.inst 0.000016 # miss rate for overall accesses 390system.cpu.icache.overall_miss_rate::total 0.000016 # miss rate for overall accesses 391system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36830.875123 # average ReadReq miss latency 392system.cpu.icache.ReadReq_avg_miss_latency::total 36830.875123 # average ReadReq miss latency 393system.cpu.icache.demand_avg_miss_latency::cpu.inst 36830.875123 # average overall miss latency 394system.cpu.icache.demand_avg_miss_latency::total 36830.875123 # average overall miss latency 395system.cpu.icache.overall_avg_miss_latency::cpu.inst 36830.875123 # average overall miss latency 396system.cpu.icache.overall_avg_miss_latency::total 36830.875123 # average overall miss latency 397system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 398system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 399system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 400system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 401system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 402system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 403system.cpu.icache.fast_writes 0 # number of fast writes performed 404system.cpu.icache.cache_copies 0 # number of cache copies performed 405system.cpu.icache.ReadReq_mshr_misses::cpu.inst 3051 # number of ReadReq MSHR misses 406system.cpu.icache.ReadReq_mshr_misses::total 3051 # number of ReadReq MSHR misses 407system.cpu.icache.demand_mshr_misses::cpu.inst 3051 # number of demand (read+write) MSHR misses 408system.cpu.icache.demand_mshr_misses::total 3051 # number of demand (read+write) MSHR misses 409system.cpu.icache.overall_mshr_misses::cpu.inst 3051 # number of overall MSHR misses 410system.cpu.icache.overall_mshr_misses::total 3051 # number of overall MSHR misses 411system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 107794500 # number of ReadReq MSHR miss cycles 412system.cpu.icache.ReadReq_mshr_miss_latency::total 107794500 # number of ReadReq MSHR miss cycles 413system.cpu.icache.demand_mshr_miss_latency::cpu.inst 107794500 # number of demand (read+write) MSHR miss cycles 414system.cpu.icache.demand_mshr_miss_latency::total 107794500 # number of demand (read+write) MSHR miss cycles 415system.cpu.icache.overall_mshr_miss_latency::cpu.inst 107794500 # number of overall MSHR miss cycles 416system.cpu.icache.overall_mshr_miss_latency::total 107794500 # number of overall MSHR miss cycles 417system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for ReadReq accesses 418system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000016 # mshr miss rate for ReadReq accesses 419system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for demand accesses 420system.cpu.icache.demand_mshr_miss_rate::total 0.000016 # mshr miss rate for demand accesses 421system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for overall accesses 422system.cpu.icache.overall_mshr_miss_rate::total 0.000016 # mshr miss rate for overall accesses 423system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35330.875123 # average ReadReq mshr miss latency 424system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35330.875123 # average ReadReq mshr miss latency 425system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35330.875123 # average overall mshr miss latency 426system.cpu.icache.demand_avg_mshr_miss_latency::total 35330.875123 # average overall mshr miss latency 427system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35330.875123 # average overall mshr miss latency 428system.cpu.icache.overall_avg_mshr_miss_latency::total 35330.875123 # average overall mshr miss latency 429system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 430system.cpu.l2cache.tags.replacements 0 # number of replacements 431system.cpu.l2cache.tags.tagsinuse 1675.663349 # Cycle average of tags in use 432system.cpu.l2cache.tags.total_refs 1380 # Total number of references to valid blocks. 433system.cpu.l2cache.tags.sampled_refs 2369 # Sample count of references to valid blocks. 434system.cpu.l2cache.tags.avg_refs 0.582524 # Average number of references to valid blocks. 435system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 436system.cpu.l2cache.tags.occ_blocks::writebacks 3.037779 # Average occupied blocks per requestor 437system.cpu.l2cache.tags.occ_blocks::cpu.inst 1169.036753 # Average occupied blocks per requestor 438system.cpu.l2cache.tags.occ_blocks::cpu.data 503.588818 # Average occupied blocks per requestor 439system.cpu.l2cache.tags.occ_percent::writebacks 0.000093 # Average percentage of cache occupancy 440system.cpu.l2cache.tags.occ_percent::cpu.inst 0.035676 # Average percentage of cache occupancy 441system.cpu.l2cache.tags.occ_percent::cpu.data 0.015368 # Average percentage of cache occupancy 442system.cpu.l2cache.tags.occ_percent::total 0.051137 # Average percentage of cache occupancy 443system.cpu.l2cache.tags.occ_task_id_blocks::1024 2369 # Occupied blocks per task id 444system.cpu.l2cache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id 445system.cpu.l2cache.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id 446system.cpu.l2cache.tags.age_task_id_blocks_1024::2 320 # Occupied blocks per task id 447system.cpu.l2cache.tags.age_task_id_blocks_1024::3 322 # Occupied blocks per task id 448system.cpu.l2cache.tags.age_task_id_blocks_1024::4 1679 # Occupied blocks per task id 449system.cpu.l2cache.tags.occ_task_id_percent::1024 0.072296 # Percentage of cache occupancy per task id 450system.cpu.l2cache.tags.tag_accesses 42317 # Number of tag accesses 451system.cpu.l2cache.tags.data_accesses 42317 # Number of data accesses 452system.cpu.l2cache.ReadReq_hits::cpu.inst 1322 # number of ReadReq hits 453system.cpu.l2cache.ReadReq_hits::cpu.data 57 # number of ReadReq hits 454system.cpu.l2cache.ReadReq_hits::total 1379 # number of ReadReq hits 455system.cpu.l2cache.Writeback_hits::writebacks 16 # number of Writeback hits 456system.cpu.l2cache.Writeback_hits::total 16 # number of Writeback hits 457system.cpu.l2cache.ReadExReq_hits::cpu.data 8 # number of ReadExReq hits 458system.cpu.l2cache.ReadExReq_hits::total 8 # number of ReadExReq hits 459system.cpu.l2cache.demand_hits::cpu.inst 1322 # number of demand (read+write) hits 460system.cpu.l2cache.demand_hits::cpu.data 65 # number of demand (read+write) hits 461system.cpu.l2cache.demand_hits::total 1387 # number of demand (read+write) hits 462system.cpu.l2cache.overall_hits::cpu.inst 1322 # number of overall hits 463system.cpu.l2cache.overall_hits::cpu.data 65 # number of overall hits 464system.cpu.l2cache.overall_hits::total 1387 # number of overall hits 465system.cpu.l2cache.ReadReq_misses::cpu.inst 1729 # number of ReadReq misses 466system.cpu.l2cache.ReadReq_misses::cpu.data 632 # number of ReadReq misses 467system.cpu.l2cache.ReadReq_misses::total 2361 # number of ReadReq misses 468system.cpu.l2cache.ReadExReq_misses::cpu.data 1092 # number of ReadExReq misses 469system.cpu.l2cache.ReadExReq_misses::total 1092 # number of ReadExReq misses 470system.cpu.l2cache.demand_misses::cpu.inst 1729 # number of demand (read+write) misses 471system.cpu.l2cache.demand_misses::cpu.data 1724 # number of demand (read+write) misses 472system.cpu.l2cache.demand_misses::total 3453 # number of demand (read+write) misses 473system.cpu.l2cache.overall_misses::cpu.inst 1729 # number of overall misses 474system.cpu.l2cache.overall_misses::cpu.data 1724 # number of overall misses 475system.cpu.l2cache.overall_misses::total 3453 # number of overall misses 476system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 90862500 # number of ReadReq miss cycles 477system.cpu.l2cache.ReadReq_miss_latency::cpu.data 33203000 # number of ReadReq miss cycles 478system.cpu.l2cache.ReadReq_miss_latency::total 124065500 # number of ReadReq miss cycles 479system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 57360500 # number of ReadExReq miss cycles 480system.cpu.l2cache.ReadExReq_miss_latency::total 57360500 # number of ReadExReq miss cycles 481system.cpu.l2cache.demand_miss_latency::cpu.inst 90862500 # number of demand (read+write) miss cycles 482system.cpu.l2cache.demand_miss_latency::cpu.data 90563500 # number of demand (read+write) miss cycles 483system.cpu.l2cache.demand_miss_latency::total 181426000 # number of demand (read+write) miss cycles 484system.cpu.l2cache.overall_miss_latency::cpu.inst 90862500 # number of overall miss cycles 485system.cpu.l2cache.overall_miss_latency::cpu.data 90563500 # number of overall miss cycles 486system.cpu.l2cache.overall_miss_latency::total 181426000 # number of overall miss cycles 487system.cpu.l2cache.ReadReq_accesses::cpu.inst 3051 # number of ReadReq accesses(hits+misses) 488system.cpu.l2cache.ReadReq_accesses::cpu.data 689 # number of ReadReq accesses(hits+misses) 489system.cpu.l2cache.ReadReq_accesses::total 3740 # number of ReadReq accesses(hits+misses) 490system.cpu.l2cache.Writeback_accesses::writebacks 16 # number of Writeback accesses(hits+misses) 491system.cpu.l2cache.Writeback_accesses::total 16 # number of Writeback accesses(hits+misses) 492system.cpu.l2cache.ReadExReq_accesses::cpu.data 1100 # number of ReadExReq accesses(hits+misses) 493system.cpu.l2cache.ReadExReq_accesses::total 1100 # number of ReadExReq accesses(hits+misses) 494system.cpu.l2cache.demand_accesses::cpu.inst 3051 # number of demand (read+write) accesses 495system.cpu.l2cache.demand_accesses::cpu.data 1789 # number of demand (read+write) accesses 496system.cpu.l2cache.demand_accesses::total 4840 # number of demand (read+write) accesses 497system.cpu.l2cache.overall_accesses::cpu.inst 3051 # number of overall (read+write) accesses 498system.cpu.l2cache.overall_accesses::cpu.data 1789 # number of overall (read+write) accesses 499system.cpu.l2cache.overall_accesses::total 4840 # number of overall (read+write) accesses 500system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.566699 # miss rate for ReadReq accesses 501system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.917271 # miss rate for ReadReq accesses 502system.cpu.l2cache.ReadReq_miss_rate::total 0.631283 # miss rate for ReadReq accesses 503system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.992727 # miss rate for ReadExReq accesses 504system.cpu.l2cache.ReadExReq_miss_rate::total 0.992727 # miss rate for ReadExReq accesses 505system.cpu.l2cache.demand_miss_rate::cpu.inst 0.566699 # miss rate for demand accesses 506system.cpu.l2cache.demand_miss_rate::cpu.data 0.963667 # miss rate for demand accesses 507system.cpu.l2cache.demand_miss_rate::total 0.713430 # miss rate for demand accesses 508system.cpu.l2cache.overall_miss_rate::cpu.inst 0.566699 # miss rate for overall accesses 509system.cpu.l2cache.overall_miss_rate::cpu.data 0.963667 # miss rate for overall accesses 510system.cpu.l2cache.overall_miss_rate::total 0.713430 # miss rate for overall accesses 511system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52552.053210 # average ReadReq miss latency 512system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52536.392405 # average ReadReq miss latency 513system.cpu.l2cache.ReadReq_avg_miss_latency::total 52547.861076 # average ReadReq miss latency 514system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52527.930403 # average ReadExReq miss latency 515system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52527.930403 # average ReadExReq miss latency 516system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52552.053210 # average overall miss latency 517system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52531.032483 # average overall miss latency 518system.cpu.l2cache.demand_avg_miss_latency::total 52541.558065 # average overall miss latency 519system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52552.053210 # average overall miss latency 520system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52531.032483 # average overall miss latency 521system.cpu.l2cache.overall_avg_miss_latency::total 52541.558065 # average overall miss latency 522system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 523system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 524system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 525system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 526system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 527system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 528system.cpu.l2cache.fast_writes 0 # number of fast writes performed 529system.cpu.l2cache.cache_copies 0 # number of cache copies performed 530system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1729 # number of ReadReq MSHR misses 531system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 632 # number of ReadReq MSHR misses 532system.cpu.l2cache.ReadReq_mshr_misses::total 2361 # number of ReadReq MSHR misses 533system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1092 # number of ReadExReq MSHR misses 534system.cpu.l2cache.ReadExReq_mshr_misses::total 1092 # number of ReadExReq MSHR misses 535system.cpu.l2cache.demand_mshr_misses::cpu.inst 1729 # number of demand (read+write) MSHR misses 536system.cpu.l2cache.demand_mshr_misses::cpu.data 1724 # number of demand (read+write) MSHR misses 537system.cpu.l2cache.demand_mshr_misses::total 3453 # number of demand (read+write) MSHR misses 538system.cpu.l2cache.overall_mshr_misses::cpu.inst 1729 # number of overall MSHR misses 539system.cpu.l2cache.overall_mshr_misses::cpu.data 1724 # number of overall MSHR misses 540system.cpu.l2cache.overall_mshr_misses::total 3453 # number of overall MSHR misses 541system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 70024500 # number of ReadReq MSHR miss cycles 542system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 25596000 # number of ReadReq MSHR miss cycles 543system.cpu.l2cache.ReadReq_mshr_miss_latency::total 95620500 # number of ReadReq MSHR miss cycles 544system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 44226000 # number of ReadExReq MSHR miss cycles 545system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 44226000 # number of ReadExReq MSHR miss cycles 546system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 70024500 # number of demand (read+write) MSHR miss cycles 547system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 69822000 # number of demand (read+write) MSHR miss cycles 548system.cpu.l2cache.demand_mshr_miss_latency::total 139846500 # number of demand (read+write) MSHR miss cycles 549system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 70024500 # number of overall MSHR miss cycles 550system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 69822000 # number of overall MSHR miss cycles 551system.cpu.l2cache.overall_mshr_miss_latency::total 139846500 # number of overall MSHR miss cycles 552system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.566699 # mshr miss rate for ReadReq accesses 553system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.917271 # mshr miss rate for ReadReq accesses 554system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.631283 # mshr miss rate for ReadReq accesses 555system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992727 # mshr miss rate for ReadExReq accesses 556system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992727 # mshr miss rate for ReadExReq accesses 557system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.566699 # mshr miss rate for demand accesses 558system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.963667 # mshr miss rate for demand accesses 559system.cpu.l2cache.demand_mshr_miss_rate::total 0.713430 # mshr miss rate for demand accesses 560system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.566699 # mshr miss rate for overall accesses 561system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.963667 # mshr miss rate for overall accesses 562system.cpu.l2cache.overall_mshr_miss_rate::total 0.713430 # mshr miss rate for overall accesses 563system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency 564system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency 565system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency 566system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency 567system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency 568system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency 569system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency 570system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency 571system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency 572system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency 573system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency 574system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 575system.cpu.toL2Bus.trans_dist::ReadReq 3740 # Transaction distribution 576system.cpu.toL2Bus.trans_dist::ReadResp 3740 # Transaction distribution 577system.cpu.toL2Bus.trans_dist::Writeback 16 # Transaction distribution 578system.cpu.toL2Bus.trans_dist::ReadExReq 1100 # Transaction distribution 579system.cpu.toL2Bus.trans_dist::ReadExResp 1100 # Transaction distribution 580system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 6102 # Packet count per connected master and slave (bytes) 581system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3594 # Packet count per connected master and slave (bytes) 582system.cpu.toL2Bus.pkt_count::total 9696 # Packet count per connected master and slave (bytes) 583system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 195264 # Cumulative packet size per connected master and slave (bytes) 584system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 115520 # Cumulative packet size per connected master and slave (bytes) 585system.cpu.toL2Bus.pkt_size::total 310784 # Cumulative packet size per connected master and slave (bytes) 586system.cpu.toL2Bus.snoops 0 # Total snoops (count) 587system.cpu.toL2Bus.snoop_fanout::samples 4856 # Request fanout histogram 588system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram 589system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram 590system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 591system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 592system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 593system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 594system.cpu.toL2Bus.snoop_fanout::3 4856 100.00% 100.00% # Request fanout histogram 595system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram 596system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 597system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram 598system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram 599system.cpu.toL2Bus.snoop_fanout::total 4856 # Request fanout histogram 600system.cpu.toL2Bus.reqLayer0.occupancy 2444000 # Layer occupancy (ticks) 601system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 602system.cpu.toL2Bus.respLayer0.occupancy 4576500 # Layer occupancy (ticks) 603system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 604system.cpu.toL2Bus.respLayer1.occupancy 2683500 # Layer occupancy (ticks) 605system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 606system.membus.trans_dist::ReadReq 2361 # Transaction distribution 607system.membus.trans_dist::ReadResp 2361 # Transaction distribution 608system.membus.trans_dist::ReadExReq 1092 # Transaction distribution 609system.membus.trans_dist::ReadExResp 1092 # Transaction distribution 610system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 6906 # Packet count per connected master and slave (bytes) 611system.membus.pkt_count::total 6906 # Packet count per connected master and slave (bytes) 612system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 220992 # Cumulative packet size per connected master and slave (bytes) 613system.membus.pkt_size::total 220992 # Cumulative packet size per connected master and slave (bytes) 614system.membus.snoops 0 # Total snoops (count) 615system.membus.snoop_fanout::samples 3453 # Request fanout histogram 616system.membus.snoop_fanout::mean 0 # Request fanout histogram 617system.membus.snoop_fanout::stdev 0 # Request fanout histogram 618system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 619system.membus.snoop_fanout::0 3453 100.00% 100.00% # Request fanout histogram 620system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 621system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 622system.membus.snoop_fanout::min_value 0 # Request fanout histogram 623system.membus.snoop_fanout::max_value 0 # Request fanout histogram 624system.membus.snoop_fanout::total 3453 # Request fanout histogram 625system.membus.reqLayer0.occupancy 3596500 # Layer occupancy (ticks) 626system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 627system.membus.respLayer1.occupancy 17408500 # Layer occupancy (ticks) 628system.membus.respLayer1.utilization 0.0 # Layer utilization (%) 629 630---------- End Simulation Statistics ---------- 631