simout revision 12268
19520SAndreas.Sandberg@ARM.comRedirecting stdout to build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-dram-ctrl/simout 29520SAndreas.Sandberg@ARM.comRedirecting stderr to build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-dram-ctrl/simerr 39520SAndreas.Sandberg@ARM.comgem5 Simulator System. http://gem5.org 49520SAndreas.Sandberg@ARM.comgem5 is copyrighted software; use the --copyright option for details. 59520SAndreas.Sandberg@ARM.com 69520SAndreas.Sandberg@ARM.comgem5 compiled Nov 15 2017 18:28:23 79520SAndreas.Sandberg@ARM.comgem5 started Nov 15 2017 18:28:28 89520SAndreas.Sandberg@ARM.comgem5 executing on e108600-lin, pid 19888 99520SAndreas.Sandberg@ARM.comcommand line: /work/andsan01/outgoing/gem5/build/NULL/gem5.opt -d build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-dram-ctrl --stats-file 'text://stats.txt?desc=False' -re /work/andsan01/outgoing/gem5/tests/testing/../run.py quick/se/70.tgen/null/none/tgen-dram-ctrl 109520SAndreas.Sandberg@ARM.com 119520SAndreas.Sandberg@ARM.comGlobal frequency set at 1000000000000 ticks per second 129520SAndreas.Sandberg@ARM.comExiting @ tick 100000000000 because simulate() limit reached 139520SAndreas.Sandberg@ARM.com