config.ini revision 9885
1[root] 2type=Root 3children=system 4full_system=false 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 9[system] 10type=System 11children=clk_domain cpu membus monitor physmem 12boot_osflags=a 13cache_line_size=64 14clk_domain=system.clk_domain 15init_param=0 16kernel= 17load_addr_mask=1099511627775 18mem_mode=timing 19mem_ranges= 20memories=system.physmem 21num_work_ids=16 22readfile= 23symbolfile= 24work_begin_ckpt_count=0 25work_begin_cpu_id_exit=-1 26work_begin_exit_count=0 27work_cpus_ckpt_count=0 28work_end_ckpt_count=0 29work_end_exit_count=0 30work_item_id=-1 31system_port=system.membus.slave[1] 32 33[system.clk_domain] 34type=SrcClockDomain 35children=voltage_domain 36clock=1000 37voltage_domain=system.clk_domain.voltage_domain 38 39[system.clk_domain.voltage_domain] 40type=VoltageDomain 41voltage=1.000000 42 43[system.cpu] 44type=TrafficGen 45clk_domain=system.clk_domain 46config_file=tests/quick/se/70.tgen/tgen-simple-dram.cfg 47elastic_req=false 48system=system 49port=system.monitor.slave 50 51[system.membus] 52type=NoncoherentBus 53clk_domain=system.clk_domain 54header_cycles=1 55use_default_range=false 56width=16 57master=system.physmem.port 58slave=system.monitor.master system.system_port 59 60[system.monitor] 61type=CommMonitor 62bandwidth_bins=20 63burst_length_bins=20 64clk_domain=system.clk_domain 65disable_addr_dists=true 66disable_bandwidth_hists=false 67disable_burst_length_hists=false 68disable_itt_dists=false 69disable_latency_hists=false 70disable_outstanding_hists=false 71disable_transaction_hists=false 72itt_bins=20 73itt_max_bin=100000 74latency_bins=20 75outstanding_bins=20 76read_addr_mask=18446744073709551615 77sample_period=1000000000 78trace_file= 79transaction_bins=20 80write_addr_mask=18446744073709551615 81master=system.membus.slave[0] 82slave=system.cpu.port 83 84[system.physmem] 85type=SimpleDRAM 86activation_limit=4 87addr_mapping=RaBaChCo 88banks_per_rank=8 89burst_length=8 90channels=1 91clk_domain=system.clk_domain 92conf_table_reported=true 93device_bus_width=8 94device_rowbuffer_size=1024 95devices_per_rank=8 96in_addr_map=true 97mem_sched_policy=frfcfs 98null=false 99page_policy=open 100range=0:134217727 101ranks_per_channel=2 102read_buffer_size=32 103static_backend_latency=10000 104static_frontend_latency=10000 105tBURST=5000 106tCL=13750 107tRCD=13750 108tREFI=7800000 109tRFC=300000 110tRP=13750 111tWTR=7500 112tXAW=40000 113write_buffer_size=32 114write_thresh_perc=70 115port=system.membus.master[0] 116 117