stats.txt revision 11570:4aac82f10951
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.128077 # Number of seconds simulated 4sim_ticks 128076834500 # Number of ticks simulated 5final_tick 128076834500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 523174 # Simulator instruction rate (inst/s) 8host_op_rate 667947 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 952153159 # Simulator tick rate (ticks/s) 10host_mem_usage 273092 # Number of bytes of host memory used 11host_seconds 134.51 # Real time elapsed on the host 12sim_insts 70373651 # Number of instructions simulated 13sim_ops 89847385 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 128076834500 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.inst 233152 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 7925248 # Number of bytes read from this memory 19system.physmem.bytes_read::total 8158400 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 233152 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 233152 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 5513600 # Number of bytes written to this memory 23system.physmem.bytes_written::total 5513600 # Number of bytes written to this memory 24system.physmem.num_reads::cpu.inst 3643 # Number of read requests responded to by this memory 25system.physmem.num_reads::cpu.data 123832 # Number of read requests responded to by this memory 26system.physmem.num_reads::total 127475 # Number of read requests responded to by this memory 27system.physmem.num_writes::writebacks 86150 # Number of write requests responded to by this memory 28system.physmem.num_writes::total 86150 # Number of write requests responded to by this memory 29system.physmem.bw_read::cpu.inst 1820407 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::cpu.data 61878856 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_read::total 63699263 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::cpu.inst 1820407 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_inst_read::total 1820407 # Instruction read bandwidth from this memory (bytes/s) 34system.physmem.bw_write::writebacks 43049159 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_write::total 43049159 # Write bandwidth from this memory (bytes/s) 36system.physmem.bw_total::writebacks 43049159 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.inst 1820407 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::cpu.data 61878856 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.bw_total::total 106748422 # Total bandwidth to/from this memory (bytes/s) 40system.pwrStateResidencyTicks::UNDEFINED 128076834500 # Cumulative time (in ticks) in various power states 41system.cpu_clk_domain.clock 500 # Clock period in ticks 42system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 128076834500 # Cumulative time (in ticks) in various power states 43system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 44system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 45system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 46system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 47system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 48system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 49system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 50system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 51system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 52system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 53system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 54system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 55system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 56system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 57system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 58system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 59system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 60system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 61system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 62system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 63system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 64system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 65system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 66system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 67system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 68system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 69system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 70system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 71system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 72system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 128076834500 # Cumulative time (in ticks) in various power states 73system.cpu.dtb.walker.walks 0 # Table walker walks requested 74system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 75system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 76system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 77system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 78system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 79system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 80system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 81system.cpu.dtb.inst_hits 0 # ITB inst hits 82system.cpu.dtb.inst_misses 0 # ITB inst misses 83system.cpu.dtb.read_hits 0 # DTB read hits 84system.cpu.dtb.read_misses 0 # DTB read misses 85system.cpu.dtb.write_hits 0 # DTB write hits 86system.cpu.dtb.write_misses 0 # DTB write misses 87system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 88system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 89system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 90system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 91system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 92system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 93system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 94system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 95system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 96system.cpu.dtb.read_accesses 0 # DTB read accesses 97system.cpu.dtb.write_accesses 0 # DTB write accesses 98system.cpu.dtb.inst_accesses 0 # ITB inst accesses 99system.cpu.dtb.hits 0 # DTB hits 100system.cpu.dtb.misses 0 # DTB misses 101system.cpu.dtb.accesses 0 # DTB accesses 102system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 128076834500 # Cumulative time (in ticks) in various power states 103system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 104system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 105system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 106system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 107system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 108system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 109system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 110system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 111system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 112system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 113system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 114system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 115system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 116system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 117system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 118system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 119system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 120system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 121system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 122system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 123system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 124system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 125system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 126system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 127system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 128system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 129system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 130system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 131system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 132system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 128076834500 # Cumulative time (in ticks) in various power states 133system.cpu.itb.walker.walks 0 # Table walker walks requested 134system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 135system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 136system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 137system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 138system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 139system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 140system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 141system.cpu.itb.inst_hits 0 # ITB inst hits 142system.cpu.itb.inst_misses 0 # ITB inst misses 143system.cpu.itb.read_hits 0 # DTB read hits 144system.cpu.itb.read_misses 0 # DTB read misses 145system.cpu.itb.write_hits 0 # DTB write hits 146system.cpu.itb.write_misses 0 # DTB write misses 147system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 148system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 149system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 150system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 151system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 152system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 153system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 154system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 155system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 156system.cpu.itb.read_accesses 0 # DTB read accesses 157system.cpu.itb.write_accesses 0 # DTB write accesses 158system.cpu.itb.inst_accesses 0 # ITB inst accesses 159system.cpu.itb.hits 0 # DTB hits 160system.cpu.itb.misses 0 # DTB misses 161system.cpu.itb.accesses 0 # DTB accesses 162system.cpu.workload.num_syscalls 1946 # Number of system calls 163system.cpu.pwrStateResidencyTicks::ON 128076834500 # Cumulative time (in ticks) in various power states 164system.cpu.numCycles 256153669 # number of cpu cycles simulated 165system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 166system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 167system.cpu.committedInsts 70373651 # Number of instructions committed 168system.cpu.committedOps 89847385 # Number of ops (including micro ops) committed 169system.cpu.num_int_alu_accesses 81528528 # Number of integer alu accesses 170system.cpu.num_fp_alu_accesses 56 # Number of float alu accesses 171system.cpu.num_func_calls 3311620 # number of times a function call or return occured 172system.cpu.num_conditional_control_insts 9253630 # number of instructions that are conditional controls 173system.cpu.num_int_insts 81528528 # number of integer instructions 174system.cpu.num_fp_insts 56 # number of float instructions 175system.cpu.num_int_register_reads 141328435 # number of times the integer registers were read 176system.cpu.num_int_register_writes 53916335 # number of times the integer registers were written 177system.cpu.num_fp_register_reads 36 # number of times the floating registers were read 178system.cpu.num_fp_register_writes 20 # number of times the floating registers were written 179system.cpu.num_cc_register_reads 334802072 # number of times the CC registers were read 180system.cpu.num_cc_register_writes 36877111 # number of times the CC registers were written 181system.cpu.num_mem_refs 43422001 # number of memory refs 182system.cpu.num_load_insts 22866262 # Number of load instructions 183system.cpu.num_store_insts 20555739 # Number of store instructions 184system.cpu.num_idle_cycles 0.002000 # Number of idle cycles 185system.cpu.num_busy_cycles 256153668.998000 # Number of busy cycles 186system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles 187system.cpu.idle_fraction 0.000000 # Percentage of idle cycles 188system.cpu.Branches 13741468 # Number of branches fetched 189system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction 190system.cpu.op_class::IntAlu 47187979 52.03% 52.03% # Class of executed instruction 191system.cpu.op_class::IntMult 80119 0.09% 52.12% # Class of executed instruction 192system.cpu.op_class::IntDiv 0 0.00% 52.12% # Class of executed instruction 193system.cpu.op_class::FloatAdd 0 0.00% 52.12% # Class of executed instruction 194system.cpu.op_class::FloatCmp 0 0.00% 52.12% # Class of executed instruction 195system.cpu.op_class::FloatCvt 0 0.00% 52.12% # Class of executed instruction 196system.cpu.op_class::FloatMult 0 0.00% 52.12% # Class of executed instruction 197system.cpu.op_class::FloatDiv 0 0.00% 52.12% # Class of executed instruction 198system.cpu.op_class::FloatSqrt 0 0.00% 52.12% # Class of executed instruction 199system.cpu.op_class::SimdAdd 0 0.00% 52.12% # Class of executed instruction 200system.cpu.op_class::SimdAddAcc 0 0.00% 52.12% # Class of executed instruction 201system.cpu.op_class::SimdAlu 0 0.00% 52.12% # Class of executed instruction 202system.cpu.op_class::SimdCmp 0 0.00% 52.12% # Class of executed instruction 203system.cpu.op_class::SimdCvt 0 0.00% 52.12% # Class of executed instruction 204system.cpu.op_class::SimdMisc 0 0.00% 52.12% # Class of executed instruction 205system.cpu.op_class::SimdMult 0 0.00% 52.12% # Class of executed instruction 206system.cpu.op_class::SimdMultAcc 0 0.00% 52.12% # Class of executed instruction 207system.cpu.op_class::SimdShift 0 0.00% 52.12% # Class of executed instruction 208system.cpu.op_class::SimdShiftAcc 0 0.00% 52.12% # Class of executed instruction 209system.cpu.op_class::SimdSqrt 0 0.00% 52.12% # Class of executed instruction 210system.cpu.op_class::SimdFloatAdd 0 0.00% 52.12% # Class of executed instruction 211system.cpu.op_class::SimdFloatAlu 0 0.00% 52.12% # Class of executed instruction 212system.cpu.op_class::SimdFloatCmp 0 0.00% 52.12% # Class of executed instruction 213system.cpu.op_class::SimdFloatCvt 0 0.00% 52.12% # Class of executed instruction 214system.cpu.op_class::SimdFloatDiv 0 0.00% 52.12% # Class of executed instruction 215system.cpu.op_class::SimdFloatMisc 7 0.00% 52.12% # Class of executed instruction 216system.cpu.op_class::SimdFloatMult 0 0.00% 52.12% # Class of executed instruction 217system.cpu.op_class::SimdFloatMultAcc 0 0.00% 52.12% # Class of executed instruction 218system.cpu.op_class::SimdFloatSqrt 0 0.00% 52.12% # Class of executed instruction 219system.cpu.op_class::MemRead 22866262 25.21% 77.33% # Class of executed instruction 220system.cpu.op_class::MemWrite 20555739 22.67% 100.00% # Class of executed instruction 221system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 222system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 223system.cpu.op_class::total 90690106 # Class of executed instruction 224system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 128076834500 # Cumulative time (in ticks) in various power states 225system.cpu.dcache.tags.replacements 155902 # number of replacements 226system.cpu.dcache.tags.tagsinuse 4075.927155 # Cycle average of tags in use 227system.cpu.dcache.tags.total_refs 42601677 # Total number of references to valid blocks. 228system.cpu.dcache.tags.sampled_refs 159998 # Sample count of references to valid blocks. 229system.cpu.dcache.tags.avg_refs 266.263810 # Average number of references to valid blocks. 230system.cpu.dcache.tags.warmup_cycle 1109655500 # Cycle when the warmup percentage was hit. 231system.cpu.dcache.tags.occ_blocks::cpu.data 4075.927155 # Average occupied blocks per requestor 232system.cpu.dcache.tags.occ_percent::cpu.data 0.995099 # Average percentage of cache occupancy 233system.cpu.dcache.tags.occ_percent::total 0.995099 # Average percentage of cache occupancy 234system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 235system.cpu.dcache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id 236system.cpu.dcache.tags.age_task_id_blocks_1024::1 787 # Occupied blocks per task id 237system.cpu.dcache.tags.age_task_id_blocks_1024::2 3263 # Occupied blocks per task id 238system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 239system.cpu.dcache.tags.tag_accesses 85731098 # Number of tag accesses 240system.cpu.dcache.tags.data_accesses 85731098 # Number of data accesses 241system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 128076834500 # Cumulative time (in ticks) in various power states 242system.cpu.dcache.ReadReq_hits::cpu.data 22743361 # number of ReadReq hits 243system.cpu.dcache.ReadReq_hits::total 22743361 # number of ReadReq hits 244system.cpu.dcache.WriteReq_hits::cpu.data 19742869 # number of WriteReq hits 245system.cpu.dcache.WriteReq_hits::total 19742869 # number of WriteReq hits 246system.cpu.dcache.SoftPFReq_hits::cpu.data 83609 # number of SoftPFReq hits 247system.cpu.dcache.SoftPFReq_hits::total 83609 # number of SoftPFReq hits 248system.cpu.dcache.LoadLockedReq_hits::cpu.data 15919 # number of LoadLockedReq hits 249system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits 250system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits 251system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits 252system.cpu.dcache.demand_hits::cpu.data 42486230 # number of demand (read+write) hits 253system.cpu.dcache.demand_hits::total 42486230 # number of demand (read+write) hits 254system.cpu.dcache.overall_hits::cpu.data 42569839 # number of overall hits 255system.cpu.dcache.overall_hits::total 42569839 # number of overall hits 256system.cpu.dcache.ReadReq_misses::cpu.data 36706 # number of ReadReq misses 257system.cpu.dcache.ReadReq_misses::total 36706 # number of ReadReq misses 258system.cpu.dcache.WriteReq_misses::cpu.data 107032 # number of WriteReq misses 259system.cpu.dcache.WriteReq_misses::total 107032 # number of WriteReq misses 260system.cpu.dcache.SoftPFReq_misses::cpu.data 40135 # number of SoftPFReq misses 261system.cpu.dcache.SoftPFReq_misses::total 40135 # number of SoftPFReq misses 262system.cpu.dcache.demand_misses::cpu.data 143738 # number of demand (read+write) misses 263system.cpu.dcache.demand_misses::total 143738 # number of demand (read+write) misses 264system.cpu.dcache.overall_misses::cpu.data 183873 # number of overall misses 265system.cpu.dcache.overall_misses::total 183873 # number of overall misses 266system.cpu.dcache.ReadReq_miss_latency::cpu.data 577584000 # number of ReadReq miss cycles 267system.cpu.dcache.ReadReq_miss_latency::total 577584000 # number of ReadReq miss cycles 268system.cpu.dcache.WriteReq_miss_latency::cpu.data 6405138000 # number of WriteReq miss cycles 269system.cpu.dcache.WriteReq_miss_latency::total 6405138000 # number of WriteReq miss cycles 270system.cpu.dcache.demand_miss_latency::cpu.data 6982722000 # number of demand (read+write) miss cycles 271system.cpu.dcache.demand_miss_latency::total 6982722000 # number of demand (read+write) miss cycles 272system.cpu.dcache.overall_miss_latency::cpu.data 6982722000 # number of overall miss cycles 273system.cpu.dcache.overall_miss_latency::total 6982722000 # number of overall miss cycles 274system.cpu.dcache.ReadReq_accesses::cpu.data 22780067 # number of ReadReq accesses(hits+misses) 275system.cpu.dcache.ReadReq_accesses::total 22780067 # number of ReadReq accesses(hits+misses) 276system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) 277system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) 278system.cpu.dcache.SoftPFReq_accesses::cpu.data 123744 # number of SoftPFReq accesses(hits+misses) 279system.cpu.dcache.SoftPFReq_accesses::total 123744 # number of SoftPFReq accesses(hits+misses) 280system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15919 # number of LoadLockedReq accesses(hits+misses) 281system.cpu.dcache.LoadLockedReq_accesses::total 15919 # number of LoadLockedReq accesses(hits+misses) 282system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) 283system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) 284system.cpu.dcache.demand_accesses::cpu.data 42629968 # number of demand (read+write) accesses 285system.cpu.dcache.demand_accesses::total 42629968 # number of demand (read+write) accesses 286system.cpu.dcache.overall_accesses::cpu.data 42753712 # number of overall (read+write) accesses 287system.cpu.dcache.overall_accesses::total 42753712 # number of overall (read+write) accesses 288system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001611 # miss rate for ReadReq accesses 289system.cpu.dcache.ReadReq_miss_rate::total 0.001611 # miss rate for ReadReq accesses 290system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005392 # miss rate for WriteReq accesses 291system.cpu.dcache.WriteReq_miss_rate::total 0.005392 # miss rate for WriteReq accesses 292system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.324339 # miss rate for SoftPFReq accesses 293system.cpu.dcache.SoftPFReq_miss_rate::total 0.324339 # miss rate for SoftPFReq accesses 294system.cpu.dcache.demand_miss_rate::cpu.data 0.003372 # miss rate for demand accesses 295system.cpu.dcache.demand_miss_rate::total 0.003372 # miss rate for demand accesses 296system.cpu.dcache.overall_miss_rate::cpu.data 0.004301 # miss rate for overall accesses 297system.cpu.dcache.overall_miss_rate::total 0.004301 # miss rate for overall accesses 298system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15735.411104 # average ReadReq miss latency 299system.cpu.dcache.ReadReq_avg_miss_latency::total 15735.411104 # average ReadReq miss latency 300system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59843.205770 # average WriteReq miss latency 301system.cpu.dcache.WriteReq_avg_miss_latency::total 59843.205770 # average WriteReq miss latency 302system.cpu.dcache.demand_avg_miss_latency::cpu.data 48579.512725 # average overall miss latency 303system.cpu.dcache.demand_avg_miss_latency::total 48579.512725 # average overall miss latency 304system.cpu.dcache.overall_avg_miss_latency::cpu.data 37975.787636 # average overall miss latency 305system.cpu.dcache.overall_avg_miss_latency::total 37975.787636 # average overall miss latency 306system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 307system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 308system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 309system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 310system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 311system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 312system.cpu.dcache.writebacks::writebacks 128175 # number of writebacks 313system.cpu.dcache.writebacks::total 128175 # number of writebacks 314system.cpu.dcache.ReadReq_mshr_hits::cpu.data 7598 # number of ReadReq MSHR hits 315system.cpu.dcache.ReadReq_mshr_hits::total 7598 # number of ReadReq MSHR hits 316system.cpu.dcache.demand_mshr_hits::cpu.data 7598 # number of demand (read+write) MSHR hits 317system.cpu.dcache.demand_mshr_hits::total 7598 # number of demand (read+write) MSHR hits 318system.cpu.dcache.overall_mshr_hits::cpu.data 7598 # number of overall MSHR hits 319system.cpu.dcache.overall_mshr_hits::total 7598 # number of overall MSHR hits 320system.cpu.dcache.ReadReq_mshr_misses::cpu.data 29108 # number of ReadReq MSHR misses 321system.cpu.dcache.ReadReq_mshr_misses::total 29108 # number of ReadReq MSHR misses 322system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107032 # number of WriteReq MSHR misses 323system.cpu.dcache.WriteReq_mshr_misses::total 107032 # number of WriteReq MSHR misses 324system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 23858 # number of SoftPFReq MSHR misses 325system.cpu.dcache.SoftPFReq_mshr_misses::total 23858 # number of SoftPFReq MSHR misses 326system.cpu.dcache.demand_mshr_misses::cpu.data 136140 # number of demand (read+write) MSHR misses 327system.cpu.dcache.demand_mshr_misses::total 136140 # number of demand (read+write) MSHR misses 328system.cpu.dcache.overall_mshr_misses::cpu.data 159998 # number of overall MSHR misses 329system.cpu.dcache.overall_mshr_misses::total 159998 # number of overall MSHR misses 330system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 495022500 # number of ReadReq MSHR miss cycles 331system.cpu.dcache.ReadReq_mshr_miss_latency::total 495022500 # number of ReadReq MSHR miss cycles 332system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6298106000 # number of WriteReq MSHR miss cycles 333system.cpu.dcache.WriteReq_mshr_miss_latency::total 6298106000 # number of WriteReq MSHR miss cycles 334system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1201109000 # number of SoftPFReq MSHR miss cycles 335system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1201109000 # number of SoftPFReq MSHR miss cycles 336system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6793128500 # number of demand (read+write) MSHR miss cycles 337system.cpu.dcache.demand_mshr_miss_latency::total 6793128500 # number of demand (read+write) MSHR miss cycles 338system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7994237500 # number of overall MSHR miss cycles 339system.cpu.dcache.overall_mshr_miss_latency::total 7994237500 # number of overall MSHR miss cycles 340system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001278 # mshr miss rate for ReadReq accesses 341system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001278 # mshr miss rate for ReadReq accesses 342system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005392 # mshr miss rate for WriteReq accesses 343system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005392 # mshr miss rate for WriteReq accesses 344system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.192801 # mshr miss rate for SoftPFReq accesses 345system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.192801 # mshr miss rate for SoftPFReq accesses 346system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003194 # mshr miss rate for demand accesses 347system.cpu.dcache.demand_mshr_miss_rate::total 0.003194 # mshr miss rate for demand accesses 348system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003742 # mshr miss rate for overall accesses 349system.cpu.dcache.overall_mshr_miss_rate::total 0.003742 # mshr miss rate for overall accesses 350system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17006.407173 # average ReadReq mshr miss latency 351system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17006.407173 # average ReadReq mshr miss latency 352system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 58843.205770 # average WriteReq mshr miss latency 353system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 58843.205770 # average WriteReq mshr miss latency 354system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 50344.077458 # average SoftPFReq mshr miss latency 355system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 50344.077458 # average SoftPFReq mshr miss latency 356system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 49898.108565 # average overall mshr miss latency 357system.cpu.dcache.demand_avg_mshr_miss_latency::total 49898.108565 # average overall mshr miss latency 358system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 49964.608933 # average overall mshr miss latency 359system.cpu.dcache.overall_avg_mshr_miss_latency::total 49964.608933 # average overall mshr miss latency 360system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 128076834500 # Cumulative time (in ticks) in various power states 361system.cpu.icache.tags.replacements 16890 # number of replacements 362system.cpu.icache.tags.tagsinuse 1732.356634 # Cycle average of tags in use 363system.cpu.icache.tags.total_refs 78126184 # Total number of references to valid blocks. 364system.cpu.icache.tags.sampled_refs 18908 # Sample count of references to valid blocks. 365system.cpu.icache.tags.avg_refs 4131.911572 # Average number of references to valid blocks. 366system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 367system.cpu.icache.tags.occ_blocks::cpu.inst 1732.356634 # Average occupied blocks per requestor 368system.cpu.icache.tags.occ_percent::cpu.inst 0.845877 # Average percentage of cache occupancy 369system.cpu.icache.tags.occ_percent::total 0.845877 # Average percentage of cache occupancy 370system.cpu.icache.tags.occ_task_id_blocks::1024 2018 # Occupied blocks per task id 371system.cpu.icache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id 372system.cpu.icache.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id 373system.cpu.icache.tags.age_task_id_blocks_1024::3 294 # Occupied blocks per task id 374system.cpu.icache.tags.age_task_id_blocks_1024::4 1645 # Occupied blocks per task id 375system.cpu.icache.tags.occ_task_id_percent::1024 0.985352 # Percentage of cache occupancy per task id 376system.cpu.icache.tags.tag_accesses 156309092 # Number of tag accesses 377system.cpu.icache.tags.data_accesses 156309092 # Number of data accesses 378system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 128076834500 # Cumulative time (in ticks) in various power states 379system.cpu.icache.ReadReq_hits::cpu.inst 78126184 # number of ReadReq hits 380system.cpu.icache.ReadReq_hits::total 78126184 # number of ReadReq hits 381system.cpu.icache.demand_hits::cpu.inst 78126184 # number of demand (read+write) hits 382system.cpu.icache.demand_hits::total 78126184 # number of demand (read+write) hits 383system.cpu.icache.overall_hits::cpu.inst 78126184 # number of overall hits 384system.cpu.icache.overall_hits::total 78126184 # number of overall hits 385system.cpu.icache.ReadReq_misses::cpu.inst 18908 # number of ReadReq misses 386system.cpu.icache.ReadReq_misses::total 18908 # number of ReadReq misses 387system.cpu.icache.demand_misses::cpu.inst 18908 # number of demand (read+write) misses 388system.cpu.icache.demand_misses::total 18908 # number of demand (read+write) misses 389system.cpu.icache.overall_misses::cpu.inst 18908 # number of overall misses 390system.cpu.icache.overall_misses::total 18908 # number of overall misses 391system.cpu.icache.ReadReq_miss_latency::cpu.inst 426200500 # number of ReadReq miss cycles 392system.cpu.icache.ReadReq_miss_latency::total 426200500 # number of ReadReq miss cycles 393system.cpu.icache.demand_miss_latency::cpu.inst 426200500 # number of demand (read+write) miss cycles 394system.cpu.icache.demand_miss_latency::total 426200500 # number of demand (read+write) miss cycles 395system.cpu.icache.overall_miss_latency::cpu.inst 426200500 # number of overall miss cycles 396system.cpu.icache.overall_miss_latency::total 426200500 # number of overall miss cycles 397system.cpu.icache.ReadReq_accesses::cpu.inst 78145092 # number of ReadReq accesses(hits+misses) 398system.cpu.icache.ReadReq_accesses::total 78145092 # number of ReadReq accesses(hits+misses) 399system.cpu.icache.demand_accesses::cpu.inst 78145092 # number of demand (read+write) accesses 400system.cpu.icache.demand_accesses::total 78145092 # number of demand (read+write) accesses 401system.cpu.icache.overall_accesses::cpu.inst 78145092 # number of overall (read+write) accesses 402system.cpu.icache.overall_accesses::total 78145092 # number of overall (read+write) accesses 403system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000242 # miss rate for ReadReq accesses 404system.cpu.icache.ReadReq_miss_rate::total 0.000242 # miss rate for ReadReq accesses 405system.cpu.icache.demand_miss_rate::cpu.inst 0.000242 # miss rate for demand accesses 406system.cpu.icache.demand_miss_rate::total 0.000242 # miss rate for demand accesses 407system.cpu.icache.overall_miss_rate::cpu.inst 0.000242 # miss rate for overall accesses 408system.cpu.icache.overall_miss_rate::total 0.000242 # miss rate for overall accesses 409system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22540.749947 # average ReadReq miss latency 410system.cpu.icache.ReadReq_avg_miss_latency::total 22540.749947 # average ReadReq miss latency 411system.cpu.icache.demand_avg_miss_latency::cpu.inst 22540.749947 # average overall miss latency 412system.cpu.icache.demand_avg_miss_latency::total 22540.749947 # average overall miss latency 413system.cpu.icache.overall_avg_miss_latency::cpu.inst 22540.749947 # average overall miss latency 414system.cpu.icache.overall_avg_miss_latency::total 22540.749947 # average overall miss latency 415system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 416system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 417system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 418system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 419system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 420system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 421system.cpu.icache.writebacks::writebacks 16890 # number of writebacks 422system.cpu.icache.writebacks::total 16890 # number of writebacks 423system.cpu.icache.ReadReq_mshr_misses::cpu.inst 18908 # number of ReadReq MSHR misses 424system.cpu.icache.ReadReq_mshr_misses::total 18908 # number of ReadReq MSHR misses 425system.cpu.icache.demand_mshr_misses::cpu.inst 18908 # number of demand (read+write) MSHR misses 426system.cpu.icache.demand_mshr_misses::total 18908 # number of demand (read+write) MSHR misses 427system.cpu.icache.overall_mshr_misses::cpu.inst 18908 # number of overall MSHR misses 428system.cpu.icache.overall_mshr_misses::total 18908 # number of overall MSHR misses 429system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 407292500 # number of ReadReq MSHR miss cycles 430system.cpu.icache.ReadReq_mshr_miss_latency::total 407292500 # number of ReadReq MSHR miss cycles 431system.cpu.icache.demand_mshr_miss_latency::cpu.inst 407292500 # number of demand (read+write) MSHR miss cycles 432system.cpu.icache.demand_mshr_miss_latency::total 407292500 # number of demand (read+write) MSHR miss cycles 433system.cpu.icache.overall_mshr_miss_latency::cpu.inst 407292500 # number of overall MSHR miss cycles 434system.cpu.icache.overall_mshr_miss_latency::total 407292500 # number of overall MSHR miss cycles 435system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for ReadReq accesses 436system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000242 # mshr miss rate for ReadReq accesses 437system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for demand accesses 438system.cpu.icache.demand_mshr_miss_rate::total 0.000242 # mshr miss rate for demand accesses 439system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for overall accesses 440system.cpu.icache.overall_mshr_miss_rate::total 0.000242 # mshr miss rate for overall accesses 441system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21540.749947 # average ReadReq mshr miss latency 442system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21540.749947 # average ReadReq mshr miss latency 443system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21540.749947 # average overall mshr miss latency 444system.cpu.icache.demand_avg_mshr_miss_latency::total 21540.749947 # average overall mshr miss latency 445system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21540.749947 # average overall mshr miss latency 446system.cpu.icache.overall_avg_mshr_miss_latency::total 21540.749947 # average overall mshr miss latency 447system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 128076834500 # Cumulative time (in ticks) in various power states 448system.cpu.l2cache.tags.replacements 95333 # number of replacements 449system.cpu.l2cache.tags.tagsinuse 30336.891531 # Cycle average of tags in use 450system.cpu.l2cache.tags.total_refs 114380 # Total number of references to valid blocks. 451system.cpu.l2cache.tags.sampled_refs 126455 # Sample count of references to valid blocks. 452system.cpu.l2cache.tags.avg_refs 0.904511 # Average number of references to valid blocks. 453system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 454system.cpu.l2cache.tags.occ_blocks::writebacks 27758.605525 # Average occupied blocks per requestor 455system.cpu.l2cache.tags.occ_blocks::cpu.inst 1088.258663 # Average occupied blocks per requestor 456system.cpu.l2cache.tags.occ_blocks::cpu.data 1490.027343 # Average occupied blocks per requestor 457system.cpu.l2cache.tags.occ_percent::writebacks 0.847125 # Average percentage of cache occupancy 458system.cpu.l2cache.tags.occ_percent::cpu.inst 0.033211 # Average percentage of cache occupancy 459system.cpu.l2cache.tags.occ_percent::cpu.data 0.045472 # Average percentage of cache occupancy 460system.cpu.l2cache.tags.occ_percent::total 0.925808 # Average percentage of cache occupancy 461system.cpu.l2cache.tags.occ_task_id_blocks::1024 31122 # Occupied blocks per task id 462system.cpu.l2cache.tags.age_task_id_blocks_1024::0 156 # Occupied blocks per task id 463system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1225 # Occupied blocks per task id 464system.cpu.l2cache.tags.age_task_id_blocks_1024::2 13921 # Occupied blocks per task id 465system.cpu.l2cache.tags.age_task_id_blocks_1024::3 15196 # Occupied blocks per task id 466system.cpu.l2cache.tags.age_task_id_blocks_1024::4 624 # Occupied blocks per task id 467system.cpu.l2cache.tags.occ_task_id_percent::1024 0.949768 # Percentage of cache occupancy per task id 468system.cpu.l2cache.tags.tag_accesses 3017503 # Number of tag accesses 469system.cpu.l2cache.tags.data_accesses 3017503 # Number of data accesses 470system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 128076834500 # Cumulative time (in ticks) in various power states 471system.cpu.l2cache.WritebackDirty_hits::writebacks 128175 # number of WritebackDirty hits 472system.cpu.l2cache.WritebackDirty_hits::total 128175 # number of WritebackDirty hits 473system.cpu.l2cache.WritebackClean_hits::writebacks 15790 # number of WritebackClean hits 474system.cpu.l2cache.WritebackClean_hits::total 15790 # number of WritebackClean hits 475system.cpu.l2cache.ReadExReq_hits::cpu.data 4751 # number of ReadExReq hits 476system.cpu.l2cache.ReadExReq_hits::total 4751 # number of ReadExReq hits 477system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 15265 # number of ReadCleanReq hits 478system.cpu.l2cache.ReadCleanReq_hits::total 15265 # number of ReadCleanReq hits 479system.cpu.l2cache.ReadSharedReq_hits::cpu.data 31415 # number of ReadSharedReq hits 480system.cpu.l2cache.ReadSharedReq_hits::total 31415 # number of ReadSharedReq hits 481system.cpu.l2cache.demand_hits::cpu.inst 15265 # number of demand (read+write) hits 482system.cpu.l2cache.demand_hits::cpu.data 36166 # number of demand (read+write) hits 483system.cpu.l2cache.demand_hits::total 51431 # number of demand (read+write) hits 484system.cpu.l2cache.overall_hits::cpu.inst 15265 # number of overall hits 485system.cpu.l2cache.overall_hits::cpu.data 36166 # number of overall hits 486system.cpu.l2cache.overall_hits::total 51431 # number of overall hits 487system.cpu.l2cache.ReadExReq_misses::cpu.data 102281 # number of ReadExReq misses 488system.cpu.l2cache.ReadExReq_misses::total 102281 # number of ReadExReq misses 489system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3643 # number of ReadCleanReq misses 490system.cpu.l2cache.ReadCleanReq_misses::total 3643 # number of ReadCleanReq misses 491system.cpu.l2cache.ReadSharedReq_misses::cpu.data 21551 # number of ReadSharedReq misses 492system.cpu.l2cache.ReadSharedReq_misses::total 21551 # number of ReadSharedReq misses 493system.cpu.l2cache.demand_misses::cpu.inst 3643 # number of demand (read+write) misses 494system.cpu.l2cache.demand_misses::cpu.data 123832 # number of demand (read+write) misses 495system.cpu.l2cache.demand_misses::total 127475 # number of demand (read+write) misses 496system.cpu.l2cache.overall_misses::cpu.inst 3643 # number of overall misses 497system.cpu.l2cache.overall_misses::cpu.data 123832 # number of overall misses 498system.cpu.l2cache.overall_misses::total 127475 # number of overall misses 499system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6087670500 # number of ReadExReq miss cycles 500system.cpu.l2cache.ReadExReq_miss_latency::total 6087670500 # number of ReadExReq miss cycles 501system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 217265500 # number of ReadCleanReq miss cycles 502system.cpu.l2cache.ReadCleanReq_miss_latency::total 217265500 # number of ReadCleanReq miss cycles 503system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1284434000 # number of ReadSharedReq miss cycles 504system.cpu.l2cache.ReadSharedReq_miss_latency::total 1284434000 # number of ReadSharedReq miss cycles 505system.cpu.l2cache.demand_miss_latency::cpu.inst 217265500 # number of demand (read+write) miss cycles 506system.cpu.l2cache.demand_miss_latency::cpu.data 7372104500 # number of demand (read+write) miss cycles 507system.cpu.l2cache.demand_miss_latency::total 7589370000 # number of demand (read+write) miss cycles 508system.cpu.l2cache.overall_miss_latency::cpu.inst 217265500 # number of overall miss cycles 509system.cpu.l2cache.overall_miss_latency::cpu.data 7372104500 # number of overall miss cycles 510system.cpu.l2cache.overall_miss_latency::total 7589370000 # number of overall miss cycles 511system.cpu.l2cache.WritebackDirty_accesses::writebacks 128175 # number of WritebackDirty accesses(hits+misses) 512system.cpu.l2cache.WritebackDirty_accesses::total 128175 # number of WritebackDirty accesses(hits+misses) 513system.cpu.l2cache.WritebackClean_accesses::writebacks 15790 # number of WritebackClean accesses(hits+misses) 514system.cpu.l2cache.WritebackClean_accesses::total 15790 # number of WritebackClean accesses(hits+misses) 515system.cpu.l2cache.ReadExReq_accesses::cpu.data 107032 # number of ReadExReq accesses(hits+misses) 516system.cpu.l2cache.ReadExReq_accesses::total 107032 # number of ReadExReq accesses(hits+misses) 517system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 18908 # number of ReadCleanReq accesses(hits+misses) 518system.cpu.l2cache.ReadCleanReq_accesses::total 18908 # number of ReadCleanReq accesses(hits+misses) 519system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 52966 # number of ReadSharedReq accesses(hits+misses) 520system.cpu.l2cache.ReadSharedReq_accesses::total 52966 # number of ReadSharedReq accesses(hits+misses) 521system.cpu.l2cache.demand_accesses::cpu.inst 18908 # number of demand (read+write) accesses 522system.cpu.l2cache.demand_accesses::cpu.data 159998 # number of demand (read+write) accesses 523system.cpu.l2cache.demand_accesses::total 178906 # number of demand (read+write) accesses 524system.cpu.l2cache.overall_accesses::cpu.inst 18908 # number of overall (read+write) accesses 525system.cpu.l2cache.overall_accesses::cpu.data 159998 # number of overall (read+write) accesses 526system.cpu.l2cache.overall_accesses::total 178906 # number of overall (read+write) accesses 527system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.955611 # miss rate for ReadExReq accesses 528system.cpu.l2cache.ReadExReq_miss_rate::total 0.955611 # miss rate for ReadExReq accesses 529system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.192670 # miss rate for ReadCleanReq accesses 530system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.192670 # miss rate for ReadCleanReq accesses 531system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.406884 # miss rate for ReadSharedReq accesses 532system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.406884 # miss rate for ReadSharedReq accesses 533system.cpu.l2cache.demand_miss_rate::cpu.inst 0.192670 # miss rate for demand accesses 534system.cpu.l2cache.demand_miss_rate::cpu.data 0.773960 # miss rate for demand accesses 535system.cpu.l2cache.demand_miss_rate::total 0.712525 # miss rate for demand accesses 536system.cpu.l2cache.overall_miss_rate::cpu.inst 0.192670 # miss rate for overall accesses 537system.cpu.l2cache.overall_miss_rate::cpu.data 0.773960 # miss rate for overall accesses 538system.cpu.l2cache.overall_miss_rate::total 0.712525 # miss rate for overall accesses 539system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59519.074901 # average ReadExReq miss latency 540system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59519.074901 # average ReadExReq miss latency 541system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59639.171013 # average ReadCleanReq miss latency 542system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59639.171013 # average ReadCleanReq miss latency 543system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59599.740151 # average ReadSharedReq miss latency 544system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59599.740151 # average ReadSharedReq miss latency 545system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59639.171013 # average overall miss latency 546system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59533.113412 # average overall miss latency 547system.cpu.l2cache.demand_avg_miss_latency::total 59536.144342 # average overall miss latency 548system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59639.171013 # average overall miss latency 549system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59533.113412 # average overall miss latency 550system.cpu.l2cache.overall_avg_miss_latency::total 59536.144342 # average overall miss latency 551system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 552system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 553system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 554system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 555system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 556system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 557system.cpu.l2cache.writebacks::writebacks 86150 # number of writebacks 558system.cpu.l2cache.writebacks::total 86150 # number of writebacks 559system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 104 # number of CleanEvict MSHR misses 560system.cpu.l2cache.CleanEvict_mshr_misses::total 104 # number of CleanEvict MSHR misses 561system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102281 # number of ReadExReq MSHR misses 562system.cpu.l2cache.ReadExReq_mshr_misses::total 102281 # number of ReadExReq MSHR misses 563system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3643 # number of ReadCleanReq MSHR misses 564system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3643 # number of ReadCleanReq MSHR misses 565system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 21551 # number of ReadSharedReq MSHR misses 566system.cpu.l2cache.ReadSharedReq_mshr_misses::total 21551 # number of ReadSharedReq MSHR misses 567system.cpu.l2cache.demand_mshr_misses::cpu.inst 3643 # number of demand (read+write) MSHR misses 568system.cpu.l2cache.demand_mshr_misses::cpu.data 123832 # number of demand (read+write) MSHR misses 569system.cpu.l2cache.demand_mshr_misses::total 127475 # number of demand (read+write) MSHR misses 570system.cpu.l2cache.overall_mshr_misses::cpu.inst 3643 # number of overall MSHR misses 571system.cpu.l2cache.overall_mshr_misses::cpu.data 123832 # number of overall MSHR misses 572system.cpu.l2cache.overall_mshr_misses::total 127475 # number of overall MSHR misses 573system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5064860500 # number of ReadExReq MSHR miss cycles 574system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5064860500 # number of ReadExReq MSHR miss cycles 575system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 180835500 # number of ReadCleanReq MSHR miss cycles 576system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 180835500 # number of ReadCleanReq MSHR miss cycles 577system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1068924000 # number of ReadSharedReq MSHR miss cycles 578system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1068924000 # number of ReadSharedReq MSHR miss cycles 579system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 180835500 # number of demand (read+write) MSHR miss cycles 580system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6133784500 # number of demand (read+write) MSHR miss cycles 581system.cpu.l2cache.demand_mshr_miss_latency::total 6314620000 # number of demand (read+write) MSHR miss cycles 582system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 180835500 # number of overall MSHR miss cycles 583system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6133784500 # number of overall MSHR miss cycles 584system.cpu.l2cache.overall_mshr_miss_latency::total 6314620000 # number of overall MSHR miss cycles 585system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 586system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 587system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955611 # mshr miss rate for ReadExReq accesses 588system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955611 # mshr miss rate for ReadExReq accesses 589system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.192670 # mshr miss rate for ReadCleanReq accesses 590system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.192670 # mshr miss rate for ReadCleanReq accesses 591system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.406884 # mshr miss rate for ReadSharedReq accesses 592system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.406884 # mshr miss rate for ReadSharedReq accesses 593system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.192670 # mshr miss rate for demand accesses 594system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.773960 # mshr miss rate for demand accesses 595system.cpu.l2cache.demand_mshr_miss_rate::total 0.712525 # mshr miss rate for demand accesses 596system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.192670 # mshr miss rate for overall accesses 597system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.773960 # mshr miss rate for overall accesses 598system.cpu.l2cache.overall_mshr_miss_rate::total 0.712525 # mshr miss rate for overall accesses 599system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49519.074901 # average ReadExReq mshr miss latency 600system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49519.074901 # average ReadExReq mshr miss latency 601system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49639.171013 # average ReadCleanReq mshr miss latency 602system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49639.171013 # average ReadCleanReq mshr miss latency 603system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49599.740151 # average ReadSharedReq mshr miss latency 604system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49599.740151 # average ReadSharedReq mshr miss latency 605system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49639.171013 # average overall mshr miss latency 606system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49533.113412 # average overall mshr miss latency 607system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49536.144342 # average overall mshr miss latency 608system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49639.171013 # average overall mshr miss latency 609system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49533.113412 # average overall mshr miss latency 610system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49536.144342 # average overall mshr miss latency 611system.cpu.toL2Bus.snoop_filter.tot_requests 351698 # Total number of requests made to the snoop filter. 612system.cpu.toL2Bus.snoop_filter.hit_single_requests 172817 # Number of requests hitting in the snoop filter with a single holder of the requested data. 613system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3696 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 614system.cpu.toL2Bus.snoop_filter.tot_snoops 3119 # Total number of snoops made to the snoop filter. 615system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3089 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 616system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 30 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 617system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 128076834500 # Cumulative time (in ticks) in various power states 618system.cpu.toL2Bus.trans_dist::ReadResp 71874 # Transaction distribution 619system.cpu.toL2Bus.trans_dist::WritebackDirty 214325 # Transaction distribution 620system.cpu.toL2Bus.trans_dist::WritebackClean 16890 # Transaction distribution 621system.cpu.toL2Bus.trans_dist::CleanEvict 36910 # Transaction distribution 622system.cpu.toL2Bus.trans_dist::ReadExReq 107032 # Transaction distribution 623system.cpu.toL2Bus.trans_dist::ReadExResp 107032 # Transaction distribution 624system.cpu.toL2Bus.trans_dist::ReadCleanReq 18908 # Transaction distribution 625system.cpu.toL2Bus.trans_dist::ReadSharedReq 52966 # Transaction distribution 626system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 54706 # Packet count per connected master and slave (bytes) 627system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 475898 # Packet count per connected master and slave (bytes) 628system.cpu.toL2Bus.pkt_count::total 530604 # Packet count per connected master and slave (bytes) 629system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2291072 # Cumulative packet size per connected master and slave (bytes) 630system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18443072 # Cumulative packet size per connected master and slave (bytes) 631system.cpu.toL2Bus.pkt_size::total 20734144 # Cumulative packet size per connected master and slave (bytes) 632system.cpu.toL2Bus.snoops 95333 # Total snoops (count) 633system.cpu.toL2Bus.snoopTraffic 5513600 # Total snoop traffic (bytes) 634system.cpu.toL2Bus.snoop_fanout::samples 274239 # Request fanout histogram 635system.cpu.toL2Bus.snoop_fanout::mean 0.025051 # Request fanout histogram 636system.cpu.toL2Bus.snoop_fanout::stdev 0.156979 # Request fanout histogram 637system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 638system.cpu.toL2Bus.snoop_fanout::0 267399 97.51% 97.51% # Request fanout histogram 639system.cpu.toL2Bus.snoop_fanout::1 6810 2.48% 99.99% # Request fanout histogram 640system.cpu.toL2Bus.snoop_fanout::2 30 0.01% 100.00% # Request fanout histogram 641system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 642system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 643system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 644system.cpu.toL2Bus.snoop_fanout::total 274239 # Request fanout histogram 645system.cpu.toL2Bus.reqLayer0.occupancy 320914000 # Layer occupancy (ticks) 646system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) 647system.cpu.toL2Bus.respLayer0.occupancy 28362000 # Layer occupancy (ticks) 648system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 649system.cpu.toL2Bus.respLayer1.occupancy 239997000 # Layer occupancy (ticks) 650system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) 651system.membus.pwrStateResidencyTicks::UNDEFINED 128076834500 # Cumulative time (in ticks) in various power states 652system.membus.trans_dist::ReadResp 25194 # Transaction distribution 653system.membus.trans_dist::WritebackDirty 86150 # Transaction distribution 654system.membus.trans_dist::CleanEvict 6168 # Transaction distribution 655system.membus.trans_dist::ReadExReq 102281 # Transaction distribution 656system.membus.trans_dist::ReadExResp 102281 # Transaction distribution 657system.membus.trans_dist::ReadSharedReq 25194 # Transaction distribution 658system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 347268 # Packet count per connected master and slave (bytes) 659system.membus.pkt_count::total 347268 # Packet count per connected master and slave (bytes) 660system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13672000 # Cumulative packet size per connected master and slave (bytes) 661system.membus.pkt_size::total 13672000 # Cumulative packet size per connected master and slave (bytes) 662system.membus.snoops 0 # Total snoops (count) 663system.membus.snoopTraffic 0 # Total snoop traffic (bytes) 664system.membus.snoop_fanout::samples 219817 # Request fanout histogram 665system.membus.snoop_fanout::mean 0 # Request fanout histogram 666system.membus.snoop_fanout::stdev 0 # Request fanout histogram 667system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 668system.membus.snoop_fanout::0 219817 100.00% 100.00% # Request fanout histogram 669system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 670system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 671system.membus.snoop_fanout::min_value 0 # Request fanout histogram 672system.membus.snoop_fanout::max_value 0 # Request fanout histogram 673system.membus.snoop_fanout::total 219817 # Request fanout histogram 674system.membus.reqLayer0.occupancy 568080092 # Layer occupancy (ticks) 675system.membus.reqLayer0.utilization 0.4 # Layer utilization (%) 676system.membus.respLayer1.occupancy 637375000 # Layer occupancy (ticks) 677system.membus.respLayer1.utilization 0.5 # Layer utilization (%) 678 679---------- End Simulation Statistics ---------- 680