xref: /gem5/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.000263                       # Number of seconds simulated
sim_ticks                                   262793500                       # Number of ticks simulated
final_tick                                  262793500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                1490059                       # Simulator instruction rate (inst/s)
host_op_rate                                  1490014                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                              590046557                       # Simulator tick rate (ticks/s)
host_mem_usage                                 244196                       # Number of bytes of host memory used
host_seconds                                     0.45                       # Real time elapsed on the host
sim_insts                                      663601                       # Number of instructions simulated
sim_ops                                        663601                       # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu0.inst            18240                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data            10560                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst             3776                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data             1408                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.inst              128                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.data              960                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu3.inst              512                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu3.data             1024                       # Number of bytes read from this memory
system.physmem.bytes_read::total                36608                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst        18240                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst         3776                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu2.inst          128                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu3.inst          512                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total           22656                       # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu0.inst               285                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data               165                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst                59                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data                22                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.inst                 2                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.data                15                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3.inst                 8                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3.data                16                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                   572                       # Number of read requests responded to by this memory
system.physmem.bw_read::cpu0.inst            69408109                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data            40183642                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst            14368696                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data             5357819                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.inst              487074                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.data             3653058                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu3.inst             1948298                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu3.data             3896596                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total               139303293                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst       69408109                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst       14368696                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu2.inst         487074                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu3.inst        1948298                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total           86212178                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst           69408109                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data           40183642                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst           14368696                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data            5357819                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.inst             487074                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.data            3653058                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3.inst            1948298                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3.data            3896596                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total              139303293                       # Total bandwidth to/from this memory (bytes/s)
system.membus.throughput                    139303293                       # Throughput (bytes/s)
system.membus.trans_dist::ReadReq                 430                       # Transaction distribution
system.membus.trans_dist::ReadResp                430                       # Transaction distribution
system.membus.trans_dist::UpgradeReq              272                       # Transaction distribution
system.membus.trans_dist::UpgradeResp              77                       # Transaction distribution
system.membus.trans_dist::ReadExReq               208                       # Transaction distribution
system.membus.trans_dist::ReadExResp              142                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side         1559                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count                          1559                       # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side        36608                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size                      36608                       # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus                  36608                       # Total data (bytes)
system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
system.membus.reqLayer0.occupancy              855296                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.3                       # Layer utilization (%)
system.membus.respLayer0.occupancy            5423500                       # Layer occupancy (ticks)
system.membus.respLayer0.utilization              2.1                       # Layer utilization (%)
system.toL2Bus.throughput                   646591335                       # Throughput (bytes/s)
system.toL2Bus.trans_dist::ReadReq               2225                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp              2225                       # Transaction distribution
system.toL2Bus.trans_dist::Writeback                1                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq             274                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp            274                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq              429                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp             429                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side          934                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side          580                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.icache.mem_side          732                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side          388                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu2.icache.mem_side          732                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side          359                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu3.icache.mem_side          734                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side          361                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count                         4820                       # Packet count per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side        29888                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side        10944                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side        23424                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side         1664                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu2.icache.mem_side        23424                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu2.dcache.mem_side         1600                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu3.icache.mem_side        23488                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu3.dcache.mem_side         1600                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size                    116032                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.data_through_bus                116032                       # Total data (bytes)
system.toL2Bus.snoop_data_through_bus           53888                       # Total snoop data (bytes)
system.toL2Bus.reqLayer0.occupancy            1474488                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.6                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy           2101500                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.8                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy           1430481                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.5                       # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy           1650489                       # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization             0.6                       # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy           1281961                       # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization             0.5                       # Layer utilization (%)
system.toL2Bus.respLayer4.occupancy           1651987                       # Layer occupancy (ticks)
system.toL2Bus.respLayer4.utilization             0.6                       # Layer utilization (%)
system.toL2Bus.respLayer5.occupancy           1173486                       # Layer occupancy (ticks)
system.toL2Bus.respLayer5.utilization             0.4                       # Layer utilization (%)
system.toL2Bus.respLayer6.occupancy           1651999                       # Layer occupancy (ticks)
system.toL2Bus.respLayer6.utilization             0.6                       # Layer utilization (%)
system.toL2Bus.respLayer7.occupancy           1177490                       # Layer occupancy (ticks)
system.toL2Bus.respLayer7.utilization             0.4                       # Layer utilization (%)
system.cpu0.workload.num_syscalls                  89                       # Number of system calls
system.cpu0.numCycles                          525587                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.committedInsts                     158574                       # Number of instructions committed
system.cpu0.committedOps                       158574                       # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses               109208                       # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses                     0                       # Number of float alu accesses
system.cpu0.num_func_calls                        390                       # number of times a function call or return occured
system.cpu0.num_conditional_control_insts        26032                       # number of instructions that are conditional controls
system.cpu0.num_int_insts                      109208                       # number of integer instructions
system.cpu0.num_fp_insts                            0                       # number of float instructions
system.cpu0.num_int_register_reads             315782                       # number of times the integer registers were read
system.cpu0.num_int_register_writes            110814                       # number of times the integer registers were written
system.cpu0.num_fp_register_reads                   0                       # number of times the floating registers were read
system.cpu0.num_fp_register_writes                  0                       # number of times the floating registers were written
system.cpu0.num_mem_refs                        74021                       # number of memory refs
system.cpu0.num_load_insts                      49007                       # Number of load instructions
system.cpu0.num_store_insts                     25014                       # Number of store instructions
system.cpu0.num_idle_cycles                         0                       # Number of idle cycles
system.cpu0.num_busy_cycles                    525587                       # Number of busy cycles
system.cpu0.not_idle_fraction                       1                       # Percentage of non-idle cycles
system.cpu0.idle_fraction                           0                       # Percentage of idle cycles
system.cpu0.icache.replacements                   215                       # number of replacements
system.cpu0.icache.tagsinuse               212.401760                       # Cycle average of tags in use
system.cpu0.icache.total_refs                  158170                       # Total number of references to valid blocks.
system.cpu0.icache.sampled_refs                   467                       # Sample count of references to valid blocks.
system.cpu0.icache.avg_refs                338.693790                       # Average number of references to valid blocks.
system.cpu0.icache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.occ_blocks::cpu0.inst   212.401760                       # Average occupied blocks per requestor
system.cpu0.icache.occ_percent::cpu0.inst     0.414847                       # Average percentage of cache occupancy
system.cpu0.icache.occ_percent::total        0.414847                       # Average percentage of cache occupancy
system.cpu0.icache.ReadReq_hits::cpu0.inst       158170                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total         158170                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst       158170                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total          158170                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst       158170                       # number of overall hits
system.cpu0.icache.overall_hits::total         158170                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst          467                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total          467                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst          467                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total           467                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst          467                       # number of overall misses
system.cpu0.icache.overall_misses::total          467                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst     18147500                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total     18147500                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst     18147500                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total     18147500                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst     18147500                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total     18147500                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst       158637                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total       158637                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst       158637                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total       158637                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst       158637                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total       158637                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.002944                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.002944                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.002944                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.002944                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.002944                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.002944                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 38859.743041                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 38859.743041                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 38859.743041                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 38859.743041                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 38859.743041                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 38859.743041                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst          467                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total          467                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst          467                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total          467                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst          467                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total          467                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst     17213500                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total     17213500                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst     17213500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total     17213500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst     17213500                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total     17213500                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.002944                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.002944                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.002944                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.002944                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.002944                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.002944                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 36859.743041                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 36859.743041                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 36859.743041                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 36859.743041                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 36859.743041                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 36859.743041                       # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.dcache.replacements                     2                       # number of replacements
system.cpu0.dcache.tagsinuse               145.572033                       # Cycle average of tags in use
system.cpu0.dcache.total_refs                   73489                       # Total number of references to valid blocks.
system.cpu0.dcache.sampled_refs                   167                       # Sample count of references to valid blocks.
system.cpu0.dcache.avg_refs                440.053892                       # Average number of references to valid blocks.
system.cpu0.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.occ_blocks::cpu0.data   145.572033                       # Average occupied blocks per requestor
system.cpu0.dcache.occ_percent::cpu0.data     0.284320                       # Average percentage of cache occupancy
system.cpu0.dcache.occ_percent::total        0.284320                       # Average percentage of cache occupancy
system.cpu0.dcache.ReadReq_hits::cpu0.data        48827                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total          48827                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data        24780                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total         24780                       # number of WriteReq hits
system.cpu0.dcache.SwapReq_hits::cpu0.data           16                       # number of SwapReq hits
system.cpu0.dcache.SwapReq_hits::total             16                       # number of SwapReq hits
system.cpu0.dcache.demand_hits::cpu0.data        73607                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total           73607                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data        73607                       # number of overall hits
system.cpu0.dcache.overall_hits::total          73607                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data          170                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total          170                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data          183                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total          183                       # number of WriteReq misses
system.cpu0.dcache.SwapReq_misses::cpu0.data           26                       # number of SwapReq misses
system.cpu0.dcache.SwapReq_misses::total           26                       # number of SwapReq misses
system.cpu0.dcache.demand_misses::cpu0.data          353                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total           353                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data          353                       # number of overall misses
system.cpu0.dcache.overall_misses::total          353                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data      4582500                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total      4582500                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data      6978000                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total      6978000                       # number of WriteReq miss cycles
system.cpu0.dcache.SwapReq_miss_latency::cpu0.data       360500                       # number of SwapReq miss cycles
system.cpu0.dcache.SwapReq_miss_latency::total       360500                       # number of SwapReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data     11560500                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total     11560500                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data     11560500                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total     11560500                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data        48997                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total        48997                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data        24963                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total        24963                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SwapReq_accesses::cpu0.data           42                       # number of SwapReq accesses(hits+misses)
system.cpu0.dcache.SwapReq_accesses::total           42                       # number of SwapReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data        73960                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total        73960                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data        73960                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total        73960                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.003470                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.003470                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.007331                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.007331                       # miss rate for WriteReq accesses
system.cpu0.dcache.SwapReq_miss_rate::cpu0.data     0.619048                       # miss rate for SwapReq accesses
system.cpu0.dcache.SwapReq_miss_rate::total     0.619048                       # miss rate for SwapReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.004773                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.004773                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.004773                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.004773                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 26955.882353                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 26955.882353                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38131.147541                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 38131.147541                       # average WriteReq miss latency
system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 13865.384615                       # average SwapReq miss latency
system.cpu0.dcache.SwapReq_avg_miss_latency::total 13865.384615                       # average SwapReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 32749.291785                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 32749.291785                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 32749.291785                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 32749.291785                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks            1                       # number of writebacks
system.cpu0.dcache.writebacks::total                1                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data          170                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total          170                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data          183                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total          183                       # number of WriteReq MSHR misses
system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data           26                       # number of SwapReq MSHR misses
system.cpu0.dcache.SwapReq_mshr_misses::total           26                       # number of SwapReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data          353                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total          353                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data          353                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total          353                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data      4237519                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total      4237519                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data      6612000                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total      6612000                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data       308500                       # number of SwapReq MSHR miss cycles
system.cpu0.dcache.SwapReq_mshr_miss_latency::total       308500                       # number of SwapReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data     10849519                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total     10849519                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data     10849519                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total     10849519                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.003470                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.003470                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.007331                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.007331                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data     0.619048                       # mshr miss rate for SwapReq accesses
system.cpu0.dcache.SwapReq_mshr_miss_rate::total     0.619048                       # mshr miss rate for SwapReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.004773                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.004773                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.004773                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.004773                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 24926.582353                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 24926.582353                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36131.147541                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36131.147541                       # average WriteReq mshr miss latency
system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 11865.384615                       # average SwapReq mshr miss latency
system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 11865.384615                       # average SwapReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 30735.181303                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 30735.181303                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 30735.181303                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 30735.181303                       # average overall mshr miss latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.numCycles                          525587                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.committedInsts                     173389                       # Number of instructions committed
system.cpu1.committedOps                       173389                       # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses               107707                       # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses                     0                       # Number of float alu accesses
system.cpu1.num_func_calls                        637                       # number of times a function call or return occured
system.cpu1.num_conditional_control_insts        36848                       # number of instructions that are conditional controls
system.cpu1.num_int_insts                      107707                       # number of integer instructions
system.cpu1.num_fp_insts                            0                       # number of float instructions
system.cpu1.num_int_register_reads             245634                       # number of times the integer registers were read
system.cpu1.num_int_register_writes             91167                       # number of times the integer registers were written
system.cpu1.num_fp_register_reads                   0                       # number of times the floating registers were read
system.cpu1.num_fp_register_writes                  0                       # number of times the floating registers were written
system.cpu1.num_mem_refs                        47028                       # number of memory refs
system.cpu1.num_load_insts                      39502                       # Number of load instructions
system.cpu1.num_store_insts                      7526                       # Number of store instructions
system.cpu1.num_idle_cycles              69346.001736                       # Number of idle cycles
system.cpu1.num_busy_cycles              456240.998264                       # Number of busy cycles
system.cpu1.not_idle_fraction                0.868060                       # Percentage of non-idle cycles
system.cpu1.idle_fraction                    0.131940                       # Percentage of idle cycles
system.cpu1.icache.replacements                   280                       # number of replacements
system.cpu1.icache.tagsinuse                70.017443                       # Cycle average of tags in use
system.cpu1.icache.total_refs                  173056                       # Total number of references to valid blocks.
system.cpu1.icache.sampled_refs                   366                       # Sample count of references to valid blocks.
system.cpu1.icache.avg_refs                472.830601                       # Average number of references to valid blocks.
system.cpu1.icache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.occ_blocks::cpu1.inst    70.017443                       # Average occupied blocks per requestor
system.cpu1.icache.occ_percent::cpu1.inst     0.136753                       # Average percentage of cache occupancy
system.cpu1.icache.occ_percent::total        0.136753                       # Average percentage of cache occupancy
system.cpu1.icache.ReadReq_hits::cpu1.inst       173056                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total         173056                       # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst       173056                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total          173056                       # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst       173056                       # number of overall hits
system.cpu1.icache.overall_hits::total         173056                       # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst          366                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total          366                       # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst          366                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total           366                       # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst          366                       # number of overall misses
system.cpu1.icache.overall_misses::total          366                       # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst      7542000                       # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total      7542000                       # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst      7542000                       # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total      7542000                       # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst      7542000                       # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total      7542000                       # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst       173422                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total       173422                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst       173422                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total       173422                       # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst       173422                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total       173422                       # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.002110                       # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total     0.002110                       # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst     0.002110                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total     0.002110                       # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst     0.002110                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total     0.002110                       # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 20606.557377                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 20606.557377                       # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 20606.557377                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 20606.557377                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 20606.557377                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 20606.557377                       # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst          366                       # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total          366                       # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst          366                       # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total          366                       # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst          366                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total          366                       # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst      6806511                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total      6806511                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst      6806511                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total      6806511                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst      6806511                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total      6806511                       # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.002110                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.002110                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.002110                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total     0.002110                       # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.002110                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total     0.002110                       # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 18597.024590                       # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 18597.024590                       # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 18597.024590                       # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total 18597.024590                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 18597.024590                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 18597.024590                       # average overall mshr miss latency
system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.dcache.replacements                     0                       # number of replacements
system.cpu1.dcache.tagsinuse                27.692937                       # Cycle average of tags in use
system.cpu1.dcache.total_refs                   17380                       # Total number of references to valid blocks.
system.cpu1.dcache.sampled_refs                    30                       # Sample count of references to valid blocks.
system.cpu1.dcache.avg_refs                579.333333                       # Average number of references to valid blocks.
system.cpu1.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.occ_blocks::cpu1.data    27.692937                       # Average occupied blocks per requestor
system.cpu1.dcache.occ_percent::cpu1.data     0.054088                       # Average percentage of cache occupancy
system.cpu1.dcache.occ_percent::total        0.054088                       # Average percentage of cache occupancy
system.cpu1.dcache.ReadReq_hits::cpu1.data        39322                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total          39322                       # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data         7334                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total          7334                       # number of WriteReq hits
system.cpu1.dcache.SwapReq_hits::cpu1.data           19                       # number of SwapReq hits
system.cpu1.dcache.SwapReq_hits::total             19                       # number of SwapReq hits
system.cpu1.dcache.demand_hits::cpu1.data        46656                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total           46656                       # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data        46656                       # number of overall hits
system.cpu1.dcache.overall_hits::total          46656                       # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data          172                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total          172                       # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data          106                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total          106                       # number of WriteReq misses
system.cpu1.dcache.SwapReq_misses::cpu1.data           65                       # number of SwapReq misses
system.cpu1.dcache.SwapReq_misses::total           65                       # number of SwapReq misses
system.cpu1.dcache.demand_misses::cpu1.data          278                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total           278                       # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data          278                       # number of overall misses
system.cpu1.dcache.overall_misses::total          278                       # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data      3331000                       # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total      3331000                       # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data      2174000                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total      2174000                       # number of WriteReq miss cycles
system.cpu1.dcache.SwapReq_miss_latency::cpu1.data       282000                       # number of SwapReq miss cycles
system.cpu1.dcache.SwapReq_miss_latency::total       282000                       # number of SwapReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data      5505000                       # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total      5505000                       # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data      5505000                       # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total      5505000                       # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data        39494                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total        39494                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data         7440                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total         7440                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.SwapReq_accesses::cpu1.data           84                       # number of SwapReq accesses(hits+misses)
system.cpu1.dcache.SwapReq_accesses::total           84                       # number of SwapReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data        46934                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total        46934                       # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data        46934                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total        46934                       # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.004355                       # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total     0.004355                       # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.014247                       # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total     0.014247                       # miss rate for WriteReq accesses
system.cpu1.dcache.SwapReq_miss_rate::cpu1.data     0.773810                       # miss rate for SwapReq accesses
system.cpu1.dcache.SwapReq_miss_rate::total     0.773810                       # miss rate for SwapReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data     0.005923                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total     0.005923                       # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data     0.005923                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total     0.005923                       # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 19366.279070                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 19366.279070                       # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 20509.433962                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 20509.433962                       # average WriteReq miss latency
system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data  4338.461538                       # average SwapReq miss latency
system.cpu1.dcache.SwapReq_avg_miss_latency::total  4338.461538                       # average SwapReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19802.158273                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 19802.158273                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 19802.158273                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 19802.158273                       # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data          172                       # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total          172                       # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data          106                       # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total          106                       # number of WriteReq MSHR misses
system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data           65                       # number of SwapReq MSHR misses
system.cpu1.dcache.SwapReq_mshr_misses::total           65                       # number of SwapReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data          278                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total          278                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data          278                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total          278                       # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data      2972539                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total      2972539                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data      1962000                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total      1962000                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data       152000                       # number of SwapReq MSHR miss cycles
system.cpu1.dcache.SwapReq_mshr_miss_latency::total       152000                       # number of SwapReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data      4934539                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total      4934539                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data      4934539                       # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total      4934539                       # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.004355                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.004355                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.014247                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.014247                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data     0.773810                       # mshr miss rate for SwapReq accesses
system.cpu1.dcache.SwapReq_mshr_miss_rate::total     0.773810                       # mshr miss rate for SwapReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.005923                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total     0.005923                       # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.005923                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total     0.005923                       # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 17282.203488                       # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 17282.203488                       # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 18509.433962                       # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 18509.433962                       # average WriteReq mshr miss latency
system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data  2338.461538                       # average SwapReq mshr miss latency
system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total  2338.461538                       # average SwapReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17750.140288                       # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17750.140288                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17750.140288                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17750.140288                       # average overall mshr miss latency
system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu2.numCycles                          525587                       # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu2.committedInsts                     164870                       # Number of instructions committed
system.cpu2.committedOps                       164870                       # Number of ops (including micro ops) committed
system.cpu2.num_int_alu_accesses               112982                       # Number of integer alu accesses
system.cpu2.num_fp_alu_accesses                     0                       # Number of float alu accesses
system.cpu2.num_func_calls                        637                       # number of times a function call or return occured
system.cpu2.num_conditional_control_insts        29953                       # number of instructions that are conditional controls
system.cpu2.num_int_insts                      112982                       # number of integer instructions
system.cpu2.num_fp_insts                            0                       # number of float instructions
system.cpu2.num_int_register_reads             294323                       # number of times the integer registers were read
system.cpu2.num_int_register_writes            112883                       # number of times the integer registers were written
system.cpu2.num_fp_register_reads                   0                       # number of times the floating registers were read
system.cpu2.num_fp_register_writes                  0                       # number of times the floating registers were written
system.cpu2.num_mem_refs                        59198                       # number of memory refs
system.cpu2.num_load_insts                      42166                       # Number of load instructions
system.cpu2.num_store_insts                     17032                       # Number of store instructions
system.cpu2.num_idle_cycles              69603.001735                       # Number of idle cycles
system.cpu2.num_busy_cycles              455983.998265                       # Number of busy cycles
system.cpu2.not_idle_fraction                0.867571                       # Percentage of non-idle cycles
system.cpu2.idle_fraction                    0.132429                       # Percentage of idle cycles
system.cpu2.icache.replacements                   280                       # number of replacements
system.cpu2.icache.tagsinuse                67.624903                       # Cycle average of tags in use
system.cpu2.icache.total_refs                  164537                       # Total number of references to valid blocks.
system.cpu2.icache.sampled_refs                   366                       # Sample count of references to valid blocks.
system.cpu2.icache.avg_refs                449.554645                       # Average number of references to valid blocks.
system.cpu2.icache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu2.icache.occ_blocks::cpu2.inst    67.624903                       # Average occupied blocks per requestor
system.cpu2.icache.occ_percent::cpu2.inst     0.132080                       # Average percentage of cache occupancy
system.cpu2.icache.occ_percent::total        0.132080                       # Average percentage of cache occupancy
system.cpu2.icache.ReadReq_hits::cpu2.inst       164537                       # number of ReadReq hits
system.cpu2.icache.ReadReq_hits::total         164537                       # number of ReadReq hits
system.cpu2.icache.demand_hits::cpu2.inst       164537                       # number of demand (read+write) hits
system.cpu2.icache.demand_hits::total          164537                       # number of demand (read+write) hits
system.cpu2.icache.overall_hits::cpu2.inst       164537                       # number of overall hits
system.cpu2.icache.overall_hits::total         164537                       # number of overall hits
system.cpu2.icache.ReadReq_misses::cpu2.inst          366                       # number of ReadReq misses
system.cpu2.icache.ReadReq_misses::total          366                       # number of ReadReq misses
system.cpu2.icache.demand_misses::cpu2.inst          366                       # number of demand (read+write) misses
system.cpu2.icache.demand_misses::total           366                       # number of demand (read+write) misses
system.cpu2.icache.overall_misses::cpu2.inst          366                       # number of overall misses
system.cpu2.icache.overall_misses::total          366                       # number of overall misses
system.cpu2.icache.ReadReq_miss_latency::cpu2.inst      5251500                       # number of ReadReq miss cycles
system.cpu2.icache.ReadReq_miss_latency::total      5251500                       # number of ReadReq miss cycles
system.cpu2.icache.demand_miss_latency::cpu2.inst      5251500                       # number of demand (read+write) miss cycles
system.cpu2.icache.demand_miss_latency::total      5251500                       # number of demand (read+write) miss cycles
system.cpu2.icache.overall_miss_latency::cpu2.inst      5251500                       # number of overall miss cycles
system.cpu2.icache.overall_miss_latency::total      5251500                       # number of overall miss cycles
system.cpu2.icache.ReadReq_accesses::cpu2.inst       164903                       # number of ReadReq accesses(hits+misses)
system.cpu2.icache.ReadReq_accesses::total       164903                       # number of ReadReq accesses(hits+misses)
system.cpu2.icache.demand_accesses::cpu2.inst       164903                       # number of demand (read+write) accesses
system.cpu2.icache.demand_accesses::total       164903                       # number of demand (read+write) accesses
system.cpu2.icache.overall_accesses::cpu2.inst       164903                       # number of overall (read+write) accesses
system.cpu2.icache.overall_accesses::total       164903                       # number of overall (read+write) accesses
system.cpu2.icache.ReadReq_miss_rate::cpu2.inst     0.002219                       # miss rate for ReadReq accesses
system.cpu2.icache.ReadReq_miss_rate::total     0.002219                       # miss rate for ReadReq accesses
system.cpu2.icache.demand_miss_rate::cpu2.inst     0.002219                       # miss rate for demand accesses
system.cpu2.icache.demand_miss_rate::total     0.002219                       # miss rate for demand accesses
system.cpu2.icache.overall_miss_rate::cpu2.inst     0.002219                       # miss rate for overall accesses
system.cpu2.icache.overall_miss_rate::total     0.002219                       # miss rate for overall accesses
system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 14348.360656                       # average ReadReq miss latency
system.cpu2.icache.ReadReq_avg_miss_latency::total 14348.360656                       # average ReadReq miss latency
system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 14348.360656                       # average overall miss latency
system.cpu2.icache.demand_avg_miss_latency::total 14348.360656                       # average overall miss latency
system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 14348.360656                       # average overall miss latency
system.cpu2.icache.overall_avg_miss_latency::total 14348.360656                       # average overall miss latency
system.cpu2.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu2.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu2.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu2.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu2.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu2.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu2.icache.fast_writes                      0                       # number of fast writes performed
system.cpu2.icache.cache_copies                     0                       # number of cache copies performed
system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst          366                       # number of ReadReq MSHR misses
system.cpu2.icache.ReadReq_mshr_misses::total          366                       # number of ReadReq MSHR misses
system.cpu2.icache.demand_mshr_misses::cpu2.inst          366                       # number of demand (read+write) MSHR misses
system.cpu2.icache.demand_mshr_misses::total          366                       # number of demand (read+write) MSHR misses
system.cpu2.icache.overall_mshr_misses::cpu2.inst          366                       # number of overall MSHR misses
system.cpu2.icache.overall_mshr_misses::total          366                       # number of overall MSHR misses
system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst      4514513                       # number of ReadReq MSHR miss cycles
system.cpu2.icache.ReadReq_mshr_miss_latency::total      4514513                       # number of ReadReq MSHR miss cycles
system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst      4514513                       # number of demand (read+write) MSHR miss cycles
system.cpu2.icache.demand_mshr_miss_latency::total      4514513                       # number of demand (read+write) MSHR miss cycles
system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst      4514513                       # number of overall MSHR miss cycles
system.cpu2.icache.overall_mshr_miss_latency::total      4514513                       # number of overall MSHR miss cycles
system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.002219                       # mshr miss rate for ReadReq accesses
system.cpu2.icache.ReadReq_mshr_miss_rate::total     0.002219                       # mshr miss rate for ReadReq accesses
system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst     0.002219                       # mshr miss rate for demand accesses
system.cpu2.icache.demand_mshr_miss_rate::total     0.002219                       # mshr miss rate for demand accesses
system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst     0.002219                       # mshr miss rate for overall accesses
system.cpu2.icache.overall_mshr_miss_rate::total     0.002219                       # mshr miss rate for overall accesses
system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12334.734973                       # average ReadReq mshr miss latency
system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 12334.734973                       # average ReadReq mshr miss latency
system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 12334.734973                       # average overall mshr miss latency
system.cpu2.icache.demand_avg_mshr_miss_latency::total 12334.734973                       # average overall mshr miss latency
system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 12334.734973                       # average overall mshr miss latency
system.cpu2.icache.overall_avg_mshr_miss_latency::total 12334.734973                       # average overall mshr miss latency
system.cpu2.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu2.dcache.replacements                     0                       # number of replacements
system.cpu2.dcache.tagsinuse                26.764140                       # Cycle average of tags in use
system.cpu2.dcache.total_refs                   36333                       # Total number of references to valid blocks.
system.cpu2.dcache.sampled_refs                    29                       # Sample count of references to valid blocks.
system.cpu2.dcache.avg_refs               1252.862069                       # Average number of references to valid blocks.
system.cpu2.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu2.dcache.occ_blocks::cpu2.data    26.764140                       # Average occupied blocks per requestor
system.cpu2.dcache.occ_percent::cpu2.data     0.052274                       # Average percentage of cache occupancy
system.cpu2.dcache.occ_percent::total        0.052274                       # Average percentage of cache occupancy
system.cpu2.dcache.ReadReq_hits::cpu2.data        42000                       # number of ReadReq hits
system.cpu2.dcache.ReadReq_hits::total          42000                       # number of ReadReq hits
system.cpu2.dcache.WriteReq_hits::cpu2.data        16859                       # number of WriteReq hits
system.cpu2.dcache.WriteReq_hits::total         16859                       # number of WriteReq hits
system.cpu2.dcache.SwapReq_hits::cpu2.data           10                       # number of SwapReq hits
system.cpu2.dcache.SwapReq_hits::total             10                       # number of SwapReq hits
system.cpu2.dcache.demand_hits::cpu2.data        58859                       # number of demand (read+write) hits
system.cpu2.dcache.demand_hits::total           58859                       # number of demand (read+write) hits
system.cpu2.dcache.overall_hits::cpu2.data        58859                       # number of overall hits
system.cpu2.dcache.overall_hits::total          58859                       # number of overall hits
system.cpu2.dcache.ReadReq_misses::cpu2.data          158                       # number of ReadReq misses
system.cpu2.dcache.ReadReq_misses::total          158                       # number of ReadReq misses
system.cpu2.dcache.WriteReq_misses::cpu2.data          109                       # number of WriteReq misses
system.cpu2.dcache.WriteReq_misses::total          109                       # number of WriteReq misses
system.cpu2.dcache.SwapReq_misses::cpu2.data           52                       # number of SwapReq misses
system.cpu2.dcache.SwapReq_misses::total           52                       # number of SwapReq misses
system.cpu2.dcache.demand_misses::cpu2.data          267                       # number of demand (read+write) misses
system.cpu2.dcache.demand_misses::total           267                       # number of demand (read+write) misses
system.cpu2.dcache.overall_misses::cpu2.data          267                       # number of overall misses
system.cpu2.dcache.overall_misses::total          267                       # number of overall misses
system.cpu2.dcache.ReadReq_miss_latency::cpu2.data      2136000                       # number of ReadReq miss cycles
system.cpu2.dcache.ReadReq_miss_latency::total      2136000                       # number of ReadReq miss cycles
system.cpu2.dcache.WriteReq_miss_latency::cpu2.data      1926500                       # number of WriteReq miss cycles
system.cpu2.dcache.WriteReq_miss_latency::total      1926500                       # number of WriteReq miss cycles
system.cpu2.dcache.SwapReq_miss_latency::cpu2.data       214000                       # number of SwapReq miss cycles
system.cpu2.dcache.SwapReq_miss_latency::total       214000                       # number of SwapReq miss cycles
system.cpu2.dcache.demand_miss_latency::cpu2.data      4062500                       # number of demand (read+write) miss cycles
system.cpu2.dcache.demand_miss_latency::total      4062500                       # number of demand (read+write) miss cycles
system.cpu2.dcache.overall_miss_latency::cpu2.data      4062500                       # number of overall miss cycles
system.cpu2.dcache.overall_miss_latency::total      4062500                       # number of overall miss cycles
system.cpu2.dcache.ReadReq_accesses::cpu2.data        42158                       # number of ReadReq accesses(hits+misses)
system.cpu2.dcache.ReadReq_accesses::total        42158                       # number of ReadReq accesses(hits+misses)
system.cpu2.dcache.WriteReq_accesses::cpu2.data        16968                       # number of WriteReq accesses(hits+misses)
system.cpu2.dcache.WriteReq_accesses::total        16968                       # number of WriteReq accesses(hits+misses)
system.cpu2.dcache.SwapReq_accesses::cpu2.data           62                       # number of SwapReq accesses(hits+misses)
system.cpu2.dcache.SwapReq_accesses::total           62                       # number of SwapReq accesses(hits+misses)
system.cpu2.dcache.demand_accesses::cpu2.data        59126                       # number of demand (read+write) accesses
system.cpu2.dcache.demand_accesses::total        59126                       # number of demand (read+write) accesses
system.cpu2.dcache.overall_accesses::cpu2.data        59126                       # number of overall (read+write) accesses
system.cpu2.dcache.overall_accesses::total        59126                       # number of overall (read+write) accesses
system.cpu2.dcache.ReadReq_miss_rate::cpu2.data     0.003748                       # miss rate for ReadReq accesses
system.cpu2.dcache.ReadReq_miss_rate::total     0.003748                       # miss rate for ReadReq accesses
system.cpu2.dcache.WriteReq_miss_rate::cpu2.data     0.006424                       # miss rate for WriteReq accesses
system.cpu2.dcache.WriteReq_miss_rate::total     0.006424                       # miss rate for WriteReq accesses
system.cpu2.dcache.SwapReq_miss_rate::cpu2.data     0.838710                       # miss rate for SwapReq accesses
system.cpu2.dcache.SwapReq_miss_rate::total     0.838710                       # miss rate for SwapReq accesses
system.cpu2.dcache.demand_miss_rate::cpu2.data     0.004516                       # miss rate for demand accesses
system.cpu2.dcache.demand_miss_rate::total     0.004516                       # miss rate for demand accesses
system.cpu2.dcache.overall_miss_rate::cpu2.data     0.004516                       # miss rate for overall accesses
system.cpu2.dcache.overall_miss_rate::total     0.004516                       # miss rate for overall accesses
system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 13518.987342                       # average ReadReq miss latency
system.cpu2.dcache.ReadReq_avg_miss_latency::total 13518.987342                       # average ReadReq miss latency
system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 17674.311927                       # average WriteReq miss latency
system.cpu2.dcache.WriteReq_avg_miss_latency::total 17674.311927                       # average WriteReq miss latency
system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data  4115.384615                       # average SwapReq miss latency
system.cpu2.dcache.SwapReq_avg_miss_latency::total  4115.384615                       # average SwapReq miss latency
system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 15215.355805                       # average overall miss latency
system.cpu2.dcache.demand_avg_miss_latency::total 15215.355805                       # average overall miss latency
system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 15215.355805                       # average overall miss latency
system.cpu2.dcache.overall_avg_miss_latency::total 15215.355805                       # average overall miss latency
system.cpu2.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu2.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu2.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu2.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu2.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu2.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu2.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu2.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data          158                       # number of ReadReq MSHR misses
system.cpu2.dcache.ReadReq_mshr_misses::total          158                       # number of ReadReq MSHR misses
system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data          109                       # number of WriteReq MSHR misses
system.cpu2.dcache.WriteReq_mshr_misses::total          109                       # number of WriteReq MSHR misses
system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data           52                       # number of SwapReq MSHR misses
system.cpu2.dcache.SwapReq_mshr_misses::total           52                       # number of SwapReq MSHR misses
system.cpu2.dcache.demand_mshr_misses::cpu2.data          267                       # number of demand (read+write) MSHR misses
system.cpu2.dcache.demand_mshr_misses::total          267                       # number of demand (read+write) MSHR misses
system.cpu2.dcache.overall_mshr_misses::cpu2.data          267                       # number of overall MSHR misses
system.cpu2.dcache.overall_mshr_misses::total          267                       # number of overall MSHR misses
system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data      1814014                       # number of ReadReq MSHR miss cycles
system.cpu2.dcache.ReadReq_mshr_miss_latency::total      1814014                       # number of ReadReq MSHR miss cycles
system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data      1708500                       # number of WriteReq MSHR miss cycles
system.cpu2.dcache.WriteReq_mshr_miss_latency::total      1708500                       # number of WriteReq MSHR miss cycles
system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data       110000                       # number of SwapReq MSHR miss cycles
system.cpu2.dcache.SwapReq_mshr_miss_latency::total       110000                       # number of SwapReq MSHR miss cycles
system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data      3522514                       # number of demand (read+write) MSHR miss cycles
system.cpu2.dcache.demand_mshr_miss_latency::total      3522514                       # number of demand (read+write) MSHR miss cycles
system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data      3522514                       # number of overall MSHR miss cycles
system.cpu2.dcache.overall_mshr_miss_latency::total      3522514                       # number of overall MSHR miss cycles
system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.003748                       # mshr miss rate for ReadReq accesses
system.cpu2.dcache.ReadReq_mshr_miss_rate::total     0.003748                       # mshr miss rate for ReadReq accesses
system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.006424                       # mshr miss rate for WriteReq accesses
system.cpu2.dcache.WriteReq_mshr_miss_rate::total     0.006424                       # mshr miss rate for WriteReq accesses
system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data     0.838710                       # mshr miss rate for SwapReq accesses
system.cpu2.dcache.SwapReq_mshr_miss_rate::total     0.838710                       # mshr miss rate for SwapReq accesses
system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data     0.004516                       # mshr miss rate for demand accesses
system.cpu2.dcache.demand_mshr_miss_rate::total     0.004516                       # mshr miss rate for demand accesses
system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data     0.004516                       # mshr miss rate for overall accesses
system.cpu2.dcache.overall_mshr_miss_rate::total     0.004516                       # mshr miss rate for overall accesses
system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 11481.101266                       # average ReadReq mshr miss latency
system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 11481.101266                       # average ReadReq mshr miss latency
system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 15674.311927                       # average WriteReq mshr miss latency
system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 15674.311927                       # average WriteReq mshr miss latency
system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data  2115.384615                       # average SwapReq mshr miss latency
system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total  2115.384615                       # average SwapReq mshr miss latency
system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 13192.936330                       # average overall mshr miss latency
system.cpu2.dcache.demand_avg_mshr_miss_latency::total 13192.936330                       # average overall mshr miss latency
system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 13192.936330                       # average overall mshr miss latency
system.cpu2.dcache.overall_avg_mshr_miss_latency::total 13192.936330                       # average overall mshr miss latency
system.cpu2.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu3.numCycles                          525586                       # number of cpu cycles simulated
system.cpu3.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu3.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu3.committedInsts                     166768                       # Number of instructions committed
system.cpu3.committedOps                       166768                       # Number of ops (including micro ops) committed
system.cpu3.num_int_alu_accesses               112266                       # Number of integer alu accesses
system.cpu3.num_fp_alu_accesses                     0                       # Number of float alu accesses
system.cpu3.num_func_calls                        637                       # number of times a function call or return occured
system.cpu3.num_conditional_control_insts        31259                       # number of instructions that are conditional controls
system.cpu3.num_int_insts                      112266                       # number of integer instructions
system.cpu3.num_fp_insts                            0                       # number of float instructions
system.cpu3.num_int_register_reads             286233                       # number of times the integer registers were read
system.cpu3.num_int_register_writes            109194                       # number of times the integer registers were written
system.cpu3.num_fp_register_reads                   0                       # number of times the floating registers were read
system.cpu3.num_fp_register_writes                  0                       # number of times the floating registers were written
system.cpu3.num_mem_refs                        57176                       # number of memory refs
system.cpu3.num_load_insts                      41805                       # Number of load instructions
system.cpu3.num_store_insts                     15371                       # Number of store instructions
system.cpu3.num_idle_cycles              69867.868801                       # Number of idle cycles
system.cpu3.num_busy_cycles              455718.131199                       # Number of busy cycles
system.cpu3.not_idle_fraction                0.867067                       # Percentage of non-idle cycles
system.cpu3.idle_fraction                    0.132933                       # Percentage of idle cycles
system.cpu3.icache.replacements                   281                       # number of replacements
system.cpu3.icache.tagsinuse                65.598360                       # Cycle average of tags in use
system.cpu3.icache.total_refs                  166434                       # Total number of references to valid blocks.
system.cpu3.icache.sampled_refs                   367                       # Sample count of references to valid blocks.
system.cpu3.icache.avg_refs                453.498638                       # Average number of references to valid blocks.
system.cpu3.icache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu3.icache.occ_blocks::cpu3.inst    65.598360                       # Average occupied blocks per requestor
system.cpu3.icache.occ_percent::cpu3.inst     0.128122                       # Average percentage of cache occupancy
system.cpu3.icache.occ_percent::total        0.128122                       # Average percentage of cache occupancy
system.cpu3.icache.ReadReq_hits::cpu3.inst       166434                       # number of ReadReq hits
system.cpu3.icache.ReadReq_hits::total         166434                       # number of ReadReq hits
system.cpu3.icache.demand_hits::cpu3.inst       166434                       # number of demand (read+write) hits
system.cpu3.icache.demand_hits::total          166434                       # number of demand (read+write) hits
system.cpu3.icache.overall_hits::cpu3.inst       166434                       # number of overall hits
system.cpu3.icache.overall_hits::total         166434                       # number of overall hits
system.cpu3.icache.ReadReq_misses::cpu3.inst          367                       # number of ReadReq misses
system.cpu3.icache.ReadReq_misses::total          367                       # number of ReadReq misses
system.cpu3.icache.demand_misses::cpu3.inst          367                       # number of demand (read+write) misses
system.cpu3.icache.demand_misses::total           367                       # number of demand (read+write) misses
system.cpu3.icache.overall_misses::cpu3.inst          367                       # number of overall misses
system.cpu3.icache.overall_misses::total          367                       # number of overall misses
system.cpu3.icache.ReadReq_miss_latency::cpu3.inst      5149000                       # number of ReadReq miss cycles
system.cpu3.icache.ReadReq_miss_latency::total      5149000                       # number of ReadReq miss cycles
system.cpu3.icache.demand_miss_latency::cpu3.inst      5149000                       # number of demand (read+write) miss cycles
system.cpu3.icache.demand_miss_latency::total      5149000                       # number of demand (read+write) miss cycles
system.cpu3.icache.overall_miss_latency::cpu3.inst      5149000                       # number of overall miss cycles
system.cpu3.icache.overall_miss_latency::total      5149000                       # number of overall miss cycles
system.cpu3.icache.ReadReq_accesses::cpu3.inst       166801                       # number of ReadReq accesses(hits+misses)
system.cpu3.icache.ReadReq_accesses::total       166801                       # number of ReadReq accesses(hits+misses)
system.cpu3.icache.demand_accesses::cpu3.inst       166801                       # number of demand (read+write) accesses
system.cpu3.icache.demand_accesses::total       166801                       # number of demand (read+write) accesses
system.cpu3.icache.overall_accesses::cpu3.inst       166801                       # number of overall (read+write) accesses
system.cpu3.icache.overall_accesses::total       166801                       # number of overall (read+write) accesses
system.cpu3.icache.ReadReq_miss_rate::cpu3.inst     0.002200                       # miss rate for ReadReq accesses
system.cpu3.icache.ReadReq_miss_rate::total     0.002200                       # miss rate for ReadReq accesses
system.cpu3.icache.demand_miss_rate::cpu3.inst     0.002200                       # miss rate for demand accesses
system.cpu3.icache.demand_miss_rate::total     0.002200                       # miss rate for demand accesses
system.cpu3.icache.overall_miss_rate::cpu3.inst     0.002200                       # miss rate for overall accesses
system.cpu3.icache.overall_miss_rate::total     0.002200                       # miss rate for overall accesses
system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 14029.972752                       # average ReadReq miss latency
system.cpu3.icache.ReadReq_avg_miss_latency::total 14029.972752                       # average ReadReq miss latency
system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 14029.972752                       # average overall miss latency
system.cpu3.icache.demand_avg_miss_latency::total 14029.972752                       # average overall miss latency
system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 14029.972752                       # average overall miss latency
system.cpu3.icache.overall_avg_miss_latency::total 14029.972752                       # average overall miss latency
system.cpu3.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu3.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu3.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu3.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu3.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu3.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu3.icache.fast_writes                      0                       # number of fast writes performed
system.cpu3.icache.cache_copies                     0                       # number of cache copies performed
system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst          367                       # number of ReadReq MSHR misses
system.cpu3.icache.ReadReq_mshr_misses::total          367                       # number of ReadReq MSHR misses
system.cpu3.icache.demand_mshr_misses::cpu3.inst          367                       # number of demand (read+write) MSHR misses
system.cpu3.icache.demand_mshr_misses::total          367                       # number of demand (read+write) MSHR misses
system.cpu3.icache.overall_mshr_misses::cpu3.inst          367                       # number of overall MSHR misses
system.cpu3.icache.overall_mshr_misses::total          367                       # number of overall MSHR misses
system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst      4414501                       # number of ReadReq MSHR miss cycles
system.cpu3.icache.ReadReq_mshr_miss_latency::total      4414501                       # number of ReadReq MSHR miss cycles
system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst      4414501                       # number of demand (read+write) MSHR miss cycles
system.cpu3.icache.demand_mshr_miss_latency::total      4414501                       # number of demand (read+write) MSHR miss cycles
system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst      4414501                       # number of overall MSHR miss cycles
system.cpu3.icache.overall_mshr_miss_latency::total      4414501                       # number of overall MSHR miss cycles
system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst     0.002200                       # mshr miss rate for ReadReq accesses
system.cpu3.icache.ReadReq_mshr_miss_rate::total     0.002200                       # mshr miss rate for ReadReq accesses
system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst     0.002200                       # mshr miss rate for demand accesses
system.cpu3.icache.demand_mshr_miss_rate::total     0.002200                       # mshr miss rate for demand accesses
system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst     0.002200                       # mshr miss rate for overall accesses
system.cpu3.icache.overall_mshr_miss_rate::total     0.002200                       # mshr miss rate for overall accesses
system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12028.613079                       # average ReadReq mshr miss latency
system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 12028.613079                       # average ReadReq mshr miss latency
system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12028.613079                       # average overall mshr miss latency
system.cpu3.icache.demand_avg_mshr_miss_latency::total 12028.613079                       # average overall mshr miss latency
system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12028.613079                       # average overall mshr miss latency
system.cpu3.icache.overall_avg_mshr_miss_latency::total 12028.613079                       # average overall mshr miss latency
system.cpu3.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu3.dcache.replacements                     0                       # number of replacements
system.cpu3.dcache.tagsinuse                25.941840                       # Cycle average of tags in use
system.cpu3.dcache.total_refs                   33003                       # Total number of references to valid blocks.
system.cpu3.dcache.sampled_refs                    29                       # Sample count of references to valid blocks.
system.cpu3.dcache.avg_refs               1138.034483                       # Average number of references to valid blocks.
system.cpu3.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu3.dcache.occ_blocks::cpu3.data    25.941840                       # Average occupied blocks per requestor
system.cpu3.dcache.occ_percent::cpu3.data     0.050668                       # Average percentage of cache occupancy
system.cpu3.dcache.occ_percent::total        0.050668                       # Average percentage of cache occupancy
system.cpu3.dcache.ReadReq_hits::cpu3.data        41638                       # number of ReadReq hits
system.cpu3.dcache.ReadReq_hits::total          41638                       # number of ReadReq hits
system.cpu3.dcache.WriteReq_hits::cpu3.data        15196                       # number of WriteReq hits
system.cpu3.dcache.WriteReq_hits::total         15196                       # number of WriteReq hits
system.cpu3.dcache.SwapReq_hits::cpu3.data           11                       # number of SwapReq hits
system.cpu3.dcache.SwapReq_hits::total             11                       # number of SwapReq hits
system.cpu3.dcache.demand_hits::cpu3.data        56834                       # number of demand (read+write) hits
system.cpu3.dcache.demand_hits::total           56834                       # number of demand (read+write) hits
system.cpu3.dcache.overall_hits::cpu3.data        56834                       # number of overall hits
system.cpu3.dcache.overall_hits::total          56834                       # number of overall hits
system.cpu3.dcache.ReadReq_misses::cpu3.data          159                       # number of ReadReq misses
system.cpu3.dcache.ReadReq_misses::total          159                       # number of ReadReq misses
system.cpu3.dcache.WriteReq_misses::cpu3.data          109                       # number of WriteReq misses
system.cpu3.dcache.WriteReq_misses::total          109                       # number of WriteReq misses
system.cpu3.dcache.SwapReq_misses::cpu3.data           53                       # number of SwapReq misses
system.cpu3.dcache.SwapReq_misses::total           53                       # number of SwapReq misses
system.cpu3.dcache.demand_misses::cpu3.data          268                       # number of demand (read+write) misses
system.cpu3.dcache.demand_misses::total           268                       # number of demand (read+write) misses
system.cpu3.dcache.overall_misses::cpu3.data          268                       # number of overall misses
system.cpu3.dcache.overall_misses::total          268                       # number of overall misses
system.cpu3.dcache.ReadReq_miss_latency::cpu3.data      2247500                       # number of ReadReq miss cycles
system.cpu3.dcache.ReadReq_miss_latency::total      2247500                       # number of ReadReq miss cycles
system.cpu3.dcache.WriteReq_miss_latency::cpu3.data      1908500                       # number of WriteReq miss cycles
system.cpu3.dcache.WriteReq_miss_latency::total      1908500                       # number of WriteReq miss cycles
system.cpu3.dcache.SwapReq_miss_latency::cpu3.data       217500                       # number of SwapReq miss cycles
system.cpu3.dcache.SwapReq_miss_latency::total       217500                       # number of SwapReq miss cycles
system.cpu3.dcache.demand_miss_latency::cpu3.data      4156000                       # number of demand (read+write) miss cycles
system.cpu3.dcache.demand_miss_latency::total      4156000                       # number of demand (read+write) miss cycles
system.cpu3.dcache.overall_miss_latency::cpu3.data      4156000                       # number of overall miss cycles
system.cpu3.dcache.overall_miss_latency::total      4156000                       # number of overall miss cycles
system.cpu3.dcache.ReadReq_accesses::cpu3.data        41797                       # number of ReadReq accesses(hits+misses)
system.cpu3.dcache.ReadReq_accesses::total        41797                       # number of ReadReq accesses(hits+misses)
system.cpu3.dcache.WriteReq_accesses::cpu3.data        15305                       # number of WriteReq accesses(hits+misses)
system.cpu3.dcache.WriteReq_accesses::total        15305                       # number of WriteReq accesses(hits+misses)
system.cpu3.dcache.SwapReq_accesses::cpu3.data           64                       # number of SwapReq accesses(hits+misses)
system.cpu3.dcache.SwapReq_accesses::total           64                       # number of SwapReq accesses(hits+misses)
system.cpu3.dcache.demand_accesses::cpu3.data        57102                       # number of demand (read+write) accesses
system.cpu3.dcache.demand_accesses::total        57102                       # number of demand (read+write) accesses
system.cpu3.dcache.overall_accesses::cpu3.data        57102                       # number of overall (read+write) accesses
system.cpu3.dcache.overall_accesses::total        57102                       # number of overall (read+write) accesses
system.cpu3.dcache.ReadReq_miss_rate::cpu3.data     0.003804                       # miss rate for ReadReq accesses
system.cpu3.dcache.ReadReq_miss_rate::total     0.003804                       # miss rate for ReadReq accesses
system.cpu3.dcache.WriteReq_miss_rate::cpu3.data     0.007122                       # miss rate for WriteReq accesses
system.cpu3.dcache.WriteReq_miss_rate::total     0.007122                       # miss rate for WriteReq accesses
system.cpu3.dcache.SwapReq_miss_rate::cpu3.data     0.828125                       # miss rate for SwapReq accesses
system.cpu3.dcache.SwapReq_miss_rate::total     0.828125                       # miss rate for SwapReq accesses
system.cpu3.dcache.demand_miss_rate::cpu3.data     0.004693                       # miss rate for demand accesses
system.cpu3.dcache.demand_miss_rate::total     0.004693                       # miss rate for demand accesses
system.cpu3.dcache.overall_miss_rate::cpu3.data     0.004693                       # miss rate for overall accesses
system.cpu3.dcache.overall_miss_rate::total     0.004693                       # miss rate for overall accesses
system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 14135.220126                       # average ReadReq miss latency
system.cpu3.dcache.ReadReq_avg_miss_latency::total 14135.220126                       # average ReadReq miss latency
system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 17509.174312                       # average WriteReq miss latency
system.cpu3.dcache.WriteReq_avg_miss_latency::total 17509.174312                       # average WriteReq miss latency
system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data  4103.773585                       # average SwapReq miss latency
system.cpu3.dcache.SwapReq_avg_miss_latency::total  4103.773585                       # average SwapReq miss latency
system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 15507.462687                       # average overall miss latency
system.cpu3.dcache.demand_avg_miss_latency::total 15507.462687                       # average overall miss latency
system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 15507.462687                       # average overall miss latency
system.cpu3.dcache.overall_avg_miss_latency::total 15507.462687                       # average overall miss latency
system.cpu3.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu3.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu3.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu3.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu3.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu3.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu3.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu3.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data          159                       # number of ReadReq MSHR misses
system.cpu3.dcache.ReadReq_mshr_misses::total          159                       # number of ReadReq MSHR misses
system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data          109                       # number of WriteReq MSHR misses
system.cpu3.dcache.WriteReq_mshr_misses::total          109                       # number of WriteReq MSHR misses
system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data           53                       # number of SwapReq MSHR misses
system.cpu3.dcache.SwapReq_mshr_misses::total           53                       # number of SwapReq MSHR misses
system.cpu3.dcache.demand_mshr_misses::cpu3.data          268                       # number of demand (read+write) MSHR misses
system.cpu3.dcache.demand_mshr_misses::total          268                       # number of demand (read+write) MSHR misses
system.cpu3.dcache.overall_mshr_misses::cpu3.data          268                       # number of overall MSHR misses
system.cpu3.dcache.overall_mshr_misses::total          268                       # number of overall MSHR misses
system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data      1924510                       # number of ReadReq MSHR miss cycles
system.cpu3.dcache.ReadReq_mshr_miss_latency::total      1924510                       # number of ReadReq MSHR miss cycles
system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data      1690500                       # number of WriteReq MSHR miss cycles
system.cpu3.dcache.WriteReq_mshr_miss_latency::total      1690500                       # number of WriteReq MSHR miss cycles
system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data       111500                       # number of SwapReq MSHR miss cycles
system.cpu3.dcache.SwapReq_mshr_miss_latency::total       111500                       # number of SwapReq MSHR miss cycles
system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data      3615010                       # number of demand (read+write) MSHR miss cycles
system.cpu3.dcache.demand_mshr_miss_latency::total      3615010                       # number of demand (read+write) MSHR miss cycles
system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data      3615010                       # number of overall MSHR miss cycles
system.cpu3.dcache.overall_mshr_miss_latency::total      3615010                       # number of overall MSHR miss cycles
system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data     0.003804                       # mshr miss rate for ReadReq accesses
system.cpu3.dcache.ReadReq_mshr_miss_rate::total     0.003804                       # mshr miss rate for ReadReq accesses
system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data     0.007122                       # mshr miss rate for WriteReq accesses
system.cpu3.dcache.WriteReq_mshr_miss_rate::total     0.007122                       # mshr miss rate for WriteReq accesses
system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data     0.828125                       # mshr miss rate for SwapReq accesses
system.cpu3.dcache.SwapReq_mshr_miss_rate::total     0.828125                       # mshr miss rate for SwapReq accesses
system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data     0.004693                       # mshr miss rate for demand accesses
system.cpu3.dcache.demand_mshr_miss_rate::total     0.004693                       # mshr miss rate for demand accesses
system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data     0.004693                       # mshr miss rate for overall accesses
system.cpu3.dcache.overall_mshr_miss_rate::total     0.004693                       # mshr miss rate for overall accesses
system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 12103.836478                       # average ReadReq mshr miss latency
system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 12103.836478                       # average ReadReq mshr miss latency
system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 15509.174312                       # average WriteReq mshr miss latency
system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 15509.174312                       # average WriteReq mshr miss latency
system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data  2103.773585                       # average SwapReq mshr miss latency
system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total  2103.773585                       # average SwapReq mshr miss latency
system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 13488.843284                       # average overall mshr miss latency
system.cpu3.dcache.demand_avg_mshr_miss_latency::total 13488.843284                       # average overall mshr miss latency
system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 13488.843284                       # average overall mshr miss latency
system.cpu3.dcache.overall_avg_mshr_miss_latency::total 13488.843284                       # average overall mshr miss latency
system.cpu3.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.l2c.replacements                             0                       # number of replacements
system.l2c.tagsinuse                       349.045938                       # Cycle average of tags in use
system.l2c.total_refs                            1220                       # Total number of references to valid blocks.
system.l2c.sampled_refs                           429                       # Sample count of references to valid blocks.
system.l2c.avg_refs                          2.843823                       # Average number of references to valid blocks.
system.l2c.warmup_cycle                             0                       # Cycle when the warmup percentage was hit.
system.l2c.occ_blocks::writebacks            0.889004                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.inst           231.790377                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.data            54.207937                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.inst            51.556644                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.data             6.123911                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu2.inst             1.773020                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu2.data             0.843759                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu3.inst             1.030265                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu3.data             0.831019                       # Average occupied blocks per requestor
system.l2c.occ_percent::writebacks           0.000014                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.inst            0.003537                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.data            0.000827                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.inst            0.000787                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.data            0.000093                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu2.inst            0.000027                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu2.data            0.000013                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu3.inst            0.000016                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu3.data            0.000013                       # Average percentage of cache occupancy
system.l2c.occ_percent::total                0.005326                       # Average percentage of cache occupancy
system.l2c.ReadReq_hits::cpu0.inst                182                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data                  5                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst                300                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data                  3                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.inst                354                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.data                  9                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu3.inst                358                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu3.data                  9                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                   1220                       # number of ReadReq hits
system.l2c.Writeback_hits::writebacks               1                       # number of Writeback hits
system.l2c.Writeback_hits::total                    1                       # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data               2                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                   2                       # number of UpgradeReq hits
system.l2c.demand_hits::cpu0.inst                 182                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data                   5                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst                 300                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data                   3                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.inst                 354                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.data                   9                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu3.inst                 358                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu3.data                   9                       # number of demand (read+write) hits
system.l2c.demand_hits::total                    1220                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.inst                182                       # number of overall hits
system.l2c.overall_hits::cpu0.data                  5                       # number of overall hits
system.l2c.overall_hits::cpu1.inst                300                       # number of overall hits
system.l2c.overall_hits::cpu1.data                  3                       # number of overall hits
system.l2c.overall_hits::cpu2.inst                354                       # number of overall hits
system.l2c.overall_hits::cpu2.data                  9                       # number of overall hits
system.l2c.overall_hits::cpu3.inst                358                       # number of overall hits
system.l2c.overall_hits::cpu3.data                  9                       # number of overall hits
system.l2c.overall_hits::total                   1220                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.inst              285                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data               66                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst               66                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data                8                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.inst               12                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.data                2                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu3.inst                9                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu3.data                2                       # number of ReadReq misses
system.l2c.ReadReq_misses::total                  450                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data            28                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data            19                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu2.data            15                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu3.data            15                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total                77                       # number of UpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data             99                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data             15                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu2.data             14                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu3.data             14                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total                142                       # number of ReadExReq misses
system.l2c.demand_misses::cpu0.inst               285                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data               165                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst                66                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data                23                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.inst                12                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.data                16                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu3.inst                 9                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu3.data                16                       # number of demand (read+write) misses
system.l2c.demand_misses::total                   592                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.inst              285                       # number of overall misses
system.l2c.overall_misses::cpu0.data              165                       # number of overall misses
system.l2c.overall_misses::cpu1.inst               66                       # number of overall misses
system.l2c.overall_misses::cpu1.data               23                       # number of overall misses
system.l2c.overall_misses::cpu2.inst               12                       # number of overall misses
system.l2c.overall_misses::cpu2.data               16                       # number of overall misses
system.l2c.overall_misses::cpu3.inst                9                       # number of overall misses
system.l2c.overall_misses::cpu3.data               16                       # number of overall misses
system.l2c.overall_misses::total                  592                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.inst     14926500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.data      3451500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst      3437500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data       418000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.inst       598000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.data       104000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu3.inst       465000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu3.data       104500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total       23505000                       # number of ReadReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data      5174000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data       801000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu2.data       747000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu3.data       729999                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total      7451999                       # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0.inst     14926500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data      8625500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst      3437500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data      1219000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.inst       598000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.data       851000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu3.inst       465000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu3.data       834499                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total        30956999                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.inst     14926500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data      8625500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst      3437500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data      1219000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.inst       598000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.data       851000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu3.inst       465000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu3.data       834499                       # number of overall miss cycles
system.l2c.overall_miss_latency::total       30956999                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.inst            467                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data             71                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst            366                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data             11                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.inst            366                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.data             11                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu3.inst            367                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu3.data             11                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total               1670                       # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks            1                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total                1                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data           30                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data           19                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu2.data           15                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu3.data           15                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total              79                       # number of UpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data           99                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data           15                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu2.data           14                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu3.data           14                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total              142                       # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.inst             467                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data             170                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst             366                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data              26                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.inst             366                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.data              25                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu3.inst             367                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu3.data              25                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total                1812                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.inst            467                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data            170                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst            366                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data             26                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.inst            366                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.data             25                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu3.inst            367                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu3.data             25                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total               1812                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.inst      0.610278                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data      0.929577                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst      0.180328                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data      0.727273                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.inst      0.032787                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.data      0.181818                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu3.inst      0.024523                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu3.data      0.181818                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.269461                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.933333                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data            1                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu2.data            1                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu3.data            1                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.974684                       # miss rate for UpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data            1                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data            1                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu2.data            1                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu3.data            1                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total               1                       # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.inst       0.610278                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.970588                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.180328                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.884615                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.inst       0.032787                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.data       0.640000                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu3.inst       0.024523                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu3.data       0.640000                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.326711                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.inst      0.610278                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.970588                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.180328                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.884615                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.inst      0.032787                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.data      0.640000                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu3.inst      0.024523                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu3.data      0.640000                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.326711                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52373.684211                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.data 52295.454545                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52083.333333                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data        52250                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.inst 49833.333333                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.data        52000                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu3.inst 51666.666667                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu3.data        52250                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 52233.333333                       # average ReadReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52262.626263                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data        53400                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu2.data 53357.142857                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu3.data 52142.785714                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 52478.866197                       # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 52373.684211                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 52275.757576                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 52083.333333                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data        53000                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.inst 49833.333333                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.data 53187.500000                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu3.inst 51666.666667                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu3.data 52156.187500                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 52292.228041                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 52373.684211                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 52275.757576                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 52083.333333                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data        53000                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.inst 49833.333333                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.data 53187.500000                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu3.inst 51666.666667                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu3.data 52156.187500                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 52292.228041                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.ReadReq_mshr_hits::cpu1.inst             7                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.data             1                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu2.inst            10                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu2.data             1                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu3.inst             1                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total                20                       # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst              7                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.data              1                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu2.inst             10                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu2.data              1                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu3.inst              1                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                 20                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst             7                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.data             1                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu2.inst            10                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu2.data             1                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu3.inst             1                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total                20                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu0.inst          285                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.data           66                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.inst           59                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data            7                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2.inst            2                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2.data            1                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu3.inst            8                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu3.data            2                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total             430                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data           28                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data           19                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu2.data           15                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu3.data           15                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total           77                       # number of UpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data           99                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data           15                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu2.data           14                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu3.data           14                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total           142                       # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst          285                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data          165                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst           59                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data           22                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.inst            2                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.data           15                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu3.inst            8                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu3.data           16                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total              572                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst          285                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data          165                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst           59                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data           22                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.inst            2                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.data           15                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu3.inst            8                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu3.data           16                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total             572                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst     11414500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.data      2640000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst      2368500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data       280000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.inst        80000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.data        40000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu3.inst       320000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu3.data        80000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total     17223000                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data      1120000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data       764491                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data       600000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data       600000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total      3084491                       # number of UpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data      3964000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data       617500                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu2.data       577500                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu3.data       560499                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total      5719499                       # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst     11414500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data      6604000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst      2368500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data       897500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.inst        80000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.data       617500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu3.inst       320000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu3.data       640499                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total     22942499                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst     11414500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data      6604000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst      2368500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data       897500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.inst        80000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.data       617500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu3.inst       320000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu3.data       640499                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total     22942499                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.610278                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.929577                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.161202                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.636364                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.inst     0.005464                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.data     0.090909                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu3.inst     0.021798                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu3.data     0.181818                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.257485                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.933333                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data            1                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data            1                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.974684                       # mshr miss rate for UpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu2.data            1                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu3.data            1                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.610278                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.970588                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.161202                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.846154                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.inst     0.005464                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.data     0.600000                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu3.inst     0.021798                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu3.data     0.640000                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.315673                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.610278                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.970588                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.161202                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.846154                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.inst     0.005464                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.data     0.600000                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu3.inst     0.021798                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu3.data     0.640000                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.315673                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40050.877193                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data        40000                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40144.067797                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data        40000                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst        40000                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data        40000                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst        40000                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data        40000                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 40053.488372                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data        40000                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40236.368421                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data        40000                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data        40000                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40058.324675                       # average UpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40040.404040                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 41166.666667                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data        41250                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 40035.642857                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 40278.161972                       # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40050.877193                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40024.242424                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40144.067797                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40795.454545                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.inst        40000                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.data 41166.666667                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu3.inst        40000                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu3.data 40031.187500                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 40109.263986                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40050.877193                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40024.242424                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40144.067797                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40795.454545                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.inst        40000                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.data 41166.666667                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu3.inst        40000                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu3.data 40031.187500                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 40109.263986                       # average overall mshr miss latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate

---------- End Simulation Statistics   ----------