stats.txt revision 8835:7c68f84d7c4e
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000088 # Number of seconds simulated 4sim_ticks 87713500 # Number of ticks simulated 5final_tick 87713500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 1664146 # Simulator instruction rate (inst/s) 8host_op_rate 1664073 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 215483439 # Simulator tick rate (ticks/s) 10host_mem_usage 1139232 # Number of bytes of host memory used 11host_seconds 0.41 # Real time elapsed on the host 12sim_insts 677340 # Number of instructions simulated 13sim_ops 677340 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read 35776 # Number of bytes read from this memory 15system.physmem.bytes_inst_read 22272 # Number of instructions bytes read from this memory 16system.physmem.bytes_written 0 # Number of bytes written to this memory 17system.physmem.num_reads 559 # Number of read requests responded to by this memory 18system.physmem.num_writes 0 # Number of write requests responded to by this memory 19system.physmem.num_other 0 # Number of other requests responded to by this memory 20system.physmem.bw_read 407873360 # Total read bandwidth from this memory (bytes/s) 21system.physmem.bw_inst_read 253917584 # Instruction read bandwidth from this memory (bytes/s) 22system.physmem.bw_total 407873360 # Total bandwidth to/from this memory (bytes/s) 23system.cpu0.workload.num_syscalls 89 # Number of system calls 24system.cpu0.numCycles 175428 # number of cpu cycles simulated 25system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 26system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 27system.cpu0.committedInsts 175339 # Number of instructions committed 28system.cpu0.committedOps 175339 # Number of ops (including micro ops) committed 29system.cpu0.num_int_alu_accesses 120388 # Number of integer alu accesses 30system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses 31system.cpu0.num_func_calls 390 # number of times a function call or return occured 32system.cpu0.num_conditional_control_insts 28825 # number of instructions that are conditional controls 33system.cpu0.num_int_insts 120388 # number of integer instructions 34system.cpu0.num_fp_insts 0 # number of float instructions 35system.cpu0.num_int_register_reads 349308 # number of times the integer registers were read 36system.cpu0.num_int_register_writes 121996 # number of times the integer registers were written 37system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read 38system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written 39system.cpu0.num_mem_refs 82398 # number of memory refs 40system.cpu0.num_load_insts 54592 # Number of load instructions 41system.cpu0.num_store_insts 27806 # Number of store instructions 42system.cpu0.num_idle_cycles 0 # Number of idle cycles 43system.cpu0.num_busy_cycles 175428 # Number of busy cycles 44system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles 45system.cpu0.idle_fraction 0 # Percentage of idle cycles 46system.cpu0.icache.replacements 215 # number of replacements 47system.cpu0.icache.tagsinuse 222.757301 # Cycle average of tags in use 48system.cpu0.icache.total_refs 174934 # Total number of references to valid blocks. 49system.cpu0.icache.sampled_refs 467 # Sample count of references to valid blocks. 50system.cpu0.icache.avg_refs 374.591006 # Average number of references to valid blocks. 51system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 52system.cpu0.icache.occ_blocks::cpu0.inst 222.757301 # Average occupied blocks per requestor 53system.cpu0.icache.occ_percent::cpu0.inst 0.435073 # Average percentage of cache occupancy 54system.cpu0.icache.occ_percent::total 0.435073 # Average percentage of cache occupancy 55system.cpu0.icache.ReadReq_hits::cpu0.inst 174934 # number of ReadReq hits 56system.cpu0.icache.ReadReq_hits::total 174934 # number of ReadReq hits 57system.cpu0.icache.demand_hits::cpu0.inst 174934 # number of demand (read+write) hits 58system.cpu0.icache.demand_hits::total 174934 # number of demand (read+write) hits 59system.cpu0.icache.overall_hits::cpu0.inst 174934 # number of overall hits 60system.cpu0.icache.overall_hits::total 174934 # number of overall hits 61system.cpu0.icache.ReadReq_misses::cpu0.inst 467 # number of ReadReq misses 62system.cpu0.icache.ReadReq_misses::total 467 # number of ReadReq misses 63system.cpu0.icache.demand_misses::cpu0.inst 467 # number of demand (read+write) misses 64system.cpu0.icache.demand_misses::total 467 # number of demand (read+write) misses 65system.cpu0.icache.overall_misses::cpu0.inst 467 # number of overall misses 66system.cpu0.icache.overall_misses::total 467 # number of overall misses 67system.cpu0.icache.ReadReq_accesses::cpu0.inst 175401 # number of ReadReq accesses(hits+misses) 68system.cpu0.icache.ReadReq_accesses::total 175401 # number of ReadReq accesses(hits+misses) 69system.cpu0.icache.demand_accesses::cpu0.inst 175401 # number of demand (read+write) accesses 70system.cpu0.icache.demand_accesses::total 175401 # number of demand (read+write) accesses 71system.cpu0.icache.overall_accesses::cpu0.inst 175401 # number of overall (read+write) accesses 72system.cpu0.icache.overall_accesses::total 175401 # number of overall (read+write) accesses 73system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002662 # miss rate for ReadReq accesses 74system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002662 # miss rate for demand accesses 75system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002662 # miss rate for overall accesses 76system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 77system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 78system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 79system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 80system.cpu0.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 81system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 82system.cpu0.icache.fast_writes 0 # number of fast writes performed 83system.cpu0.icache.cache_copies 0 # number of cache copies performed 84system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 85system.cpu0.dcache.replacements 9 # number of replacements 86system.cpu0.dcache.tagsinuse 145.712770 # Cycle average of tags in use 87system.cpu0.dcache.total_refs 61599 # Total number of references to valid blocks. 88system.cpu0.dcache.sampled_refs 170 # Sample count of references to valid blocks. 89system.cpu0.dcache.avg_refs 362.347059 # Average number of references to valid blocks. 90system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 91system.cpu0.dcache.occ_blocks::cpu0.data 145.712770 # Average occupied blocks per requestor 92system.cpu0.dcache.occ_percent::cpu0.data 0.284595 # Average percentage of cache occupancy 93system.cpu0.dcache.occ_percent::total 0.284595 # Average percentage of cache occupancy 94system.cpu0.dcache.ReadReq_hits::cpu0.data 54431 # number of ReadReq hits 95system.cpu0.dcache.ReadReq_hits::total 54431 # number of ReadReq hits 96system.cpu0.dcache.WriteReq_hits::cpu0.data 27578 # number of WriteReq hits 97system.cpu0.dcache.WriteReq_hits::total 27578 # number of WriteReq hits 98system.cpu0.dcache.SwapReq_hits::cpu0.data 15 # number of SwapReq hits 99system.cpu0.dcache.SwapReq_hits::total 15 # number of SwapReq hits 100system.cpu0.dcache.demand_hits::cpu0.data 82009 # number of demand (read+write) hits 101system.cpu0.dcache.demand_hits::total 82009 # number of demand (read+write) hits 102system.cpu0.dcache.overall_hits::cpu0.data 82009 # number of overall hits 103system.cpu0.dcache.overall_hits::total 82009 # number of overall hits 104system.cpu0.dcache.ReadReq_misses::cpu0.data 151 # number of ReadReq misses 105system.cpu0.dcache.ReadReq_misses::total 151 # number of ReadReq misses 106system.cpu0.dcache.WriteReq_misses::cpu0.data 177 # number of WriteReq misses 107system.cpu0.dcache.WriteReq_misses::total 177 # number of WriteReq misses 108system.cpu0.dcache.SwapReq_misses::cpu0.data 27 # number of SwapReq misses 109system.cpu0.dcache.SwapReq_misses::total 27 # number of SwapReq misses 110system.cpu0.dcache.demand_misses::cpu0.data 328 # number of demand (read+write) misses 111system.cpu0.dcache.demand_misses::total 328 # number of demand (read+write) misses 112system.cpu0.dcache.overall_misses::cpu0.data 328 # number of overall misses 113system.cpu0.dcache.overall_misses::total 328 # number of overall misses 114system.cpu0.dcache.ReadReq_accesses::cpu0.data 54582 # number of ReadReq accesses(hits+misses) 115system.cpu0.dcache.ReadReq_accesses::total 54582 # number of ReadReq accesses(hits+misses) 116system.cpu0.dcache.WriteReq_accesses::cpu0.data 27755 # number of WriteReq accesses(hits+misses) 117system.cpu0.dcache.WriteReq_accesses::total 27755 # number of WriteReq accesses(hits+misses) 118system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) 119system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) 120system.cpu0.dcache.demand_accesses::cpu0.data 82337 # number of demand (read+write) accesses 121system.cpu0.dcache.demand_accesses::total 82337 # number of demand (read+write) accesses 122system.cpu0.dcache.overall_accesses::cpu0.data 82337 # number of overall (read+write) accesses 123system.cpu0.dcache.overall_accesses::total 82337 # number of overall (read+write) accesses 124system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.002766 # miss rate for ReadReq accesses 125system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.006377 # miss rate for WriteReq accesses 126system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.642857 # miss rate for SwapReq accesses 127system.cpu0.dcache.demand_miss_rate::cpu0.data 0.003984 # miss rate for demand accesses 128system.cpu0.dcache.overall_miss_rate::cpu0.data 0.003984 # miss rate for overall accesses 129system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 130system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 131system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 132system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 133system.cpu0.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 134system.cpu0.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 135system.cpu0.dcache.fast_writes 0 # number of fast writes performed 136system.cpu0.dcache.cache_copies 0 # number of cache copies performed 137system.cpu0.dcache.writebacks::writebacks 6 # number of writebacks 138system.cpu0.dcache.writebacks::total 6 # number of writebacks 139system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 140system.cpu1.numCycles 173308 # number of cpu cycles simulated 141system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 142system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 143system.cpu1.committedInsts 167398 # Number of instructions committed 144system.cpu1.committedOps 167398 # Number of ops (including micro ops) committed 145system.cpu1.num_int_alu_accesses 109926 # Number of integer alu accesses 146system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses 147system.cpu1.num_func_calls 633 # number of times a function call or return occured 148system.cpu1.num_conditional_control_insts 32743 # number of instructions that are conditional controls 149system.cpu1.num_int_insts 109926 # number of integer instructions 150system.cpu1.num_fp_insts 0 # number of float instructions 151system.cpu1.num_int_register_reads 270038 # number of times the integer registers were read 152system.cpu1.num_int_register_writes 100721 # number of times the integer registers were written 153system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read 154system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written 155system.cpu1.num_mem_refs 53394 # number of memory refs 156system.cpu1.num_load_insts 40652 # Number of load instructions 157system.cpu1.num_store_insts 12742 # Number of store instructions 158system.cpu1.num_idle_cycles 7886.574443 # Number of idle cycles 159system.cpu1.num_busy_cycles 165421.425557 # Number of busy cycles 160system.cpu1.not_idle_fraction 0.954494 # Percentage of non-idle cycles 161system.cpu1.idle_fraction 0.045506 # Percentage of idle cycles 162system.cpu1.icache.replacements 278 # number of replacements 163system.cpu1.icache.tagsinuse 76.746014 # Cycle average of tags in use 164system.cpu1.icache.total_refs 167072 # Total number of references to valid blocks. 165system.cpu1.icache.sampled_refs 358 # Sample count of references to valid blocks. 166system.cpu1.icache.avg_refs 466.681564 # Average number of references to valid blocks. 167system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 168system.cpu1.icache.occ_blocks::cpu1.inst 76.746014 # Average occupied blocks per requestor 169system.cpu1.icache.occ_percent::cpu1.inst 0.149895 # Average percentage of cache occupancy 170system.cpu1.icache.occ_percent::total 0.149895 # Average percentage of cache occupancy 171system.cpu1.icache.ReadReq_hits::cpu1.inst 167072 # number of ReadReq hits 172system.cpu1.icache.ReadReq_hits::total 167072 # number of ReadReq hits 173system.cpu1.icache.demand_hits::cpu1.inst 167072 # number of demand (read+write) hits 174system.cpu1.icache.demand_hits::total 167072 # number of demand (read+write) hits 175system.cpu1.icache.overall_hits::cpu1.inst 167072 # number of overall hits 176system.cpu1.icache.overall_hits::total 167072 # number of overall hits 177system.cpu1.icache.ReadReq_misses::cpu1.inst 358 # number of ReadReq misses 178system.cpu1.icache.ReadReq_misses::total 358 # number of ReadReq misses 179system.cpu1.icache.demand_misses::cpu1.inst 358 # number of demand (read+write) misses 180system.cpu1.icache.demand_misses::total 358 # number of demand (read+write) misses 181system.cpu1.icache.overall_misses::cpu1.inst 358 # number of overall misses 182system.cpu1.icache.overall_misses::total 358 # number of overall misses 183system.cpu1.icache.ReadReq_accesses::cpu1.inst 167430 # number of ReadReq accesses(hits+misses) 184system.cpu1.icache.ReadReq_accesses::total 167430 # number of ReadReq accesses(hits+misses) 185system.cpu1.icache.demand_accesses::cpu1.inst 167430 # number of demand (read+write) accesses 186system.cpu1.icache.demand_accesses::total 167430 # number of demand (read+write) accesses 187system.cpu1.icache.overall_accesses::cpu1.inst 167430 # number of overall (read+write) accesses 188system.cpu1.icache.overall_accesses::total 167430 # number of overall (read+write) accesses 189system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002138 # miss rate for ReadReq accesses 190system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002138 # miss rate for demand accesses 191system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002138 # miss rate for overall accesses 192system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 193system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 194system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 195system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 196system.cpu1.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 197system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 198system.cpu1.icache.fast_writes 0 # number of fast writes performed 199system.cpu1.icache.cache_copies 0 # number of cache copies performed 200system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 201system.cpu1.dcache.replacements 2 # number of replacements 202system.cpu1.dcache.tagsinuse 29.073016 # Cycle average of tags in use 203system.cpu1.dcache.total_refs 26889 # Total number of references to valid blocks. 204system.cpu1.dcache.sampled_refs 28 # Sample count of references to valid blocks. 205system.cpu1.dcache.avg_refs 960.321429 # Average number of references to valid blocks. 206system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 207system.cpu1.dcache.occ_blocks::cpu1.data 29.073016 # Average occupied blocks per requestor 208system.cpu1.dcache.occ_percent::cpu1.data 0.056783 # Average percentage of cache occupancy 209system.cpu1.dcache.occ_percent::total 0.056783 # Average percentage of cache occupancy 210system.cpu1.dcache.ReadReq_hits::cpu1.data 40468 # number of ReadReq hits 211system.cpu1.dcache.ReadReq_hits::total 40468 # number of ReadReq hits 212system.cpu1.dcache.WriteReq_hits::cpu1.data 12563 # number of WriteReq hits 213system.cpu1.dcache.WriteReq_hits::total 12563 # number of WriteReq hits 214system.cpu1.dcache.SwapReq_hits::cpu1.data 14 # number of SwapReq hits 215system.cpu1.dcache.SwapReq_hits::total 14 # number of SwapReq hits 216system.cpu1.dcache.demand_hits::cpu1.data 53031 # number of demand (read+write) hits 217system.cpu1.dcache.demand_hits::total 53031 # number of demand (read+write) hits 218system.cpu1.dcache.overall_hits::cpu1.data 53031 # number of overall hits 219system.cpu1.dcache.overall_hits::total 53031 # number of overall hits 220system.cpu1.dcache.ReadReq_misses::cpu1.data 176 # number of ReadReq misses 221system.cpu1.dcache.ReadReq_misses::total 176 # number of ReadReq misses 222system.cpu1.dcache.WriteReq_misses::cpu1.data 106 # number of WriteReq misses 223system.cpu1.dcache.WriteReq_misses::total 106 # number of WriteReq misses 224system.cpu1.dcache.SwapReq_misses::cpu1.data 57 # number of SwapReq misses 225system.cpu1.dcache.SwapReq_misses::total 57 # number of SwapReq misses 226system.cpu1.dcache.demand_misses::cpu1.data 282 # number of demand (read+write) misses 227system.cpu1.dcache.demand_misses::total 282 # number of demand (read+write) misses 228system.cpu1.dcache.overall_misses::cpu1.data 282 # number of overall misses 229system.cpu1.dcache.overall_misses::total 282 # number of overall misses 230system.cpu1.dcache.ReadReq_accesses::cpu1.data 40644 # number of ReadReq accesses(hits+misses) 231system.cpu1.dcache.ReadReq_accesses::total 40644 # number of ReadReq accesses(hits+misses) 232system.cpu1.dcache.WriteReq_accesses::cpu1.data 12669 # number of WriteReq accesses(hits+misses) 233system.cpu1.dcache.WriteReq_accesses::total 12669 # number of WriteReq accesses(hits+misses) 234system.cpu1.dcache.SwapReq_accesses::cpu1.data 71 # number of SwapReq accesses(hits+misses) 235system.cpu1.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses) 236system.cpu1.dcache.demand_accesses::cpu1.data 53313 # number of demand (read+write) accesses 237system.cpu1.dcache.demand_accesses::total 53313 # number of demand (read+write) accesses 238system.cpu1.dcache.overall_accesses::cpu1.data 53313 # number of overall (read+write) accesses 239system.cpu1.dcache.overall_accesses::total 53313 # number of overall (read+write) accesses 240system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.004330 # miss rate for ReadReq accesses 241system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.008367 # miss rate for WriteReq accesses 242system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.802817 # miss rate for SwapReq accesses 243system.cpu1.dcache.demand_miss_rate::cpu1.data 0.005290 # miss rate for demand accesses 244system.cpu1.dcache.overall_miss_rate::cpu1.data 0.005290 # miss rate for overall accesses 245system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 246system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 247system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 248system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 249system.cpu1.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 250system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 251system.cpu1.dcache.fast_writes 0 # number of fast writes performed 252system.cpu1.dcache.cache_copies 0 # number of cache copies performed 253system.cpu1.dcache.writebacks::writebacks 1 # number of writebacks 254system.cpu1.dcache.writebacks::total 1 # number of writebacks 255system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 256system.cpu2.numCycles 173308 # number of cpu cycles simulated 257system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started 258system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed 259system.cpu2.committedInsts 167334 # Number of instructions committed 260system.cpu2.committedOps 167334 # Number of ops (including micro ops) committed 261system.cpu2.num_int_alu_accesses 113333 # Number of integer alu accesses 262system.cpu2.num_fp_alu_accesses 0 # Number of float alu accesses 263system.cpu2.num_func_calls 633 # number of times a function call or return occured 264system.cpu2.num_conditional_control_insts 31007 # number of instructions that are conditional controls 265system.cpu2.num_int_insts 113333 # number of integer instructions 266system.cpu2.num_fp_insts 0 # number of float instructions 267system.cpu2.num_int_register_reads 290613 # number of times the integer registers were read 268system.cpu2.num_int_register_writes 109308 # number of times the integer registers were written 269system.cpu2.num_fp_register_reads 0 # number of times the floating registers were read 270system.cpu2.num_fp_register_writes 0 # number of times the floating registers were written 271system.cpu2.num_mem_refs 58537 # number of memory refs 272system.cpu2.num_load_insts 42362 # Number of load instructions 273system.cpu2.num_store_insts 16175 # Number of store instructions 274system.cpu2.num_idle_cycles 7949.801380 # Number of idle cycles 275system.cpu2.num_busy_cycles 165358.198620 # Number of busy cycles 276system.cpu2.not_idle_fraction 0.954129 # Percentage of non-idle cycles 277system.cpu2.idle_fraction 0.045871 # Percentage of idle cycles 278system.cpu2.icache.replacements 278 # number of replacements 279system.cpu2.icache.tagsinuse 74.775474 # Cycle average of tags in use 280system.cpu2.icache.total_refs 167008 # Total number of references to valid blocks. 281system.cpu2.icache.sampled_refs 358 # Sample count of references to valid blocks. 282system.cpu2.icache.avg_refs 466.502793 # Average number of references to valid blocks. 283system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 284system.cpu2.icache.occ_blocks::cpu2.inst 74.775474 # Average occupied blocks per requestor 285system.cpu2.icache.occ_percent::cpu2.inst 0.146046 # Average percentage of cache occupancy 286system.cpu2.icache.occ_percent::total 0.146046 # Average percentage of cache occupancy 287system.cpu2.icache.ReadReq_hits::cpu2.inst 167008 # number of ReadReq hits 288system.cpu2.icache.ReadReq_hits::total 167008 # number of ReadReq hits 289system.cpu2.icache.demand_hits::cpu2.inst 167008 # number of demand (read+write) hits 290system.cpu2.icache.demand_hits::total 167008 # number of demand (read+write) hits 291system.cpu2.icache.overall_hits::cpu2.inst 167008 # number of overall hits 292system.cpu2.icache.overall_hits::total 167008 # number of overall hits 293system.cpu2.icache.ReadReq_misses::cpu2.inst 358 # number of ReadReq misses 294system.cpu2.icache.ReadReq_misses::total 358 # number of ReadReq misses 295system.cpu2.icache.demand_misses::cpu2.inst 358 # number of demand (read+write) misses 296system.cpu2.icache.demand_misses::total 358 # number of demand (read+write) misses 297system.cpu2.icache.overall_misses::cpu2.inst 358 # number of overall misses 298system.cpu2.icache.overall_misses::total 358 # number of overall misses 299system.cpu2.icache.ReadReq_accesses::cpu2.inst 167366 # number of ReadReq accesses(hits+misses) 300system.cpu2.icache.ReadReq_accesses::total 167366 # number of ReadReq accesses(hits+misses) 301system.cpu2.icache.demand_accesses::cpu2.inst 167366 # number of demand (read+write) accesses 302system.cpu2.icache.demand_accesses::total 167366 # number of demand (read+write) accesses 303system.cpu2.icache.overall_accesses::cpu2.inst 167366 # number of overall (read+write) accesses 304system.cpu2.icache.overall_accesses::total 167366 # number of overall (read+write) accesses 305system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.002139 # miss rate for ReadReq accesses 306system.cpu2.icache.demand_miss_rate::cpu2.inst 0.002139 # miss rate for demand accesses 307system.cpu2.icache.overall_miss_rate::cpu2.inst 0.002139 # miss rate for overall accesses 308system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 309system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 310system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked 311system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked 312system.cpu2.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 313system.cpu2.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 314system.cpu2.icache.fast_writes 0 # number of fast writes performed 315system.cpu2.icache.cache_copies 0 # number of cache copies performed 316system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate 317system.cpu2.dcache.replacements 2 # number of replacements 318system.cpu2.dcache.tagsinuse 28.420699 # Cycle average of tags in use 319system.cpu2.dcache.total_refs 33771 # Total number of references to valid blocks. 320system.cpu2.dcache.sampled_refs 28 # Sample count of references to valid blocks. 321system.cpu2.dcache.avg_refs 1206.107143 # Average number of references to valid blocks. 322system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 323system.cpu2.dcache.occ_blocks::cpu2.data 28.420699 # Average occupied blocks per requestor 324system.cpu2.dcache.occ_percent::cpu2.data 0.055509 # Average percentage of cache occupancy 325system.cpu2.dcache.occ_percent::total 0.055509 # Average percentage of cache occupancy 326system.cpu2.dcache.ReadReq_hits::cpu2.data 42192 # number of ReadReq hits 327system.cpu2.dcache.ReadReq_hits::total 42192 # number of ReadReq hits 328system.cpu2.dcache.WriteReq_hits::cpu2.data 15998 # number of WriteReq hits 329system.cpu2.dcache.WriteReq_hits::total 15998 # number of WriteReq hits 330system.cpu2.dcache.SwapReq_hits::cpu2.data 11 # number of SwapReq hits 331system.cpu2.dcache.SwapReq_hits::total 11 # number of SwapReq hits 332system.cpu2.dcache.demand_hits::cpu2.data 58190 # number of demand (read+write) hits 333system.cpu2.dcache.demand_hits::total 58190 # number of demand (read+write) hits 334system.cpu2.dcache.overall_hits::cpu2.data 58190 # number of overall hits 335system.cpu2.dcache.overall_hits::total 58190 # number of overall hits 336system.cpu2.dcache.ReadReq_misses::cpu2.data 162 # number of ReadReq misses 337system.cpu2.dcache.ReadReq_misses::total 162 # number of ReadReq misses 338system.cpu2.dcache.WriteReq_misses::cpu2.data 109 # number of WriteReq misses 339system.cpu2.dcache.WriteReq_misses::total 109 # number of WriteReq misses 340system.cpu2.dcache.SwapReq_misses::cpu2.data 55 # number of SwapReq misses 341system.cpu2.dcache.SwapReq_misses::total 55 # number of SwapReq misses 342system.cpu2.dcache.demand_misses::cpu2.data 271 # number of demand (read+write) misses 343system.cpu2.dcache.demand_misses::total 271 # number of demand (read+write) misses 344system.cpu2.dcache.overall_misses::cpu2.data 271 # number of overall misses 345system.cpu2.dcache.overall_misses::total 271 # number of overall misses 346system.cpu2.dcache.ReadReq_accesses::cpu2.data 42354 # number of ReadReq accesses(hits+misses) 347system.cpu2.dcache.ReadReq_accesses::total 42354 # number of ReadReq accesses(hits+misses) 348system.cpu2.dcache.WriteReq_accesses::cpu2.data 16107 # number of WriteReq accesses(hits+misses) 349system.cpu2.dcache.WriteReq_accesses::total 16107 # number of WriteReq accesses(hits+misses) 350system.cpu2.dcache.SwapReq_accesses::cpu2.data 66 # number of SwapReq accesses(hits+misses) 351system.cpu2.dcache.SwapReq_accesses::total 66 # number of SwapReq accesses(hits+misses) 352system.cpu2.dcache.demand_accesses::cpu2.data 58461 # number of demand (read+write) accesses 353system.cpu2.dcache.demand_accesses::total 58461 # number of demand (read+write) accesses 354system.cpu2.dcache.overall_accesses::cpu2.data 58461 # number of overall (read+write) accesses 355system.cpu2.dcache.overall_accesses::total 58461 # number of overall (read+write) accesses 356system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.003825 # miss rate for ReadReq accesses 357system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.006767 # miss rate for WriteReq accesses 358system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.833333 # miss rate for SwapReq accesses 359system.cpu2.dcache.demand_miss_rate::cpu2.data 0.004636 # miss rate for demand accesses 360system.cpu2.dcache.overall_miss_rate::cpu2.data 0.004636 # miss rate for overall accesses 361system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 362system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 363system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 364system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked 365system.cpu2.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 366system.cpu2.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 367system.cpu2.dcache.fast_writes 0 # number of fast writes performed 368system.cpu2.dcache.cache_copies 0 # number of cache copies performed 369system.cpu2.dcache.writebacks::writebacks 1 # number of writebacks 370system.cpu2.dcache.writebacks::total 1 # number of writebacks 371system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 372system.cpu3.numCycles 173307 # number of cpu cycles simulated 373system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started 374system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed 375system.cpu3.committedInsts 167269 # Number of instructions committed 376system.cpu3.committedOps 167269 # Number of ops (including micro ops) committed 377system.cpu3.num_int_alu_accesses 111554 # Number of integer alu accesses 378system.cpu3.num_fp_alu_accesses 0 # Number of float alu accesses 379system.cpu3.num_func_calls 633 # number of times a function call or return occured 380system.cpu3.num_conditional_control_insts 31865 # number of instructions that are conditional controls 381system.cpu3.num_int_insts 111554 # number of integer instructions 382system.cpu3.num_fp_insts 0 # number of float instructions 383system.cpu3.num_int_register_reads 280060 # number of times the integer registers were read 384system.cpu3.num_int_register_writes 104916 # number of times the integer registers were written 385system.cpu3.num_fp_register_reads 0 # number of times the floating registers were read 386system.cpu3.num_fp_register_writes 0 # number of times the floating registers were written 387system.cpu3.num_mem_refs 55900 # number of memory refs 388system.cpu3.num_load_insts 41466 # Number of load instructions 389system.cpu3.num_store_insts 14434 # Number of store instructions 390system.cpu3.num_idle_cycles 8013.969997 # Number of idle cycles 391system.cpu3.num_busy_cycles 165293.030003 # Number of busy cycles 392system.cpu3.not_idle_fraction 0.953759 # Percentage of non-idle cycles 393system.cpu3.idle_fraction 0.046241 # Percentage of idle cycles 394system.cpu3.icache.replacements 279 # number of replacements 395system.cpu3.icache.tagsinuse 72.869097 # Cycle average of tags in use 396system.cpu3.icache.total_refs 166942 # Total number of references to valid blocks. 397system.cpu3.icache.sampled_refs 359 # Sample count of references to valid blocks. 398system.cpu3.icache.avg_refs 465.019499 # Average number of references to valid blocks. 399system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 400system.cpu3.icache.occ_blocks::cpu3.inst 72.869097 # Average occupied blocks per requestor 401system.cpu3.icache.occ_percent::cpu3.inst 0.142322 # Average percentage of cache occupancy 402system.cpu3.icache.occ_percent::total 0.142322 # Average percentage of cache occupancy 403system.cpu3.icache.ReadReq_hits::cpu3.inst 166942 # number of ReadReq hits 404system.cpu3.icache.ReadReq_hits::total 166942 # number of ReadReq hits 405system.cpu3.icache.demand_hits::cpu3.inst 166942 # number of demand (read+write) hits 406system.cpu3.icache.demand_hits::total 166942 # number of demand (read+write) hits 407system.cpu3.icache.overall_hits::cpu3.inst 166942 # number of overall hits 408system.cpu3.icache.overall_hits::total 166942 # number of overall hits 409system.cpu3.icache.ReadReq_misses::cpu3.inst 359 # number of ReadReq misses 410system.cpu3.icache.ReadReq_misses::total 359 # number of ReadReq misses 411system.cpu3.icache.demand_misses::cpu3.inst 359 # number of demand (read+write) misses 412system.cpu3.icache.demand_misses::total 359 # number of demand (read+write) misses 413system.cpu3.icache.overall_misses::cpu3.inst 359 # number of overall misses 414system.cpu3.icache.overall_misses::total 359 # number of overall misses 415system.cpu3.icache.ReadReq_accesses::cpu3.inst 167301 # number of ReadReq accesses(hits+misses) 416system.cpu3.icache.ReadReq_accesses::total 167301 # number of ReadReq accesses(hits+misses) 417system.cpu3.icache.demand_accesses::cpu3.inst 167301 # number of demand (read+write) accesses 418system.cpu3.icache.demand_accesses::total 167301 # number of demand (read+write) accesses 419system.cpu3.icache.overall_accesses::cpu3.inst 167301 # number of overall (read+write) accesses 420system.cpu3.icache.overall_accesses::total 167301 # number of overall (read+write) accesses 421system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.002146 # miss rate for ReadReq accesses 422system.cpu3.icache.demand_miss_rate::cpu3.inst 0.002146 # miss rate for demand accesses 423system.cpu3.icache.overall_miss_rate::cpu3.inst 0.002146 # miss rate for overall accesses 424system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 425system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 426system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked 427system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked 428system.cpu3.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 429system.cpu3.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 430system.cpu3.icache.fast_writes 0 # number of fast writes performed 431system.cpu3.icache.cache_copies 0 # number of cache copies performed 432system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate 433system.cpu3.dcache.replacements 2 # number of replacements 434system.cpu3.dcache.tagsinuse 27.588376 # Cycle average of tags in use 435system.cpu3.dcache.total_refs 30309 # Total number of references to valid blocks. 436system.cpu3.dcache.sampled_refs 29 # Sample count of references to valid blocks. 437system.cpu3.dcache.avg_refs 1045.137931 # Average number of references to valid blocks. 438system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 439system.cpu3.dcache.occ_blocks::cpu3.data 27.588376 # Average occupied blocks per requestor 440system.cpu3.dcache.occ_percent::cpu3.data 0.053884 # Average percentage of cache occupancy 441system.cpu3.dcache.occ_percent::total 0.053884 # Average percentage of cache occupancy 442system.cpu3.dcache.ReadReq_hits::cpu3.data 41299 # number of ReadReq hits 443system.cpu3.dcache.ReadReq_hits::total 41299 # number of ReadReq hits 444system.cpu3.dcache.WriteReq_hits::cpu3.data 14260 # number of WriteReq hits 445system.cpu3.dcache.WriteReq_hits::total 14260 # number of WriteReq hits 446system.cpu3.dcache.SwapReq_hits::cpu3.data 15 # number of SwapReq hits 447system.cpu3.dcache.SwapReq_hits::total 15 # number of SwapReq hits 448system.cpu3.dcache.demand_hits::cpu3.data 55559 # number of demand (read+write) hits 449system.cpu3.dcache.demand_hits::total 55559 # number of demand (read+write) hits 450system.cpu3.dcache.overall_hits::cpu3.data 55559 # number of overall hits 451system.cpu3.dcache.overall_hits::total 55559 # number of overall hits 452system.cpu3.dcache.ReadReq_misses::cpu3.data 159 # number of ReadReq misses 453system.cpu3.dcache.ReadReq_misses::total 159 # number of ReadReq misses 454system.cpu3.dcache.WriteReq_misses::cpu3.data 102 # number of WriteReq misses 455system.cpu3.dcache.WriteReq_misses::total 102 # number of WriteReq misses 456system.cpu3.dcache.SwapReq_misses::cpu3.data 55 # number of SwapReq misses 457system.cpu3.dcache.SwapReq_misses::total 55 # number of SwapReq misses 458system.cpu3.dcache.demand_misses::cpu3.data 261 # number of demand (read+write) misses 459system.cpu3.dcache.demand_misses::total 261 # number of demand (read+write) misses 460system.cpu3.dcache.overall_misses::cpu3.data 261 # number of overall misses 461system.cpu3.dcache.overall_misses::total 261 # number of overall misses 462system.cpu3.dcache.ReadReq_accesses::cpu3.data 41458 # number of ReadReq accesses(hits+misses) 463system.cpu3.dcache.ReadReq_accesses::total 41458 # number of ReadReq accesses(hits+misses) 464system.cpu3.dcache.WriteReq_accesses::cpu3.data 14362 # number of WriteReq accesses(hits+misses) 465system.cpu3.dcache.WriteReq_accesses::total 14362 # number of WriteReq accesses(hits+misses) 466system.cpu3.dcache.SwapReq_accesses::cpu3.data 70 # number of SwapReq accesses(hits+misses) 467system.cpu3.dcache.SwapReq_accesses::total 70 # number of SwapReq accesses(hits+misses) 468system.cpu3.dcache.demand_accesses::cpu3.data 55820 # number of demand (read+write) accesses 469system.cpu3.dcache.demand_accesses::total 55820 # number of demand (read+write) accesses 470system.cpu3.dcache.overall_accesses::cpu3.data 55820 # number of overall (read+write) accesses 471system.cpu3.dcache.overall_accesses::total 55820 # number of overall (read+write) accesses 472system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.003835 # miss rate for ReadReq accesses 473system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.007102 # miss rate for WriteReq accesses 474system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.785714 # miss rate for SwapReq accesses 475system.cpu3.dcache.demand_miss_rate::cpu3.data 0.004676 # miss rate for demand accesses 476system.cpu3.dcache.overall_miss_rate::cpu3.data 0.004676 # miss rate for overall accesses 477system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 478system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 479system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 480system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked 481system.cpu3.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 482system.cpu3.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 483system.cpu3.dcache.fast_writes 0 # number of fast writes performed 484system.cpu3.dcache.cache_copies 0 # number of cache copies performed 485system.cpu3.dcache.writebacks::writebacks 1 # number of writebacks 486system.cpu3.dcache.writebacks::total 1 # number of writebacks 487system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 488system.l2c.replacements 0 # number of replacements 489system.l2c.tagsinuse 371.980910 # Cycle average of tags in use 490system.l2c.total_refs 1223 # Total number of references to valid blocks. 491system.l2c.sampled_refs 426 # Sample count of references to valid blocks. 492system.l2c.avg_refs 2.870892 # Average number of references to valid blocks. 493system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. 494system.l2c.occ_blocks::writebacks 6.390048 # Average occupied blocks per requestor 495system.l2c.occ_blocks::cpu0.inst 239.409595 # Average occupied blocks per requestor 496system.l2c.occ_blocks::cpu0.data 55.204245 # Average occupied blocks per requestor 497system.l2c.occ_blocks::cpu1.inst 59.507442 # Average occupied blocks per requestor 498system.l2c.occ_blocks::cpu1.data 6.720647 # Average occupied blocks per requestor 499system.l2c.occ_blocks::cpu2.inst 1.930518 # Average occupied blocks per requestor 500system.l2c.occ_blocks::cpu2.data 0.935341 # Average occupied blocks per requestor 501system.l2c.occ_blocks::cpu3.inst 0.977501 # Average occupied blocks per requestor 502system.l2c.occ_blocks::cpu3.data 0.905573 # Average occupied blocks per requestor 503system.l2c.occ_percent::writebacks 0.000098 # Average percentage of cache occupancy 504system.l2c.occ_percent::cpu0.inst 0.003653 # Average percentage of cache occupancy 505system.l2c.occ_percent::cpu0.data 0.000842 # Average percentage of cache occupancy 506system.l2c.occ_percent::cpu1.inst 0.000908 # Average percentage of cache occupancy 507system.l2c.occ_percent::cpu1.data 0.000103 # Average percentage of cache occupancy 508system.l2c.occ_percent::cpu2.inst 0.000029 # Average percentage of cache occupancy 509system.l2c.occ_percent::cpu2.data 0.000014 # Average percentage of cache occupancy 510system.l2c.occ_percent::cpu3.inst 0.000015 # Average percentage of cache occupancy 511system.l2c.occ_percent::cpu3.data 0.000014 # Average percentage of cache occupancy 512system.l2c.occ_percent::total 0.005676 # Average percentage of cache occupancy 513system.l2c.ReadReq_hits::cpu0.inst 185 # number of ReadReq hits 514system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits 515system.l2c.ReadReq_hits::cpu1.inst 296 # number of ReadReq hits 516system.l2c.ReadReq_hits::cpu1.data 5 # number of ReadReq hits 517system.l2c.ReadReq_hits::cpu2.inst 356 # number of ReadReq hits 518system.l2c.ReadReq_hits::cpu2.data 11 # number of ReadReq hits 519system.l2c.ReadReq_hits::cpu3.inst 357 # number of ReadReq hits 520system.l2c.ReadReq_hits::cpu3.data 11 # number of ReadReq hits 521system.l2c.ReadReq_hits::total 1226 # number of ReadReq hits 522system.l2c.Writeback_hits::writebacks 9 # number of Writeback hits 523system.l2c.Writeback_hits::total 9 # number of Writeback hits 524system.l2c.UpgradeReq_hits::cpu0.data 2 # number of UpgradeReq hits 525system.l2c.UpgradeReq_hits::total 2 # number of UpgradeReq hits 526system.l2c.demand_hits::cpu0.inst 185 # number of demand (read+write) hits 527system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits 528system.l2c.demand_hits::cpu1.inst 296 # number of demand (read+write) hits 529system.l2c.demand_hits::cpu1.data 5 # number of demand (read+write) hits 530system.l2c.demand_hits::cpu2.inst 356 # number of demand (read+write) hits 531system.l2c.demand_hits::cpu2.data 11 # number of demand (read+write) hits 532system.l2c.demand_hits::cpu3.inst 357 # number of demand (read+write) hits 533system.l2c.demand_hits::cpu3.data 11 # number of demand (read+write) hits 534system.l2c.demand_hits::total 1226 # number of demand (read+write) hits 535system.l2c.overall_hits::cpu0.inst 185 # number of overall hits 536system.l2c.overall_hits::cpu0.data 5 # number of overall hits 537system.l2c.overall_hits::cpu1.inst 296 # number of overall hits 538system.l2c.overall_hits::cpu1.data 5 # number of overall hits 539system.l2c.overall_hits::cpu2.inst 356 # number of overall hits 540system.l2c.overall_hits::cpu2.data 11 # number of overall hits 541system.l2c.overall_hits::cpu3.inst 357 # number of overall hits 542system.l2c.overall_hits::cpu3.data 11 # number of overall hits 543system.l2c.overall_hits::total 1226 # number of overall hits 544system.l2c.ReadReq_misses::cpu0.inst 282 # number of ReadReq misses 545system.l2c.ReadReq_misses::cpu0.data 66 # number of ReadReq misses 546system.l2c.ReadReq_misses::cpu1.inst 62 # number of ReadReq misses 547system.l2c.ReadReq_misses::cpu1.data 7 # number of ReadReq misses 548system.l2c.ReadReq_misses::cpu2.inst 2 # number of ReadReq misses 549system.l2c.ReadReq_misses::cpu2.data 1 # number of ReadReq misses 550system.l2c.ReadReq_misses::cpu3.inst 2 # number of ReadReq misses 551system.l2c.ReadReq_misses::cpu3.data 1 # number of ReadReq misses 552system.l2c.ReadReq_misses::total 423 # number of ReadReq misses 553system.l2c.UpgradeReq_misses::cpu0.data 29 # number of UpgradeReq misses 554system.l2c.UpgradeReq_misses::cpu1.data 19 # number of UpgradeReq misses 555system.l2c.UpgradeReq_misses::cpu2.data 20 # number of UpgradeReq misses 556system.l2c.UpgradeReq_misses::cpu3.data 19 # number of UpgradeReq misses 557system.l2c.UpgradeReq_misses::total 87 # number of UpgradeReq misses 558system.l2c.ReadExReq_misses::cpu0.data 99 # number of ReadExReq misses 559system.l2c.ReadExReq_misses::cpu1.data 13 # number of ReadExReq misses 560system.l2c.ReadExReq_misses::cpu2.data 12 # number of ReadExReq misses 561system.l2c.ReadExReq_misses::cpu3.data 12 # number of ReadExReq misses 562system.l2c.ReadExReq_misses::total 136 # number of ReadExReq misses 563system.l2c.demand_misses::cpu0.inst 282 # number of demand (read+write) misses 564system.l2c.demand_misses::cpu0.data 165 # number of demand (read+write) misses 565system.l2c.demand_misses::cpu1.inst 62 # number of demand (read+write) misses 566system.l2c.demand_misses::cpu1.data 20 # number of demand (read+write) misses 567system.l2c.demand_misses::cpu2.inst 2 # number of demand (read+write) misses 568system.l2c.demand_misses::cpu2.data 13 # number of demand (read+write) misses 569system.l2c.demand_misses::cpu3.inst 2 # number of demand (read+write) misses 570system.l2c.demand_misses::cpu3.data 13 # number of demand (read+write) misses 571system.l2c.demand_misses::total 559 # number of demand (read+write) misses 572system.l2c.overall_misses::cpu0.inst 282 # number of overall misses 573system.l2c.overall_misses::cpu0.data 165 # number of overall misses 574system.l2c.overall_misses::cpu1.inst 62 # number of overall misses 575system.l2c.overall_misses::cpu1.data 20 # number of overall misses 576system.l2c.overall_misses::cpu2.inst 2 # number of overall misses 577system.l2c.overall_misses::cpu2.data 13 # number of overall misses 578system.l2c.overall_misses::cpu3.inst 2 # number of overall misses 579system.l2c.overall_misses::cpu3.data 13 # number of overall misses 580system.l2c.overall_misses::total 559 # number of overall misses 581system.l2c.ReadReq_accesses::cpu0.inst 467 # number of ReadReq accesses(hits+misses) 582system.l2c.ReadReq_accesses::cpu0.data 71 # number of ReadReq accesses(hits+misses) 583system.l2c.ReadReq_accesses::cpu1.inst 358 # number of ReadReq accesses(hits+misses) 584system.l2c.ReadReq_accesses::cpu1.data 12 # number of ReadReq accesses(hits+misses) 585system.l2c.ReadReq_accesses::cpu2.inst 358 # number of ReadReq accesses(hits+misses) 586system.l2c.ReadReq_accesses::cpu2.data 12 # number of ReadReq accesses(hits+misses) 587system.l2c.ReadReq_accesses::cpu3.inst 359 # number of ReadReq accesses(hits+misses) 588system.l2c.ReadReq_accesses::cpu3.data 12 # number of ReadReq accesses(hits+misses) 589system.l2c.ReadReq_accesses::total 1649 # number of ReadReq accesses(hits+misses) 590system.l2c.Writeback_accesses::writebacks 9 # number of Writeback accesses(hits+misses) 591system.l2c.Writeback_accesses::total 9 # number of Writeback accesses(hits+misses) 592system.l2c.UpgradeReq_accesses::cpu0.data 31 # number of UpgradeReq accesses(hits+misses) 593system.l2c.UpgradeReq_accesses::cpu1.data 19 # number of UpgradeReq accesses(hits+misses) 594system.l2c.UpgradeReq_accesses::cpu2.data 20 # number of UpgradeReq accesses(hits+misses) 595system.l2c.UpgradeReq_accesses::cpu3.data 19 # number of UpgradeReq accesses(hits+misses) 596system.l2c.UpgradeReq_accesses::total 89 # number of UpgradeReq accesses(hits+misses) 597system.l2c.ReadExReq_accesses::cpu0.data 99 # number of ReadExReq accesses(hits+misses) 598system.l2c.ReadExReq_accesses::cpu1.data 13 # number of ReadExReq accesses(hits+misses) 599system.l2c.ReadExReq_accesses::cpu2.data 12 # number of ReadExReq accesses(hits+misses) 600system.l2c.ReadExReq_accesses::cpu3.data 12 # number of ReadExReq accesses(hits+misses) 601system.l2c.ReadExReq_accesses::total 136 # number of ReadExReq accesses(hits+misses) 602system.l2c.demand_accesses::cpu0.inst 467 # number of demand (read+write) accesses 603system.l2c.demand_accesses::cpu0.data 170 # number of demand (read+write) accesses 604system.l2c.demand_accesses::cpu1.inst 358 # number of demand (read+write) accesses 605system.l2c.demand_accesses::cpu1.data 25 # number of demand (read+write) accesses 606system.l2c.demand_accesses::cpu2.inst 358 # number of demand (read+write) accesses 607system.l2c.demand_accesses::cpu2.data 24 # number of demand (read+write) accesses 608system.l2c.demand_accesses::cpu3.inst 359 # number of demand (read+write) accesses 609system.l2c.demand_accesses::cpu3.data 24 # number of demand (read+write) accesses 610system.l2c.demand_accesses::total 1785 # number of demand (read+write) accesses 611system.l2c.overall_accesses::cpu0.inst 467 # number of overall (read+write) accesses 612system.l2c.overall_accesses::cpu0.data 170 # number of overall (read+write) accesses 613system.l2c.overall_accesses::cpu1.inst 358 # number of overall (read+write) accesses 614system.l2c.overall_accesses::cpu1.data 25 # number of overall (read+write) accesses 615system.l2c.overall_accesses::cpu2.inst 358 # number of overall (read+write) accesses 616system.l2c.overall_accesses::cpu2.data 24 # number of overall (read+write) accesses 617system.l2c.overall_accesses::cpu3.inst 359 # number of overall (read+write) accesses 618system.l2c.overall_accesses::cpu3.data 24 # number of overall (read+write) accesses 619system.l2c.overall_accesses::total 1785 # number of overall (read+write) accesses 620system.l2c.ReadReq_miss_rate::cpu0.inst 0.603854 # miss rate for ReadReq accesses 621system.l2c.ReadReq_miss_rate::cpu0.data 0.929577 # miss rate for ReadReq accesses 622system.l2c.ReadReq_miss_rate::cpu1.inst 0.173184 # miss rate for ReadReq accesses 623system.l2c.ReadReq_miss_rate::cpu1.data 0.583333 # miss rate for ReadReq accesses 624system.l2c.ReadReq_miss_rate::cpu2.inst 0.005587 # miss rate for ReadReq accesses 625system.l2c.ReadReq_miss_rate::cpu2.data 0.083333 # miss rate for ReadReq accesses 626system.l2c.ReadReq_miss_rate::cpu3.inst 0.005571 # miss rate for ReadReq accesses 627system.l2c.ReadReq_miss_rate::cpu3.data 0.083333 # miss rate for ReadReq accesses 628system.l2c.UpgradeReq_miss_rate::cpu0.data 0.935484 # miss rate for UpgradeReq accesses 629system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses 630system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses 631system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses 632system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses 633system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses 634system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses 635system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses 636system.l2c.demand_miss_rate::cpu0.inst 0.603854 # miss rate for demand accesses 637system.l2c.demand_miss_rate::cpu0.data 0.970588 # miss rate for demand accesses 638system.l2c.demand_miss_rate::cpu1.inst 0.173184 # miss rate for demand accesses 639system.l2c.demand_miss_rate::cpu1.data 0.800000 # miss rate for demand accesses 640system.l2c.demand_miss_rate::cpu2.inst 0.005587 # miss rate for demand accesses 641system.l2c.demand_miss_rate::cpu2.data 0.541667 # miss rate for demand accesses 642system.l2c.demand_miss_rate::cpu3.inst 0.005571 # miss rate for demand accesses 643system.l2c.demand_miss_rate::cpu3.data 0.541667 # miss rate for demand accesses 644system.l2c.overall_miss_rate::cpu0.inst 0.603854 # miss rate for overall accesses 645system.l2c.overall_miss_rate::cpu0.data 0.970588 # miss rate for overall accesses 646system.l2c.overall_miss_rate::cpu1.inst 0.173184 # miss rate for overall accesses 647system.l2c.overall_miss_rate::cpu1.data 0.800000 # miss rate for overall accesses 648system.l2c.overall_miss_rate::cpu2.inst 0.005587 # miss rate for overall accesses 649system.l2c.overall_miss_rate::cpu2.data 0.541667 # miss rate for overall accesses 650system.l2c.overall_miss_rate::cpu3.inst 0.005571 # miss rate for overall accesses 651system.l2c.overall_miss_rate::cpu3.data 0.541667 # miss rate for overall accesses 652system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 653system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 654system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 655system.l2c.blocked::no_targets 0 # number of cycles access was blocked 656system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 657system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 658system.l2c.fast_writes 0 # number of fast writes performed 659system.l2c.cache_copies 0 # number of cache copies performed 660system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 661 662---------- End Simulation Statistics ---------- 663