stats.txt revision 8802:ef66a9083bc4
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000088 # Number of seconds simulated 4sim_ticks 87713500 # Number of ticks simulated 5final_tick 87713500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 1650324 # Simulator instruction rate (inst/s) 8host_tick_rate 213702670 # Simulator tick rate (ticks/s) 9host_mem_usage 1140448 # Number of bytes of host memory used 10host_seconds 0.41 # Real time elapsed on the host 11sim_insts 677340 # Number of instructions simulated 12system.physmem.bytes_read 35776 # Number of bytes read from this memory 13system.physmem.bytes_inst_read 22272 # Number of instructions bytes read from this memory 14system.physmem.bytes_written 0 # Number of bytes written to this memory 15system.physmem.num_reads 559 # Number of read requests responded to by this memory 16system.physmem.num_writes 0 # Number of write requests responded to by this memory 17system.physmem.num_other 0 # Number of other requests responded to by this memory 18system.physmem.bw_read 407873360 # Total read bandwidth from this memory (bytes/s) 19system.physmem.bw_inst_read 253917584 # Instruction read bandwidth from this memory (bytes/s) 20system.physmem.bw_total 407873360 # Total bandwidth to/from this memory (bytes/s) 21system.cpu0.workload.num_syscalls 89 # Number of system calls 22system.cpu0.numCycles 175428 # number of cpu cycles simulated 23system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 24system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 25system.cpu0.num_insts 175339 # Number of instructions executed 26system.cpu0.num_int_alu_accesses 120388 # Number of integer alu accesses 27system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses 28system.cpu0.num_func_calls 390 # number of times a function call or return occured 29system.cpu0.num_conditional_control_insts 28825 # number of instructions that are conditional controls 30system.cpu0.num_int_insts 120388 # number of integer instructions 31system.cpu0.num_fp_insts 0 # number of float instructions 32system.cpu0.num_int_register_reads 349308 # number of times the integer registers were read 33system.cpu0.num_int_register_writes 121996 # number of times the integer registers were written 34system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read 35system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written 36system.cpu0.num_mem_refs 82398 # number of memory refs 37system.cpu0.num_load_insts 54592 # Number of load instructions 38system.cpu0.num_store_insts 27806 # Number of store instructions 39system.cpu0.num_idle_cycles 0 # Number of idle cycles 40system.cpu0.num_busy_cycles 175428 # Number of busy cycles 41system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles 42system.cpu0.idle_fraction 0 # Percentage of idle cycles 43system.cpu0.icache.replacements 215 # number of replacements 44system.cpu0.icache.tagsinuse 222.757301 # Cycle average of tags in use 45system.cpu0.icache.total_refs 174934 # Total number of references to valid blocks. 46system.cpu0.icache.sampled_refs 467 # Sample count of references to valid blocks. 47system.cpu0.icache.avg_refs 374.591006 # Average number of references to valid blocks. 48system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 49system.cpu0.icache.occ_blocks::0 222.757301 # Average occupied blocks per context 50system.cpu0.icache.occ_percent::0 0.435073 # Average percentage of cache occupancy 51system.cpu0.icache.ReadReq_hits 174934 # number of ReadReq hits 52system.cpu0.icache.demand_hits 174934 # number of demand (read+write) hits 53system.cpu0.icache.overall_hits 174934 # number of overall hits 54system.cpu0.icache.ReadReq_misses 467 # number of ReadReq misses 55system.cpu0.icache.demand_misses 467 # number of demand (read+write) misses 56system.cpu0.icache.overall_misses 467 # number of overall misses 57system.cpu0.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles 58system.cpu0.icache.overall_miss_latency 0 # number of overall miss cycles 59system.cpu0.icache.ReadReq_accesses 175401 # number of ReadReq accesses(hits+misses) 60system.cpu0.icache.demand_accesses 175401 # number of demand (read+write) accesses 61system.cpu0.icache.overall_accesses 175401 # number of overall (read+write) accesses 62system.cpu0.icache.ReadReq_miss_rate 0.002662 # miss rate for ReadReq accesses 63system.cpu0.icache.demand_miss_rate 0.002662 # miss rate for demand accesses 64system.cpu0.icache.overall_miss_rate 0.002662 # miss rate for overall accesses 65system.cpu0.icache.demand_avg_miss_latency 0 # average overall miss latency 66system.cpu0.icache.overall_avg_miss_latency 0 # average overall miss latency 67system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 68system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 69system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 70system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 71system.cpu0.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 72system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 73system.cpu0.icache.fast_writes 0 # number of fast writes performed 74system.cpu0.icache.cache_copies 0 # number of cache copies performed 75system.cpu0.icache.writebacks 0 # number of writebacks 76system.cpu0.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 77system.cpu0.icache.overall_mshr_hits 0 # number of overall MSHR hits 78system.cpu0.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses 79system.cpu0.icache.overall_mshr_misses 0 # number of overall MSHR misses 80system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 81system.cpu0.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles 82system.cpu0.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles 83system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 84system.cpu0.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses 85system.cpu0.icache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses 86system.cpu0.icache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency 87system.cpu0.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency 88system.cpu0.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 89system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated 90system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 91system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 92system.cpu0.dcache.replacements 9 # number of replacements 93system.cpu0.dcache.tagsinuse 145.712770 # Cycle average of tags in use 94system.cpu0.dcache.total_refs 61599 # Total number of references to valid blocks. 95system.cpu0.dcache.sampled_refs 170 # Sample count of references to valid blocks. 96system.cpu0.dcache.avg_refs 362.347059 # Average number of references to valid blocks. 97system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 98system.cpu0.dcache.occ_blocks::0 145.712770 # Average occupied blocks per context 99system.cpu0.dcache.occ_percent::0 0.284595 # Average percentage of cache occupancy 100system.cpu0.dcache.ReadReq_hits 54431 # number of ReadReq hits 101system.cpu0.dcache.WriteReq_hits 27578 # number of WriteReq hits 102system.cpu0.dcache.SwapReq_hits 15 # number of SwapReq hits 103system.cpu0.dcache.demand_hits 82009 # number of demand (read+write) hits 104system.cpu0.dcache.overall_hits 82009 # number of overall hits 105system.cpu0.dcache.ReadReq_misses 151 # number of ReadReq misses 106system.cpu0.dcache.WriteReq_misses 177 # number of WriteReq misses 107system.cpu0.dcache.SwapReq_misses 27 # number of SwapReq misses 108system.cpu0.dcache.demand_misses 328 # number of demand (read+write) misses 109system.cpu0.dcache.overall_misses 328 # number of overall misses 110system.cpu0.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles 111system.cpu0.dcache.overall_miss_latency 0 # number of overall miss cycles 112system.cpu0.dcache.ReadReq_accesses 54582 # number of ReadReq accesses(hits+misses) 113system.cpu0.dcache.WriteReq_accesses 27755 # number of WriteReq accesses(hits+misses) 114system.cpu0.dcache.SwapReq_accesses 42 # number of SwapReq accesses(hits+misses) 115system.cpu0.dcache.demand_accesses 82337 # number of demand (read+write) accesses 116system.cpu0.dcache.overall_accesses 82337 # number of overall (read+write) accesses 117system.cpu0.dcache.ReadReq_miss_rate 0.002766 # miss rate for ReadReq accesses 118system.cpu0.dcache.WriteReq_miss_rate 0.006377 # miss rate for WriteReq accesses 119system.cpu0.dcache.SwapReq_miss_rate 0.642857 # miss rate for SwapReq accesses 120system.cpu0.dcache.demand_miss_rate 0.003984 # miss rate for demand accesses 121system.cpu0.dcache.overall_miss_rate 0.003984 # miss rate for overall accesses 122system.cpu0.dcache.demand_avg_miss_latency 0 # average overall miss latency 123system.cpu0.dcache.overall_avg_miss_latency 0 # average overall miss latency 124system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 125system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 126system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 127system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 128system.cpu0.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 129system.cpu0.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 130system.cpu0.dcache.fast_writes 0 # number of fast writes performed 131system.cpu0.dcache.cache_copies 0 # number of cache copies performed 132system.cpu0.dcache.writebacks 6 # number of writebacks 133system.cpu0.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 134system.cpu0.dcache.overall_mshr_hits 0 # number of overall MSHR hits 135system.cpu0.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses 136system.cpu0.dcache.overall_mshr_misses 0 # number of overall MSHR misses 137system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 138system.cpu0.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles 139system.cpu0.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles 140system.cpu0.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 141system.cpu0.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses 142system.cpu0.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses 143system.cpu0.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency 144system.cpu0.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency 145system.cpu0.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 146system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated 147system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 148system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 149system.cpu1.numCycles 173308 # number of cpu cycles simulated 150system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 151system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 152system.cpu1.num_insts 167398 # Number of instructions executed 153system.cpu1.num_int_alu_accesses 109926 # Number of integer alu accesses 154system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses 155system.cpu1.num_func_calls 633 # number of times a function call or return occured 156system.cpu1.num_conditional_control_insts 32743 # number of instructions that are conditional controls 157system.cpu1.num_int_insts 109926 # number of integer instructions 158system.cpu1.num_fp_insts 0 # number of float instructions 159system.cpu1.num_int_register_reads 270038 # number of times the integer registers were read 160system.cpu1.num_int_register_writes 100721 # number of times the integer registers were written 161system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read 162system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written 163system.cpu1.num_mem_refs 53394 # number of memory refs 164system.cpu1.num_load_insts 40652 # Number of load instructions 165system.cpu1.num_store_insts 12742 # Number of store instructions 166system.cpu1.num_idle_cycles 7886.574443 # Number of idle cycles 167system.cpu1.num_busy_cycles 165421.425557 # Number of busy cycles 168system.cpu1.not_idle_fraction 0.954494 # Percentage of non-idle cycles 169system.cpu1.idle_fraction 0.045506 # Percentage of idle cycles 170system.cpu1.icache.replacements 278 # number of replacements 171system.cpu1.icache.tagsinuse 76.746014 # Cycle average of tags in use 172system.cpu1.icache.total_refs 167072 # Total number of references to valid blocks. 173system.cpu1.icache.sampled_refs 358 # Sample count of references to valid blocks. 174system.cpu1.icache.avg_refs 466.681564 # Average number of references to valid blocks. 175system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 176system.cpu1.icache.occ_blocks::0 76.746014 # Average occupied blocks per context 177system.cpu1.icache.occ_percent::0 0.149895 # Average percentage of cache occupancy 178system.cpu1.icache.ReadReq_hits 167072 # number of ReadReq hits 179system.cpu1.icache.demand_hits 167072 # number of demand (read+write) hits 180system.cpu1.icache.overall_hits 167072 # number of overall hits 181system.cpu1.icache.ReadReq_misses 358 # number of ReadReq misses 182system.cpu1.icache.demand_misses 358 # number of demand (read+write) misses 183system.cpu1.icache.overall_misses 358 # number of overall misses 184system.cpu1.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles 185system.cpu1.icache.overall_miss_latency 0 # number of overall miss cycles 186system.cpu1.icache.ReadReq_accesses 167430 # number of ReadReq accesses(hits+misses) 187system.cpu1.icache.demand_accesses 167430 # number of demand (read+write) accesses 188system.cpu1.icache.overall_accesses 167430 # number of overall (read+write) accesses 189system.cpu1.icache.ReadReq_miss_rate 0.002138 # miss rate for ReadReq accesses 190system.cpu1.icache.demand_miss_rate 0.002138 # miss rate for demand accesses 191system.cpu1.icache.overall_miss_rate 0.002138 # miss rate for overall accesses 192system.cpu1.icache.demand_avg_miss_latency 0 # average overall miss latency 193system.cpu1.icache.overall_avg_miss_latency 0 # average overall miss latency 194system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 195system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 196system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 197system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 198system.cpu1.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 199system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 200system.cpu1.icache.fast_writes 0 # number of fast writes performed 201system.cpu1.icache.cache_copies 0 # number of cache copies performed 202system.cpu1.icache.writebacks 0 # number of writebacks 203system.cpu1.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 204system.cpu1.icache.overall_mshr_hits 0 # number of overall MSHR hits 205system.cpu1.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses 206system.cpu1.icache.overall_mshr_misses 0 # number of overall MSHR misses 207system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 208system.cpu1.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles 209system.cpu1.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles 210system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 211system.cpu1.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses 212system.cpu1.icache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses 213system.cpu1.icache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency 214system.cpu1.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency 215system.cpu1.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 216system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated 217system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 218system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 219system.cpu1.dcache.replacements 2 # number of replacements 220system.cpu1.dcache.tagsinuse 29.073016 # Cycle average of tags in use 221system.cpu1.dcache.total_refs 26889 # Total number of references to valid blocks. 222system.cpu1.dcache.sampled_refs 28 # Sample count of references to valid blocks. 223system.cpu1.dcache.avg_refs 960.321429 # Average number of references to valid blocks. 224system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 225system.cpu1.dcache.occ_blocks::0 29.073016 # Average occupied blocks per context 226system.cpu1.dcache.occ_percent::0 0.056783 # Average percentage of cache occupancy 227system.cpu1.dcache.ReadReq_hits 40468 # number of ReadReq hits 228system.cpu1.dcache.WriteReq_hits 12563 # number of WriteReq hits 229system.cpu1.dcache.SwapReq_hits 14 # number of SwapReq hits 230system.cpu1.dcache.demand_hits 53031 # number of demand (read+write) hits 231system.cpu1.dcache.overall_hits 53031 # number of overall hits 232system.cpu1.dcache.ReadReq_misses 176 # number of ReadReq misses 233system.cpu1.dcache.WriteReq_misses 106 # number of WriteReq misses 234system.cpu1.dcache.SwapReq_misses 57 # number of SwapReq misses 235system.cpu1.dcache.demand_misses 282 # number of demand (read+write) misses 236system.cpu1.dcache.overall_misses 282 # number of overall misses 237system.cpu1.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles 238system.cpu1.dcache.overall_miss_latency 0 # number of overall miss cycles 239system.cpu1.dcache.ReadReq_accesses 40644 # number of ReadReq accesses(hits+misses) 240system.cpu1.dcache.WriteReq_accesses 12669 # number of WriteReq accesses(hits+misses) 241system.cpu1.dcache.SwapReq_accesses 71 # number of SwapReq accesses(hits+misses) 242system.cpu1.dcache.demand_accesses 53313 # number of demand (read+write) accesses 243system.cpu1.dcache.overall_accesses 53313 # number of overall (read+write) accesses 244system.cpu1.dcache.ReadReq_miss_rate 0.004330 # miss rate for ReadReq accesses 245system.cpu1.dcache.WriteReq_miss_rate 0.008367 # miss rate for WriteReq accesses 246system.cpu1.dcache.SwapReq_miss_rate 0.802817 # miss rate for SwapReq accesses 247system.cpu1.dcache.demand_miss_rate 0.005290 # miss rate for demand accesses 248system.cpu1.dcache.overall_miss_rate 0.005290 # miss rate for overall accesses 249system.cpu1.dcache.demand_avg_miss_latency 0 # average overall miss latency 250system.cpu1.dcache.overall_avg_miss_latency 0 # average overall miss latency 251system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 252system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 253system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 254system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 255system.cpu1.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 256system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 257system.cpu1.dcache.fast_writes 0 # number of fast writes performed 258system.cpu1.dcache.cache_copies 0 # number of cache copies performed 259system.cpu1.dcache.writebacks 1 # number of writebacks 260system.cpu1.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 261system.cpu1.dcache.overall_mshr_hits 0 # number of overall MSHR hits 262system.cpu1.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses 263system.cpu1.dcache.overall_mshr_misses 0 # number of overall MSHR misses 264system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 265system.cpu1.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles 266system.cpu1.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles 267system.cpu1.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 268system.cpu1.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses 269system.cpu1.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses 270system.cpu1.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency 271system.cpu1.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency 272system.cpu1.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 273system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated 274system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 275system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 276system.cpu2.numCycles 173308 # number of cpu cycles simulated 277system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started 278system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed 279system.cpu2.num_insts 167334 # Number of instructions executed 280system.cpu2.num_int_alu_accesses 113333 # Number of integer alu accesses 281system.cpu2.num_fp_alu_accesses 0 # Number of float alu accesses 282system.cpu2.num_func_calls 633 # number of times a function call or return occured 283system.cpu2.num_conditional_control_insts 31007 # number of instructions that are conditional controls 284system.cpu2.num_int_insts 113333 # number of integer instructions 285system.cpu2.num_fp_insts 0 # number of float instructions 286system.cpu2.num_int_register_reads 290613 # number of times the integer registers were read 287system.cpu2.num_int_register_writes 109308 # number of times the integer registers were written 288system.cpu2.num_fp_register_reads 0 # number of times the floating registers were read 289system.cpu2.num_fp_register_writes 0 # number of times the floating registers were written 290system.cpu2.num_mem_refs 58537 # number of memory refs 291system.cpu2.num_load_insts 42362 # Number of load instructions 292system.cpu2.num_store_insts 16175 # Number of store instructions 293system.cpu2.num_idle_cycles 7949.801380 # Number of idle cycles 294system.cpu2.num_busy_cycles 165358.198620 # Number of busy cycles 295system.cpu2.not_idle_fraction 0.954129 # Percentage of non-idle cycles 296system.cpu2.idle_fraction 0.045871 # Percentage of idle cycles 297system.cpu2.icache.replacements 278 # number of replacements 298system.cpu2.icache.tagsinuse 74.775474 # Cycle average of tags in use 299system.cpu2.icache.total_refs 167008 # Total number of references to valid blocks. 300system.cpu2.icache.sampled_refs 358 # Sample count of references to valid blocks. 301system.cpu2.icache.avg_refs 466.502793 # Average number of references to valid blocks. 302system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 303system.cpu2.icache.occ_blocks::0 74.775474 # Average occupied blocks per context 304system.cpu2.icache.occ_percent::0 0.146046 # Average percentage of cache occupancy 305system.cpu2.icache.ReadReq_hits 167008 # number of ReadReq hits 306system.cpu2.icache.demand_hits 167008 # number of demand (read+write) hits 307system.cpu2.icache.overall_hits 167008 # number of overall hits 308system.cpu2.icache.ReadReq_misses 358 # number of ReadReq misses 309system.cpu2.icache.demand_misses 358 # number of demand (read+write) misses 310system.cpu2.icache.overall_misses 358 # number of overall misses 311system.cpu2.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles 312system.cpu2.icache.overall_miss_latency 0 # number of overall miss cycles 313system.cpu2.icache.ReadReq_accesses 167366 # number of ReadReq accesses(hits+misses) 314system.cpu2.icache.demand_accesses 167366 # number of demand (read+write) accesses 315system.cpu2.icache.overall_accesses 167366 # number of overall (read+write) accesses 316system.cpu2.icache.ReadReq_miss_rate 0.002139 # miss rate for ReadReq accesses 317system.cpu2.icache.demand_miss_rate 0.002139 # miss rate for demand accesses 318system.cpu2.icache.overall_miss_rate 0.002139 # miss rate for overall accesses 319system.cpu2.icache.demand_avg_miss_latency 0 # average overall miss latency 320system.cpu2.icache.overall_avg_miss_latency 0 # average overall miss latency 321system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 322system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 323system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked 324system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked 325system.cpu2.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 326system.cpu2.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 327system.cpu2.icache.fast_writes 0 # number of fast writes performed 328system.cpu2.icache.cache_copies 0 # number of cache copies performed 329system.cpu2.icache.writebacks 0 # number of writebacks 330system.cpu2.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 331system.cpu2.icache.overall_mshr_hits 0 # number of overall MSHR hits 332system.cpu2.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses 333system.cpu2.icache.overall_mshr_misses 0 # number of overall MSHR misses 334system.cpu2.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 335system.cpu2.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles 336system.cpu2.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles 337system.cpu2.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 338system.cpu2.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses 339system.cpu2.icache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses 340system.cpu2.icache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency 341system.cpu2.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency 342system.cpu2.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 343system.cpu2.icache.mshr_cap_events 0 # number of times MSHR cap was activated 344system.cpu2.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 345system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate 346system.cpu2.dcache.replacements 2 # number of replacements 347system.cpu2.dcache.tagsinuse 28.420699 # Cycle average of tags in use 348system.cpu2.dcache.total_refs 33771 # Total number of references to valid blocks. 349system.cpu2.dcache.sampled_refs 28 # Sample count of references to valid blocks. 350system.cpu2.dcache.avg_refs 1206.107143 # Average number of references to valid blocks. 351system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 352system.cpu2.dcache.occ_blocks::0 28.420699 # Average occupied blocks per context 353system.cpu2.dcache.occ_percent::0 0.055509 # Average percentage of cache occupancy 354system.cpu2.dcache.ReadReq_hits 42192 # number of ReadReq hits 355system.cpu2.dcache.WriteReq_hits 15998 # number of WriteReq hits 356system.cpu2.dcache.SwapReq_hits 11 # number of SwapReq hits 357system.cpu2.dcache.demand_hits 58190 # number of demand (read+write) hits 358system.cpu2.dcache.overall_hits 58190 # number of overall hits 359system.cpu2.dcache.ReadReq_misses 162 # number of ReadReq misses 360system.cpu2.dcache.WriteReq_misses 109 # number of WriteReq misses 361system.cpu2.dcache.SwapReq_misses 55 # number of SwapReq misses 362system.cpu2.dcache.demand_misses 271 # number of demand (read+write) misses 363system.cpu2.dcache.overall_misses 271 # number of overall misses 364system.cpu2.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles 365system.cpu2.dcache.overall_miss_latency 0 # number of overall miss cycles 366system.cpu2.dcache.ReadReq_accesses 42354 # number of ReadReq accesses(hits+misses) 367system.cpu2.dcache.WriteReq_accesses 16107 # number of WriteReq accesses(hits+misses) 368system.cpu2.dcache.SwapReq_accesses 66 # number of SwapReq accesses(hits+misses) 369system.cpu2.dcache.demand_accesses 58461 # number of demand (read+write) accesses 370system.cpu2.dcache.overall_accesses 58461 # number of overall (read+write) accesses 371system.cpu2.dcache.ReadReq_miss_rate 0.003825 # miss rate for ReadReq accesses 372system.cpu2.dcache.WriteReq_miss_rate 0.006767 # miss rate for WriteReq accesses 373system.cpu2.dcache.SwapReq_miss_rate 0.833333 # miss rate for SwapReq accesses 374system.cpu2.dcache.demand_miss_rate 0.004636 # miss rate for demand accesses 375system.cpu2.dcache.overall_miss_rate 0.004636 # miss rate for overall accesses 376system.cpu2.dcache.demand_avg_miss_latency 0 # average overall miss latency 377system.cpu2.dcache.overall_avg_miss_latency 0 # average overall miss latency 378system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 379system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 380system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 381system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked 382system.cpu2.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 383system.cpu2.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 384system.cpu2.dcache.fast_writes 0 # number of fast writes performed 385system.cpu2.dcache.cache_copies 0 # number of cache copies performed 386system.cpu2.dcache.writebacks 1 # number of writebacks 387system.cpu2.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 388system.cpu2.dcache.overall_mshr_hits 0 # number of overall MSHR hits 389system.cpu2.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses 390system.cpu2.dcache.overall_mshr_misses 0 # number of overall MSHR misses 391system.cpu2.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 392system.cpu2.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles 393system.cpu2.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles 394system.cpu2.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 395system.cpu2.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses 396system.cpu2.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses 397system.cpu2.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency 398system.cpu2.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency 399system.cpu2.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 400system.cpu2.dcache.mshr_cap_events 0 # number of times MSHR cap was activated 401system.cpu2.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 402system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 403system.cpu3.numCycles 173307 # number of cpu cycles simulated 404system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started 405system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed 406system.cpu3.num_insts 167269 # Number of instructions executed 407system.cpu3.num_int_alu_accesses 111554 # Number of integer alu accesses 408system.cpu3.num_fp_alu_accesses 0 # Number of float alu accesses 409system.cpu3.num_func_calls 633 # number of times a function call or return occured 410system.cpu3.num_conditional_control_insts 31865 # number of instructions that are conditional controls 411system.cpu3.num_int_insts 111554 # number of integer instructions 412system.cpu3.num_fp_insts 0 # number of float instructions 413system.cpu3.num_int_register_reads 280060 # number of times the integer registers were read 414system.cpu3.num_int_register_writes 104916 # number of times the integer registers were written 415system.cpu3.num_fp_register_reads 0 # number of times the floating registers were read 416system.cpu3.num_fp_register_writes 0 # number of times the floating registers were written 417system.cpu3.num_mem_refs 55900 # number of memory refs 418system.cpu3.num_load_insts 41466 # Number of load instructions 419system.cpu3.num_store_insts 14434 # Number of store instructions 420system.cpu3.num_idle_cycles 8013.969997 # Number of idle cycles 421system.cpu3.num_busy_cycles 165293.030003 # Number of busy cycles 422system.cpu3.not_idle_fraction 0.953759 # Percentage of non-idle cycles 423system.cpu3.idle_fraction 0.046241 # Percentage of idle cycles 424system.cpu3.icache.replacements 279 # number of replacements 425system.cpu3.icache.tagsinuse 72.869097 # Cycle average of tags in use 426system.cpu3.icache.total_refs 166942 # Total number of references to valid blocks. 427system.cpu3.icache.sampled_refs 359 # Sample count of references to valid blocks. 428system.cpu3.icache.avg_refs 465.019499 # Average number of references to valid blocks. 429system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 430system.cpu3.icache.occ_blocks::0 72.869097 # Average occupied blocks per context 431system.cpu3.icache.occ_percent::0 0.142322 # Average percentage of cache occupancy 432system.cpu3.icache.ReadReq_hits 166942 # number of ReadReq hits 433system.cpu3.icache.demand_hits 166942 # number of demand (read+write) hits 434system.cpu3.icache.overall_hits 166942 # number of overall hits 435system.cpu3.icache.ReadReq_misses 359 # number of ReadReq misses 436system.cpu3.icache.demand_misses 359 # number of demand (read+write) misses 437system.cpu3.icache.overall_misses 359 # number of overall misses 438system.cpu3.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles 439system.cpu3.icache.overall_miss_latency 0 # number of overall miss cycles 440system.cpu3.icache.ReadReq_accesses 167301 # number of ReadReq accesses(hits+misses) 441system.cpu3.icache.demand_accesses 167301 # number of demand (read+write) accesses 442system.cpu3.icache.overall_accesses 167301 # number of overall (read+write) accesses 443system.cpu3.icache.ReadReq_miss_rate 0.002146 # miss rate for ReadReq accesses 444system.cpu3.icache.demand_miss_rate 0.002146 # miss rate for demand accesses 445system.cpu3.icache.overall_miss_rate 0.002146 # miss rate for overall accesses 446system.cpu3.icache.demand_avg_miss_latency 0 # average overall miss latency 447system.cpu3.icache.overall_avg_miss_latency 0 # average overall miss latency 448system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 449system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 450system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked 451system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked 452system.cpu3.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 453system.cpu3.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 454system.cpu3.icache.fast_writes 0 # number of fast writes performed 455system.cpu3.icache.cache_copies 0 # number of cache copies performed 456system.cpu3.icache.writebacks 0 # number of writebacks 457system.cpu3.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 458system.cpu3.icache.overall_mshr_hits 0 # number of overall MSHR hits 459system.cpu3.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses 460system.cpu3.icache.overall_mshr_misses 0 # number of overall MSHR misses 461system.cpu3.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 462system.cpu3.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles 463system.cpu3.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles 464system.cpu3.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 465system.cpu3.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses 466system.cpu3.icache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses 467system.cpu3.icache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency 468system.cpu3.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency 469system.cpu3.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 470system.cpu3.icache.mshr_cap_events 0 # number of times MSHR cap was activated 471system.cpu3.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 472system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate 473system.cpu3.dcache.replacements 2 # number of replacements 474system.cpu3.dcache.tagsinuse 27.588376 # Cycle average of tags in use 475system.cpu3.dcache.total_refs 30309 # Total number of references to valid blocks. 476system.cpu3.dcache.sampled_refs 29 # Sample count of references to valid blocks. 477system.cpu3.dcache.avg_refs 1045.137931 # Average number of references to valid blocks. 478system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 479system.cpu3.dcache.occ_blocks::0 27.588376 # Average occupied blocks per context 480system.cpu3.dcache.occ_percent::0 0.053884 # Average percentage of cache occupancy 481system.cpu3.dcache.ReadReq_hits 41299 # number of ReadReq hits 482system.cpu3.dcache.WriteReq_hits 14260 # number of WriteReq hits 483system.cpu3.dcache.SwapReq_hits 15 # number of SwapReq hits 484system.cpu3.dcache.demand_hits 55559 # number of demand (read+write) hits 485system.cpu3.dcache.overall_hits 55559 # number of overall hits 486system.cpu3.dcache.ReadReq_misses 159 # number of ReadReq misses 487system.cpu3.dcache.WriteReq_misses 102 # number of WriteReq misses 488system.cpu3.dcache.SwapReq_misses 55 # number of SwapReq misses 489system.cpu3.dcache.demand_misses 261 # number of demand (read+write) misses 490system.cpu3.dcache.overall_misses 261 # number of overall misses 491system.cpu3.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles 492system.cpu3.dcache.overall_miss_latency 0 # number of overall miss cycles 493system.cpu3.dcache.ReadReq_accesses 41458 # number of ReadReq accesses(hits+misses) 494system.cpu3.dcache.WriteReq_accesses 14362 # number of WriteReq accesses(hits+misses) 495system.cpu3.dcache.SwapReq_accesses 70 # number of SwapReq accesses(hits+misses) 496system.cpu3.dcache.demand_accesses 55820 # number of demand (read+write) accesses 497system.cpu3.dcache.overall_accesses 55820 # number of overall (read+write) accesses 498system.cpu3.dcache.ReadReq_miss_rate 0.003835 # miss rate for ReadReq accesses 499system.cpu3.dcache.WriteReq_miss_rate 0.007102 # miss rate for WriteReq accesses 500system.cpu3.dcache.SwapReq_miss_rate 0.785714 # miss rate for SwapReq accesses 501system.cpu3.dcache.demand_miss_rate 0.004676 # miss rate for demand accesses 502system.cpu3.dcache.overall_miss_rate 0.004676 # miss rate for overall accesses 503system.cpu3.dcache.demand_avg_miss_latency 0 # average overall miss latency 504system.cpu3.dcache.overall_avg_miss_latency 0 # average overall miss latency 505system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 506system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 507system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 508system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked 509system.cpu3.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 510system.cpu3.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 511system.cpu3.dcache.fast_writes 0 # number of fast writes performed 512system.cpu3.dcache.cache_copies 0 # number of cache copies performed 513system.cpu3.dcache.writebacks 1 # number of writebacks 514system.cpu3.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 515system.cpu3.dcache.overall_mshr_hits 0 # number of overall MSHR hits 516system.cpu3.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses 517system.cpu3.dcache.overall_mshr_misses 0 # number of overall MSHR misses 518system.cpu3.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 519system.cpu3.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles 520system.cpu3.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles 521system.cpu3.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 522system.cpu3.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses 523system.cpu3.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses 524system.cpu3.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency 525system.cpu3.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency 526system.cpu3.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 527system.cpu3.dcache.mshr_cap_events 0 # number of times MSHR cap was activated 528system.cpu3.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 529system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 530system.l2c.replacements 0 # number of replacements 531system.l2c.tagsinuse 371.980910 # Cycle average of tags in use 532system.l2c.total_refs 1223 # Total number of references to valid blocks. 533system.l2c.sampled_refs 426 # Sample count of references to valid blocks. 534system.l2c.avg_refs 2.870892 # Average number of references to valid blocks. 535system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. 536system.l2c.occ_blocks::0 294.613840 # Average occupied blocks per context 537system.l2c.occ_blocks::1 66.228089 # Average occupied blocks per context 538system.l2c.occ_blocks::2 2.865859 # Average occupied blocks per context 539system.l2c.occ_blocks::3 1.883074 # Average occupied blocks per context 540system.l2c.occ_blocks::4 6.390048 # Average occupied blocks per context 541system.l2c.occ_percent::0 0.004495 # Average percentage of cache occupancy 542system.l2c.occ_percent::1 0.001011 # Average percentage of cache occupancy 543system.l2c.occ_percent::2 0.000044 # Average percentage of cache occupancy 544system.l2c.occ_percent::3 0.000029 # Average percentage of cache occupancy 545system.l2c.occ_percent::4 0.000098 # Average percentage of cache occupancy 546system.l2c.ReadReq_hits::0 190 # number of ReadReq hits 547system.l2c.ReadReq_hits::1 301 # number of ReadReq hits 548system.l2c.ReadReq_hits::2 367 # number of ReadReq hits 549system.l2c.ReadReq_hits::3 368 # number of ReadReq hits 550system.l2c.ReadReq_hits::total 1226 # number of ReadReq hits 551system.l2c.Writeback_hits::0 9 # number of Writeback hits 552system.l2c.Writeback_hits::total 9 # number of Writeback hits 553system.l2c.UpgradeReq_hits::0 2 # number of UpgradeReq hits 554system.l2c.UpgradeReq_hits::total 2 # number of UpgradeReq hits 555system.l2c.demand_hits::0 190 # number of demand (read+write) hits 556system.l2c.demand_hits::1 301 # number of demand (read+write) hits 557system.l2c.demand_hits::2 367 # number of demand (read+write) hits 558system.l2c.demand_hits::3 368 # number of demand (read+write) hits 559system.l2c.demand_hits::total 1226 # number of demand (read+write) hits 560system.l2c.overall_hits::0 190 # number of overall hits 561system.l2c.overall_hits::1 301 # number of overall hits 562system.l2c.overall_hits::2 367 # number of overall hits 563system.l2c.overall_hits::3 368 # number of overall hits 564system.l2c.overall_hits::total 1226 # number of overall hits 565system.l2c.ReadReq_misses::0 348 # number of ReadReq misses 566system.l2c.ReadReq_misses::1 69 # number of ReadReq misses 567system.l2c.ReadReq_misses::2 3 # number of ReadReq misses 568system.l2c.ReadReq_misses::3 3 # number of ReadReq misses 569system.l2c.ReadReq_misses::total 423 # number of ReadReq misses 570system.l2c.UpgradeReq_misses::0 29 # number of UpgradeReq misses 571system.l2c.UpgradeReq_misses::1 19 # number of UpgradeReq misses 572system.l2c.UpgradeReq_misses::2 20 # number of UpgradeReq misses 573system.l2c.UpgradeReq_misses::3 19 # number of UpgradeReq misses 574system.l2c.UpgradeReq_misses::total 87 # number of UpgradeReq misses 575system.l2c.ReadExReq_misses::0 99 # number of ReadExReq misses 576system.l2c.ReadExReq_misses::1 13 # number of ReadExReq misses 577system.l2c.ReadExReq_misses::2 12 # number of ReadExReq misses 578system.l2c.ReadExReq_misses::3 12 # number of ReadExReq misses 579system.l2c.ReadExReq_misses::total 136 # number of ReadExReq misses 580system.l2c.demand_misses::0 447 # number of demand (read+write) misses 581system.l2c.demand_misses::1 82 # number of demand (read+write) misses 582system.l2c.demand_misses::2 15 # number of demand (read+write) misses 583system.l2c.demand_misses::3 15 # number of demand (read+write) misses 584system.l2c.demand_misses::total 559 # number of demand (read+write) misses 585system.l2c.overall_misses::0 447 # number of overall misses 586system.l2c.overall_misses::1 82 # number of overall misses 587system.l2c.overall_misses::2 15 # number of overall misses 588system.l2c.overall_misses::3 15 # number of overall misses 589system.l2c.overall_misses::total 559 # number of overall misses 590system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles 591system.l2c.overall_miss_latency 0 # number of overall miss cycles 592system.l2c.ReadReq_accesses::0 538 # number of ReadReq accesses(hits+misses) 593system.l2c.ReadReq_accesses::1 370 # number of ReadReq accesses(hits+misses) 594system.l2c.ReadReq_accesses::2 370 # number of ReadReq accesses(hits+misses) 595system.l2c.ReadReq_accesses::3 371 # number of ReadReq accesses(hits+misses) 596system.l2c.ReadReq_accesses::total 1649 # number of ReadReq accesses(hits+misses) 597system.l2c.Writeback_accesses::0 9 # number of Writeback accesses(hits+misses) 598system.l2c.Writeback_accesses::total 9 # number of Writeback accesses(hits+misses) 599system.l2c.UpgradeReq_accesses::0 31 # number of UpgradeReq accesses(hits+misses) 600system.l2c.UpgradeReq_accesses::1 19 # number of UpgradeReq accesses(hits+misses) 601system.l2c.UpgradeReq_accesses::2 20 # number of UpgradeReq accesses(hits+misses) 602system.l2c.UpgradeReq_accesses::3 19 # number of UpgradeReq accesses(hits+misses) 603system.l2c.UpgradeReq_accesses::total 89 # number of UpgradeReq accesses(hits+misses) 604system.l2c.ReadExReq_accesses::0 99 # number of ReadExReq accesses(hits+misses) 605system.l2c.ReadExReq_accesses::1 13 # number of ReadExReq accesses(hits+misses) 606system.l2c.ReadExReq_accesses::2 12 # number of ReadExReq accesses(hits+misses) 607system.l2c.ReadExReq_accesses::3 12 # number of ReadExReq accesses(hits+misses) 608system.l2c.ReadExReq_accesses::total 136 # number of ReadExReq accesses(hits+misses) 609system.l2c.demand_accesses::0 637 # number of demand (read+write) accesses 610system.l2c.demand_accesses::1 383 # number of demand (read+write) accesses 611system.l2c.demand_accesses::2 382 # number of demand (read+write) accesses 612system.l2c.demand_accesses::3 383 # number of demand (read+write) accesses 613system.l2c.demand_accesses::total 1785 # number of demand (read+write) accesses 614system.l2c.overall_accesses::0 637 # number of overall (read+write) accesses 615system.l2c.overall_accesses::1 383 # number of overall (read+write) accesses 616system.l2c.overall_accesses::2 382 # number of overall (read+write) accesses 617system.l2c.overall_accesses::3 383 # number of overall (read+write) accesses 618system.l2c.overall_accesses::total 1785 # number of overall (read+write) accesses 619system.l2c.ReadReq_miss_rate::0 0.646840 # miss rate for ReadReq accesses 620system.l2c.ReadReq_miss_rate::1 0.186486 # miss rate for ReadReq accesses 621system.l2c.ReadReq_miss_rate::2 0.008108 # miss rate for ReadReq accesses 622system.l2c.ReadReq_miss_rate::3 0.008086 # miss rate for ReadReq accesses 623system.l2c.ReadReq_miss_rate::total 0.849521 # miss rate for ReadReq accesses 624system.l2c.UpgradeReq_miss_rate::0 0.935484 # miss rate for UpgradeReq accesses 625system.l2c.UpgradeReq_miss_rate::1 1 # miss rate for UpgradeReq accesses 626system.l2c.UpgradeReq_miss_rate::2 1 # miss rate for UpgradeReq accesses 627system.l2c.UpgradeReq_miss_rate::3 1 # miss rate for UpgradeReq accesses 628system.l2c.UpgradeReq_miss_rate::total 3.935484 # miss rate for UpgradeReq accesses 629system.l2c.ReadExReq_miss_rate::0 1 # miss rate for ReadExReq accesses 630system.l2c.ReadExReq_miss_rate::1 1 # miss rate for ReadExReq accesses 631system.l2c.ReadExReq_miss_rate::2 1 # miss rate for ReadExReq accesses 632system.l2c.ReadExReq_miss_rate::3 1 # miss rate for ReadExReq accesses 633system.l2c.ReadExReq_miss_rate::total 4 # miss rate for ReadExReq accesses 634system.l2c.demand_miss_rate::0 0.701727 # miss rate for demand accesses 635system.l2c.demand_miss_rate::1 0.214099 # miss rate for demand accesses 636system.l2c.demand_miss_rate::2 0.039267 # miss rate for demand accesses 637system.l2c.demand_miss_rate::3 0.039164 # miss rate for demand accesses 638system.l2c.demand_miss_rate::total 0.994258 # miss rate for demand accesses 639system.l2c.overall_miss_rate::0 0.701727 # miss rate for overall accesses 640system.l2c.overall_miss_rate::1 0.214099 # miss rate for overall accesses 641system.l2c.overall_miss_rate::2 0.039267 # miss rate for overall accesses 642system.l2c.overall_miss_rate::3 0.039164 # miss rate for overall accesses 643system.l2c.overall_miss_rate::total 0.994258 # miss rate for overall accesses 644system.l2c.demand_avg_miss_latency::0 0 # average overall miss latency 645system.l2c.demand_avg_miss_latency::1 0 # average overall miss latency 646system.l2c.demand_avg_miss_latency::2 0 # average overall miss latency 647system.l2c.demand_avg_miss_latency::3 0 # average overall miss latency 648system.l2c.demand_avg_miss_latency::total 0 # average overall miss latency 649system.l2c.overall_avg_miss_latency::0 0 # average overall miss latency 650system.l2c.overall_avg_miss_latency::1 0 # average overall miss latency 651system.l2c.overall_avg_miss_latency::2 0 # average overall miss latency 652system.l2c.overall_avg_miss_latency::3 0 # average overall miss latency 653system.l2c.overall_avg_miss_latency::total 0 # average overall miss latency 654system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 655system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 656system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 657system.l2c.blocked::no_targets 0 # number of cycles access was blocked 658system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 659system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 660system.l2c.fast_writes 0 # number of fast writes performed 661system.l2c.cache_copies 0 # number of cache copies performed 662system.l2c.writebacks 0 # number of writebacks 663system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 664system.l2c.overall_mshr_hits 0 # number of overall MSHR hits 665system.l2c.demand_mshr_misses 0 # number of demand (read+write) MSHR misses 666system.l2c.overall_mshr_misses 0 # number of overall MSHR misses 667system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 668system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles 669system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles 670system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 671system.l2c.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses 672system.l2c.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses 673system.l2c.demand_mshr_miss_rate::2 0 # mshr miss rate for demand accesses 674system.l2c.demand_mshr_miss_rate::3 0 # mshr miss rate for demand accesses 675system.l2c.demand_mshr_miss_rate::total 0 # mshr miss rate for demand accesses 676system.l2c.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses 677system.l2c.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses 678system.l2c.overall_mshr_miss_rate::2 0 # mshr miss rate for overall accesses 679system.l2c.overall_mshr_miss_rate::3 0 # mshr miss rate for overall accesses 680system.l2c.overall_mshr_miss_rate::total 0 # mshr miss rate for overall accesses 681system.l2c.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency 682system.l2c.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency 683system.l2c.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 684system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated 685system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 686system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 687 688---------- End Simulation Statistics ---------- 689