stats.txt revision 11507
111507SCurtis.Dunham@arm.com 211507SCurtis.Dunham@arm.com---------- Begin Simulation Statistics ---------- 311507SCurtis.Dunham@arm.comsim_seconds 0.000088 # Number of seconds simulated 411507SCurtis.Dunham@arm.comsim_ticks 87707000 # Number of ticks simulated 511507SCurtis.Dunham@arm.comfinal_tick 87707000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 611507SCurtis.Dunham@arm.comsim_freq 1000000000000 # Frequency of simulated ticks 711507SCurtis.Dunham@arm.comhost_inst_rate 856943 # Simulator instruction rate (inst/s) 811507SCurtis.Dunham@arm.comhost_op_rate 856930 # Simulator op (including micro ops) rate (op/s) 911507SCurtis.Dunham@arm.comhost_tick_rate 110961270 # Simulator tick rate (ticks/s) 1011507SCurtis.Dunham@arm.comhost_mem_usage 258436 # Number of bytes of host memory used 1111507SCurtis.Dunham@arm.comhost_seconds 0.79 # Real time elapsed on the host 1211507SCurtis.Dunham@arm.comsim_insts 677333 # Number of instructions simulated 1311507SCurtis.Dunham@arm.comsim_ops 677333 # Number of ops (including micro ops) simulated 1411507SCurtis.Dunham@arm.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1511507SCurtis.Dunham@arm.comsystem.clk_domain.clock 1000 # Clock period in ticks 1611507SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu0.inst 18048 # Number of bytes read from this memory 1711507SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu0.data 10560 # Number of bytes read from this memory 1811507SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu1.inst 3968 # Number of bytes read from this memory 1911507SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu1.data 1280 # Number of bytes read from this memory 2011507SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu2.inst 192 # Number of bytes read from this memory 2111507SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu2.data 832 # Number of bytes read from this memory 2211507SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu3.inst 64 # Number of bytes read from this memory 2311507SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu3.data 832 # Number of bytes read from this memory 2411507SCurtis.Dunham@arm.comsystem.physmem.bytes_read::total 35776 # Number of bytes read from this memory 2511507SCurtis.Dunham@arm.comsystem.physmem.bytes_inst_read::cpu0.inst 18048 # Number of instructions bytes read from this memory 2611507SCurtis.Dunham@arm.comsystem.physmem.bytes_inst_read::cpu1.inst 3968 # Number of instructions bytes read from this memory 2711507SCurtis.Dunham@arm.comsystem.physmem.bytes_inst_read::cpu2.inst 192 # Number of instructions bytes read from this memory 2811507SCurtis.Dunham@arm.comsystem.physmem.bytes_inst_read::cpu3.inst 64 # Number of instructions bytes read from this memory 2911507SCurtis.Dunham@arm.comsystem.physmem.bytes_inst_read::total 22272 # Number of instructions bytes read from this memory 3011507SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu0.inst 282 # Number of read requests responded to by this memory 3111507SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu0.data 165 # Number of read requests responded to by this memory 3211507SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu1.inst 62 # Number of read requests responded to by this memory 3311507SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu1.data 20 # Number of read requests responded to by this memory 3411507SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu2.inst 3 # Number of read requests responded to by this memory 3511507SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu2.data 13 # Number of read requests responded to by this memory 3611507SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu3.inst 1 # Number of read requests responded to by this memory 3711507SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu3.data 13 # Number of read requests responded to by this memory 3811507SCurtis.Dunham@arm.comsystem.physmem.num_reads::total 559 # Number of read requests responded to by this memory 3911507SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu0.inst 205776050 # Total read bandwidth from this memory (bytes/s) 4011507SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu0.data 120400880 # Total read bandwidth from this memory (bytes/s) 4111507SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu1.inst 45241543 # Total read bandwidth from this memory (bytes/s) 4211507SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu1.data 14594046 # Total read bandwidth from this memory (bytes/s) 4311507SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu2.inst 2189107 # Total read bandwidth from this memory (bytes/s) 4411507SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu2.data 9486130 # Total read bandwidth from this memory (bytes/s) 4511507SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu3.inst 729702 # Total read bandwidth from this memory (bytes/s) 4611507SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu3.data 9486130 # Total read bandwidth from this memory (bytes/s) 4711507SCurtis.Dunham@arm.comsystem.physmem.bw_read::total 407903588 # Total read bandwidth from this memory (bytes/s) 4811507SCurtis.Dunham@arm.comsystem.physmem.bw_inst_read::cpu0.inst 205776050 # Instruction read bandwidth from this memory (bytes/s) 4911507SCurtis.Dunham@arm.comsystem.physmem.bw_inst_read::cpu1.inst 45241543 # Instruction read bandwidth from this memory (bytes/s) 5011507SCurtis.Dunham@arm.comsystem.physmem.bw_inst_read::cpu2.inst 2189107 # Instruction read bandwidth from this memory (bytes/s) 5111507SCurtis.Dunham@arm.comsystem.physmem.bw_inst_read::cpu3.inst 729702 # Instruction read bandwidth from this memory (bytes/s) 5211507SCurtis.Dunham@arm.comsystem.physmem.bw_inst_read::total 253936402 # Instruction read bandwidth from this memory (bytes/s) 5311507SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu0.inst 205776050 # Total bandwidth to/from this memory (bytes/s) 5411507SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu0.data 120400880 # Total bandwidth to/from this memory (bytes/s) 5511507SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu1.inst 45241543 # Total bandwidth to/from this memory (bytes/s) 5611507SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu1.data 14594046 # Total bandwidth to/from this memory (bytes/s) 5711507SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu2.inst 2189107 # Total bandwidth to/from this memory (bytes/s) 5811507SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu2.data 9486130 # Total bandwidth to/from this memory (bytes/s) 5911507SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu3.inst 729702 # Total bandwidth to/from this memory (bytes/s) 6011507SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu3.data 9486130 # Total bandwidth to/from this memory (bytes/s) 6111507SCurtis.Dunham@arm.comsystem.physmem.bw_total::total 407903588 # Total bandwidth to/from this memory (bytes/s) 6211507SCurtis.Dunham@arm.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 6311507SCurtis.Dunham@arm.comsystem.cpu0.workload.num_syscalls 89 # Number of system calls 6411507SCurtis.Dunham@arm.comsystem.cpu0.numCycles 175415 # number of cpu cycles simulated 6511507SCurtis.Dunham@arm.comsystem.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 6611507SCurtis.Dunham@arm.comsystem.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 6711507SCurtis.Dunham@arm.comsystem.cpu0.committedInsts 175326 # Number of instructions committed 6811507SCurtis.Dunham@arm.comsystem.cpu0.committedOps 175326 # Number of ops (including micro ops) committed 6911507SCurtis.Dunham@arm.comsystem.cpu0.num_int_alu_accesses 120376 # Number of integer alu accesses 7011507SCurtis.Dunham@arm.comsystem.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses 7111507SCurtis.Dunham@arm.comsystem.cpu0.num_func_calls 390 # number of times a function call or return occured 7211507SCurtis.Dunham@arm.comsystem.cpu0.num_conditional_control_insts 28824 # number of instructions that are conditional controls 7311507SCurtis.Dunham@arm.comsystem.cpu0.num_int_insts 120376 # number of integer instructions 7411507SCurtis.Dunham@arm.comsystem.cpu0.num_fp_insts 0 # number of float instructions 7511507SCurtis.Dunham@arm.comsystem.cpu0.num_int_register_reads 349286 # number of times the integer registers were read 7611507SCurtis.Dunham@arm.comsystem.cpu0.num_int_register_writes 121983 # number of times the integer registers were written 7711507SCurtis.Dunham@arm.comsystem.cpu0.num_fp_register_reads 0 # number of times the floating registers were read 7811507SCurtis.Dunham@arm.comsystem.cpu0.num_fp_register_writes 0 # number of times the floating registers were written 7911507SCurtis.Dunham@arm.comsystem.cpu0.num_mem_refs 82397 # number of memory refs 8011507SCurtis.Dunham@arm.comsystem.cpu0.num_load_insts 54591 # Number of load instructions 8111507SCurtis.Dunham@arm.comsystem.cpu0.num_store_insts 27806 # Number of store instructions 8211507SCurtis.Dunham@arm.comsystem.cpu0.num_idle_cycles 0.002000 # Number of idle cycles 8311507SCurtis.Dunham@arm.comsystem.cpu0.num_busy_cycles 175414.998000 # Number of busy cycles 8411507SCurtis.Dunham@arm.comsystem.cpu0.not_idle_fraction 1.000000 # Percentage of non-idle cycles 8511507SCurtis.Dunham@arm.comsystem.cpu0.idle_fraction 0.000000 # Percentage of idle cycles 8611507SCurtis.Dunham@arm.comsystem.cpu0.Branches 29689 # Number of branches fetched 8711507SCurtis.Dunham@arm.comsystem.cpu0.op_class::No_OpClass 26416 15.06% 15.06% # Class of executed instruction 8811507SCurtis.Dunham@arm.comsystem.cpu0.op_class::IntAlu 66491 37.91% 52.97% # Class of executed instruction 8911507SCurtis.Dunham@arm.comsystem.cpu0.op_class::IntMult 0 0.00% 52.97% # Class of executed instruction 9011507SCurtis.Dunham@arm.comsystem.cpu0.op_class::IntDiv 0 0.00% 52.97% # Class of executed instruction 9111507SCurtis.Dunham@arm.comsystem.cpu0.op_class::FloatAdd 0 0.00% 52.97% # Class of executed instruction 9211507SCurtis.Dunham@arm.comsystem.cpu0.op_class::FloatCmp 0 0.00% 52.97% # Class of executed instruction 9311507SCurtis.Dunham@arm.comsystem.cpu0.op_class::FloatCvt 0 0.00% 52.97% # Class of executed instruction 9411507SCurtis.Dunham@arm.comsystem.cpu0.op_class::FloatMult 0 0.00% 52.97% # Class of executed instruction 9511507SCurtis.Dunham@arm.comsystem.cpu0.op_class::FloatDiv 0 0.00% 52.97% # Class of executed instruction 9611507SCurtis.Dunham@arm.comsystem.cpu0.op_class::FloatSqrt 0 0.00% 52.97% # Class of executed instruction 9711507SCurtis.Dunham@arm.comsystem.cpu0.op_class::SimdAdd 0 0.00% 52.97% # Class of executed instruction 9811507SCurtis.Dunham@arm.comsystem.cpu0.op_class::SimdAddAcc 0 0.00% 52.97% # Class of executed instruction 9911507SCurtis.Dunham@arm.comsystem.cpu0.op_class::SimdAlu 0 0.00% 52.97% # Class of executed instruction 10011507SCurtis.Dunham@arm.comsystem.cpu0.op_class::SimdCmp 0 0.00% 52.97% # Class of executed instruction 10111507SCurtis.Dunham@arm.comsystem.cpu0.op_class::SimdCvt 0 0.00% 52.97% # Class of executed instruction 10211507SCurtis.Dunham@arm.comsystem.cpu0.op_class::SimdMisc 0 0.00% 52.97% # Class of executed instruction 10311507SCurtis.Dunham@arm.comsystem.cpu0.op_class::SimdMult 0 0.00% 52.97% # Class of executed instruction 10411507SCurtis.Dunham@arm.comsystem.cpu0.op_class::SimdMultAcc 0 0.00% 52.97% # Class of executed instruction 10511507SCurtis.Dunham@arm.comsystem.cpu0.op_class::SimdShift 0 0.00% 52.97% # Class of executed instruction 10611507SCurtis.Dunham@arm.comsystem.cpu0.op_class::SimdShiftAcc 0 0.00% 52.97% # Class of executed instruction 10711507SCurtis.Dunham@arm.comsystem.cpu0.op_class::SimdSqrt 0 0.00% 52.97% # Class of executed instruction 10811507SCurtis.Dunham@arm.comsystem.cpu0.op_class::SimdFloatAdd 0 0.00% 52.97% # Class of executed instruction 10911507SCurtis.Dunham@arm.comsystem.cpu0.op_class::SimdFloatAlu 0 0.00% 52.97% # Class of executed instruction 11011507SCurtis.Dunham@arm.comsystem.cpu0.op_class::SimdFloatCmp 0 0.00% 52.97% # Class of executed instruction 11111507SCurtis.Dunham@arm.comsystem.cpu0.op_class::SimdFloatCvt 0 0.00% 52.97% # Class of executed instruction 11211507SCurtis.Dunham@arm.comsystem.cpu0.op_class::SimdFloatDiv 0 0.00% 52.97% # Class of executed instruction 11311507SCurtis.Dunham@arm.comsystem.cpu0.op_class::SimdFloatMisc 0 0.00% 52.97% # Class of executed instruction 11411507SCurtis.Dunham@arm.comsystem.cpu0.op_class::SimdFloatMult 0 0.00% 52.97% # Class of executed instruction 11511507SCurtis.Dunham@arm.comsystem.cpu0.op_class::SimdFloatMultAcc 0 0.00% 52.97% # Class of executed instruction 11611507SCurtis.Dunham@arm.comsystem.cpu0.op_class::SimdFloatSqrt 0 0.00% 52.97% # Class of executed instruction 11711507SCurtis.Dunham@arm.comsystem.cpu0.op_class::MemRead 54675 31.17% 84.15% # Class of executed instruction 11811507SCurtis.Dunham@arm.comsystem.cpu0.op_class::MemWrite 27806 15.85% 100.00% # Class of executed instruction 11911507SCurtis.Dunham@arm.comsystem.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 12011507SCurtis.Dunham@arm.comsystem.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 12111507SCurtis.Dunham@arm.comsystem.cpu0.op_class::total 175388 # Class of executed instruction 12211507SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.replacements 2 # number of replacements 12311507SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.tagsinuse 150.745705 # Cycle average of tags in use 12411507SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.total_refs 81882 # Total number of references to valid blocks. 12511507SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.sampled_refs 167 # Sample count of references to valid blocks. 12611507SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.avg_refs 490.311377 # Average number of references to valid blocks. 12711507SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 12811507SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.occ_blocks::cpu0.data 150.745705 # Average occupied blocks per requestor 12911507SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.occ_percent::cpu0.data 0.294425 # Average percentage of cache occupancy 13011507SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.occ_percent::total 0.294425 # Average percentage of cache occupancy 13111507SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.occ_task_id_blocks::1024 165 # Occupied blocks per task id 13211507SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id 13311507SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::1 149 # Occupied blocks per task id 13411507SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.occ_task_id_percent::1024 0.322266 # Percentage of cache occupancy per task id 13511507SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.tag_accesses 329804 # Number of tag accesses 13611507SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.data_accesses 329804 # Number of data accesses 13711507SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_hits::cpu0.data 54430 # number of ReadReq hits 13811507SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_hits::total 54430 # number of ReadReq hits 13911507SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_hits::cpu0.data 27578 # number of WriteReq hits 14011507SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_hits::total 27578 # number of WriteReq hits 14111507SCurtis.Dunham@arm.comsystem.cpu0.dcache.SwapReq_hits::cpu0.data 15 # number of SwapReq hits 14211507SCurtis.Dunham@arm.comsystem.cpu0.dcache.SwapReq_hits::total 15 # number of SwapReq hits 14311507SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_hits::cpu0.data 82008 # number of demand (read+write) hits 14411507SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_hits::total 82008 # number of demand (read+write) hits 14511507SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_hits::cpu0.data 82008 # number of overall hits 14611507SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_hits::total 82008 # number of overall hits 14711507SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_misses::cpu0.data 151 # number of ReadReq misses 14811507SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_misses::total 151 # number of ReadReq misses 14911507SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_misses::cpu0.data 177 # number of WriteReq misses 15011507SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_misses::total 177 # number of WriteReq misses 15111507SCurtis.Dunham@arm.comsystem.cpu0.dcache.SwapReq_misses::cpu0.data 27 # number of SwapReq misses 15211507SCurtis.Dunham@arm.comsystem.cpu0.dcache.SwapReq_misses::total 27 # number of SwapReq misses 15311507SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_misses::cpu0.data 328 # number of demand (read+write) misses 15411507SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_misses::total 328 # number of demand (read+write) misses 15511507SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_misses::cpu0.data 328 # number of overall misses 15611507SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_misses::total 328 # number of overall misses 15711507SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_accesses::cpu0.data 54581 # number of ReadReq accesses(hits+misses) 15811507SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_accesses::total 54581 # number of ReadReq accesses(hits+misses) 15911507SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_accesses::cpu0.data 27755 # number of WriteReq accesses(hits+misses) 16011507SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_accesses::total 27755 # number of WriteReq accesses(hits+misses) 16111507SCurtis.Dunham@arm.comsystem.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) 16211507SCurtis.Dunham@arm.comsystem.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) 16311507SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_accesses::cpu0.data 82336 # number of demand (read+write) accesses 16411507SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_accesses::total 82336 # number of demand (read+write) accesses 16511507SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_accesses::cpu0.data 82336 # number of overall (read+write) accesses 16611507SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_accesses::total 82336 # number of overall (read+write) accesses 16711507SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.002767 # miss rate for ReadReq accesses 16811507SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_miss_rate::total 0.002767 # miss rate for ReadReq accesses 16911507SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.006377 # miss rate for WriteReq accesses 17011507SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_miss_rate::total 0.006377 # miss rate for WriteReq accesses 17111507SCurtis.Dunham@arm.comsystem.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.642857 # miss rate for SwapReq accesses 17211507SCurtis.Dunham@arm.comsystem.cpu0.dcache.SwapReq_miss_rate::total 0.642857 # miss rate for SwapReq accesses 17311507SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_miss_rate::cpu0.data 0.003984 # miss rate for demand accesses 17411507SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_miss_rate::total 0.003984 # miss rate for demand accesses 17511507SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_miss_rate::cpu0.data 0.003984 # miss rate for overall accesses 17611507SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_miss_rate::total 0.003984 # miss rate for overall accesses 17711507SCurtis.Dunham@arm.comsystem.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 17811507SCurtis.Dunham@arm.comsystem.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 17911507SCurtis.Dunham@arm.comsystem.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 18011507SCurtis.Dunham@arm.comsystem.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 18111507SCurtis.Dunham@arm.comsystem.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 18211507SCurtis.Dunham@arm.comsystem.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 18311507SCurtis.Dunham@arm.comsystem.cpu0.dcache.writebacks::writebacks 1 # number of writebacks 18411507SCurtis.Dunham@arm.comsystem.cpu0.dcache.writebacks::total 1 # number of writebacks 18511507SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.replacements 215 # number of replacements 18611507SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.tagsinuse 222.772732 # Cycle average of tags in use 18711507SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.total_refs 174921 # Total number of references to valid blocks. 18811507SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.sampled_refs 467 # Sample count of references to valid blocks. 18911507SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.avg_refs 374.563169 # Average number of references to valid blocks. 19011507SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 19111507SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.occ_blocks::cpu0.inst 222.772732 # Average occupied blocks per requestor 19211507SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.occ_percent::cpu0.inst 0.435103 # Average percentage of cache occupancy 19311507SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.occ_percent::total 0.435103 # Average percentage of cache occupancy 19411507SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.occ_task_id_blocks::1024 252 # Occupied blocks per task id 19511507SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id 19611507SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::1 199 # Occupied blocks per task id 19711507SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.occ_task_id_percent::1024 0.492188 # Percentage of cache occupancy per task id 19811507SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.tag_accesses 175855 # Number of tag accesses 19911507SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.data_accesses 175855 # Number of data accesses 20011507SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_hits::cpu0.inst 174921 # number of ReadReq hits 20111507SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_hits::total 174921 # number of ReadReq hits 20211507SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_hits::cpu0.inst 174921 # number of demand (read+write) hits 20311507SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_hits::total 174921 # number of demand (read+write) hits 20411507SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_hits::cpu0.inst 174921 # number of overall hits 20511507SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_hits::total 174921 # number of overall hits 20611507SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_misses::cpu0.inst 467 # number of ReadReq misses 20711507SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_misses::total 467 # number of ReadReq misses 20811507SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_misses::cpu0.inst 467 # number of demand (read+write) misses 20911507SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_misses::total 467 # number of demand (read+write) misses 21011507SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_misses::cpu0.inst 467 # number of overall misses 21111507SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_misses::total 467 # number of overall misses 21211507SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_accesses::cpu0.inst 175388 # number of ReadReq accesses(hits+misses) 21311507SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_accesses::total 175388 # number of ReadReq accesses(hits+misses) 21411507SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_accesses::cpu0.inst 175388 # number of demand (read+write) accesses 21511507SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_accesses::total 175388 # number of demand (read+write) accesses 21611507SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_accesses::cpu0.inst 175388 # number of overall (read+write) accesses 21711507SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_accesses::total 175388 # number of overall (read+write) accesses 21811507SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002663 # miss rate for ReadReq accesses 21911507SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_miss_rate::total 0.002663 # miss rate for ReadReq accesses 22011507SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_miss_rate::cpu0.inst 0.002663 # miss rate for demand accesses 22111507SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_miss_rate::total 0.002663 # miss rate for demand accesses 22211507SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_miss_rate::cpu0.inst 0.002663 # miss rate for overall accesses 22311507SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_miss_rate::total 0.002663 # miss rate for overall accesses 22411507SCurtis.Dunham@arm.comsystem.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 22511507SCurtis.Dunham@arm.comsystem.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 22611507SCurtis.Dunham@arm.comsystem.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 22711507SCurtis.Dunham@arm.comsystem.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 22811507SCurtis.Dunham@arm.comsystem.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 22911507SCurtis.Dunham@arm.comsystem.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 23011507SCurtis.Dunham@arm.comsystem.cpu0.icache.writebacks::writebacks 215 # number of writebacks 23111507SCurtis.Dunham@arm.comsystem.cpu0.icache.writebacks::total 215 # number of writebacks 23211507SCurtis.Dunham@arm.comsystem.cpu1.numCycles 173297 # number of cpu cycles simulated 23311507SCurtis.Dunham@arm.comsystem.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 23411507SCurtis.Dunham@arm.comsystem.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 23511507SCurtis.Dunham@arm.comsystem.cpu1.committedInsts 167400 # Number of instructions committed 23611507SCurtis.Dunham@arm.comsystem.cpu1.committedOps 167400 # Number of ops (including micro ops) committed 23711507SCurtis.Dunham@arm.comsystem.cpu1.num_int_alu_accesses 107326 # Number of integer alu accesses 23811507SCurtis.Dunham@arm.comsystem.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses 23911507SCurtis.Dunham@arm.comsystem.cpu1.num_func_calls 633 # number of times a function call or return occured 24011507SCurtis.Dunham@arm.comsystem.cpu1.num_conditional_control_insts 34043 # number of instructions that are conditional controls 24111507SCurtis.Dunham@arm.comsystem.cpu1.num_int_insts 107326 # number of integer instructions 24211507SCurtis.Dunham@arm.comsystem.cpu1.num_fp_insts 0 # number of float instructions 24311507SCurtis.Dunham@arm.comsystem.cpu1.num_int_register_reads 254436 # number of times the integer registers were read 24411507SCurtis.Dunham@arm.comsystem.cpu1.num_int_register_writes 94218 # number of times the integer registers were written 24511507SCurtis.Dunham@arm.comsystem.cpu1.num_fp_register_reads 0 # number of times the floating registers were read 24611507SCurtis.Dunham@arm.comsystem.cpu1.num_fp_register_writes 0 # number of times the floating registers were written 24711507SCurtis.Dunham@arm.comsystem.cpu1.num_mem_refs 49494 # number of memory refs 24811507SCurtis.Dunham@arm.comsystem.cpu1.num_load_insts 39345 # Number of load instructions 24911507SCurtis.Dunham@arm.comsystem.cpu1.num_store_insts 10149 # Number of store instructions 25011507SCurtis.Dunham@arm.comsystem.cpu1.num_idle_cycles 7872.827276 # Number of idle cycles 25111507SCurtis.Dunham@arm.comsystem.cpu1.num_busy_cycles 165424.172724 # Number of busy cycles 25211507SCurtis.Dunham@arm.comsystem.cpu1.not_idle_fraction 0.954570 # Percentage of non-idle cycles 25311507SCurtis.Dunham@arm.comsystem.cpu1.idle_fraction 0.045430 # Percentage of idle cycles 25411507SCurtis.Dunham@arm.comsystem.cpu1.Branches 35694 # Number of branches fetched 25511507SCurtis.Dunham@arm.comsystem.cpu1.op_class::No_OpClass 26475 15.81% 15.81% # Class of executed instruction 25611507SCurtis.Dunham@arm.comsystem.cpu1.op_class::IntAlu 71873 42.93% 58.74% # Class of executed instruction 25711507SCurtis.Dunham@arm.comsystem.cpu1.op_class::IntMult 0 0.00% 58.74% # Class of executed instruction 25811507SCurtis.Dunham@arm.comsystem.cpu1.op_class::IntDiv 0 0.00% 58.74% # Class of executed instruction 25911507SCurtis.Dunham@arm.comsystem.cpu1.op_class::FloatAdd 0 0.00% 58.74% # Class of executed instruction 26011507SCurtis.Dunham@arm.comsystem.cpu1.op_class::FloatCmp 0 0.00% 58.74% # Class of executed instruction 26111507SCurtis.Dunham@arm.comsystem.cpu1.op_class::FloatCvt 0 0.00% 58.74% # Class of executed instruction 26211507SCurtis.Dunham@arm.comsystem.cpu1.op_class::FloatMult 0 0.00% 58.74% # Class of executed instruction 26311507SCurtis.Dunham@arm.comsystem.cpu1.op_class::FloatDiv 0 0.00% 58.74% # Class of executed instruction 26411507SCurtis.Dunham@arm.comsystem.cpu1.op_class::FloatSqrt 0 0.00% 58.74% # Class of executed instruction 26511507SCurtis.Dunham@arm.comsystem.cpu1.op_class::SimdAdd 0 0.00% 58.74% # Class of executed instruction 26611507SCurtis.Dunham@arm.comsystem.cpu1.op_class::SimdAddAcc 0 0.00% 58.74% # Class of executed instruction 26711507SCurtis.Dunham@arm.comsystem.cpu1.op_class::SimdAlu 0 0.00% 58.74% # Class of executed instruction 26811507SCurtis.Dunham@arm.comsystem.cpu1.op_class::SimdCmp 0 0.00% 58.74% # Class of executed instruction 26911507SCurtis.Dunham@arm.comsystem.cpu1.op_class::SimdCvt 0 0.00% 58.74% # Class of executed instruction 27011507SCurtis.Dunham@arm.comsystem.cpu1.op_class::SimdMisc 0 0.00% 58.74% # Class of executed instruction 27111507SCurtis.Dunham@arm.comsystem.cpu1.op_class::SimdMult 0 0.00% 58.74% # Class of executed instruction 27211507SCurtis.Dunham@arm.comsystem.cpu1.op_class::SimdMultAcc 0 0.00% 58.74% # Class of executed instruction 27311507SCurtis.Dunham@arm.comsystem.cpu1.op_class::SimdShift 0 0.00% 58.74% # Class of executed instruction 27411507SCurtis.Dunham@arm.comsystem.cpu1.op_class::SimdShiftAcc 0 0.00% 58.74% # Class of executed instruction 27511507SCurtis.Dunham@arm.comsystem.cpu1.op_class::SimdSqrt 0 0.00% 58.74% # Class of executed instruction 27611507SCurtis.Dunham@arm.comsystem.cpu1.op_class::SimdFloatAdd 0 0.00% 58.74% # Class of executed instruction 27711507SCurtis.Dunham@arm.comsystem.cpu1.op_class::SimdFloatAlu 0 0.00% 58.74% # Class of executed instruction 27811507SCurtis.Dunham@arm.comsystem.cpu1.op_class::SimdFloatCmp 0 0.00% 58.74% # Class of executed instruction 27911507SCurtis.Dunham@arm.comsystem.cpu1.op_class::SimdFloatCvt 0 0.00% 58.74% # Class of executed instruction 28011507SCurtis.Dunham@arm.comsystem.cpu1.op_class::SimdFloatDiv 0 0.00% 58.74% # Class of executed instruction 28111507SCurtis.Dunham@arm.comsystem.cpu1.op_class::SimdFloatMisc 0 0.00% 58.74% # Class of executed instruction 28211507SCurtis.Dunham@arm.comsystem.cpu1.op_class::SimdFloatMult 0 0.00% 58.74% # Class of executed instruction 28311507SCurtis.Dunham@arm.comsystem.cpu1.op_class::SimdFloatMultAcc 0 0.00% 58.74% # Class of executed instruction 28411507SCurtis.Dunham@arm.comsystem.cpu1.op_class::SimdFloatSqrt 0 0.00% 58.74% # Class of executed instruction 28511507SCurtis.Dunham@arm.comsystem.cpu1.op_class::MemRead 58935 35.20% 93.94% # Class of executed instruction 28611507SCurtis.Dunham@arm.comsystem.cpu1.op_class::MemWrite 10149 6.06% 100.00% # Class of executed instruction 28711507SCurtis.Dunham@arm.comsystem.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 28811507SCurtis.Dunham@arm.comsystem.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 28911507SCurtis.Dunham@arm.comsystem.cpu1.op_class::total 167432 # Class of executed instruction 29011507SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.replacements 0 # number of replacements 29111507SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.tagsinuse 30.295170 # Cycle average of tags in use 29211507SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.total_refs 21529 # Total number of references to valid blocks. 29311507SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.sampled_refs 26 # Sample count of references to valid blocks. 29411507SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.avg_refs 828.038462 # Average number of references to valid blocks. 29511507SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 29611507SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.occ_blocks::cpu1.data 30.295170 # Average occupied blocks per requestor 29711507SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.occ_percent::cpu1.data 0.059170 # Average percentage of cache occupancy 29811507SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.occ_percent::total 0.059170 # Average percentage of cache occupancy 29911507SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.occ_task_id_blocks::1024 26 # Occupied blocks per task id 30011507SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id 30111507SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.occ_task_id_percent::1024 0.050781 # Percentage of cache occupancy per task id 30211507SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.tag_accesses 198211 # Number of tag accesses 30311507SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.data_accesses 198211 # Number of data accesses 30411507SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_hits::cpu1.data 39152 # number of ReadReq hits 30511507SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_hits::total 39152 # number of ReadReq hits 30611507SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_hits::cpu1.data 9968 # number of WriteReq hits 30711507SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_hits::total 9968 # number of WriteReq hits 30811507SCurtis.Dunham@arm.comsystem.cpu1.dcache.SwapReq_hits::cpu1.data 16 # number of SwapReq hits 30911507SCurtis.Dunham@arm.comsystem.cpu1.dcache.SwapReq_hits::total 16 # number of SwapReq hits 31011507SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_hits::cpu1.data 49120 # number of demand (read+write) hits 31111507SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_hits::total 49120 # number of demand (read+write) hits 31211507SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_hits::cpu1.data 49120 # number of overall hits 31311507SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_hits::total 49120 # number of overall hits 31411507SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_misses::cpu1.data 185 # number of ReadReq misses 31511507SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_misses::total 185 # number of ReadReq misses 31611507SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_misses::cpu1.data 102 # number of WriteReq misses 31711507SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_misses::total 102 # number of WriteReq misses 31811507SCurtis.Dunham@arm.comsystem.cpu1.dcache.SwapReq_misses::cpu1.data 61 # number of SwapReq misses 31911507SCurtis.Dunham@arm.comsystem.cpu1.dcache.SwapReq_misses::total 61 # number of SwapReq misses 32011507SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_misses::cpu1.data 287 # number of demand (read+write) misses 32111507SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_misses::total 287 # number of demand (read+write) misses 32211507SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_misses::cpu1.data 287 # number of overall misses 32311507SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_misses::total 287 # number of overall misses 32411507SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_accesses::cpu1.data 39337 # number of ReadReq accesses(hits+misses) 32511507SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_accesses::total 39337 # number of ReadReq accesses(hits+misses) 32611507SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_accesses::cpu1.data 10070 # number of WriteReq accesses(hits+misses) 32711507SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_accesses::total 10070 # number of WriteReq accesses(hits+misses) 32811507SCurtis.Dunham@arm.comsystem.cpu1.dcache.SwapReq_accesses::cpu1.data 77 # number of SwapReq accesses(hits+misses) 32911507SCurtis.Dunham@arm.comsystem.cpu1.dcache.SwapReq_accesses::total 77 # number of SwapReq accesses(hits+misses) 33011507SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_accesses::cpu1.data 49407 # number of demand (read+write) accesses 33111507SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_accesses::total 49407 # number of demand (read+write) accesses 33211507SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_accesses::cpu1.data 49407 # number of overall (read+write) accesses 33311507SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_accesses::total 49407 # number of overall (read+write) accesses 33411507SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.004703 # miss rate for ReadReq accesses 33511507SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_miss_rate::total 0.004703 # miss rate for ReadReq accesses 33611507SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.010129 # miss rate for WriteReq accesses 33711507SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_miss_rate::total 0.010129 # miss rate for WriteReq accesses 33811507SCurtis.Dunham@arm.comsystem.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.792208 # miss rate for SwapReq accesses 33911507SCurtis.Dunham@arm.comsystem.cpu1.dcache.SwapReq_miss_rate::total 0.792208 # miss rate for SwapReq accesses 34011507SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_miss_rate::cpu1.data 0.005809 # miss rate for demand accesses 34111507SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_miss_rate::total 0.005809 # miss rate for demand accesses 34211507SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_miss_rate::cpu1.data 0.005809 # miss rate for overall accesses 34311507SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_miss_rate::total 0.005809 # miss rate for overall accesses 34411507SCurtis.Dunham@arm.comsystem.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 34511507SCurtis.Dunham@arm.comsystem.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 34611507SCurtis.Dunham@arm.comsystem.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 34711507SCurtis.Dunham@arm.comsystem.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 34811507SCurtis.Dunham@arm.comsystem.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 34911507SCurtis.Dunham@arm.comsystem.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 35011507SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.replacements 278 # number of replacements 35111507SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.tagsinuse 76.752158 # Cycle average of tags in use 35211507SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.total_refs 167074 # Total number of references to valid blocks. 35311507SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.sampled_refs 358 # Sample count of references to valid blocks. 35411507SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.avg_refs 466.687151 # Average number of references to valid blocks. 35511507SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 35611507SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.occ_blocks::cpu1.inst 76.752158 # Average occupied blocks per requestor 35711507SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.occ_percent::cpu1.inst 0.149907 # Average percentage of cache occupancy 35811507SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.occ_percent::total 0.149907 # Average percentage of cache occupancy 35911507SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.occ_task_id_blocks::1024 80 # Occupied blocks per task id 36011507SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id 36111507SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::1 71 # Occupied blocks per task id 36211507SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.occ_task_id_percent::1024 0.156250 # Percentage of cache occupancy per task id 36311507SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.tag_accesses 167790 # Number of tag accesses 36411507SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.data_accesses 167790 # Number of data accesses 36511507SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_hits::cpu1.inst 167074 # number of ReadReq hits 36611507SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_hits::total 167074 # number of ReadReq hits 36711507SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_hits::cpu1.inst 167074 # number of demand (read+write) hits 36811507SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_hits::total 167074 # number of demand (read+write) hits 36911507SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_hits::cpu1.inst 167074 # number of overall hits 37011507SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_hits::total 167074 # number of overall hits 37111507SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_misses::cpu1.inst 358 # number of ReadReq misses 37211507SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_misses::total 358 # number of ReadReq misses 37311507SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_misses::cpu1.inst 358 # number of demand (read+write) misses 37411507SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_misses::total 358 # number of demand (read+write) misses 37511507SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_misses::cpu1.inst 358 # number of overall misses 37611507SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_misses::total 358 # number of overall misses 37711507SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_accesses::cpu1.inst 167432 # number of ReadReq accesses(hits+misses) 37811507SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_accesses::total 167432 # number of ReadReq accesses(hits+misses) 37911507SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_accesses::cpu1.inst 167432 # number of demand (read+write) accesses 38011507SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_accesses::total 167432 # number of demand (read+write) accesses 38111507SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_accesses::cpu1.inst 167432 # number of overall (read+write) accesses 38211507SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_accesses::total 167432 # number of overall (read+write) accesses 38311507SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002138 # miss rate for ReadReq accesses 38411507SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_miss_rate::total 0.002138 # miss rate for ReadReq accesses 38511507SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_miss_rate::cpu1.inst 0.002138 # miss rate for demand accesses 38611507SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_miss_rate::total 0.002138 # miss rate for demand accesses 38711507SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_miss_rate::cpu1.inst 0.002138 # miss rate for overall accesses 38811507SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_miss_rate::total 0.002138 # miss rate for overall accesses 38911507SCurtis.Dunham@arm.comsystem.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 39011507SCurtis.Dunham@arm.comsystem.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 39111507SCurtis.Dunham@arm.comsystem.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 39211507SCurtis.Dunham@arm.comsystem.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 39311507SCurtis.Dunham@arm.comsystem.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 39411507SCurtis.Dunham@arm.comsystem.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 39511507SCurtis.Dunham@arm.comsystem.cpu1.icache.writebacks::writebacks 278 # number of writebacks 39611507SCurtis.Dunham@arm.comsystem.cpu1.icache.writebacks::total 278 # number of writebacks 39711507SCurtis.Dunham@arm.comsystem.cpu2.numCycles 173296 # number of cpu cycles simulated 39811507SCurtis.Dunham@arm.comsystem.cpu2.numWorkItemsStarted 0 # number of work items this cpu started 39911507SCurtis.Dunham@arm.comsystem.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed 40011507SCurtis.Dunham@arm.comsystem.cpu2.committedInsts 167335 # Number of instructions committed 40111507SCurtis.Dunham@arm.comsystem.cpu2.committedOps 167335 # Number of ops (including micro ops) committed 40211507SCurtis.Dunham@arm.comsystem.cpu2.num_int_alu_accesses 114196 # Number of integer alu accesses 40311507SCurtis.Dunham@arm.comsystem.cpu2.num_fp_alu_accesses 0 # Number of float alu accesses 40411507SCurtis.Dunham@arm.comsystem.cpu2.num_func_calls 633 # number of times a function call or return occured 40511507SCurtis.Dunham@arm.comsystem.cpu2.num_conditional_control_insts 30577 # number of instructions that are conditional controls 40611507SCurtis.Dunham@arm.comsystem.cpu2.num_int_insts 114196 # number of integer instructions 40711507SCurtis.Dunham@arm.comsystem.cpu2.num_fp_insts 0 # number of float instructions 40811507SCurtis.Dunham@arm.comsystem.cpu2.num_int_register_reads 295784 # number of times the integer registers were read 40911507SCurtis.Dunham@arm.comsystem.cpu2.num_int_register_writes 111461 # number of times the integer registers were written 41011507SCurtis.Dunham@arm.comsystem.cpu2.num_fp_register_reads 0 # number of times the floating registers were read 41111507SCurtis.Dunham@arm.comsystem.cpu2.num_fp_register_writes 0 # number of times the floating registers were written 41211507SCurtis.Dunham@arm.comsystem.cpu2.num_mem_refs 59830 # number of memory refs 41311507SCurtis.Dunham@arm.comsystem.cpu2.num_load_insts 42793 # Number of load instructions 41411507SCurtis.Dunham@arm.comsystem.cpu2.num_store_insts 17037 # Number of store instructions 41511507SCurtis.Dunham@arm.comsystem.cpu2.num_idle_cycles 7936.997017 # Number of idle cycles 41611507SCurtis.Dunham@arm.comsystem.cpu2.num_busy_cycles 165359.002983 # Number of busy cycles 41711507SCurtis.Dunham@arm.comsystem.cpu2.not_idle_fraction 0.954200 # Percentage of non-idle cycles 41811507SCurtis.Dunham@arm.comsystem.cpu2.idle_fraction 0.045800 # Percentage of idle cycles 41911507SCurtis.Dunham@arm.comsystem.cpu2.Branches 32221 # Number of branches fetched 42011507SCurtis.Dunham@arm.comsystem.cpu2.op_class::No_OpClass 23013 13.75% 13.75% # Class of executed instruction 42111507SCurtis.Dunham@arm.comsystem.cpu2.op_class::IntAlu 75303 44.99% 58.74% # Class of executed instruction 42211507SCurtis.Dunham@arm.comsystem.cpu2.op_class::IntMult 0 0.00% 58.74% # Class of executed instruction 42311507SCurtis.Dunham@arm.comsystem.cpu2.op_class::IntDiv 0 0.00% 58.74% # Class of executed instruction 42411507SCurtis.Dunham@arm.comsystem.cpu2.op_class::FloatAdd 0 0.00% 58.74% # Class of executed instruction 42511507SCurtis.Dunham@arm.comsystem.cpu2.op_class::FloatCmp 0 0.00% 58.74% # Class of executed instruction 42611507SCurtis.Dunham@arm.comsystem.cpu2.op_class::FloatCvt 0 0.00% 58.74% # Class of executed instruction 42711507SCurtis.Dunham@arm.comsystem.cpu2.op_class::FloatMult 0 0.00% 58.74% # Class of executed instruction 42811507SCurtis.Dunham@arm.comsystem.cpu2.op_class::FloatDiv 0 0.00% 58.74% # Class of executed instruction 42911507SCurtis.Dunham@arm.comsystem.cpu2.op_class::FloatSqrt 0 0.00% 58.74% # Class of executed instruction 43011507SCurtis.Dunham@arm.comsystem.cpu2.op_class::SimdAdd 0 0.00% 58.74% # Class of executed instruction 43111507SCurtis.Dunham@arm.comsystem.cpu2.op_class::SimdAddAcc 0 0.00% 58.74% # Class of executed instruction 43211507SCurtis.Dunham@arm.comsystem.cpu2.op_class::SimdAlu 0 0.00% 58.74% # Class of executed instruction 43311507SCurtis.Dunham@arm.comsystem.cpu2.op_class::SimdCmp 0 0.00% 58.74% # Class of executed instruction 43411507SCurtis.Dunham@arm.comsystem.cpu2.op_class::SimdCvt 0 0.00% 58.74% # Class of executed instruction 43511507SCurtis.Dunham@arm.comsystem.cpu2.op_class::SimdMisc 0 0.00% 58.74% # Class of executed instruction 43611507SCurtis.Dunham@arm.comsystem.cpu2.op_class::SimdMult 0 0.00% 58.74% # Class of executed instruction 43711507SCurtis.Dunham@arm.comsystem.cpu2.op_class::SimdMultAcc 0 0.00% 58.74% # Class of executed instruction 43811507SCurtis.Dunham@arm.comsystem.cpu2.op_class::SimdShift 0 0.00% 58.74% # Class of executed instruction 43911507SCurtis.Dunham@arm.comsystem.cpu2.op_class::SimdShiftAcc 0 0.00% 58.74% # Class of executed instruction 44011507SCurtis.Dunham@arm.comsystem.cpu2.op_class::SimdSqrt 0 0.00% 58.74% # Class of executed instruction 44111507SCurtis.Dunham@arm.comsystem.cpu2.op_class::SimdFloatAdd 0 0.00% 58.74% # Class of executed instruction 44211507SCurtis.Dunham@arm.comsystem.cpu2.op_class::SimdFloatAlu 0 0.00% 58.74% # Class of executed instruction 44311507SCurtis.Dunham@arm.comsystem.cpu2.op_class::SimdFloatCmp 0 0.00% 58.74% # Class of executed instruction 44411507SCurtis.Dunham@arm.comsystem.cpu2.op_class::SimdFloatCvt 0 0.00% 58.74% # Class of executed instruction 44511507SCurtis.Dunham@arm.comsystem.cpu2.op_class::SimdFloatDiv 0 0.00% 58.74% # Class of executed instruction 44611507SCurtis.Dunham@arm.comsystem.cpu2.op_class::SimdFloatMisc 0 0.00% 58.74% # Class of executed instruction 44711507SCurtis.Dunham@arm.comsystem.cpu2.op_class::SimdFloatMult 0 0.00% 58.74% # Class of executed instruction 44811507SCurtis.Dunham@arm.comsystem.cpu2.op_class::SimdFloatMultAcc 0 0.00% 58.74% # Class of executed instruction 44911507SCurtis.Dunham@arm.comsystem.cpu2.op_class::SimdFloatSqrt 0 0.00% 58.74% # Class of executed instruction 45011507SCurtis.Dunham@arm.comsystem.cpu2.op_class::MemRead 52014 31.08% 89.82% # Class of executed instruction 45111507SCurtis.Dunham@arm.comsystem.cpu2.op_class::MemWrite 17037 10.18% 100.00% # Class of executed instruction 45211507SCurtis.Dunham@arm.comsystem.cpu2.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 45311507SCurtis.Dunham@arm.comsystem.cpu2.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 45411507SCurtis.Dunham@arm.comsystem.cpu2.op_class::total 167367 # Class of executed instruction 45511507SCurtis.Dunham@arm.comsystem.cpu2.dcache.tags.replacements 0 # number of replacements 45611507SCurtis.Dunham@arm.comsystem.cpu2.dcache.tags.tagsinuse 29.575165 # Cycle average of tags in use 45711507SCurtis.Dunham@arm.comsystem.cpu2.dcache.tags.total_refs 35457 # Total number of references to valid blocks. 45811507SCurtis.Dunham@arm.comsystem.cpu2.dcache.tags.sampled_refs 27 # Sample count of references to valid blocks. 45911507SCurtis.Dunham@arm.comsystem.cpu2.dcache.tags.avg_refs 1313.222222 # Average number of references to valid blocks. 46011507SCurtis.Dunham@arm.comsystem.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 46111507SCurtis.Dunham@arm.comsystem.cpu2.dcache.tags.occ_blocks::cpu2.data 29.575165 # Average occupied blocks per requestor 46211507SCurtis.Dunham@arm.comsystem.cpu2.dcache.tags.occ_percent::cpu2.data 0.057764 # Average percentage of cache occupancy 46311507SCurtis.Dunham@arm.comsystem.cpu2.dcache.tags.occ_percent::total 0.057764 # Average percentage of cache occupancy 46411507SCurtis.Dunham@arm.comsystem.cpu2.dcache.tags.occ_task_id_blocks::1024 27 # Occupied blocks per task id 46511507SCurtis.Dunham@arm.comsystem.cpu2.dcache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id 46611507SCurtis.Dunham@arm.comsystem.cpu2.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id 46711507SCurtis.Dunham@arm.comsystem.cpu2.dcache.tags.occ_task_id_percent::1024 0.052734 # Percentage of cache occupancy per task id 46811507SCurtis.Dunham@arm.comsystem.cpu2.dcache.tags.tag_accesses 239521 # Number of tag accesses 46911507SCurtis.Dunham@arm.comsystem.cpu2.dcache.tags.data_accesses 239521 # Number of data accesses 47011507SCurtis.Dunham@arm.comsystem.cpu2.dcache.ReadReq_hits::cpu2.data 42635 # number of ReadReq hits 47111507SCurtis.Dunham@arm.comsystem.cpu2.dcache.ReadReq_hits::total 42635 # number of ReadReq hits 47211507SCurtis.Dunham@arm.comsystem.cpu2.dcache.WriteReq_hits::cpu2.data 16864 # number of WriteReq hits 47311507SCurtis.Dunham@arm.comsystem.cpu2.dcache.WriteReq_hits::total 16864 # number of WriteReq hits 47411507SCurtis.Dunham@arm.comsystem.cpu2.dcache.SwapReq_hits::cpu2.data 12 # number of SwapReq hits 47511507SCurtis.Dunham@arm.comsystem.cpu2.dcache.SwapReq_hits::total 12 # number of SwapReq hits 47611507SCurtis.Dunham@arm.comsystem.cpu2.dcache.demand_hits::cpu2.data 59499 # number of demand (read+write) hits 47711507SCurtis.Dunham@arm.comsystem.cpu2.dcache.demand_hits::total 59499 # number of demand (read+write) hits 47811507SCurtis.Dunham@arm.comsystem.cpu2.dcache.overall_hits::cpu2.data 59499 # number of overall hits 47911507SCurtis.Dunham@arm.comsystem.cpu2.dcache.overall_hits::total 59499 # number of overall hits 48011507SCurtis.Dunham@arm.comsystem.cpu2.dcache.ReadReq_misses::cpu2.data 150 # number of ReadReq misses 48111507SCurtis.Dunham@arm.comsystem.cpu2.dcache.ReadReq_misses::total 150 # number of ReadReq misses 48211507SCurtis.Dunham@arm.comsystem.cpu2.dcache.WriteReq_misses::cpu2.data 105 # number of WriteReq misses 48311507SCurtis.Dunham@arm.comsystem.cpu2.dcache.WriteReq_misses::total 105 # number of WriteReq misses 48411507SCurtis.Dunham@arm.comsystem.cpu2.dcache.SwapReq_misses::cpu2.data 54 # number of SwapReq misses 48511507SCurtis.Dunham@arm.comsystem.cpu2.dcache.SwapReq_misses::total 54 # number of SwapReq misses 48611507SCurtis.Dunham@arm.comsystem.cpu2.dcache.demand_misses::cpu2.data 255 # number of demand (read+write) misses 48711507SCurtis.Dunham@arm.comsystem.cpu2.dcache.demand_misses::total 255 # number of demand (read+write) misses 48811507SCurtis.Dunham@arm.comsystem.cpu2.dcache.overall_misses::cpu2.data 255 # number of overall misses 48911507SCurtis.Dunham@arm.comsystem.cpu2.dcache.overall_misses::total 255 # number of overall misses 49011507SCurtis.Dunham@arm.comsystem.cpu2.dcache.ReadReq_accesses::cpu2.data 42785 # number of ReadReq accesses(hits+misses) 49111507SCurtis.Dunham@arm.comsystem.cpu2.dcache.ReadReq_accesses::total 42785 # number of ReadReq accesses(hits+misses) 49211507SCurtis.Dunham@arm.comsystem.cpu2.dcache.WriteReq_accesses::cpu2.data 16969 # number of WriteReq accesses(hits+misses) 49311507SCurtis.Dunham@arm.comsystem.cpu2.dcache.WriteReq_accesses::total 16969 # number of WriteReq accesses(hits+misses) 49411507SCurtis.Dunham@arm.comsystem.cpu2.dcache.SwapReq_accesses::cpu2.data 66 # number of SwapReq accesses(hits+misses) 49511507SCurtis.Dunham@arm.comsystem.cpu2.dcache.SwapReq_accesses::total 66 # number of SwapReq accesses(hits+misses) 49611507SCurtis.Dunham@arm.comsystem.cpu2.dcache.demand_accesses::cpu2.data 59754 # number of demand (read+write) accesses 49711507SCurtis.Dunham@arm.comsystem.cpu2.dcache.demand_accesses::total 59754 # number of demand (read+write) accesses 49811507SCurtis.Dunham@arm.comsystem.cpu2.dcache.overall_accesses::cpu2.data 59754 # number of overall (read+write) accesses 49911507SCurtis.Dunham@arm.comsystem.cpu2.dcache.overall_accesses::total 59754 # number of overall (read+write) accesses 50011507SCurtis.Dunham@arm.comsystem.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.003506 # miss rate for ReadReq accesses 50111507SCurtis.Dunham@arm.comsystem.cpu2.dcache.ReadReq_miss_rate::total 0.003506 # miss rate for ReadReq accesses 50211507SCurtis.Dunham@arm.comsystem.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.006188 # miss rate for WriteReq accesses 50311507SCurtis.Dunham@arm.comsystem.cpu2.dcache.WriteReq_miss_rate::total 0.006188 # miss rate for WriteReq accesses 50411507SCurtis.Dunham@arm.comsystem.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.818182 # miss rate for SwapReq accesses 50511507SCurtis.Dunham@arm.comsystem.cpu2.dcache.SwapReq_miss_rate::total 0.818182 # miss rate for SwapReq accesses 50611507SCurtis.Dunham@arm.comsystem.cpu2.dcache.demand_miss_rate::cpu2.data 0.004267 # miss rate for demand accesses 50711507SCurtis.Dunham@arm.comsystem.cpu2.dcache.demand_miss_rate::total 0.004267 # miss rate for demand accesses 50811507SCurtis.Dunham@arm.comsystem.cpu2.dcache.overall_miss_rate::cpu2.data 0.004267 # miss rate for overall accesses 50911507SCurtis.Dunham@arm.comsystem.cpu2.dcache.overall_miss_rate::total 0.004267 # miss rate for overall accesses 51011507SCurtis.Dunham@arm.comsystem.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 51111507SCurtis.Dunham@arm.comsystem.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 51211507SCurtis.Dunham@arm.comsystem.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 51311507SCurtis.Dunham@arm.comsystem.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked 51411507SCurtis.Dunham@arm.comsystem.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 51511507SCurtis.Dunham@arm.comsystem.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 51611507SCurtis.Dunham@arm.comsystem.cpu2.icache.tags.replacements 278 # number of replacements 51711507SCurtis.Dunham@arm.comsystem.cpu2.icache.tags.tagsinuse 74.781471 # Cycle average of tags in use 51811507SCurtis.Dunham@arm.comsystem.cpu2.icache.tags.total_refs 167009 # Total number of references to valid blocks. 51911507SCurtis.Dunham@arm.comsystem.cpu2.icache.tags.sampled_refs 358 # Sample count of references to valid blocks. 52011507SCurtis.Dunham@arm.comsystem.cpu2.icache.tags.avg_refs 466.505587 # Average number of references to valid blocks. 52111507SCurtis.Dunham@arm.comsystem.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 52211507SCurtis.Dunham@arm.comsystem.cpu2.icache.tags.occ_blocks::cpu2.inst 74.781471 # Average occupied blocks per requestor 52311507SCurtis.Dunham@arm.comsystem.cpu2.icache.tags.occ_percent::cpu2.inst 0.146058 # Average percentage of cache occupancy 52411507SCurtis.Dunham@arm.comsystem.cpu2.icache.tags.occ_percent::total 0.146058 # Average percentage of cache occupancy 52511507SCurtis.Dunham@arm.comsystem.cpu2.icache.tags.occ_task_id_blocks::1024 80 # Occupied blocks per task id 52611507SCurtis.Dunham@arm.comsystem.cpu2.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id 52711507SCurtis.Dunham@arm.comsystem.cpu2.icache.tags.age_task_id_blocks_1024::1 71 # Occupied blocks per task id 52811507SCurtis.Dunham@arm.comsystem.cpu2.icache.tags.occ_task_id_percent::1024 0.156250 # Percentage of cache occupancy per task id 52911507SCurtis.Dunham@arm.comsystem.cpu2.icache.tags.tag_accesses 167725 # Number of tag accesses 53011507SCurtis.Dunham@arm.comsystem.cpu2.icache.tags.data_accesses 167725 # Number of data accesses 53111507SCurtis.Dunham@arm.comsystem.cpu2.icache.ReadReq_hits::cpu2.inst 167009 # number of ReadReq hits 53211507SCurtis.Dunham@arm.comsystem.cpu2.icache.ReadReq_hits::total 167009 # number of ReadReq hits 53311507SCurtis.Dunham@arm.comsystem.cpu2.icache.demand_hits::cpu2.inst 167009 # number of demand (read+write) hits 53411507SCurtis.Dunham@arm.comsystem.cpu2.icache.demand_hits::total 167009 # number of demand (read+write) hits 53511507SCurtis.Dunham@arm.comsystem.cpu2.icache.overall_hits::cpu2.inst 167009 # number of overall hits 53611507SCurtis.Dunham@arm.comsystem.cpu2.icache.overall_hits::total 167009 # number of overall hits 53711507SCurtis.Dunham@arm.comsystem.cpu2.icache.ReadReq_misses::cpu2.inst 358 # number of ReadReq misses 53811507SCurtis.Dunham@arm.comsystem.cpu2.icache.ReadReq_misses::total 358 # number of ReadReq misses 53911507SCurtis.Dunham@arm.comsystem.cpu2.icache.demand_misses::cpu2.inst 358 # number of demand (read+write) misses 54011507SCurtis.Dunham@arm.comsystem.cpu2.icache.demand_misses::total 358 # number of demand (read+write) misses 54111507SCurtis.Dunham@arm.comsystem.cpu2.icache.overall_misses::cpu2.inst 358 # number of overall misses 54211507SCurtis.Dunham@arm.comsystem.cpu2.icache.overall_misses::total 358 # number of overall misses 54311507SCurtis.Dunham@arm.comsystem.cpu2.icache.ReadReq_accesses::cpu2.inst 167367 # number of ReadReq accesses(hits+misses) 54411507SCurtis.Dunham@arm.comsystem.cpu2.icache.ReadReq_accesses::total 167367 # number of ReadReq accesses(hits+misses) 54511507SCurtis.Dunham@arm.comsystem.cpu2.icache.demand_accesses::cpu2.inst 167367 # number of demand (read+write) accesses 54611507SCurtis.Dunham@arm.comsystem.cpu2.icache.demand_accesses::total 167367 # number of demand (read+write) accesses 54711507SCurtis.Dunham@arm.comsystem.cpu2.icache.overall_accesses::cpu2.inst 167367 # number of overall (read+write) accesses 54811507SCurtis.Dunham@arm.comsystem.cpu2.icache.overall_accesses::total 167367 # number of overall (read+write) accesses 54911507SCurtis.Dunham@arm.comsystem.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.002139 # miss rate for ReadReq accesses 55011507SCurtis.Dunham@arm.comsystem.cpu2.icache.ReadReq_miss_rate::total 0.002139 # miss rate for ReadReq accesses 55111507SCurtis.Dunham@arm.comsystem.cpu2.icache.demand_miss_rate::cpu2.inst 0.002139 # miss rate for demand accesses 55211507SCurtis.Dunham@arm.comsystem.cpu2.icache.demand_miss_rate::total 0.002139 # miss rate for demand accesses 55311507SCurtis.Dunham@arm.comsystem.cpu2.icache.overall_miss_rate::cpu2.inst 0.002139 # miss rate for overall accesses 55411507SCurtis.Dunham@arm.comsystem.cpu2.icache.overall_miss_rate::total 0.002139 # miss rate for overall accesses 55511507SCurtis.Dunham@arm.comsystem.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 55611507SCurtis.Dunham@arm.comsystem.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 55711507SCurtis.Dunham@arm.comsystem.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked 55811507SCurtis.Dunham@arm.comsystem.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked 55911507SCurtis.Dunham@arm.comsystem.cpu2.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 56011507SCurtis.Dunham@arm.comsystem.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 56111507SCurtis.Dunham@arm.comsystem.cpu2.icache.writebacks::writebacks 278 # number of writebacks 56211507SCurtis.Dunham@arm.comsystem.cpu2.icache.writebacks::total 278 # number of writebacks 56311507SCurtis.Dunham@arm.comsystem.cpu3.numCycles 173297 # number of cpu cycles simulated 56411507SCurtis.Dunham@arm.comsystem.cpu3.numWorkItemsStarted 0 # number of work items this cpu started 56511507SCurtis.Dunham@arm.comsystem.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed 56611507SCurtis.Dunham@arm.comsystem.cpu3.committedInsts 167272 # Number of instructions committed 56711507SCurtis.Dunham@arm.comsystem.cpu3.committedOps 167272 # Number of ops (including micro ops) committed 56811507SCurtis.Dunham@arm.comsystem.cpu3.num_int_alu_accesses 113295 # Number of integer alu accesses 56911507SCurtis.Dunham@arm.comsystem.cpu3.num_fp_alu_accesses 0 # Number of float alu accesses 57011507SCurtis.Dunham@arm.comsystem.cpu3.num_func_calls 633 # number of times a function call or return occured 57111507SCurtis.Dunham@arm.comsystem.cpu3.num_conditional_control_insts 30996 # number of instructions that are conditional controls 57211507SCurtis.Dunham@arm.comsystem.cpu3.num_int_insts 113295 # number of integer instructions 57311507SCurtis.Dunham@arm.comsystem.cpu3.num_fp_insts 0 # number of float instructions 57411507SCurtis.Dunham@arm.comsystem.cpu3.num_int_register_reads 290503 # number of times the integer registers were read 57511507SCurtis.Dunham@arm.comsystem.cpu3.num_int_register_writes 109270 # number of times the integer registers were written 57611507SCurtis.Dunham@arm.comsystem.cpu3.num_fp_register_reads 0 # number of times the floating registers were read 57711507SCurtis.Dunham@arm.comsystem.cpu3.num_fp_register_writes 0 # number of times the floating registers were written 57811507SCurtis.Dunham@arm.comsystem.cpu3.num_mem_refs 58510 # number of memory refs 57911507SCurtis.Dunham@arm.comsystem.cpu3.num_load_insts 42344 # Number of load instructions 58011507SCurtis.Dunham@arm.comsystem.cpu3.num_store_insts 16166 # Number of store instructions 58111507SCurtis.Dunham@arm.comsystem.cpu3.num_idle_cycles 7999.282495 # Number of idle cycles 58211507SCurtis.Dunham@arm.comsystem.cpu3.num_busy_cycles 165297.717505 # Number of busy cycles 58311507SCurtis.Dunham@arm.comsystem.cpu3.not_idle_fraction 0.953841 # Percentage of non-idle cycles 58411507SCurtis.Dunham@arm.comsystem.cpu3.idle_fraction 0.046159 # Percentage of idle cycles 58511507SCurtis.Dunham@arm.comsystem.cpu3.Branches 32639 # Number of branches fetched 58611507SCurtis.Dunham@arm.comsystem.cpu3.op_class::No_OpClass 23433 14.01% 14.01% # Class of executed instruction 58711507SCurtis.Dunham@arm.comsystem.cpu3.op_class::IntAlu 74851 44.74% 58.75% # Class of executed instruction 58811507SCurtis.Dunham@arm.comsystem.cpu3.op_class::IntMult 0 0.00% 58.75% # Class of executed instruction 58911507SCurtis.Dunham@arm.comsystem.cpu3.op_class::IntDiv 0 0.00% 58.75% # Class of executed instruction 59011507SCurtis.Dunham@arm.comsystem.cpu3.op_class::FloatAdd 0 0.00% 58.75% # Class of executed instruction 59111507SCurtis.Dunham@arm.comsystem.cpu3.op_class::FloatCmp 0 0.00% 58.75% # Class of executed instruction 59211507SCurtis.Dunham@arm.comsystem.cpu3.op_class::FloatCvt 0 0.00% 58.75% # Class of executed instruction 59311507SCurtis.Dunham@arm.comsystem.cpu3.op_class::FloatMult 0 0.00% 58.75% # Class of executed instruction 59411507SCurtis.Dunham@arm.comsystem.cpu3.op_class::FloatDiv 0 0.00% 58.75% # Class of executed instruction 59511507SCurtis.Dunham@arm.comsystem.cpu3.op_class::FloatSqrt 0 0.00% 58.75% # Class of executed instruction 59611507SCurtis.Dunham@arm.comsystem.cpu3.op_class::SimdAdd 0 0.00% 58.75% # Class of executed instruction 59711507SCurtis.Dunham@arm.comsystem.cpu3.op_class::SimdAddAcc 0 0.00% 58.75% # Class of executed instruction 59811507SCurtis.Dunham@arm.comsystem.cpu3.op_class::SimdAlu 0 0.00% 58.75% # Class of executed instruction 59911507SCurtis.Dunham@arm.comsystem.cpu3.op_class::SimdCmp 0 0.00% 58.75% # Class of executed instruction 60011507SCurtis.Dunham@arm.comsystem.cpu3.op_class::SimdCvt 0 0.00% 58.75% # Class of executed instruction 60111507SCurtis.Dunham@arm.comsystem.cpu3.op_class::SimdMisc 0 0.00% 58.75% # Class of executed instruction 60211507SCurtis.Dunham@arm.comsystem.cpu3.op_class::SimdMult 0 0.00% 58.75% # Class of executed instruction 60311507SCurtis.Dunham@arm.comsystem.cpu3.op_class::SimdMultAcc 0 0.00% 58.75% # Class of executed instruction 60411507SCurtis.Dunham@arm.comsystem.cpu3.op_class::SimdShift 0 0.00% 58.75% # Class of executed instruction 60511507SCurtis.Dunham@arm.comsystem.cpu3.op_class::SimdShiftAcc 0 0.00% 58.75% # Class of executed instruction 60611507SCurtis.Dunham@arm.comsystem.cpu3.op_class::SimdSqrt 0 0.00% 58.75% # Class of executed instruction 60711507SCurtis.Dunham@arm.comsystem.cpu3.op_class::SimdFloatAdd 0 0.00% 58.75% # Class of executed instruction 60811507SCurtis.Dunham@arm.comsystem.cpu3.op_class::SimdFloatAlu 0 0.00% 58.75% # Class of executed instruction 60911507SCurtis.Dunham@arm.comsystem.cpu3.op_class::SimdFloatCmp 0 0.00% 58.75% # Class of executed instruction 61011507SCurtis.Dunham@arm.comsystem.cpu3.op_class::SimdFloatCvt 0 0.00% 58.75% # Class of executed instruction 61111507SCurtis.Dunham@arm.comsystem.cpu3.op_class::SimdFloatDiv 0 0.00% 58.75% # Class of executed instruction 61211507SCurtis.Dunham@arm.comsystem.cpu3.op_class::SimdFloatMisc 0 0.00% 58.75% # Class of executed instruction 61311507SCurtis.Dunham@arm.comsystem.cpu3.op_class::SimdFloatMult 0 0.00% 58.75% # Class of executed instruction 61411507SCurtis.Dunham@arm.comsystem.cpu3.op_class::SimdFloatMultAcc 0 0.00% 58.75% # Class of executed instruction 61511507SCurtis.Dunham@arm.comsystem.cpu3.op_class::SimdFloatSqrt 0 0.00% 58.75% # Class of executed instruction 61611507SCurtis.Dunham@arm.comsystem.cpu3.op_class::MemRead 52854 31.59% 90.34% # Class of executed instruction 61711507SCurtis.Dunham@arm.comsystem.cpu3.op_class::MemWrite 16166 9.66% 100.00% # Class of executed instruction 61811507SCurtis.Dunham@arm.comsystem.cpu3.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 61911507SCurtis.Dunham@arm.comsystem.cpu3.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 62011507SCurtis.Dunham@arm.comsystem.cpu3.op_class::total 167304 # Class of executed instruction 62111507SCurtis.Dunham@arm.comsystem.cpu3.dcache.tags.replacements 0 # number of replacements 62211507SCurtis.Dunham@arm.comsystem.cpu3.dcache.tags.tagsinuse 28.848199 # Cycle average of tags in use 62311507SCurtis.Dunham@arm.comsystem.cpu3.dcache.tags.total_refs 33595 # Total number of references to valid blocks. 62411507SCurtis.Dunham@arm.comsystem.cpu3.dcache.tags.sampled_refs 26 # Sample count of references to valid blocks. 62511507SCurtis.Dunham@arm.comsystem.cpu3.dcache.tags.avg_refs 1292.115385 # Average number of references to valid blocks. 62611507SCurtis.Dunham@arm.comsystem.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 62711507SCurtis.Dunham@arm.comsystem.cpu3.dcache.tags.occ_blocks::cpu3.data 28.848199 # Average occupied blocks per requestor 62811507SCurtis.Dunham@arm.comsystem.cpu3.dcache.tags.occ_percent::cpu3.data 0.056344 # Average percentage of cache occupancy 62911507SCurtis.Dunham@arm.comsystem.cpu3.dcache.tags.occ_percent::total 0.056344 # Average percentage of cache occupancy 63011507SCurtis.Dunham@arm.comsystem.cpu3.dcache.tags.occ_task_id_blocks::1024 26 # Occupied blocks per task id 63111507SCurtis.Dunham@arm.comsystem.cpu3.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id 63211507SCurtis.Dunham@arm.comsystem.cpu3.dcache.tags.occ_task_id_percent::1024 0.050781 # Percentage of cache occupancy per task id 63311507SCurtis.Dunham@arm.comsystem.cpu3.dcache.tags.tag_accesses 234241 # Number of tag accesses 63411507SCurtis.Dunham@arm.comsystem.cpu3.dcache.tags.data_accesses 234241 # Number of data accesses 63511507SCurtis.Dunham@arm.comsystem.cpu3.dcache.ReadReq_hits::cpu3.data 42185 # number of ReadReq hits 63611507SCurtis.Dunham@arm.comsystem.cpu3.dcache.ReadReq_hits::total 42185 # number of ReadReq hits 63711507SCurtis.Dunham@arm.comsystem.cpu3.dcache.WriteReq_hits::cpu3.data 15991 # number of WriteReq hits 63811507SCurtis.Dunham@arm.comsystem.cpu3.dcache.WriteReq_hits::total 15991 # number of WriteReq hits 63911507SCurtis.Dunham@arm.comsystem.cpu3.dcache.SwapReq_hits::cpu3.data 12 # number of SwapReq hits 64011507SCurtis.Dunham@arm.comsystem.cpu3.dcache.SwapReq_hits::total 12 # number of SwapReq hits 64111507SCurtis.Dunham@arm.comsystem.cpu3.dcache.demand_hits::cpu3.data 58176 # number of demand (read+write) hits 64211507SCurtis.Dunham@arm.comsystem.cpu3.dcache.demand_hits::total 58176 # number of demand (read+write) hits 64311507SCurtis.Dunham@arm.comsystem.cpu3.dcache.overall_hits::cpu3.data 58176 # number of overall hits 64411507SCurtis.Dunham@arm.comsystem.cpu3.dcache.overall_hits::total 58176 # number of overall hits 64511507SCurtis.Dunham@arm.comsystem.cpu3.dcache.ReadReq_misses::cpu3.data 151 # number of ReadReq misses 64611507SCurtis.Dunham@arm.comsystem.cpu3.dcache.ReadReq_misses::total 151 # number of ReadReq misses 64711507SCurtis.Dunham@arm.comsystem.cpu3.dcache.WriteReq_misses::cpu3.data 109 # number of WriteReq misses 64811507SCurtis.Dunham@arm.comsystem.cpu3.dcache.WriteReq_misses::total 109 # number of WriteReq misses 64911507SCurtis.Dunham@arm.comsystem.cpu3.dcache.SwapReq_misses::cpu3.data 52 # number of SwapReq misses 65011507SCurtis.Dunham@arm.comsystem.cpu3.dcache.SwapReq_misses::total 52 # number of SwapReq misses 65111507SCurtis.Dunham@arm.comsystem.cpu3.dcache.demand_misses::cpu3.data 260 # number of demand (read+write) misses 65211507SCurtis.Dunham@arm.comsystem.cpu3.dcache.demand_misses::total 260 # number of demand (read+write) misses 65311507SCurtis.Dunham@arm.comsystem.cpu3.dcache.overall_misses::cpu3.data 260 # number of overall misses 65411507SCurtis.Dunham@arm.comsystem.cpu3.dcache.overall_misses::total 260 # number of overall misses 65511507SCurtis.Dunham@arm.comsystem.cpu3.dcache.ReadReq_accesses::cpu3.data 42336 # number of ReadReq accesses(hits+misses) 65611507SCurtis.Dunham@arm.comsystem.cpu3.dcache.ReadReq_accesses::total 42336 # number of ReadReq accesses(hits+misses) 65711507SCurtis.Dunham@arm.comsystem.cpu3.dcache.WriteReq_accesses::cpu3.data 16100 # number of WriteReq accesses(hits+misses) 65811507SCurtis.Dunham@arm.comsystem.cpu3.dcache.WriteReq_accesses::total 16100 # number of WriteReq accesses(hits+misses) 65911507SCurtis.Dunham@arm.comsystem.cpu3.dcache.SwapReq_accesses::cpu3.data 64 # number of SwapReq accesses(hits+misses) 66011507SCurtis.Dunham@arm.comsystem.cpu3.dcache.SwapReq_accesses::total 64 # number of SwapReq accesses(hits+misses) 66111507SCurtis.Dunham@arm.comsystem.cpu3.dcache.demand_accesses::cpu3.data 58436 # number of demand (read+write) accesses 66211507SCurtis.Dunham@arm.comsystem.cpu3.dcache.demand_accesses::total 58436 # number of demand (read+write) accesses 66311507SCurtis.Dunham@arm.comsystem.cpu3.dcache.overall_accesses::cpu3.data 58436 # number of overall (read+write) accesses 66411507SCurtis.Dunham@arm.comsystem.cpu3.dcache.overall_accesses::total 58436 # number of overall (read+write) accesses 66511507SCurtis.Dunham@arm.comsystem.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.003567 # miss rate for ReadReq accesses 66611507SCurtis.Dunham@arm.comsystem.cpu3.dcache.ReadReq_miss_rate::total 0.003567 # miss rate for ReadReq accesses 66711507SCurtis.Dunham@arm.comsystem.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.006770 # miss rate for WriteReq accesses 66811507SCurtis.Dunham@arm.comsystem.cpu3.dcache.WriteReq_miss_rate::total 0.006770 # miss rate for WriteReq accesses 66911507SCurtis.Dunham@arm.comsystem.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.812500 # miss rate for SwapReq accesses 67011507SCurtis.Dunham@arm.comsystem.cpu3.dcache.SwapReq_miss_rate::total 0.812500 # miss rate for SwapReq accesses 67111507SCurtis.Dunham@arm.comsystem.cpu3.dcache.demand_miss_rate::cpu3.data 0.004449 # miss rate for demand accesses 67211507SCurtis.Dunham@arm.comsystem.cpu3.dcache.demand_miss_rate::total 0.004449 # miss rate for demand accesses 67311507SCurtis.Dunham@arm.comsystem.cpu3.dcache.overall_miss_rate::cpu3.data 0.004449 # miss rate for overall accesses 67411507SCurtis.Dunham@arm.comsystem.cpu3.dcache.overall_miss_rate::total 0.004449 # miss rate for overall accesses 67511507SCurtis.Dunham@arm.comsystem.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 67611507SCurtis.Dunham@arm.comsystem.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 67711507SCurtis.Dunham@arm.comsystem.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 67811507SCurtis.Dunham@arm.comsystem.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked 67911507SCurtis.Dunham@arm.comsystem.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 68011507SCurtis.Dunham@arm.comsystem.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 68111507SCurtis.Dunham@arm.comsystem.cpu3.icache.tags.replacements 279 # number of replacements 68211507SCurtis.Dunham@arm.comsystem.cpu3.icache.tags.tagsinuse 72.874953 # Cycle average of tags in use 68311507SCurtis.Dunham@arm.comsystem.cpu3.icache.tags.total_refs 166945 # Total number of references to valid blocks. 68411507SCurtis.Dunham@arm.comsystem.cpu3.icache.tags.sampled_refs 359 # Sample count of references to valid blocks. 68511507SCurtis.Dunham@arm.comsystem.cpu3.icache.tags.avg_refs 465.027855 # Average number of references to valid blocks. 68611507SCurtis.Dunham@arm.comsystem.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 68711507SCurtis.Dunham@arm.comsystem.cpu3.icache.tags.occ_blocks::cpu3.inst 72.874953 # Average occupied blocks per requestor 68811507SCurtis.Dunham@arm.comsystem.cpu3.icache.tags.occ_percent::cpu3.inst 0.142334 # Average percentage of cache occupancy 68911507SCurtis.Dunham@arm.comsystem.cpu3.icache.tags.occ_percent::total 0.142334 # Average percentage of cache occupancy 69011507SCurtis.Dunham@arm.comsystem.cpu3.icache.tags.occ_task_id_blocks::1024 80 # Occupied blocks per task id 69111507SCurtis.Dunham@arm.comsystem.cpu3.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id 69211507SCurtis.Dunham@arm.comsystem.cpu3.icache.tags.age_task_id_blocks_1024::1 71 # Occupied blocks per task id 69311507SCurtis.Dunham@arm.comsystem.cpu3.icache.tags.occ_task_id_percent::1024 0.156250 # Percentage of cache occupancy per task id 69411507SCurtis.Dunham@arm.comsystem.cpu3.icache.tags.tag_accesses 167663 # Number of tag accesses 69511507SCurtis.Dunham@arm.comsystem.cpu3.icache.tags.data_accesses 167663 # Number of data accesses 69611507SCurtis.Dunham@arm.comsystem.cpu3.icache.ReadReq_hits::cpu3.inst 166945 # number of ReadReq hits 69711507SCurtis.Dunham@arm.comsystem.cpu3.icache.ReadReq_hits::total 166945 # number of ReadReq hits 69811507SCurtis.Dunham@arm.comsystem.cpu3.icache.demand_hits::cpu3.inst 166945 # number of demand (read+write) hits 69911507SCurtis.Dunham@arm.comsystem.cpu3.icache.demand_hits::total 166945 # number of demand (read+write) hits 70011507SCurtis.Dunham@arm.comsystem.cpu3.icache.overall_hits::cpu3.inst 166945 # number of overall hits 70111507SCurtis.Dunham@arm.comsystem.cpu3.icache.overall_hits::total 166945 # number of overall hits 70211507SCurtis.Dunham@arm.comsystem.cpu3.icache.ReadReq_misses::cpu3.inst 359 # number of ReadReq misses 70311507SCurtis.Dunham@arm.comsystem.cpu3.icache.ReadReq_misses::total 359 # number of ReadReq misses 70411507SCurtis.Dunham@arm.comsystem.cpu3.icache.demand_misses::cpu3.inst 359 # number of demand (read+write) misses 70511507SCurtis.Dunham@arm.comsystem.cpu3.icache.demand_misses::total 359 # number of demand (read+write) misses 70611507SCurtis.Dunham@arm.comsystem.cpu3.icache.overall_misses::cpu3.inst 359 # number of overall misses 70711507SCurtis.Dunham@arm.comsystem.cpu3.icache.overall_misses::total 359 # number of overall misses 70811507SCurtis.Dunham@arm.comsystem.cpu3.icache.ReadReq_accesses::cpu3.inst 167304 # number of ReadReq accesses(hits+misses) 70911507SCurtis.Dunham@arm.comsystem.cpu3.icache.ReadReq_accesses::total 167304 # number of ReadReq accesses(hits+misses) 71011507SCurtis.Dunham@arm.comsystem.cpu3.icache.demand_accesses::cpu3.inst 167304 # number of demand (read+write) accesses 71111507SCurtis.Dunham@arm.comsystem.cpu3.icache.demand_accesses::total 167304 # number of demand (read+write) accesses 71211507SCurtis.Dunham@arm.comsystem.cpu3.icache.overall_accesses::cpu3.inst 167304 # number of overall (read+write) accesses 71311507SCurtis.Dunham@arm.comsystem.cpu3.icache.overall_accesses::total 167304 # number of overall (read+write) accesses 71411507SCurtis.Dunham@arm.comsystem.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.002146 # miss rate for ReadReq accesses 71511507SCurtis.Dunham@arm.comsystem.cpu3.icache.ReadReq_miss_rate::total 0.002146 # miss rate for ReadReq accesses 71611507SCurtis.Dunham@arm.comsystem.cpu3.icache.demand_miss_rate::cpu3.inst 0.002146 # miss rate for demand accesses 71711507SCurtis.Dunham@arm.comsystem.cpu3.icache.demand_miss_rate::total 0.002146 # miss rate for demand accesses 71811507SCurtis.Dunham@arm.comsystem.cpu3.icache.overall_miss_rate::cpu3.inst 0.002146 # miss rate for overall accesses 71911507SCurtis.Dunham@arm.comsystem.cpu3.icache.overall_miss_rate::total 0.002146 # miss rate for overall accesses 72011507SCurtis.Dunham@arm.comsystem.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 72111507SCurtis.Dunham@arm.comsystem.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 72211507SCurtis.Dunham@arm.comsystem.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked 72311507SCurtis.Dunham@arm.comsystem.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked 72411507SCurtis.Dunham@arm.comsystem.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 72511507SCurtis.Dunham@arm.comsystem.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 72611507SCurtis.Dunham@arm.comsystem.cpu3.icache.writebacks::writebacks 279 # number of writebacks 72711507SCurtis.Dunham@arm.comsystem.cpu3.icache.writebacks::total 279 # number of writebacks 72811507SCurtis.Dunham@arm.comsystem.l2c.tags.replacements 0 # number of replacements 72911507SCurtis.Dunham@arm.comsystem.l2c.tags.tagsinuse 367.545675 # Cycle average of tags in use 73011507SCurtis.Dunham@arm.comsystem.l2c.tags.total_refs 1716 # Total number of references to valid blocks. 73111507SCurtis.Dunham@arm.comsystem.l2c.tags.sampled_refs 422 # Sample count of references to valid blocks. 73211507SCurtis.Dunham@arm.comsystem.l2c.tags.avg_refs 4.066351 # Average number of references to valid blocks. 73311507SCurtis.Dunham@arm.comsystem.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 73411507SCurtis.Dunham@arm.comsystem.l2c.tags.occ_blocks::writebacks 0.966439 # Average occupied blocks per requestor 73511507SCurtis.Dunham@arm.comsystem.l2c.tags.occ_blocks::cpu0.inst 239.426226 # Average occupied blocks per requestor 73611507SCurtis.Dunham@arm.comsystem.l2c.tags.occ_blocks::cpu0.data 56.170311 # Average occupied blocks per requestor 73711507SCurtis.Dunham@arm.comsystem.l2c.tags.occ_blocks::cpu1.inst 59.512205 # Average occupied blocks per requestor 73811507SCurtis.Dunham@arm.comsystem.l2c.tags.occ_blocks::cpu1.data 6.721185 # Average occupied blocks per requestor 73911507SCurtis.Dunham@arm.comsystem.l2c.tags.occ_blocks::cpu2.inst 1.942787 # Average occupied blocks per requestor 74011507SCurtis.Dunham@arm.comsystem.l2c.tags.occ_blocks::cpu2.data 0.935416 # Average occupied blocks per requestor 74111507SCurtis.Dunham@arm.comsystem.l2c.tags.occ_blocks::cpu3.inst 0.965459 # Average occupied blocks per requestor 74211507SCurtis.Dunham@arm.comsystem.l2c.tags.occ_blocks::cpu3.data 0.905646 # Average occupied blocks per requestor 74311507SCurtis.Dunham@arm.comsystem.l2c.tags.occ_percent::writebacks 0.000015 # Average percentage of cache occupancy 74411507SCurtis.Dunham@arm.comsystem.l2c.tags.occ_percent::cpu0.inst 0.003653 # Average percentage of cache occupancy 74511507SCurtis.Dunham@arm.comsystem.l2c.tags.occ_percent::cpu0.data 0.000857 # Average percentage of cache occupancy 74611507SCurtis.Dunham@arm.comsystem.l2c.tags.occ_percent::cpu1.inst 0.000908 # Average percentage of cache occupancy 74711507SCurtis.Dunham@arm.comsystem.l2c.tags.occ_percent::cpu1.data 0.000103 # Average percentage of cache occupancy 74811507SCurtis.Dunham@arm.comsystem.l2c.tags.occ_percent::cpu2.inst 0.000030 # Average percentage of cache occupancy 74911507SCurtis.Dunham@arm.comsystem.l2c.tags.occ_percent::cpu2.data 0.000014 # Average percentage of cache occupancy 75011507SCurtis.Dunham@arm.comsystem.l2c.tags.occ_percent::cpu3.inst 0.000015 # Average percentage of cache occupancy 75111507SCurtis.Dunham@arm.comsystem.l2c.tags.occ_percent::cpu3.data 0.000014 # Average percentage of cache occupancy 75211507SCurtis.Dunham@arm.comsystem.l2c.tags.occ_percent::total 0.005608 # Average percentage of cache occupancy 75311507SCurtis.Dunham@arm.comsystem.l2c.tags.occ_task_id_blocks::1024 422 # Occupied blocks per task id 75411507SCurtis.Dunham@arm.comsystem.l2c.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id 75511507SCurtis.Dunham@arm.comsystem.l2c.tags.age_task_id_blocks_1024::1 374 # Occupied blocks per task id 75611507SCurtis.Dunham@arm.comsystem.l2c.tags.occ_task_id_percent::1024 0.006439 # Percentage of cache occupancy per task id 75711507SCurtis.Dunham@arm.comsystem.l2c.tags.tag_accesses 19424 # Number of tag accesses 75811507SCurtis.Dunham@arm.comsystem.l2c.tags.data_accesses 19424 # Number of data accesses 75911507SCurtis.Dunham@arm.comsystem.l2c.WritebackDirty_hits::writebacks 1 # number of WritebackDirty hits 76011507SCurtis.Dunham@arm.comsystem.l2c.WritebackDirty_hits::total 1 # number of WritebackDirty hits 76111507SCurtis.Dunham@arm.comsystem.l2c.WritebackClean_hits::writebacks 495 # number of WritebackClean hits 76211507SCurtis.Dunham@arm.comsystem.l2c.WritebackClean_hits::total 495 # number of WritebackClean hits 76311507SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_hits::cpu0.data 2 # number of UpgradeReq hits 76411507SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_hits::total 2 # number of UpgradeReq hits 76511507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_hits::cpu0.inst 185 # number of ReadCleanReq hits 76611507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_hits::cpu1.inst 296 # number of ReadCleanReq hits 76711507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_hits::cpu2.inst 355 # number of ReadCleanReq hits 76811507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_hits::cpu3.inst 358 # number of ReadCleanReq hits 76911507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_hits::total 1194 # number of ReadCleanReq hits 77011507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.data 5 # number of ReadSharedReq hits 77111507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.data 3 # number of ReadSharedReq hits 77211507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_hits::cpu2.data 9 # number of ReadSharedReq hits 77311507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_hits::cpu3.data 9 # number of ReadSharedReq hits 77411507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_hits::total 26 # number of ReadSharedReq hits 77511507SCurtis.Dunham@arm.comsystem.l2c.demand_hits::cpu0.inst 185 # number of demand (read+write) hits 77611507SCurtis.Dunham@arm.comsystem.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits 77711507SCurtis.Dunham@arm.comsystem.l2c.demand_hits::cpu1.inst 296 # number of demand (read+write) hits 77811507SCurtis.Dunham@arm.comsystem.l2c.demand_hits::cpu1.data 3 # number of demand (read+write) hits 77911507SCurtis.Dunham@arm.comsystem.l2c.demand_hits::cpu2.inst 355 # number of demand (read+write) hits 78011507SCurtis.Dunham@arm.comsystem.l2c.demand_hits::cpu2.data 9 # number of demand (read+write) hits 78111507SCurtis.Dunham@arm.comsystem.l2c.demand_hits::cpu3.inst 358 # number of demand (read+write) hits 78211507SCurtis.Dunham@arm.comsystem.l2c.demand_hits::cpu3.data 9 # number of demand (read+write) hits 78311507SCurtis.Dunham@arm.comsystem.l2c.demand_hits::total 1220 # number of demand (read+write) hits 78411507SCurtis.Dunham@arm.comsystem.l2c.overall_hits::cpu0.inst 185 # number of overall hits 78511507SCurtis.Dunham@arm.comsystem.l2c.overall_hits::cpu0.data 5 # number of overall hits 78611507SCurtis.Dunham@arm.comsystem.l2c.overall_hits::cpu1.inst 296 # number of overall hits 78711507SCurtis.Dunham@arm.comsystem.l2c.overall_hits::cpu1.data 3 # number of overall hits 78811507SCurtis.Dunham@arm.comsystem.l2c.overall_hits::cpu2.inst 355 # number of overall hits 78911507SCurtis.Dunham@arm.comsystem.l2c.overall_hits::cpu2.data 9 # number of overall hits 79011507SCurtis.Dunham@arm.comsystem.l2c.overall_hits::cpu3.inst 358 # number of overall hits 79111507SCurtis.Dunham@arm.comsystem.l2c.overall_hits::cpu3.data 9 # number of overall hits 79211507SCurtis.Dunham@arm.comsystem.l2c.overall_hits::total 1220 # number of overall hits 79311507SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_misses::cpu0.data 28 # number of UpgradeReq misses 79411507SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_misses::cpu1.data 16 # number of UpgradeReq misses 79511507SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_misses::cpu2.data 17 # number of UpgradeReq misses 79611507SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_misses::cpu3.data 19 # number of UpgradeReq misses 79711507SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_misses::total 80 # number of UpgradeReq misses 79811507SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_misses::cpu0.data 99 # number of ReadExReq misses 79911507SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_misses::cpu1.data 13 # number of ReadExReq misses 80011507SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_misses::cpu2.data 12 # number of ReadExReq misses 80111507SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_misses::cpu3.data 12 # number of ReadExReq misses 80211507SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_misses::total 136 # number of ReadExReq misses 80311507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_misses::cpu0.inst 282 # number of ReadCleanReq misses 80411507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_misses::cpu1.inst 62 # number of ReadCleanReq misses 80511507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_misses::cpu2.inst 3 # number of ReadCleanReq misses 80611507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_misses::cpu3.inst 1 # number of ReadCleanReq misses 80711507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_misses::total 348 # number of ReadCleanReq misses 80811507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.data 66 # number of ReadSharedReq misses 80911507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.data 7 # number of ReadSharedReq misses 81011507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_misses::cpu2.data 1 # number of ReadSharedReq misses 81111507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_misses::cpu3.data 1 # number of ReadSharedReq misses 81211507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_misses::total 75 # number of ReadSharedReq misses 81311507SCurtis.Dunham@arm.comsystem.l2c.demand_misses::cpu0.inst 282 # number of demand (read+write) misses 81411507SCurtis.Dunham@arm.comsystem.l2c.demand_misses::cpu0.data 165 # number of demand (read+write) misses 81511507SCurtis.Dunham@arm.comsystem.l2c.demand_misses::cpu1.inst 62 # number of demand (read+write) misses 81611507SCurtis.Dunham@arm.comsystem.l2c.demand_misses::cpu1.data 20 # number of demand (read+write) misses 81711507SCurtis.Dunham@arm.comsystem.l2c.demand_misses::cpu2.inst 3 # number of demand (read+write) misses 81811507SCurtis.Dunham@arm.comsystem.l2c.demand_misses::cpu2.data 13 # number of demand (read+write) misses 81911507SCurtis.Dunham@arm.comsystem.l2c.demand_misses::cpu3.inst 1 # number of demand (read+write) misses 82011507SCurtis.Dunham@arm.comsystem.l2c.demand_misses::cpu3.data 13 # number of demand (read+write) misses 82111507SCurtis.Dunham@arm.comsystem.l2c.demand_misses::total 559 # number of demand (read+write) misses 82211507SCurtis.Dunham@arm.comsystem.l2c.overall_misses::cpu0.inst 282 # number of overall misses 82311507SCurtis.Dunham@arm.comsystem.l2c.overall_misses::cpu0.data 165 # number of overall misses 82411507SCurtis.Dunham@arm.comsystem.l2c.overall_misses::cpu1.inst 62 # number of overall misses 82511507SCurtis.Dunham@arm.comsystem.l2c.overall_misses::cpu1.data 20 # number of overall misses 82611507SCurtis.Dunham@arm.comsystem.l2c.overall_misses::cpu2.inst 3 # number of overall misses 82711507SCurtis.Dunham@arm.comsystem.l2c.overall_misses::cpu2.data 13 # number of overall misses 82811507SCurtis.Dunham@arm.comsystem.l2c.overall_misses::cpu3.inst 1 # number of overall misses 82911507SCurtis.Dunham@arm.comsystem.l2c.overall_misses::cpu3.data 13 # number of overall misses 83011507SCurtis.Dunham@arm.comsystem.l2c.overall_misses::total 559 # number of overall misses 83111507SCurtis.Dunham@arm.comsystem.l2c.WritebackDirty_accesses::writebacks 1 # number of WritebackDirty accesses(hits+misses) 83211507SCurtis.Dunham@arm.comsystem.l2c.WritebackDirty_accesses::total 1 # number of WritebackDirty accesses(hits+misses) 83311507SCurtis.Dunham@arm.comsystem.l2c.WritebackClean_accesses::writebacks 495 # number of WritebackClean accesses(hits+misses) 83411507SCurtis.Dunham@arm.comsystem.l2c.WritebackClean_accesses::total 495 # number of WritebackClean accesses(hits+misses) 83511507SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_accesses::cpu0.data 30 # number of UpgradeReq accesses(hits+misses) 83611507SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_accesses::cpu1.data 16 # number of UpgradeReq accesses(hits+misses) 83711507SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_accesses::cpu2.data 17 # number of UpgradeReq accesses(hits+misses) 83811507SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_accesses::cpu3.data 19 # number of UpgradeReq accesses(hits+misses) 83911507SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_accesses::total 82 # number of UpgradeReq accesses(hits+misses) 84011507SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_accesses::cpu0.data 99 # number of ReadExReq accesses(hits+misses) 84111507SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_accesses::cpu1.data 13 # number of ReadExReq accesses(hits+misses) 84211507SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_accesses::cpu2.data 12 # number of ReadExReq accesses(hits+misses) 84311507SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_accesses::cpu3.data 12 # number of ReadExReq accesses(hits+misses) 84411507SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_accesses::total 136 # number of ReadExReq accesses(hits+misses) 84511507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_accesses::cpu0.inst 467 # number of ReadCleanReq accesses(hits+misses) 84611507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_accesses::cpu1.inst 358 # number of ReadCleanReq accesses(hits+misses) 84711507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_accesses::cpu2.inst 358 # number of ReadCleanReq accesses(hits+misses) 84811507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_accesses::cpu3.inst 359 # number of ReadCleanReq accesses(hits+misses) 84911507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_accesses::total 1542 # number of ReadCleanReq accesses(hits+misses) 85011507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.data 71 # number of ReadSharedReq accesses(hits+misses) 85111507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.data 10 # number of ReadSharedReq accesses(hits+misses) 85211507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_accesses::cpu2.data 10 # number of ReadSharedReq accesses(hits+misses) 85311507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_accesses::cpu3.data 10 # number of ReadSharedReq accesses(hits+misses) 85411507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_accesses::total 101 # number of ReadSharedReq accesses(hits+misses) 85511507SCurtis.Dunham@arm.comsystem.l2c.demand_accesses::cpu0.inst 467 # number of demand (read+write) accesses 85611507SCurtis.Dunham@arm.comsystem.l2c.demand_accesses::cpu0.data 170 # number of demand (read+write) accesses 85711507SCurtis.Dunham@arm.comsystem.l2c.demand_accesses::cpu1.inst 358 # number of demand (read+write) accesses 85811507SCurtis.Dunham@arm.comsystem.l2c.demand_accesses::cpu1.data 23 # number of demand (read+write) accesses 85911507SCurtis.Dunham@arm.comsystem.l2c.demand_accesses::cpu2.inst 358 # number of demand (read+write) accesses 86011507SCurtis.Dunham@arm.comsystem.l2c.demand_accesses::cpu2.data 22 # number of demand (read+write) accesses 86111507SCurtis.Dunham@arm.comsystem.l2c.demand_accesses::cpu3.inst 359 # number of demand (read+write) accesses 86211507SCurtis.Dunham@arm.comsystem.l2c.demand_accesses::cpu3.data 22 # number of demand (read+write) accesses 86311507SCurtis.Dunham@arm.comsystem.l2c.demand_accesses::total 1779 # number of demand (read+write) accesses 86411507SCurtis.Dunham@arm.comsystem.l2c.overall_accesses::cpu0.inst 467 # number of overall (read+write) accesses 86511507SCurtis.Dunham@arm.comsystem.l2c.overall_accesses::cpu0.data 170 # number of overall (read+write) accesses 86611507SCurtis.Dunham@arm.comsystem.l2c.overall_accesses::cpu1.inst 358 # number of overall (read+write) accesses 86711507SCurtis.Dunham@arm.comsystem.l2c.overall_accesses::cpu1.data 23 # number of overall (read+write) accesses 86811507SCurtis.Dunham@arm.comsystem.l2c.overall_accesses::cpu2.inst 358 # number of overall (read+write) accesses 86911507SCurtis.Dunham@arm.comsystem.l2c.overall_accesses::cpu2.data 22 # number of overall (read+write) accesses 87011507SCurtis.Dunham@arm.comsystem.l2c.overall_accesses::cpu3.inst 359 # number of overall (read+write) accesses 87111507SCurtis.Dunham@arm.comsystem.l2c.overall_accesses::cpu3.data 22 # number of overall (read+write) accesses 87211507SCurtis.Dunham@arm.comsystem.l2c.overall_accesses::total 1779 # number of overall (read+write) accesses 87311507SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_miss_rate::cpu0.data 0.933333 # miss rate for UpgradeReq accesses 87411507SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses 87511507SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses 87611507SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses 87711507SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_miss_rate::total 0.975610 # miss rate for UpgradeReq accesses 87811507SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses 87911507SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses 88011507SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses 88111507SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses 88211507SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 88311507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.603854 # miss rate for ReadCleanReq accesses 88411507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.173184 # miss rate for ReadCleanReq accesses 88511507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_miss_rate::cpu2.inst 0.008380 # miss rate for ReadCleanReq accesses 88611507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_miss_rate::cpu3.inst 0.002786 # miss rate for ReadCleanReq accesses 88711507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_miss_rate::total 0.225681 # miss rate for ReadCleanReq accesses 88811507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.data 0.929577 # miss rate for ReadSharedReq accesses 88911507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.data 0.700000 # miss rate for ReadSharedReq accesses 89011507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu2.data 0.100000 # miss rate for ReadSharedReq accesses 89111507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu3.data 0.100000 # miss rate for ReadSharedReq accesses 89211507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_rate::total 0.742574 # miss rate for ReadSharedReq accesses 89311507SCurtis.Dunham@arm.comsystem.l2c.demand_miss_rate::cpu0.inst 0.603854 # miss rate for demand accesses 89411507SCurtis.Dunham@arm.comsystem.l2c.demand_miss_rate::cpu0.data 0.970588 # miss rate for demand accesses 89511507SCurtis.Dunham@arm.comsystem.l2c.demand_miss_rate::cpu1.inst 0.173184 # miss rate for demand accesses 89611507SCurtis.Dunham@arm.comsystem.l2c.demand_miss_rate::cpu1.data 0.869565 # miss rate for demand accesses 89711507SCurtis.Dunham@arm.comsystem.l2c.demand_miss_rate::cpu2.inst 0.008380 # miss rate for demand accesses 89811507SCurtis.Dunham@arm.comsystem.l2c.demand_miss_rate::cpu2.data 0.590909 # miss rate for demand accesses 89911507SCurtis.Dunham@arm.comsystem.l2c.demand_miss_rate::cpu3.inst 0.002786 # miss rate for demand accesses 90011507SCurtis.Dunham@arm.comsystem.l2c.demand_miss_rate::cpu3.data 0.590909 # miss rate for demand accesses 90111507SCurtis.Dunham@arm.comsystem.l2c.demand_miss_rate::total 0.314221 # miss rate for demand accesses 90211507SCurtis.Dunham@arm.comsystem.l2c.overall_miss_rate::cpu0.inst 0.603854 # miss rate for overall accesses 90311507SCurtis.Dunham@arm.comsystem.l2c.overall_miss_rate::cpu0.data 0.970588 # miss rate for overall accesses 90411507SCurtis.Dunham@arm.comsystem.l2c.overall_miss_rate::cpu1.inst 0.173184 # miss rate for overall accesses 90511507SCurtis.Dunham@arm.comsystem.l2c.overall_miss_rate::cpu1.data 0.869565 # miss rate for overall accesses 90611507SCurtis.Dunham@arm.comsystem.l2c.overall_miss_rate::cpu2.inst 0.008380 # miss rate for overall accesses 90711507SCurtis.Dunham@arm.comsystem.l2c.overall_miss_rate::cpu2.data 0.590909 # miss rate for overall accesses 90811507SCurtis.Dunham@arm.comsystem.l2c.overall_miss_rate::cpu3.inst 0.002786 # miss rate for overall accesses 90911507SCurtis.Dunham@arm.comsystem.l2c.overall_miss_rate::cpu3.data 0.590909 # miss rate for overall accesses 91011507SCurtis.Dunham@arm.comsystem.l2c.overall_miss_rate::total 0.314221 # miss rate for overall accesses 91111507SCurtis.Dunham@arm.comsystem.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 91211507SCurtis.Dunham@arm.comsystem.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 91311507SCurtis.Dunham@arm.comsystem.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 91411507SCurtis.Dunham@arm.comsystem.l2c.blocked::no_targets 0 # number of cycles access was blocked 91511507SCurtis.Dunham@arm.comsystem.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 91611507SCurtis.Dunham@arm.comsystem.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 91711507SCurtis.Dunham@arm.comsystem.membus.snoop_filter.tot_requests 879 # Total number of requests made to the snoop filter. 91811507SCurtis.Dunham@arm.comsystem.membus.snoop_filter.hit_single_requests 320 # Number of requests hitting in the snoop filter with a single holder of the requested data. 91911507SCurtis.Dunham@arm.comsystem.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 92011507SCurtis.Dunham@arm.comsystem.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 92111507SCurtis.Dunham@arm.comsystem.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 92211507SCurtis.Dunham@arm.comsystem.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 92311507SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadResp 423 # Transaction distribution 92411507SCurtis.Dunham@arm.comsystem.membus.trans_dist::UpgradeReq 273 # Transaction distribution 92511507SCurtis.Dunham@arm.comsystem.membus.trans_dist::UpgradeResp 80 # Transaction distribution 92611507SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadExReq 183 # Transaction distribution 92711507SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadExResp 136 # Transaction distribution 92811507SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadSharedReq 423 # Transaction distribution 92911507SCurtis.Dunham@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1518 # Packet count per connected master and slave (bytes) 93011507SCurtis.Dunham@arm.comsystem.membus.pkt_count::total 1518 # Packet count per connected master and slave (bytes) 93111507SCurtis.Dunham@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.physmem.port 35776 # Cumulative packet size per connected master and slave (bytes) 93211507SCurtis.Dunham@arm.comsystem.membus.pkt_size::total 35776 # Cumulative packet size per connected master and slave (bytes) 93311507SCurtis.Dunham@arm.comsystem.membus.snoops 0 # Total snoops (count) 93411507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::samples 879 # Request fanout histogram 93511507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::mean 0 # Request fanout histogram 93611507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::stdev 0 # Request fanout histogram 93711507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 93811507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::0 879 100.00% 100.00% # Request fanout histogram 93911507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 94011507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 94111507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::min_value 0 # Request fanout histogram 94211507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::max_value 0 # Request fanout histogram 94311507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::total 879 # Request fanout histogram 94411507SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_filter.tot_requests 3918 # Total number of requests made to the snoop filter. 94511507SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_filter.hit_single_requests 1221 # Number of requests hitting in the snoop filter with a single holder of the requested data. 94611507SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_filter.hit_multi_requests 1709 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 94711507SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 94811507SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 94911507SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 95011507SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::ReadResp 2179 # Transaction distribution 95111507SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::WritebackDirty 1 # Transaction distribution 95211507SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::WritebackClean 1050 # Transaction distribution 95311507SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::CleanEvict 1 # Transaction distribution 95411507SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::UpgradeReq 275 # Transaction distribution 95511507SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::UpgradeResp 275 # Transaction distribution 95611507SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::ReadExReq 412 # Transaction distribution 95711507SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::ReadExResp 412 # Transaction distribution 95811507SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::ReadCleanReq 1542 # Transaction distribution 95911507SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::ReadSharedReq 637 # Transaction distribution 96011507SCurtis.Dunham@arm.comsystem.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1149 # Packet count per connected master and slave (bytes) 96111507SCurtis.Dunham@arm.comsystem.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 712 # Packet count per connected master and slave (bytes) 96211507SCurtis.Dunham@arm.comsystem.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 994 # Packet count per connected master and slave (bytes) 96311507SCurtis.Dunham@arm.comsystem.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 696 # Packet count per connected master and slave (bytes) 96411507SCurtis.Dunham@arm.comsystem.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 994 # Packet count per connected master and slave (bytes) 96511507SCurtis.Dunham@arm.comsystem.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 618 # Packet count per connected master and slave (bytes) 96611507SCurtis.Dunham@arm.comsystem.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 997 # Packet count per connected master and slave (bytes) 96711507SCurtis.Dunham@arm.comsystem.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 624 # Packet count per connected master and slave (bytes) 96811507SCurtis.Dunham@arm.comsystem.toL2Bus.pkt_count::total 6784 # Packet count per connected master and slave (bytes) 96911507SCurtis.Dunham@arm.comsystem.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 43648 # Cumulative packet size per connected master and slave (bytes) 97011507SCurtis.Dunham@arm.comsystem.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 18752 # Cumulative packet size per connected master and slave (bytes) 97111507SCurtis.Dunham@arm.comsystem.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 40704 # Cumulative packet size per connected master and slave (bytes) 97211507SCurtis.Dunham@arm.comsystem.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 17600 # Cumulative packet size per connected master and slave (bytes) 97311507SCurtis.Dunham@arm.comsystem.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 40704 # Cumulative packet size per connected master and slave (bytes) 97411507SCurtis.Dunham@arm.comsystem.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 15424 # Cumulative packet size per connected master and slave (bytes) 97511507SCurtis.Dunham@arm.comsystem.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 40832 # Cumulative packet size per connected master and slave (bytes) 97611507SCurtis.Dunham@arm.comsystem.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 15424 # Cumulative packet size per connected master and slave (bytes) 97711507SCurtis.Dunham@arm.comsystem.toL2Bus.pkt_size::total 233088 # Cumulative packet size per connected master and slave (bytes) 97811507SCurtis.Dunham@arm.comsystem.toL2Bus.snoops 0 # Total snoops (count) 97911507SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::samples 3918 # Request fanout histogram 98011507SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::mean 1.246554 # Request fanout histogram 98111507SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::stdev 1.199505 # Request fanout histogram 98211507SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 98311507SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::0 1485 37.90% 37.90% # Request fanout histogram 98411507SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::1 951 24.27% 62.17% # Request fanout histogram 98511507SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::2 513 13.09% 75.27% # Request fanout histogram 98611507SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::3 969 24.73% 100.00% # Request fanout histogram 98711507SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram 98811507SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::5 0 0.00% 100.00% # Request fanout histogram 98911507SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram 99011507SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::7 0 0.00% 100.00% # Request fanout histogram 99111507SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram 99211507SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 99311507SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 99411507SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram 99511507SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::total 3918 # Request fanout histogram 99611507SCurtis.Dunham@arm.com 99711507SCurtis.Dunham@arm.com---------- End Simulation Statistics ---------- 998