stats.txt revision 9797:9cd5f91e7a79
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000111 # Number of seconds simulated 4sim_ticks 110804500 # Number of ticks simulated 5final_tick 110804500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 110530 # Simulator instruction rate (inst/s) 8host_op_rate 110530 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 11745373 # Simulator tick rate (ticks/s) 10host_mem_usage 249508 # Number of bytes of host memory used 11host_seconds 9.43 # Real time elapsed on the host 12sim_insts 1042724 # Number of instructions simulated 13sim_ops 1042724 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu0.inst 22784 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu0.data 10752 # Number of bytes read from this memory 16system.physmem.bytes_read::cpu1.inst 640 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu1.data 832 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu2.inst 4672 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu2.data 1280 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu3.inst 384 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu3.data 832 # Number of bytes read from this memory 22system.physmem.bytes_read::total 42176 # Number of bytes read from this memory 23system.physmem.bytes_inst_read::cpu0.inst 22784 # Number of instructions bytes read from this memory 24system.physmem.bytes_inst_read::cpu1.inst 640 # Number of instructions bytes read from this memory 25system.physmem.bytes_inst_read::cpu2.inst 4672 # Number of instructions bytes read from this memory 26system.physmem.bytes_inst_read::cpu3.inst 384 # Number of instructions bytes read from this memory 27system.physmem.bytes_inst_read::total 28480 # Number of instructions bytes read from this memory 28system.physmem.num_reads::cpu0.inst 356 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu0.data 168 # Number of read requests responded to by this memory 30system.physmem.num_reads::cpu1.inst 10 # Number of read requests responded to by this memory 31system.physmem.num_reads::cpu1.data 13 # Number of read requests responded to by this memory 32system.physmem.num_reads::cpu2.inst 73 # Number of read requests responded to by this memory 33system.physmem.num_reads::cpu2.data 20 # Number of read requests responded to by this memory 34system.physmem.num_reads::cpu3.inst 6 # Number of read requests responded to by this memory 35system.physmem.num_reads::cpu3.data 13 # Number of read requests responded to by this memory 36system.physmem.num_reads::total 659 # Number of read requests responded to by this memory 37system.physmem.bw_read::cpu0.inst 205623418 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu0.data 97035770 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::cpu1.inst 5775939 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::cpu1.data 7508720 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::cpu2.inst 42164353 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_read::cpu2.data 11551877 # Total read bandwidth from this memory (bytes/s) 43system.physmem.bw_read::cpu3.inst 3465563 # Total read bandwidth from this memory (bytes/s) 44system.physmem.bw_read::cpu3.data 7508720 # Total read bandwidth from this memory (bytes/s) 45system.physmem.bw_read::total 380634361 # Total read bandwidth from this memory (bytes/s) 46system.physmem.bw_inst_read::cpu0.inst 205623418 # Instruction read bandwidth from this memory (bytes/s) 47system.physmem.bw_inst_read::cpu1.inst 5775939 # Instruction read bandwidth from this memory (bytes/s) 48system.physmem.bw_inst_read::cpu2.inst 42164353 # Instruction read bandwidth from this memory (bytes/s) 49system.physmem.bw_inst_read::cpu3.inst 3465563 # Instruction read bandwidth from this memory (bytes/s) 50system.physmem.bw_inst_read::total 257029272 # Instruction read bandwidth from this memory (bytes/s) 51system.physmem.bw_total::cpu0.inst 205623418 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::cpu0.data 97035770 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.bw_total::cpu1.inst 5775939 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.bw_total::cpu1.data 7508720 # Total bandwidth to/from this memory (bytes/s) 55system.physmem.bw_total::cpu2.inst 42164353 # Total bandwidth to/from this memory (bytes/s) 56system.physmem.bw_total::cpu2.data 11551877 # Total bandwidth to/from this memory (bytes/s) 57system.physmem.bw_total::cpu3.inst 3465563 # Total bandwidth to/from this memory (bytes/s) 58system.physmem.bw_total::cpu3.data 7508720 # Total bandwidth to/from this memory (bytes/s) 59system.physmem.bw_total::total 380634361 # Total bandwidth to/from this memory (bytes/s) 60system.physmem.readReqs 660 # Total number of read requests seen 61system.physmem.writeReqs 0 # Total number of write requests seen 62system.physmem.cpureqs 736 # Reqs generatd by CPU via cache - shady 63system.physmem.bytesRead 42176 # Total number of bytes read from memory 64system.physmem.bytesWritten 0 # Total number of bytes written to memory 65system.physmem.bytesConsumedRd 42176 # bytesRead derated as per pkt->getSize() 66system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() 67system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q 68system.physmem.neitherReadNorWrite 76 # Reqs where no action is needed 69system.physmem.perBankRdReqs::0 115 # Track reads on a per bank basis 70system.physmem.perBankRdReqs::1 39 # Track reads on a per bank basis 71system.physmem.perBankRdReqs::2 29 # Track reads on a per bank basis 72system.physmem.perBankRdReqs::3 60 # Track reads on a per bank basis 73system.physmem.perBankRdReqs::4 65 # Track reads on a per bank basis 74system.physmem.perBankRdReqs::5 27 # Track reads on a per bank basis 75system.physmem.perBankRdReqs::6 18 # Track reads on a per bank basis 76system.physmem.perBankRdReqs::7 24 # Track reads on a per bank basis 77system.physmem.perBankRdReqs::8 7 # Track reads on a per bank basis 78system.physmem.perBankRdReqs::9 28 # Track reads on a per bank basis 79system.physmem.perBankRdReqs::10 23 # Track reads on a per bank basis 80system.physmem.perBankRdReqs::11 12 # Track reads on a per bank basis 81system.physmem.perBankRdReqs::12 60 # Track reads on a per bank basis 82system.physmem.perBankRdReqs::13 38 # Track reads on a per bank basis 83system.physmem.perBankRdReqs::14 17 # Track reads on a per bank basis 84system.physmem.perBankRdReqs::15 98 # Track reads on a per bank basis 85system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis 86system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis 87system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis 88system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis 89system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis 90system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis 91system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis 92system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis 93system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis 94system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis 95system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis 96system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis 97system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis 98system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis 99system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis 100system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis 101system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 102system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry 103system.physmem.totGap 110776500 # Total gap between requests 104system.physmem.readPktSize::0 0 # Categorize read packet sizes 105system.physmem.readPktSize::1 0 # Categorize read packet sizes 106system.physmem.readPktSize::2 0 # Categorize read packet sizes 107system.physmem.readPktSize::3 0 # Categorize read packet sizes 108system.physmem.readPktSize::4 0 # Categorize read packet sizes 109system.physmem.readPktSize::5 0 # Categorize read packet sizes 110system.physmem.readPktSize::6 660 # Categorize read packet sizes 111system.physmem.writePktSize::0 0 # Categorize write packet sizes 112system.physmem.writePktSize::1 0 # Categorize write packet sizes 113system.physmem.writePktSize::2 0 # Categorize write packet sizes 114system.physmem.writePktSize::3 0 # Categorize write packet sizes 115system.physmem.writePktSize::4 0 # Categorize write packet sizes 116system.physmem.writePktSize::5 0 # Categorize write packet sizes 117system.physmem.writePktSize::6 0 # Categorize write packet sizes 118system.physmem.rdQLenPdf::0 404 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::1 193 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::2 49 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::3 12 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 150system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 182system.physmem.bytesPerActivate::samples 128 # Bytes accessed per row activation 183system.physmem.bytesPerActivate::mean 281.500000 # Bytes accessed per row activation 184system.physmem.bytesPerActivate::gmean 172.723314 # Bytes accessed per row activation 185system.physmem.bytesPerActivate::stdev 317.555625 # Bytes accessed per row activation 186system.physmem.bytesPerActivate::64 51 39.84% 39.84% # Bytes accessed per row activation 187system.physmem.bytesPerActivate::128 11 8.59% 48.44% # Bytes accessed per row activation 188system.physmem.bytesPerActivate::192 15 11.72% 60.16% # Bytes accessed per row activation 189system.physmem.bytesPerActivate::256 9 7.03% 67.19% # Bytes accessed per row activation 190system.physmem.bytesPerActivate::320 10 7.81% 75.00% # Bytes accessed per row activation 191system.physmem.bytesPerActivate::384 5 3.91% 78.91% # Bytes accessed per row activation 192system.physmem.bytesPerActivate::448 3 2.34% 81.25% # Bytes accessed per row activation 193system.physmem.bytesPerActivate::512 4 3.12% 84.38% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::576 3 2.34% 86.72% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::640 4 3.12% 89.84% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::704 2 1.56% 91.41% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::768 2 1.56% 92.97% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::832 2 1.56% 94.53% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::1024 4 3.12% 97.66% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::1152 1 0.78% 98.44% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::1536 1 0.78% 99.22% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::1984 1 0.78% 100.00% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::total 128 # Bytes accessed per row activation 204system.physmem.totQLat 3818750 # Total cycles spent in queuing delays 205system.physmem.totMemAccLat 18118750 # Sum of mem lat for all requests 206system.physmem.totBusLat 3300000 # Total cycles spent in databus access 207system.physmem.totBankLat 11000000 # Total cycles spent in bank access 208system.physmem.avgQLat 5785.98 # Average queueing delay per request 209system.physmem.avgBankLat 16666.67 # Average bank access latency per request 210system.physmem.avgBusLat 5000.00 # Average bus latency per request 211system.physmem.avgMemAccLat 27452.65 # Average memory access latency 212system.physmem.avgRdBW 380.63 # Average achieved read bandwidth in MB/s 213system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s 214system.physmem.avgConsumedRdBW 380.63 # Average consumed read bandwidth in MB/s 215system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s 216system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s 217system.physmem.busUtil 2.97 # Data bus utilization in percentage 218system.physmem.avgRdQLen 0.16 # Average read queue length over time 219system.physmem.avgWrQLen 0.00 # Average write queue length over time 220system.physmem.readRowHits 532 # Number of row buffer hits during reads 221system.physmem.writeRowHits 0 # Number of row buffer hits during writes 222system.physmem.readRowHitRate 80.61 # Row buffer hit rate for reads 223system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 224system.physmem.avgGap 167843.18 # Average gap between requests 225system.membus.throughput 380634361 # Throughput (bytes/s) 226system.membus.trans_dist::ReadReq 529 # Transaction distribution 227system.membus.trans_dist::ReadResp 528 # Transaction distribution 228system.membus.trans_dist::UpgradeReq 287 # Transaction distribution 229system.membus.trans_dist::UpgradeResp 76 # Transaction distribution 230system.membus.trans_dist::ReadExReq 163 # Transaction distribution 231system.membus.trans_dist::ReadExResp 131 # Transaction distribution 232system.membus.pkt_count_system.l2c.mem_side 1714 # Packet count per connected master and slave (bytes) 233system.membus.pkt_count 1714 # Packet count per connected master and slave (bytes) 234system.membus.tot_pkt_size_system.l2c.mem_side 42176 # Cumulative packet size per connected master and slave (bytes) 235system.membus.tot_pkt_size 42176 # Cumulative packet size per connected master and slave (bytes) 236system.membus.data_through_bus 42176 # Total data (bytes) 237system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 238system.membus.reqLayer0.occupancy 929000 # Layer occupancy (ticks) 239system.membus.reqLayer0.utilization 0.8 # Layer utilization (%) 240system.membus.respLayer1.occupancy 6308925 # Layer occupancy (ticks) 241system.membus.respLayer1.utilization 5.7 # Layer utilization (%) 242system.toL2Bus.throughput 1691772446 # Throughput (bytes/s) 243system.toL2Bus.trans_dist::ReadReq 2536 # Transaction distribution 244system.toL2Bus.trans_dist::ReadResp 2535 # Transaction distribution 245system.toL2Bus.trans_dist::Writeback 1 # Transaction distribution 246system.toL2Bus.trans_dist::UpgradeReq 290 # Transaction distribution 247system.toL2Bus.trans_dist::UpgradeResp 290 # Transaction distribution 248system.toL2Bus.trans_dist::ReadExReq 393 # Transaction distribution 249system.toL2Bus.trans_dist::ReadExResp 393 # Transaction distribution 250system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 1175 # Packet count per connected master and slave (bytes) 251system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 586 # Packet count per connected master and slave (bytes) 252system.toL2Bus.pkt_count_system.cpu1.icache.mem_side 856 # Packet count per connected master and slave (bytes) 253system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side 365 # Packet count per connected master and slave (bytes) 254system.toL2Bus.pkt_count_system.cpu2.icache.mem_side 850 # Packet count per connected master and slave (bytes) 255system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side 371 # Packet count per connected master and slave (bytes) 256system.toL2Bus.pkt_count_system.cpu3.icache.mem_side 860 # Packet count per connected master and slave (bytes) 257system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side 352 # Packet count per connected master and slave (bytes) 258system.toL2Bus.pkt_count 5415 # Packet count per connected master and slave (bytes) 259system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 37568 # Cumulative packet size per connected master and slave (bytes) 260system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 11136 # Cumulative packet size per connected master and slave (bytes) 261system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side 27392 # Cumulative packet size per connected master and slave (bytes) 262system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side 1536 # Cumulative packet size per connected master and slave (bytes) 263system.toL2Bus.tot_pkt_size_system.cpu2.icache.mem_side 27200 # Cumulative packet size per connected master and slave (bytes) 264system.toL2Bus.tot_pkt_size_system.cpu2.dcache.mem_side 1600 # Cumulative packet size per connected master and slave (bytes) 265system.toL2Bus.tot_pkt_size_system.cpu3.icache.mem_side 27520 # Cumulative packet size per connected master and slave (bytes) 266system.toL2Bus.tot_pkt_size_system.cpu3.dcache.mem_side 1536 # Cumulative packet size per connected master and slave (bytes) 267system.toL2Bus.tot_pkt_size 135488 # Cumulative packet size per connected master and slave (bytes) 268system.toL2Bus.data_through_bus 135488 # Total data (bytes) 269system.toL2Bus.snoop_data_through_bus 51968 # Total snoop data (bytes) 270system.toL2Bus.reqLayer0.occupancy 1623982 # Layer occupancy (ticks) 271system.toL2Bus.reqLayer0.utilization 1.5 # Layer utilization (%) 272system.toL2Bus.respLayer0.occupancy 2710248 # Layer occupancy (ticks) 273system.toL2Bus.respLayer0.utilization 2.4 # Layer utilization (%) 274system.toL2Bus.respLayer1.occupancy 1462515 # Layer occupancy (ticks) 275system.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) 276system.toL2Bus.respLayer2.occupancy 1929494 # Layer occupancy (ticks) 277system.toL2Bus.respLayer2.utilization 1.7 # Layer utilization (%) 278system.toL2Bus.respLayer3.occupancy 1189495 # Layer occupancy (ticks) 279system.toL2Bus.respLayer3.utilization 1.1 # Layer utilization (%) 280system.toL2Bus.respLayer4.occupancy 1927246 # Layer occupancy (ticks) 281system.toL2Bus.respLayer4.utilization 1.7 # Layer utilization (%) 282system.toL2Bus.respLayer5.occupancy 1192987 # Layer occupancy (ticks) 283system.toL2Bus.respLayer5.utilization 1.1 # Layer utilization (%) 284system.toL2Bus.respLayer6.occupancy 1937245 # Layer occupancy (ticks) 285system.toL2Bus.respLayer6.utilization 1.7 # Layer utilization (%) 286system.toL2Bus.respLayer7.occupancy 1118007 # Layer occupancy (ticks) 287system.toL2Bus.respLayer7.utilization 1.0 # Layer utilization (%) 288system.cpu0.branchPred.lookups 82992 # Number of BP lookups 289system.cpu0.branchPred.condPredicted 80791 # Number of conditional branches predicted 290system.cpu0.branchPred.condIncorrect 1218 # Number of conditional branches incorrect 291system.cpu0.branchPred.BTBLookups 80321 # Number of BTB lookups 292system.cpu0.branchPred.BTBHits 78273 # Number of BTB hits 293system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 294system.cpu0.branchPred.BTBHitPct 97.450231 # BTB Hit Percentage 295system.cpu0.branchPred.usedRAS 512 # Number of times the RAS was used to get a target. 296system.cpu0.branchPred.RASInCorrect 132 # Number of incorrect RAS predictions. 297system.cpu0.workload.num_syscalls 89 # Number of system calls 298system.cpu0.numCycles 221610 # number of cpu cycles simulated 299system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 300system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 301system.cpu0.fetch.icacheStallCycles 17247 # Number of cycles fetch is stalled on an Icache miss 302system.cpu0.fetch.Insts 492529 # Number of instructions fetch has processed 303system.cpu0.fetch.Branches 82992 # Number of branches that fetch encountered 304system.cpu0.fetch.predictedBranches 78785 # Number of branches that fetch has predicted taken 305system.cpu0.fetch.Cycles 161677 # Number of cycles fetch has run and was not squashing or blocked 306system.cpu0.fetch.SquashCycles 3808 # Number of cycles fetch has spent squashing 307system.cpu0.fetch.BlockedCycles 13819 # Number of cycles fetch has spent blocked 308system.cpu0.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 309system.cpu0.fetch.PendingTrapStallCycles 1570 # Number of stall cycles due to pending traps 310system.cpu0.fetch.CacheLines 5835 # Number of cache lines fetched 311system.cpu0.fetch.IcacheSquashes 493 # Number of outstanding Icache misses that were squashed 312system.cpu0.fetch.rateDist::samples 196760 # Number of instructions fetched each cycle (Total) 313system.cpu0.fetch.rateDist::mean 2.503197 # Number of instructions fetched each cycle (Total) 314system.cpu0.fetch.rateDist::stdev 2.215126 # Number of instructions fetched each cycle (Total) 315system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 316system.cpu0.fetch.rateDist::0 35083 17.83% 17.83% # Number of instructions fetched each cycle (Total) 317system.cpu0.fetch.rateDist::1 80084 40.70% 58.53% # Number of instructions fetched each cycle (Total) 318system.cpu0.fetch.rateDist::2 578 0.29% 58.83% # Number of instructions fetched each cycle (Total) 319system.cpu0.fetch.rateDist::3 973 0.49% 59.32% # Number of instructions fetched each cycle (Total) 320system.cpu0.fetch.rateDist::4 477 0.24% 59.56% # Number of instructions fetched each cycle (Total) 321system.cpu0.fetch.rateDist::5 76189 38.72% 98.28% # Number of instructions fetched each cycle (Total) 322system.cpu0.fetch.rateDist::6 571 0.29% 98.57% # Number of instructions fetched each cycle (Total) 323system.cpu0.fetch.rateDist::7 349 0.18% 98.75% # Number of instructions fetched each cycle (Total) 324system.cpu0.fetch.rateDist::8 2456 1.25% 100.00% # Number of instructions fetched each cycle (Total) 325system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 326system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 327system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 328system.cpu0.fetch.rateDist::total 196760 # Number of instructions fetched each cycle (Total) 329system.cpu0.fetch.branchRate 0.374496 # Number of branch fetches per cycle 330system.cpu0.fetch.rate 2.222503 # Number of inst fetches per cycle 331system.cpu0.decode.IdleCycles 17898 # Number of cycles decode is idle 332system.cpu0.decode.BlockedCycles 15432 # Number of cycles decode is blocked 333system.cpu0.decode.RunCycles 160701 # Number of cycles decode is running 334system.cpu0.decode.UnblockCycles 287 # Number of cycles decode is unblocking 335system.cpu0.decode.SquashCycles 2442 # Number of cycles decode is squashing 336system.cpu0.decode.DecodedInsts 489694 # Number of instructions handled by decode 337system.cpu0.rename.SquashCycles 2442 # Number of cycles rename is squashing 338system.cpu0.rename.IdleCycles 18563 # Number of cycles rename is idle 339system.cpu0.rename.BlockCycles 848 # Number of cycles rename is blocking 340system.cpu0.rename.serializeStallCycles 13994 # count of cycles rename stalled for serializing inst 341system.cpu0.rename.RunCycles 160355 # Number of cycles rename is running 342system.cpu0.rename.UnblockCycles 558 # Number of cycles rename is unblocking 343system.cpu0.rename.RenamedInsts 486837 # Number of instructions processed by rename 344system.cpu0.rename.LSQFullEvents 188 # Number of times rename has blocked due to LSQ full 345system.cpu0.rename.RenamedOperands 332900 # Number of destination operands rename has renamed 346system.cpu0.rename.RenameLookups 970872 # Number of register rename lookups that rename has made 347system.cpu0.rename.int_rename_lookups 970872 # Number of integer rename lookups 348system.cpu0.rename.CommittedMaps 319955 # Number of HB maps that are committed 349system.cpu0.rename.UndoneMaps 12945 # Number of HB maps that are undone due to squashing 350system.cpu0.rename.serializingInsts 867 # count of serializing insts renamed 351system.cpu0.rename.tempSerializingInsts 888 # count of temporary serializing insts renamed 352system.cpu0.rename.skidInsts 3605 # count of insts added to the skid buffer 353system.cpu0.memDep0.insertedLoads 155755 # Number of loads inserted to the mem dependence unit. 354system.cpu0.memDep0.insertedStores 78714 # Number of stores inserted to the mem dependence unit. 355system.cpu0.memDep0.conflictingLoads 75965 # Number of conflicting loads. 356system.cpu0.memDep0.conflictingStores 75781 # Number of conflicting stores. 357system.cpu0.iq.iqInstsAdded 407125 # Number of instructions added to the IQ (excludes non-spec) 358system.cpu0.iq.iqNonSpecInstsAdded 911 # Number of non-speculative instructions added to the IQ 359system.cpu0.iq.iqInstsIssued 404423 # Number of instructions issued 360system.cpu0.iq.iqSquashedInstsIssued 128 # Number of squashed instructions issued 361system.cpu0.iq.iqSquashedInstsExamined 10748 # Number of squashed instructions iterated over during squash; mainly for profiling 362system.cpu0.iq.iqSquashedOperandsExamined 9686 # Number of squashed operands that are examined and possibly removed from graph 363system.cpu0.iq.iqSquashedNonSpecRemoved 352 # Number of squashed non-spec instructions that were removed 364system.cpu0.iq.issued_per_cycle::samples 196760 # Number of insts issued each cycle 365system.cpu0.iq.issued_per_cycle::mean 2.055413 # Number of insts issued each cycle 366system.cpu0.iq.issued_per_cycle::stdev 1.097364 # Number of insts issued each cycle 367system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 368system.cpu0.iq.issued_per_cycle::0 34065 17.31% 17.31% # Number of insts issued each cycle 369system.cpu0.iq.issued_per_cycle::1 4908 2.49% 19.81% # Number of insts issued each cycle 370system.cpu0.iq.issued_per_cycle::2 77935 39.61% 59.42% # Number of insts issued each cycle 371system.cpu0.iq.issued_per_cycle::3 77266 39.27% 98.69% # Number of insts issued each cycle 372system.cpu0.iq.issued_per_cycle::4 1571 0.80% 99.48% # Number of insts issued each cycle 373system.cpu0.iq.issued_per_cycle::5 648 0.33% 99.81% # Number of insts issued each cycle 374system.cpu0.iq.issued_per_cycle::6 262 0.13% 99.95% # Number of insts issued each cycle 375system.cpu0.iq.issued_per_cycle::7 89 0.05% 99.99% # Number of insts issued each cycle 376system.cpu0.iq.issued_per_cycle::8 16 0.01% 100.00% # Number of insts issued each cycle 377system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 378system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 379system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 380system.cpu0.iq.issued_per_cycle::total 196760 # Number of insts issued each cycle 381system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 382system.cpu0.iq.fu_full::IntAlu 57 25.91% 25.91% # attempts to use FU when none available 383system.cpu0.iq.fu_full::IntMult 0 0.00% 25.91% # attempts to use FU when none available 384system.cpu0.iq.fu_full::IntDiv 0 0.00% 25.91% # attempts to use FU when none available 385system.cpu0.iq.fu_full::FloatAdd 0 0.00% 25.91% # attempts to use FU when none available 386system.cpu0.iq.fu_full::FloatCmp 0 0.00% 25.91% # attempts to use FU when none available 387system.cpu0.iq.fu_full::FloatCvt 0 0.00% 25.91% # attempts to use FU when none available 388system.cpu0.iq.fu_full::FloatMult 0 0.00% 25.91% # attempts to use FU when none available 389system.cpu0.iq.fu_full::FloatDiv 0 0.00% 25.91% # attempts to use FU when none available 390system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 25.91% # attempts to use FU when none available 391system.cpu0.iq.fu_full::SimdAdd 0 0.00% 25.91% # attempts to use FU when none available 392system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 25.91% # attempts to use FU when none available 393system.cpu0.iq.fu_full::SimdAlu 0 0.00% 25.91% # attempts to use FU when none available 394system.cpu0.iq.fu_full::SimdCmp 0 0.00% 25.91% # attempts to use FU when none available 395system.cpu0.iq.fu_full::SimdCvt 0 0.00% 25.91% # attempts to use FU when none available 396system.cpu0.iq.fu_full::SimdMisc 0 0.00% 25.91% # attempts to use FU when none available 397system.cpu0.iq.fu_full::SimdMult 0 0.00% 25.91% # attempts to use FU when none available 398system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 25.91% # attempts to use FU when none available 399system.cpu0.iq.fu_full::SimdShift 0 0.00% 25.91% # attempts to use FU when none available 400system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 25.91% # attempts to use FU when none available 401system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 25.91% # attempts to use FU when none available 402system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 25.91% # attempts to use FU when none available 403system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 25.91% # attempts to use FU when none available 404system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 25.91% # attempts to use FU when none available 405system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 25.91% # attempts to use FU when none available 406system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 25.91% # attempts to use FU when none available 407system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 25.91% # attempts to use FU when none available 408system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 25.91% # attempts to use FU when none available 409system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.91% # attempts to use FU when none available 410system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 25.91% # attempts to use FU when none available 411system.cpu0.iq.fu_full::MemRead 51 23.18% 49.09% # attempts to use FU when none available 412system.cpu0.iq.fu_full::MemWrite 112 50.91% 100.00% # attempts to use FU when none available 413system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 414system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 415system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 416system.cpu0.iq.FU_type_0::IntAlu 170994 42.28% 42.28% # Type of FU issued 417system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.28% # Type of FU issued 418system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.28% # Type of FU issued 419system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.28% # Type of FU issued 420system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.28% # Type of FU issued 421system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.28% # Type of FU issued 422system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.28% # Type of FU issued 423system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.28% # Type of FU issued 424system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.28% # Type of FU issued 425system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.28% # Type of FU issued 426system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.28% # Type of FU issued 427system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.28% # Type of FU issued 428system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.28% # Type of FU issued 429system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.28% # Type of FU issued 430system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.28% # Type of FU issued 431system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.28% # Type of FU issued 432system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.28% # Type of FU issued 433system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.28% # Type of FU issued 434system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.28% # Type of FU issued 435system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.28% # Type of FU issued 436system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.28% # Type of FU issued 437system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.28% # Type of FU issued 438system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.28% # Type of FU issued 439system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.28% # Type of FU issued 440system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.28% # Type of FU issued 441system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.28% # Type of FU issued 442system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.28% # Type of FU issued 443system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.28% # Type of FU issued 444system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.28% # Type of FU issued 445system.cpu0.iq.FU_type_0::MemRead 155300 38.40% 80.68% # Type of FU issued 446system.cpu0.iq.FU_type_0::MemWrite 78129 19.32% 100.00% # Type of FU issued 447system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 448system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 449system.cpu0.iq.FU_type_0::total 404423 # Type of FU issued 450system.cpu0.iq.rate 1.824931 # Inst issue rate 451system.cpu0.iq.fu_busy_cnt 220 # FU busy when requested 452system.cpu0.iq.fu_busy_rate 0.000544 # FU busy rate (busy events/executed inst) 453system.cpu0.iq.int_inst_queue_reads 1005954 # Number of integer instruction queue reads 454system.cpu0.iq.int_inst_queue_writes 418838 # Number of integer instruction queue writes 455system.cpu0.iq.int_inst_queue_wakeup_accesses 402603 # Number of integer instruction queue wakeup accesses 456system.cpu0.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads 457system.cpu0.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes 458system.cpu0.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses 459system.cpu0.iq.int_alu_accesses 404643 # Number of integer alu accesses 460system.cpu0.iq.fp_alu_accesses 0 # Number of floating point alu accesses 461system.cpu0.iew.lsq.thread0.forwLoads 75498 # Number of loads that had data forwarded from stores 462system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 463system.cpu0.iew.lsq.thread0.squashedLoads 2188 # Number of loads squashed 464system.cpu0.iew.lsq.thread0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed 465system.cpu0.iew.lsq.thread0.memOrderViolation 54 # Number of memory ordering violations 466system.cpu0.iew.lsq.thread0.squashedStores 1424 # Number of stores squashed 467system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 468system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 469system.cpu0.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 470system.cpu0.iew.lsq.thread0.cacheBlocked 19 # Number of times an access to memory failed due to the cache being blocked 471system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle 472system.cpu0.iew.iewSquashCycles 2442 # Number of cycles IEW is squashing 473system.cpu0.iew.iewBlockCycles 391 # Number of cycles IEW is blocking 474system.cpu0.iew.iewUnblockCycles 33 # Number of cycles IEW is unblocking 475system.cpu0.iew.iewDispatchedInsts 484551 # Number of instructions dispatched to IQ 476system.cpu0.iew.iewDispSquashedInsts 313 # Number of squashed instructions skipped by dispatch 477system.cpu0.iew.iewDispLoadInsts 155755 # Number of dispatched load instructions 478system.cpu0.iew.iewDispStoreInsts 78714 # Number of dispatched store instructions 479system.cpu0.iew.iewDispNonSpecInsts 799 # Number of dispatched non-speculative instructions 480system.cpu0.iew.iewIQFullEvents 38 # Number of times the IQ has become full, causing a stall 481system.cpu0.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 482system.cpu0.iew.memOrderViolationEvents 54 # Number of memory order violations 483system.cpu0.iew.predictedTakenIncorrect 343 # Number of branches that were predicted taken incorrectly 484system.cpu0.iew.predictedNotTakenIncorrect 1106 # Number of branches that were predicted not taken incorrectly 485system.cpu0.iew.branchMispredicts 1449 # Number of branch mispredicts detected at execute 486system.cpu0.iew.iewExecutedInsts 403352 # Number of executed instructions 487system.cpu0.iew.iewExecLoadInsts 154964 # Number of load instructions executed 488system.cpu0.iew.iewExecSquashedInsts 1071 # Number of squashed instructions skipped in execute 489system.cpu0.iew.exec_swp 0 # number of swp insts executed 490system.cpu0.iew.exec_nop 76515 # number of nop insts executed 491system.cpu0.iew.exec_refs 232993 # number of memory reference insts executed 492system.cpu0.iew.exec_branches 80132 # Number of branches executed 493system.cpu0.iew.exec_stores 78029 # Number of stores executed 494system.cpu0.iew.exec_rate 1.820098 # Inst execution rate 495system.cpu0.iew.wb_sent 402944 # cumulative count of insts sent to commit 496system.cpu0.iew.wb_count 402603 # cumulative count of insts written-back 497system.cpu0.iew.wb_producers 238549 # num instructions producing a value 498system.cpu0.iew.wb_consumers 241004 # num instructions consuming a value 499system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 500system.cpu0.iew.wb_rate 1.816719 # insts written-back per cycle 501system.cpu0.iew.wb_fanout 0.989813 # average fanout of values written-back 502system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 503system.cpu0.commit.commitSquashedInsts 12240 # The number of squashed insts skipped by commit 504system.cpu0.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards 505system.cpu0.commit.branchMispredicts 1218 # The number of times a branch was mispredicted 506system.cpu0.commit.committed_per_cycle::samples 194318 # Number of insts commited each cycle 507system.cpu0.commit.committed_per_cycle::mean 2.430470 # Number of insts commited each cycle 508system.cpu0.commit.committed_per_cycle::stdev 2.136197 # Number of insts commited each cycle 509system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 510system.cpu0.commit.committed_per_cycle::0 34493 17.75% 17.75% # Number of insts commited each cycle 511system.cpu0.commit.committed_per_cycle::1 79895 41.12% 58.87% # Number of insts commited each cycle 512system.cpu0.commit.committed_per_cycle::2 2401 1.24% 60.10% # Number of insts commited each cycle 513system.cpu0.commit.committed_per_cycle::3 689 0.35% 60.46% # Number of insts commited each cycle 514system.cpu0.commit.committed_per_cycle::4 530 0.27% 60.73% # Number of insts commited each cycle 515system.cpu0.commit.committed_per_cycle::5 75316 38.76% 99.49% # Number of insts commited each cycle 516system.cpu0.commit.committed_per_cycle::6 445 0.23% 99.72% # Number of insts commited each cycle 517system.cpu0.commit.committed_per_cycle::7 242 0.12% 99.84% # Number of insts commited each cycle 518system.cpu0.commit.committed_per_cycle::8 307 0.16% 100.00% # Number of insts commited each cycle 519system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 520system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 521system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 522system.cpu0.commit.committed_per_cycle::total 194318 # Number of insts commited each cycle 523system.cpu0.commit.committedInsts 472284 # Number of instructions committed 524system.cpu0.commit.committedOps 472284 # Number of ops (including micro ops) committed 525system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed 526system.cpu0.commit.refs 230857 # Number of memory references committed 527system.cpu0.commit.loads 153567 # Number of loads committed 528system.cpu0.commit.membars 84 # Number of memory barriers committed 529system.cpu0.commit.branches 79177 # Number of branches committed 530system.cpu0.commit.fp_insts 0 # Number of committed floating point instructions. 531system.cpu0.commit.int_insts 318286 # Number of committed integer instructions. 532system.cpu0.commit.function_calls 223 # Number of function calls committed. 533system.cpu0.commit.bw_lim_events 307 # number cycles where commit BW limit reached 534system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits 535system.cpu0.rob.rob_reads 677374 # The number of ROB reads 536system.cpu0.rob.rob_writes 971507 # The number of ROB writes 537system.cpu0.timesIdled 326 # Number of times that the entire CPU went into an idle state and unscheduled itself 538system.cpu0.idleCycles 24850 # Total number of cycles that the CPU has spent unscheduled due to idling 539system.cpu0.committedInsts 396291 # Number of Instructions Simulated 540system.cpu0.committedOps 396291 # Number of Ops (including micro ops) Simulated 541system.cpu0.committedInsts_total 396291 # Number of Instructions Simulated 542system.cpu0.cpi 0.559210 # CPI: Cycles Per Instruction 543system.cpu0.cpi_total 0.559210 # CPI: Total CPI of All Threads 544system.cpu0.ipc 1.788236 # IPC: Instructions Per Cycle 545system.cpu0.ipc_total 1.788236 # IPC: Total IPC of All Threads 546system.cpu0.int_regfile_reads 721592 # number of integer regfile reads 547system.cpu0.int_regfile_writes 325227 # number of integer regfile writes 548system.cpu0.fp_regfile_reads 192 # number of floating regfile reads 549system.cpu0.misc_regfile_reads 234817 # number of misc regfile reads 550system.cpu0.misc_regfile_writes 564 # number of misc regfile writes 551system.cpu0.icache.tags.replacements 297 # number of replacements 552system.cpu0.icache.tags.tagsinuse 241.148232 # Cycle average of tags in use 553system.cpu0.icache.tags.total_refs 5079 # Total number of references to valid blocks. 554system.cpu0.icache.tags.sampled_refs 587 # Sample count of references to valid blocks. 555system.cpu0.icache.tags.avg_refs 8.652470 # Average number of references to valid blocks. 556system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 557system.cpu0.icache.tags.occ_blocks::cpu0.inst 241.148232 # Average occupied blocks per requestor 558system.cpu0.icache.tags.occ_percent::cpu0.inst 0.470993 # Average percentage of cache occupancy 559system.cpu0.icache.tags.occ_percent::total 0.470993 # Average percentage of cache occupancy 560system.cpu0.icache.ReadReq_hits::cpu0.inst 5079 # number of ReadReq hits 561system.cpu0.icache.ReadReq_hits::total 5079 # number of ReadReq hits 562system.cpu0.icache.demand_hits::cpu0.inst 5079 # number of demand (read+write) hits 563system.cpu0.icache.demand_hits::total 5079 # number of demand (read+write) hits 564system.cpu0.icache.overall_hits::cpu0.inst 5079 # number of overall hits 565system.cpu0.icache.overall_hits::total 5079 # number of overall hits 566system.cpu0.icache.ReadReq_misses::cpu0.inst 756 # number of ReadReq misses 567system.cpu0.icache.ReadReq_misses::total 756 # number of ReadReq misses 568system.cpu0.icache.demand_misses::cpu0.inst 756 # number of demand (read+write) misses 569system.cpu0.icache.demand_misses::total 756 # number of demand (read+write) misses 570system.cpu0.icache.overall_misses::cpu0.inst 756 # number of overall misses 571system.cpu0.icache.overall_misses::total 756 # number of overall misses 572system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 35147245 # number of ReadReq miss cycles 573system.cpu0.icache.ReadReq_miss_latency::total 35147245 # number of ReadReq miss cycles 574system.cpu0.icache.demand_miss_latency::cpu0.inst 35147245 # number of demand (read+write) miss cycles 575system.cpu0.icache.demand_miss_latency::total 35147245 # number of demand (read+write) miss cycles 576system.cpu0.icache.overall_miss_latency::cpu0.inst 35147245 # number of overall miss cycles 577system.cpu0.icache.overall_miss_latency::total 35147245 # number of overall miss cycles 578system.cpu0.icache.ReadReq_accesses::cpu0.inst 5835 # number of ReadReq accesses(hits+misses) 579system.cpu0.icache.ReadReq_accesses::total 5835 # number of ReadReq accesses(hits+misses) 580system.cpu0.icache.demand_accesses::cpu0.inst 5835 # number of demand (read+write) accesses 581system.cpu0.icache.demand_accesses::total 5835 # number of demand (read+write) accesses 582system.cpu0.icache.overall_accesses::cpu0.inst 5835 # number of overall (read+write) accesses 583system.cpu0.icache.overall_accesses::total 5835 # number of overall (read+write) accesses 584system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.129563 # miss rate for ReadReq accesses 585system.cpu0.icache.ReadReq_miss_rate::total 0.129563 # miss rate for ReadReq accesses 586system.cpu0.icache.demand_miss_rate::cpu0.inst 0.129563 # miss rate for demand accesses 587system.cpu0.icache.demand_miss_rate::total 0.129563 # miss rate for demand accesses 588system.cpu0.icache.overall_miss_rate::cpu0.inst 0.129563 # miss rate for overall accesses 589system.cpu0.icache.overall_miss_rate::total 0.129563 # miss rate for overall accesses 590system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 46491.064815 # average ReadReq miss latency 591system.cpu0.icache.ReadReq_avg_miss_latency::total 46491.064815 # average ReadReq miss latency 592system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 46491.064815 # average overall miss latency 593system.cpu0.icache.demand_avg_miss_latency::total 46491.064815 # average overall miss latency 594system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 46491.064815 # average overall miss latency 595system.cpu0.icache.overall_avg_miss_latency::total 46491.064815 # average overall miss latency 596system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 597system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 598system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 599system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 600system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 601system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 602system.cpu0.icache.fast_writes 0 # number of fast writes performed 603system.cpu0.icache.cache_copies 0 # number of cache copies performed 604system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 168 # number of ReadReq MSHR hits 605system.cpu0.icache.ReadReq_mshr_hits::total 168 # number of ReadReq MSHR hits 606system.cpu0.icache.demand_mshr_hits::cpu0.inst 168 # number of demand (read+write) MSHR hits 607system.cpu0.icache.demand_mshr_hits::total 168 # number of demand (read+write) MSHR hits 608system.cpu0.icache.overall_mshr_hits::cpu0.inst 168 # number of overall MSHR hits 609system.cpu0.icache.overall_mshr_hits::total 168 # number of overall MSHR hits 610system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 588 # number of ReadReq MSHR misses 611system.cpu0.icache.ReadReq_mshr_misses::total 588 # number of ReadReq MSHR misses 612system.cpu0.icache.demand_mshr_misses::cpu0.inst 588 # number of demand (read+write) MSHR misses 613system.cpu0.icache.demand_mshr_misses::total 588 # number of demand (read+write) MSHR misses 614system.cpu0.icache.overall_mshr_misses::cpu0.inst 588 # number of overall MSHR misses 615system.cpu0.icache.overall_mshr_misses::total 588 # number of overall MSHR misses 616system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 27250252 # number of ReadReq MSHR miss cycles 617system.cpu0.icache.ReadReq_mshr_miss_latency::total 27250252 # number of ReadReq MSHR miss cycles 618system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 27250252 # number of demand (read+write) MSHR miss cycles 619system.cpu0.icache.demand_mshr_miss_latency::total 27250252 # number of demand (read+write) MSHR miss cycles 620system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 27250252 # number of overall MSHR miss cycles 621system.cpu0.icache.overall_mshr_miss_latency::total 27250252 # number of overall MSHR miss cycles 622system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.100771 # mshr miss rate for ReadReq accesses 623system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.100771 # mshr miss rate for ReadReq accesses 624system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.100771 # mshr miss rate for demand accesses 625system.cpu0.icache.demand_mshr_miss_rate::total 0.100771 # mshr miss rate for demand accesses 626system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.100771 # mshr miss rate for overall accesses 627system.cpu0.icache.overall_mshr_miss_rate::total 0.100771 # mshr miss rate for overall accesses 628system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 46343.965986 # average ReadReq mshr miss latency 629system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 46343.965986 # average ReadReq mshr miss latency 630system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 46343.965986 # average overall mshr miss latency 631system.cpu0.icache.demand_avg_mshr_miss_latency::total 46343.965986 # average overall mshr miss latency 632system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 46343.965986 # average overall mshr miss latency 633system.cpu0.icache.overall_avg_mshr_miss_latency::total 46343.965986 # average overall mshr miss latency 634system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 635system.cpu0.dcache.tags.replacements 2 # number of replacements 636system.cpu0.dcache.tags.tagsinuse 141.869283 # Cycle average of tags in use 637system.cpu0.dcache.tags.total_refs 155614 # Total number of references to valid blocks. 638system.cpu0.dcache.tags.sampled_refs 170 # Sample count of references to valid blocks. 639system.cpu0.dcache.tags.avg_refs 915.376471 # Average number of references to valid blocks. 640system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 641system.cpu0.dcache.tags.occ_blocks::cpu0.data 141.869283 # Average occupied blocks per requestor 642system.cpu0.dcache.tags.occ_percent::cpu0.data 0.277088 # Average percentage of cache occupancy 643system.cpu0.dcache.tags.occ_percent::total 0.277088 # Average percentage of cache occupancy 644system.cpu0.dcache.ReadReq_hits::cpu0.data 78995 # number of ReadReq hits 645system.cpu0.dcache.ReadReq_hits::total 78995 # number of ReadReq hits 646system.cpu0.dcache.WriteReq_hits::cpu0.data 76703 # number of WriteReq hits 647system.cpu0.dcache.WriteReq_hits::total 76703 # number of WriteReq hits 648system.cpu0.dcache.SwapReq_hits::cpu0.data 21 # number of SwapReq hits 649system.cpu0.dcache.SwapReq_hits::total 21 # number of SwapReq hits 650system.cpu0.dcache.demand_hits::cpu0.data 155698 # number of demand (read+write) hits 651system.cpu0.dcache.demand_hits::total 155698 # number of demand (read+write) hits 652system.cpu0.dcache.overall_hits::cpu0.data 155698 # number of overall hits 653system.cpu0.dcache.overall_hits::total 155698 # number of overall hits 654system.cpu0.dcache.ReadReq_misses::cpu0.data 410 # number of ReadReq misses 655system.cpu0.dcache.ReadReq_misses::total 410 # number of ReadReq misses 656system.cpu0.dcache.WriteReq_misses::cpu0.data 545 # number of WriteReq misses 657system.cpu0.dcache.WriteReq_misses::total 545 # number of WriteReq misses 658system.cpu0.dcache.SwapReq_misses::cpu0.data 21 # number of SwapReq misses 659system.cpu0.dcache.SwapReq_misses::total 21 # number of SwapReq misses 660system.cpu0.dcache.demand_misses::cpu0.data 955 # number of demand (read+write) misses 661system.cpu0.dcache.demand_misses::total 955 # number of demand (read+write) misses 662system.cpu0.dcache.overall_misses::cpu0.data 955 # number of overall misses 663system.cpu0.dcache.overall_misses::total 955 # number of overall misses 664system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 13319205 # number of ReadReq miss cycles 665system.cpu0.dcache.ReadReq_miss_latency::total 13319205 # number of ReadReq miss cycles 666system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 35150505 # number of WriteReq miss cycles 667system.cpu0.dcache.WriteReq_miss_latency::total 35150505 # number of WriteReq miss cycles 668system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 418750 # number of SwapReq miss cycles 669system.cpu0.dcache.SwapReq_miss_latency::total 418750 # number of SwapReq miss cycles 670system.cpu0.dcache.demand_miss_latency::cpu0.data 48469710 # number of demand (read+write) miss cycles 671system.cpu0.dcache.demand_miss_latency::total 48469710 # number of demand (read+write) miss cycles 672system.cpu0.dcache.overall_miss_latency::cpu0.data 48469710 # number of overall miss cycles 673system.cpu0.dcache.overall_miss_latency::total 48469710 # number of overall miss cycles 674system.cpu0.dcache.ReadReq_accesses::cpu0.data 79405 # number of ReadReq accesses(hits+misses) 675system.cpu0.dcache.ReadReq_accesses::total 79405 # number of ReadReq accesses(hits+misses) 676system.cpu0.dcache.WriteReq_accesses::cpu0.data 77248 # number of WriteReq accesses(hits+misses) 677system.cpu0.dcache.WriteReq_accesses::total 77248 # number of WriteReq accesses(hits+misses) 678system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) 679system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) 680system.cpu0.dcache.demand_accesses::cpu0.data 156653 # number of demand (read+write) accesses 681system.cpu0.dcache.demand_accesses::total 156653 # number of demand (read+write) accesses 682system.cpu0.dcache.overall_accesses::cpu0.data 156653 # number of overall (read+write) accesses 683system.cpu0.dcache.overall_accesses::total 156653 # number of overall (read+write) accesses 684system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.005163 # miss rate for ReadReq accesses 685system.cpu0.dcache.ReadReq_miss_rate::total 0.005163 # miss rate for ReadReq accesses 686system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007055 # miss rate for WriteReq accesses 687system.cpu0.dcache.WriteReq_miss_rate::total 0.007055 # miss rate for WriteReq accesses 688system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.500000 # miss rate for SwapReq accesses 689system.cpu0.dcache.SwapReq_miss_rate::total 0.500000 # miss rate for SwapReq accesses 690system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006096 # miss rate for demand accesses 691system.cpu0.dcache.demand_miss_rate::total 0.006096 # miss rate for demand accesses 692system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006096 # miss rate for overall accesses 693system.cpu0.dcache.overall_miss_rate::total 0.006096 # miss rate for overall accesses 694system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 32485.865854 # average ReadReq miss latency 695system.cpu0.dcache.ReadReq_avg_miss_latency::total 32485.865854 # average ReadReq miss latency 696system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 64496.339450 # average WriteReq miss latency 697system.cpu0.dcache.WriteReq_avg_miss_latency::total 64496.339450 # average WriteReq miss latency 698system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 19940.476190 # average SwapReq miss latency 699system.cpu0.dcache.SwapReq_avg_miss_latency::total 19940.476190 # average SwapReq miss latency 700system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 50753.623037 # average overall miss latency 701system.cpu0.dcache.demand_avg_miss_latency::total 50753.623037 # average overall miss latency 702system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 50753.623037 # average overall miss latency 703system.cpu0.dcache.overall_avg_miss_latency::total 50753.623037 # average overall miss latency 704system.cpu0.dcache.blocked_cycles::no_mshrs 503 # number of cycles access was blocked 705system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 706system.cpu0.dcache.blocked::no_mshrs 21 # number of cycles access was blocked 707system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 708system.cpu0.dcache.avg_blocked_cycles::no_mshrs 23.952381 # average number of cycles each access was blocked 709system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 710system.cpu0.dcache.fast_writes 0 # number of fast writes performed 711system.cpu0.dcache.cache_copies 0 # number of cache copies performed 712system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks 713system.cpu0.dcache.writebacks::total 1 # number of writebacks 714system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 223 # number of ReadReq MSHR hits 715system.cpu0.dcache.ReadReq_mshr_hits::total 223 # number of ReadReq MSHR hits 716system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 370 # number of WriteReq MSHR hits 717system.cpu0.dcache.WriteReq_mshr_hits::total 370 # number of WriteReq MSHR hits 718system.cpu0.dcache.demand_mshr_hits::cpu0.data 593 # number of demand (read+write) MSHR hits 719system.cpu0.dcache.demand_mshr_hits::total 593 # number of demand (read+write) MSHR hits 720system.cpu0.dcache.overall_mshr_hits::cpu0.data 593 # number of overall MSHR hits 721system.cpu0.dcache.overall_mshr_hits::total 593 # number of overall MSHR hits 722system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 187 # number of ReadReq MSHR misses 723system.cpu0.dcache.ReadReq_mshr_misses::total 187 # number of ReadReq MSHR misses 724system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 175 # number of WriteReq MSHR misses 725system.cpu0.dcache.WriteReq_mshr_misses::total 175 # number of WriteReq MSHR misses 726system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 21 # number of SwapReq MSHR misses 727system.cpu0.dcache.SwapReq_mshr_misses::total 21 # number of SwapReq MSHR misses 728system.cpu0.dcache.demand_mshr_misses::cpu0.data 362 # number of demand (read+write) MSHR misses 729system.cpu0.dcache.demand_mshr_misses::total 362 # number of demand (read+write) MSHR misses 730system.cpu0.dcache.overall_mshr_misses::cpu0.data 362 # number of overall MSHR misses 731system.cpu0.dcache.overall_mshr_misses::total 362 # number of overall MSHR misses 732system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 6285007 # number of ReadReq MSHR miss cycles 733system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6285007 # number of ReadReq MSHR miss cycles 734system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7788228 # number of WriteReq MSHR miss cycles 735system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7788228 # number of WriteReq MSHR miss cycles 736system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 375250 # number of SwapReq MSHR miss cycles 737system.cpu0.dcache.SwapReq_mshr_miss_latency::total 375250 # number of SwapReq MSHR miss cycles 738system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 14073235 # number of demand (read+write) MSHR miss cycles 739system.cpu0.dcache.demand_mshr_miss_latency::total 14073235 # number of demand (read+write) MSHR miss cycles 740system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 14073235 # number of overall MSHR miss cycles 741system.cpu0.dcache.overall_mshr_miss_latency::total 14073235 # number of overall MSHR miss cycles 742system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002355 # mshr miss rate for ReadReq accesses 743system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002355 # mshr miss rate for ReadReq accesses 744system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002265 # mshr miss rate for WriteReq accesses 745system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002265 # mshr miss rate for WriteReq accesses 746system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.500000 # mshr miss rate for SwapReq accesses 747system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SwapReq accesses 748system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002311 # mshr miss rate for demand accesses 749system.cpu0.dcache.demand_mshr_miss_rate::total 0.002311 # mshr miss rate for demand accesses 750system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002311 # mshr miss rate for overall accesses 751system.cpu0.dcache.overall_mshr_miss_rate::total 0.002311 # mshr miss rate for overall accesses 752system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 33609.663102 # average ReadReq mshr miss latency 753system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 33609.663102 # average ReadReq mshr miss latency 754system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 44504.160000 # average WriteReq mshr miss latency 755system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 44504.160000 # average WriteReq mshr miss latency 756system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 17869.047619 # average SwapReq mshr miss latency 757system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 17869.047619 # average SwapReq mshr miss latency 758system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 38876.339779 # average overall mshr miss latency 759system.cpu0.dcache.demand_avg_mshr_miss_latency::total 38876.339779 # average overall mshr miss latency 760system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 38876.339779 # average overall mshr miss latency 761system.cpu0.dcache.overall_avg_mshr_miss_latency::total 38876.339779 # average overall mshr miss latency 762system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 763system.cpu1.branchPred.lookups 43495 # Number of BP lookups 764system.cpu1.branchPred.condPredicted 40766 # Number of conditional branches predicted 765system.cpu1.branchPred.condIncorrect 1279 # Number of conditional branches incorrect 766system.cpu1.branchPred.BTBLookups 37360 # Number of BTB lookups 767system.cpu1.branchPred.BTBHits 36580 # Number of BTB hits 768system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 769system.cpu1.branchPred.BTBHitPct 97.912206 # BTB Hit Percentage 770system.cpu1.branchPred.usedRAS 665 # Number of times the RAS was used to get a target. 771system.cpu1.branchPred.RASInCorrect 232 # Number of incorrect RAS predictions. 772system.cpu1.numCycles 177681 # number of cpu cycles simulated 773system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 774system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 775system.cpu1.fetch.icacheStallCycles 34028 # Number of cycles fetch is stalled on an Icache miss 776system.cpu1.fetch.Insts 233746 # Number of instructions fetch has processed 777system.cpu1.fetch.Branches 43495 # Number of branches that fetch encountered 778system.cpu1.fetch.predictedBranches 37245 # Number of branches that fetch has predicted taken 779system.cpu1.fetch.Cycles 88254 # Number of cycles fetch has run and was not squashing or blocked 780system.cpu1.fetch.SquashCycles 3762 # Number of cycles fetch has spent squashing 781system.cpu1.fetch.BlockedCycles 42089 # Number of cycles fetch has spent blocked 782system.cpu1.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 783system.cpu1.fetch.NoActiveThreadStallCycles 7739 # Number of stall cycles due to no active thread to fetch from 784system.cpu1.fetch.PendingTrapStallCycles 785 # Number of stall cycles due to pending traps 785system.cpu1.fetch.CacheLines 25656 # Number of cache lines fetched 786system.cpu1.fetch.IcacheSquashes 258 # Number of outstanding Icache misses that were squashed 787system.cpu1.fetch.rateDist::samples 175306 # Number of instructions fetched each cycle (Total) 788system.cpu1.fetch.rateDist::mean 1.333360 # Number of instructions fetched each cycle (Total) 789system.cpu1.fetch.rateDist::stdev 1.985884 # Number of instructions fetched each cycle (Total) 790system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 791system.cpu1.fetch.rateDist::0 87052 49.66% 49.66% # Number of instructions fetched each cycle (Total) 792system.cpu1.fetch.rateDist::1 46435 26.49% 76.15% # Number of instructions fetched each cycle (Total) 793system.cpu1.fetch.rateDist::2 9084 5.18% 81.33% # Number of instructions fetched each cycle (Total) 794system.cpu1.fetch.rateDist::3 3194 1.82% 83.15% # Number of instructions fetched each cycle (Total) 795system.cpu1.fetch.rateDist::4 686 0.39% 83.54% # Number of instructions fetched each cycle (Total) 796system.cpu1.fetch.rateDist::5 23635 13.48% 97.02% # Number of instructions fetched each cycle (Total) 797system.cpu1.fetch.rateDist::6 1173 0.67% 97.69% # Number of instructions fetched each cycle (Total) 798system.cpu1.fetch.rateDist::7 772 0.44% 98.13% # Number of instructions fetched each cycle (Total) 799system.cpu1.fetch.rateDist::8 3275 1.87% 100.00% # Number of instructions fetched each cycle (Total) 800system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 801system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 802system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 803system.cpu1.fetch.rateDist::total 175306 # Number of instructions fetched each cycle (Total) 804system.cpu1.fetch.branchRate 0.244793 # Number of branch fetches per cycle 805system.cpu1.fetch.rate 1.315537 # Number of inst fetches per cycle 806system.cpu1.decode.IdleCycles 41969 # Number of cycles decode is idle 807system.cpu1.decode.BlockedCycles 35783 # Number of cycles decode is blocked 808system.cpu1.decode.RunCycles 79597 # Number of cycles decode is running 809system.cpu1.decode.UnblockCycles 7812 # Number of cycles decode is unblocking 810system.cpu1.decode.SquashCycles 2406 # Number of cycles decode is squashing 811system.cpu1.decode.DecodedInsts 230200 # Number of instructions handled by decode 812system.cpu1.rename.SquashCycles 2406 # Number of cycles rename is squashing 813system.cpu1.rename.IdleCycles 42677 # Number of cycles rename is idle 814system.cpu1.rename.BlockCycles 23059 # Number of cycles rename is blocking 815system.cpu1.rename.serializeStallCycles 11946 # count of cycles rename stalled for serializing inst 816system.cpu1.rename.RunCycles 72053 # Number of cycles rename is running 817system.cpu1.rename.UnblockCycles 15426 # Number of cycles rename is unblocking 818system.cpu1.rename.RenamedInsts 227940 # Number of instructions processed by rename 819system.cpu1.rename.IQFullEvents 4 # Number of times rename has blocked due to IQ full 820system.cpu1.rename.LSQFullEvents 19 # Number of times rename has blocked due to LSQ full 821system.cpu1.rename.RenamedOperands 156532 # Number of destination operands rename has renamed 822system.cpu1.rename.RenameLookups 420697 # Number of register rename lookups that rename has made 823system.cpu1.rename.int_rename_lookups 420697 # Number of integer rename lookups 824system.cpu1.rename.CommittedMaps 143693 # Number of HB maps that are committed 825system.cpu1.rename.UndoneMaps 12839 # Number of HB maps that are undone due to squashing 826system.cpu1.rename.serializingInsts 1114 # count of serializing insts renamed 827system.cpu1.rename.tempSerializingInsts 1240 # count of temporary serializing insts renamed 828system.cpu1.rename.skidInsts 18203 # count of insts added to the skid buffer 829system.cpu1.memDep0.insertedLoads 60713 # Number of loads inserted to the mem dependence unit. 830system.cpu1.memDep0.insertedStores 26873 # Number of stores inserted to the mem dependence unit. 831system.cpu1.memDep0.conflictingLoads 30033 # Number of conflicting loads. 832system.cpu1.memDep0.conflictingStores 21821 # Number of conflicting stores. 833system.cpu1.iq.iqInstsAdded 184781 # Number of instructions added to the IQ (excludes non-spec) 834system.cpu1.iq.iqNonSpecInstsAdded 9329 # Number of non-speculative instructions added to the IQ 835system.cpu1.iq.iqInstsIssued 189617 # Number of instructions issued 836system.cpu1.iq.iqSquashedInstsIssued 108 # Number of squashed instructions issued 837system.cpu1.iq.iqSquashedInstsExamined 10957 # Number of squashed instructions iterated over during squash; mainly for profiling 838system.cpu1.iq.iqSquashedOperandsExamined 10934 # Number of squashed operands that are examined and possibly removed from graph 839system.cpu1.iq.iqSquashedNonSpecRemoved 690 # Number of squashed non-spec instructions that were removed 840system.cpu1.iq.issued_per_cycle::samples 175306 # Number of insts issued each cycle 841system.cpu1.iq.issued_per_cycle::mean 1.081634 # Number of insts issued each cycle 842system.cpu1.iq.issued_per_cycle::stdev 1.264768 # Number of insts issued each cycle 843system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 844system.cpu1.iq.issued_per_cycle::0 84668 48.30% 48.30% # Number of insts issued each cycle 845system.cpu1.iq.issued_per_cycle::1 30997 17.68% 65.98% # Number of insts issued each cycle 846system.cpu1.iq.issued_per_cycle::2 27119 15.47% 81.45% # Number of insts issued each cycle 847system.cpu1.iq.issued_per_cycle::3 27768 15.84% 97.29% # Number of insts issued each cycle 848system.cpu1.iq.issued_per_cycle::4 3226 1.84% 99.13% # Number of insts issued each cycle 849system.cpu1.iq.issued_per_cycle::5 1160 0.66% 99.79% # Number of insts issued each cycle 850system.cpu1.iq.issued_per_cycle::6 259 0.15% 99.94% # Number of insts issued each cycle 851system.cpu1.iq.issued_per_cycle::7 52 0.03% 99.97% # Number of insts issued each cycle 852system.cpu1.iq.issued_per_cycle::8 57 0.03% 100.00% # Number of insts issued each cycle 853system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 854system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 855system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 856system.cpu1.iq.issued_per_cycle::total 175306 # Number of insts issued each cycle 857system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 858system.cpu1.iq.fu_full::IntAlu 12 4.55% 4.55% # attempts to use FU when none available 859system.cpu1.iq.fu_full::IntMult 0 0.00% 4.55% # attempts to use FU when none available 860system.cpu1.iq.fu_full::IntDiv 0 0.00% 4.55% # attempts to use FU when none available 861system.cpu1.iq.fu_full::FloatAdd 0 0.00% 4.55% # attempts to use FU when none available 862system.cpu1.iq.fu_full::FloatCmp 0 0.00% 4.55% # attempts to use FU when none available 863system.cpu1.iq.fu_full::FloatCvt 0 0.00% 4.55% # attempts to use FU when none available 864system.cpu1.iq.fu_full::FloatMult 0 0.00% 4.55% # attempts to use FU when none available 865system.cpu1.iq.fu_full::FloatDiv 0 0.00% 4.55% # attempts to use FU when none available 866system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 4.55% # attempts to use FU when none available 867system.cpu1.iq.fu_full::SimdAdd 0 0.00% 4.55% # attempts to use FU when none available 868system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 4.55% # attempts to use FU when none available 869system.cpu1.iq.fu_full::SimdAlu 0 0.00% 4.55% # attempts to use FU when none available 870system.cpu1.iq.fu_full::SimdCmp 0 0.00% 4.55% # attempts to use FU when none available 871system.cpu1.iq.fu_full::SimdCvt 0 0.00% 4.55% # attempts to use FU when none available 872system.cpu1.iq.fu_full::SimdMisc 0 0.00% 4.55% # attempts to use FU when none available 873system.cpu1.iq.fu_full::SimdMult 0 0.00% 4.55% # attempts to use FU when none available 874system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 4.55% # attempts to use FU when none available 875system.cpu1.iq.fu_full::SimdShift 0 0.00% 4.55% # attempts to use FU when none available 876system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 4.55% # attempts to use FU when none available 877system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 4.55% # attempts to use FU when none available 878system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 4.55% # attempts to use FU when none available 879system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 4.55% # attempts to use FU when none available 880system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 4.55% # attempts to use FU when none available 881system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 4.55% # attempts to use FU when none available 882system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 4.55% # attempts to use FU when none available 883system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 4.55% # attempts to use FU when none available 884system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 4.55% # attempts to use FU when none available 885system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.55% # attempts to use FU when none available 886system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 4.55% # attempts to use FU when none available 887system.cpu1.iq.fu_full::MemRead 42 15.91% 20.45% # attempts to use FU when none available 888system.cpu1.iq.fu_full::MemWrite 210 79.55% 100.00% # attempts to use FU when none available 889system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 890system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 891system.cpu1.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 892system.cpu1.iq.FU_type_0::IntAlu 95616 50.43% 50.43% # Type of FU issued 893system.cpu1.iq.FU_type_0::IntMult 0 0.00% 50.43% # Type of FU issued 894system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 50.43% # Type of FU issued 895system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 50.43% # Type of FU issued 896system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 50.43% # Type of FU issued 897system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 50.43% # Type of FU issued 898system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 50.43% # Type of FU issued 899system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 50.43% # Type of FU issued 900system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 50.43% # Type of FU issued 901system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 50.43% # Type of FU issued 902system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 50.43% # Type of FU issued 903system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 50.43% # Type of FU issued 904system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 50.43% # Type of FU issued 905system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 50.43% # Type of FU issued 906system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 50.43% # Type of FU issued 907system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 50.43% # Type of FU issued 908system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 50.43% # Type of FU issued 909system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 50.43% # Type of FU issued 910system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 50.43% # Type of FU issued 911system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 50.43% # Type of FU issued 912system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 50.43% # Type of FU issued 913system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 50.43% # Type of FU issued 914system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 50.43% # Type of FU issued 915system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 50.43% # Type of FU issued 916system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 50.43% # Type of FU issued 917system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 50.43% # Type of FU issued 918system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 50.43% # Type of FU issued 919system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 50.43% # Type of FU issued 920system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 50.43% # Type of FU issued 921system.cpu1.iq.FU_type_0::MemRead 67820 35.77% 86.19% # Type of FU issued 922system.cpu1.iq.FU_type_0::MemWrite 26181 13.81% 100.00% # Type of FU issued 923system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 924system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 925system.cpu1.iq.FU_type_0::total 189617 # Type of FU issued 926system.cpu1.iq.rate 1.067177 # Inst issue rate 927system.cpu1.iq.fu_busy_cnt 264 # FU busy when requested 928system.cpu1.iq.fu_busy_rate 0.001392 # FU busy rate (busy events/executed inst) 929system.cpu1.iq.int_inst_queue_reads 554912 # Number of integer instruction queue reads 930system.cpu1.iq.int_inst_queue_writes 205110 # Number of integer instruction queue writes 931system.cpu1.iq.int_inst_queue_wakeup_accesses 187814 # Number of integer instruction queue wakeup accesses 932system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads 933system.cpu1.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes 934system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses 935system.cpu1.iq.int_alu_accesses 189881 # Number of integer alu accesses 936system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses 937system.cpu1.iew.lsq.thread0.forwLoads 21562 # Number of loads that had data forwarded from stores 938system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 939system.cpu1.iew.lsq.thread0.squashedLoads 2474 # Number of loads squashed 940system.cpu1.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed 941system.cpu1.iew.lsq.thread0.memOrderViolation 43 # Number of memory ordering violations 942system.cpu1.iew.lsq.thread0.squashedStores 1439 # Number of stores squashed 943system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 944system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 945system.cpu1.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 946system.cpu1.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked 947system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle 948system.cpu1.iew.iewSquashCycles 2406 # Number of cycles IEW is squashing 949system.cpu1.iew.iewBlockCycles 736 # Number of cycles IEW is blocking 950system.cpu1.iew.iewUnblockCycles 43 # Number of cycles IEW is unblocking 951system.cpu1.iew.iewDispatchedInsts 225068 # Number of instructions dispatched to IQ 952system.cpu1.iew.iewDispSquashedInsts 373 # Number of squashed instructions skipped by dispatch 953system.cpu1.iew.iewDispLoadInsts 60713 # Number of dispatched load instructions 954system.cpu1.iew.iewDispStoreInsts 26873 # Number of dispatched store instructions 955system.cpu1.iew.iewDispNonSpecInsts 1076 # Number of dispatched non-speculative instructions 956system.cpu1.iew.iewIQFullEvents 42 # Number of times the IQ has become full, causing a stall 957system.cpu1.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 958system.cpu1.iew.memOrderViolationEvents 43 # Number of memory order violations 959system.cpu1.iew.predictedTakenIncorrect 453 # Number of branches that were predicted taken incorrectly 960system.cpu1.iew.predictedNotTakenIncorrect 939 # Number of branches that were predicted not taken incorrectly 961system.cpu1.iew.branchMispredicts 1392 # Number of branch mispredicts detected at execute 962system.cpu1.iew.iewExecutedInsts 188449 # Number of executed instructions 963system.cpu1.iew.iewExecLoadInsts 59619 # Number of load instructions executed 964system.cpu1.iew.iewExecSquashedInsts 1168 # Number of squashed instructions skipped in execute 965system.cpu1.iew.exec_swp 0 # number of swp insts executed 966system.cpu1.iew.exec_nop 30958 # number of nop insts executed 967system.cpu1.iew.exec_refs 85720 # number of memory reference insts executed 968system.cpu1.iew.exec_branches 40129 # Number of branches executed 969system.cpu1.iew.exec_stores 26101 # Number of stores executed 970system.cpu1.iew.exec_rate 1.060603 # Inst execution rate 971system.cpu1.iew.wb_sent 188127 # cumulative count of insts sent to commit 972system.cpu1.iew.wb_count 187814 # cumulative count of insts written-back 973system.cpu1.iew.wb_producers 102456 # num instructions producing a value 974system.cpu1.iew.wb_consumers 107134 # num instructions consuming a value 975system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 976system.cpu1.iew.wb_rate 1.057029 # insts written-back per cycle 977system.cpu1.iew.wb_fanout 0.956335 # average fanout of values written-back 978system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 979system.cpu1.commit.commitSquashedInsts 12618 # The number of squashed insts skipped by commit 980system.cpu1.commit.commitNonSpecStalls 8639 # The number of times commit has been forced to stall to communicate backwards 981system.cpu1.commit.branchMispredicts 1279 # The number of times a branch was mispredicted 982system.cpu1.commit.committed_per_cycle::samples 165161 # Number of insts commited each cycle 983system.cpu1.commit.committed_per_cycle::mean 1.286212 # Number of insts commited each cycle 984system.cpu1.commit.committed_per_cycle::stdev 1.860966 # Number of insts commited each cycle 985system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 986system.cpu1.commit.committed_per_cycle::0 85256 51.62% 51.62% # Number of insts commited each cycle 987system.cpu1.commit.committed_per_cycle::1 38272 23.17% 74.79% # Number of insts commited each cycle 988system.cpu1.commit.committed_per_cycle::2 6084 3.68% 78.48% # Number of insts commited each cycle 989system.cpu1.commit.committed_per_cycle::3 9527 5.77% 84.24% # Number of insts commited each cycle 990system.cpu1.commit.committed_per_cycle::4 1571 0.95% 85.20% # Number of insts commited each cycle 991system.cpu1.commit.committed_per_cycle::5 22201 13.44% 98.64% # Number of insts commited each cycle 992system.cpu1.commit.committed_per_cycle::6 436 0.26% 98.90% # Number of insts commited each cycle 993system.cpu1.commit.committed_per_cycle::7 1006 0.61% 99.51% # Number of insts commited each cycle 994system.cpu1.commit.committed_per_cycle::8 808 0.49% 100.00% # Number of insts commited each cycle 995system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 996system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 997system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 998system.cpu1.commit.committed_per_cycle::total 165161 # Number of insts commited each cycle 999system.cpu1.commit.committedInsts 212432 # Number of instructions committed 1000system.cpu1.commit.committedOps 212432 # Number of ops (including micro ops) committed 1001system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed 1002system.cpu1.commit.refs 83673 # Number of memory references committed 1003system.cpu1.commit.loads 58239 # Number of loads committed 1004system.cpu1.commit.membars 7917 # Number of memory barriers committed 1005system.cpu1.commit.branches 39308 # Number of branches committed 1006system.cpu1.commit.fp_insts 0 # Number of committed floating point instructions. 1007system.cpu1.commit.int_insts 145097 # Number of committed integer instructions. 1008system.cpu1.commit.function_calls 322 # Number of function calls committed. 1009system.cpu1.commit.bw_lim_events 808 # number cycles where commit BW limit reached 1010system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits 1011system.cpu1.rob.rob_reads 388816 # The number of ROB reads 1012system.cpu1.rob.rob_writes 452512 # The number of ROB writes 1013system.cpu1.timesIdled 218 # Number of times that the entire CPU went into an idle state and unscheduled itself 1014system.cpu1.idleCycles 2375 # Total number of cycles that the CPU has spent unscheduled due to idling 1015system.cpu1.quiesceCycles 43927 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1016system.cpu1.committedInsts 174425 # Number of Instructions Simulated 1017system.cpu1.committedOps 174425 # Number of Ops (including micro ops) Simulated 1018system.cpu1.committedInsts_total 174425 # Number of Instructions Simulated 1019system.cpu1.cpi 1.018667 # CPI: Cycles Per Instruction 1020system.cpu1.cpi_total 1.018667 # CPI: Total CPI of All Threads 1021system.cpu1.ipc 0.981675 # IPC: Instructions Per Cycle 1022system.cpu1.ipc_total 0.981675 # IPC: Total IPC of All Threads 1023system.cpu1.int_regfile_reads 315718 # number of integer regfile reads 1024system.cpu1.int_regfile_writes 148477 # number of integer regfile writes 1025system.cpu1.fp_regfile_writes 64 # number of floating regfile writes 1026system.cpu1.misc_regfile_reads 87269 # number of misc regfile reads 1027system.cpu1.misc_regfile_writes 648 # number of misc regfile writes 1028system.cpu1.icache.tags.replacements 318 # number of replacements 1029system.cpu1.icache.tags.tagsinuse 79.958659 # Cycle average of tags in use 1030system.cpu1.icache.tags.total_refs 25178 # Total number of references to valid blocks. 1031system.cpu1.icache.tags.sampled_refs 428 # Sample count of references to valid blocks. 1032system.cpu1.icache.tags.avg_refs 58.827103 # Average number of references to valid blocks. 1033system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1034system.cpu1.icache.tags.occ_blocks::cpu1.inst 79.958659 # Average occupied blocks per requestor 1035system.cpu1.icache.tags.occ_percent::cpu1.inst 0.156169 # Average percentage of cache occupancy 1036system.cpu1.icache.tags.occ_percent::total 0.156169 # Average percentage of cache occupancy 1037system.cpu1.icache.ReadReq_hits::cpu1.inst 25178 # number of ReadReq hits 1038system.cpu1.icache.ReadReq_hits::total 25178 # number of ReadReq hits 1039system.cpu1.icache.demand_hits::cpu1.inst 25178 # number of demand (read+write) hits 1040system.cpu1.icache.demand_hits::total 25178 # number of demand (read+write) hits 1041system.cpu1.icache.overall_hits::cpu1.inst 25178 # number of overall hits 1042system.cpu1.icache.overall_hits::total 25178 # number of overall hits 1043system.cpu1.icache.ReadReq_misses::cpu1.inst 478 # number of ReadReq misses 1044system.cpu1.icache.ReadReq_misses::total 478 # number of ReadReq misses 1045system.cpu1.icache.demand_misses::cpu1.inst 478 # number of demand (read+write) misses 1046system.cpu1.icache.demand_misses::total 478 # number of demand (read+write) misses 1047system.cpu1.icache.overall_misses::cpu1.inst 478 # number of overall misses 1048system.cpu1.icache.overall_misses::total 478 # number of overall misses 1049system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7224243 # number of ReadReq miss cycles 1050system.cpu1.icache.ReadReq_miss_latency::total 7224243 # number of ReadReq miss cycles 1051system.cpu1.icache.demand_miss_latency::cpu1.inst 7224243 # number of demand (read+write) miss cycles 1052system.cpu1.icache.demand_miss_latency::total 7224243 # number of demand (read+write) miss cycles 1053system.cpu1.icache.overall_miss_latency::cpu1.inst 7224243 # number of overall miss cycles 1054system.cpu1.icache.overall_miss_latency::total 7224243 # number of overall miss cycles 1055system.cpu1.icache.ReadReq_accesses::cpu1.inst 25656 # number of ReadReq accesses(hits+misses) 1056system.cpu1.icache.ReadReq_accesses::total 25656 # number of ReadReq accesses(hits+misses) 1057system.cpu1.icache.demand_accesses::cpu1.inst 25656 # number of demand (read+write) accesses 1058system.cpu1.icache.demand_accesses::total 25656 # number of demand (read+write) accesses 1059system.cpu1.icache.overall_accesses::cpu1.inst 25656 # number of overall (read+write) accesses 1060system.cpu1.icache.overall_accesses::total 25656 # number of overall (read+write) accesses 1061system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.018631 # miss rate for ReadReq accesses 1062system.cpu1.icache.ReadReq_miss_rate::total 0.018631 # miss rate for ReadReq accesses 1063system.cpu1.icache.demand_miss_rate::cpu1.inst 0.018631 # miss rate for demand accesses 1064system.cpu1.icache.demand_miss_rate::total 0.018631 # miss rate for demand accesses 1065system.cpu1.icache.overall_miss_rate::cpu1.inst 0.018631 # miss rate for overall accesses 1066system.cpu1.icache.overall_miss_rate::total 0.018631 # miss rate for overall accesses 1067system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15113.479079 # average ReadReq miss latency 1068system.cpu1.icache.ReadReq_avg_miss_latency::total 15113.479079 # average ReadReq miss latency 1069system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15113.479079 # average overall miss latency 1070system.cpu1.icache.demand_avg_miss_latency::total 15113.479079 # average overall miss latency 1071system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15113.479079 # average overall miss latency 1072system.cpu1.icache.overall_avg_miss_latency::total 15113.479079 # average overall miss latency 1073system.cpu1.icache.blocked_cycles::no_mshrs 26 # number of cycles access was blocked 1074system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1075system.cpu1.icache.blocked::no_mshrs 2 # number of cycles access was blocked 1076system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1077system.cpu1.icache.avg_blocked_cycles::no_mshrs 13 # average number of cycles each access was blocked 1078system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1079system.cpu1.icache.fast_writes 0 # number of fast writes performed 1080system.cpu1.icache.cache_copies 0 # number of cache copies performed 1081system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 50 # number of ReadReq MSHR hits 1082system.cpu1.icache.ReadReq_mshr_hits::total 50 # number of ReadReq MSHR hits 1083system.cpu1.icache.demand_mshr_hits::cpu1.inst 50 # number of demand (read+write) MSHR hits 1084system.cpu1.icache.demand_mshr_hits::total 50 # number of demand (read+write) MSHR hits 1085system.cpu1.icache.overall_mshr_hits::cpu1.inst 50 # number of overall MSHR hits 1086system.cpu1.icache.overall_mshr_hits::total 50 # number of overall MSHR hits 1087system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 428 # number of ReadReq MSHR misses 1088system.cpu1.icache.ReadReq_mshr_misses::total 428 # number of ReadReq MSHR misses 1089system.cpu1.icache.demand_mshr_misses::cpu1.inst 428 # number of demand (read+write) MSHR misses 1090system.cpu1.icache.demand_mshr_misses::total 428 # number of demand (read+write) MSHR misses 1091system.cpu1.icache.overall_mshr_misses::cpu1.inst 428 # number of overall MSHR misses 1092system.cpu1.icache.overall_mshr_misses::total 428 # number of overall MSHR misses 1093system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5769006 # number of ReadReq MSHR miss cycles 1094system.cpu1.icache.ReadReq_mshr_miss_latency::total 5769006 # number of ReadReq MSHR miss cycles 1095system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5769006 # number of demand (read+write) MSHR miss cycles 1096system.cpu1.icache.demand_mshr_miss_latency::total 5769006 # number of demand (read+write) MSHR miss cycles 1097system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5769006 # number of overall MSHR miss cycles 1098system.cpu1.icache.overall_mshr_miss_latency::total 5769006 # number of overall MSHR miss cycles 1099system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016682 # mshr miss rate for ReadReq accesses 1100system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.016682 # mshr miss rate for ReadReq accesses 1101system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.016682 # mshr miss rate for demand accesses 1102system.cpu1.icache.demand_mshr_miss_rate::total 0.016682 # mshr miss rate for demand accesses 1103system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.016682 # mshr miss rate for overall accesses 1104system.cpu1.icache.overall_mshr_miss_rate::total 0.016682 # mshr miss rate for overall accesses 1105system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13478.985981 # average ReadReq mshr miss latency 1106system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13478.985981 # average ReadReq mshr miss latency 1107system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13478.985981 # average overall mshr miss latency 1108system.cpu1.icache.demand_avg_mshr_miss_latency::total 13478.985981 # average overall mshr miss latency 1109system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13478.985981 # average overall mshr miss latency 1110system.cpu1.icache.overall_avg_mshr_miss_latency::total 13478.985981 # average overall mshr miss latency 1111system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1112system.cpu1.dcache.tags.replacements 0 # number of replacements 1113system.cpu1.dcache.tags.tagsinuse 24.742100 # Cycle average of tags in use 1114system.cpu1.dcache.tags.total_refs 31558 # Total number of references to valid blocks. 1115system.cpu1.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. 1116system.cpu1.dcache.tags.avg_refs 1088.206897 # Average number of references to valid blocks. 1117system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1118system.cpu1.dcache.tags.occ_blocks::cpu1.data 24.742100 # Average occupied blocks per requestor 1119system.cpu1.dcache.tags.occ_percent::cpu1.data 0.048324 # Average percentage of cache occupancy 1120system.cpu1.dcache.tags.occ_percent::total 0.048324 # Average percentage of cache occupancy 1121system.cpu1.dcache.ReadReq_hits::cpu1.data 37722 # number of ReadReq hits 1122system.cpu1.dcache.ReadReq_hits::total 37722 # number of ReadReq hits 1123system.cpu1.dcache.WriteReq_hits::cpu1.data 25226 # number of WriteReq hits 1124system.cpu1.dcache.WriteReq_hits::total 25226 # number of WriteReq hits 1125system.cpu1.dcache.SwapReq_hits::cpu1.data 16 # number of SwapReq hits 1126system.cpu1.dcache.SwapReq_hits::total 16 # number of SwapReq hits 1127system.cpu1.dcache.demand_hits::cpu1.data 62948 # number of demand (read+write) hits 1128system.cpu1.dcache.demand_hits::total 62948 # number of demand (read+write) hits 1129system.cpu1.dcache.overall_hits::cpu1.data 62948 # number of overall hits 1130system.cpu1.dcache.overall_hits::total 62948 # number of overall hits 1131system.cpu1.dcache.ReadReq_misses::cpu1.data 319 # number of ReadReq misses 1132system.cpu1.dcache.ReadReq_misses::total 319 # number of ReadReq misses 1133system.cpu1.dcache.WriteReq_misses::cpu1.data 132 # number of WriteReq misses 1134system.cpu1.dcache.WriteReq_misses::total 132 # number of WriteReq misses 1135system.cpu1.dcache.SwapReq_misses::cpu1.data 60 # number of SwapReq misses 1136system.cpu1.dcache.SwapReq_misses::total 60 # number of SwapReq misses 1137system.cpu1.dcache.demand_misses::cpu1.data 451 # number of demand (read+write) misses 1138system.cpu1.dcache.demand_misses::total 451 # number of demand (read+write) misses 1139system.cpu1.dcache.overall_misses::cpu1.data 451 # number of overall misses 1140system.cpu1.dcache.overall_misses::total 451 # number of overall misses 1141system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3919891 # number of ReadReq miss cycles 1142system.cpu1.dcache.ReadReq_miss_latency::total 3919891 # number of ReadReq miss cycles 1143system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2617261 # number of WriteReq miss cycles 1144system.cpu1.dcache.WriteReq_miss_latency::total 2617261 # number of WriteReq miss cycles 1145system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 548504 # number of SwapReq miss cycles 1146system.cpu1.dcache.SwapReq_miss_latency::total 548504 # number of SwapReq miss cycles 1147system.cpu1.dcache.demand_miss_latency::cpu1.data 6537152 # number of demand (read+write) miss cycles 1148system.cpu1.dcache.demand_miss_latency::total 6537152 # number of demand (read+write) miss cycles 1149system.cpu1.dcache.overall_miss_latency::cpu1.data 6537152 # number of overall miss cycles 1150system.cpu1.dcache.overall_miss_latency::total 6537152 # number of overall miss cycles 1151system.cpu1.dcache.ReadReq_accesses::cpu1.data 38041 # number of ReadReq accesses(hits+misses) 1152system.cpu1.dcache.ReadReq_accesses::total 38041 # number of ReadReq accesses(hits+misses) 1153system.cpu1.dcache.WriteReq_accesses::cpu1.data 25358 # number of WriteReq accesses(hits+misses) 1154system.cpu1.dcache.WriteReq_accesses::total 25358 # number of WriteReq accesses(hits+misses) 1155system.cpu1.dcache.SwapReq_accesses::cpu1.data 76 # number of SwapReq accesses(hits+misses) 1156system.cpu1.dcache.SwapReq_accesses::total 76 # number of SwapReq accesses(hits+misses) 1157system.cpu1.dcache.demand_accesses::cpu1.data 63399 # number of demand (read+write) accesses 1158system.cpu1.dcache.demand_accesses::total 63399 # number of demand (read+write) accesses 1159system.cpu1.dcache.overall_accesses::cpu1.data 63399 # number of overall (read+write) accesses 1160system.cpu1.dcache.overall_accesses::total 63399 # number of overall (read+write) accesses 1161system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.008386 # miss rate for ReadReq accesses 1162system.cpu1.dcache.ReadReq_miss_rate::total 0.008386 # miss rate for ReadReq accesses 1163system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.005205 # miss rate for WriteReq accesses 1164system.cpu1.dcache.WriteReq_miss_rate::total 0.005205 # miss rate for WriteReq accesses 1165system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.789474 # miss rate for SwapReq accesses 1166system.cpu1.dcache.SwapReq_miss_rate::total 0.789474 # miss rate for SwapReq accesses 1167system.cpu1.dcache.demand_miss_rate::cpu1.data 0.007114 # miss rate for demand accesses 1168system.cpu1.dcache.demand_miss_rate::total 0.007114 # miss rate for demand accesses 1169system.cpu1.dcache.overall_miss_rate::cpu1.data 0.007114 # miss rate for overall accesses 1170system.cpu1.dcache.overall_miss_rate::total 0.007114 # miss rate for overall accesses 1171system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12288.059561 # average ReadReq miss latency 1172system.cpu1.dcache.ReadReq_avg_miss_latency::total 12288.059561 # average ReadReq miss latency 1173system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 19827.734848 # average WriteReq miss latency 1174system.cpu1.dcache.WriteReq_avg_miss_latency::total 19827.734848 # average WriteReq miss latency 1175system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 9141.733333 # average SwapReq miss latency 1176system.cpu1.dcache.SwapReq_avg_miss_latency::total 9141.733333 # average SwapReq miss latency 1177system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14494.793792 # average overall miss latency 1178system.cpu1.dcache.demand_avg_miss_latency::total 14494.793792 # average overall miss latency 1179system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14494.793792 # average overall miss latency 1180system.cpu1.dcache.overall_avg_miss_latency::total 14494.793792 # average overall miss latency 1181system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1182system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1183system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1184system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1185system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1186system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1187system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1188system.cpu1.dcache.cache_copies 0 # number of cache copies performed 1189system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 154 # number of ReadReq MSHR hits 1190system.cpu1.dcache.ReadReq_mshr_hits::total 154 # number of ReadReq MSHR hits 1191system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 32 # number of WriteReq MSHR hits 1192system.cpu1.dcache.WriteReq_mshr_hits::total 32 # number of WriteReq MSHR hits 1193system.cpu1.dcache.demand_mshr_hits::cpu1.data 186 # number of demand (read+write) MSHR hits 1194system.cpu1.dcache.demand_mshr_hits::total 186 # number of demand (read+write) MSHR hits 1195system.cpu1.dcache.overall_mshr_hits::cpu1.data 186 # number of overall MSHR hits 1196system.cpu1.dcache.overall_mshr_hits::total 186 # number of overall MSHR hits 1197system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 165 # number of ReadReq MSHR misses 1198system.cpu1.dcache.ReadReq_mshr_misses::total 165 # number of ReadReq MSHR misses 1199system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 100 # number of WriteReq MSHR misses 1200system.cpu1.dcache.WriteReq_mshr_misses::total 100 # number of WriteReq MSHR misses 1201system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 60 # number of SwapReq MSHR misses 1202system.cpu1.dcache.SwapReq_mshr_misses::total 60 # number of SwapReq MSHR misses 1203system.cpu1.dcache.demand_mshr_misses::cpu1.data 265 # number of demand (read+write) MSHR misses 1204system.cpu1.dcache.demand_mshr_misses::total 265 # number of demand (read+write) MSHR misses 1205system.cpu1.dcache.overall_mshr_misses::cpu1.data 265 # number of overall MSHR misses 1206system.cpu1.dcache.overall_mshr_misses::total 265 # number of overall MSHR misses 1207system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1138770 # number of ReadReq MSHR miss cycles 1208system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1138770 # number of ReadReq MSHR miss cycles 1209system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1290739 # number of WriteReq MSHR miss cycles 1210system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1290739 # number of WriteReq MSHR miss cycles 1211system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 428496 # number of SwapReq MSHR miss cycles 1212system.cpu1.dcache.SwapReq_mshr_miss_latency::total 428496 # number of SwapReq MSHR miss cycles 1213system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2429509 # number of demand (read+write) MSHR miss cycles 1214system.cpu1.dcache.demand_mshr_miss_latency::total 2429509 # number of demand (read+write) MSHR miss cycles 1215system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2429509 # number of overall MSHR miss cycles 1216system.cpu1.dcache.overall_mshr_miss_latency::total 2429509 # number of overall MSHR miss cycles 1217system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.004337 # mshr miss rate for ReadReq accesses 1218system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.004337 # mshr miss rate for ReadReq accesses 1219system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.003944 # mshr miss rate for WriteReq accesses 1220system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.003944 # mshr miss rate for WriteReq accesses 1221system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.789474 # mshr miss rate for SwapReq accesses 1222system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.789474 # mshr miss rate for SwapReq accesses 1223system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.004180 # mshr miss rate for demand accesses 1224system.cpu1.dcache.demand_mshr_miss_rate::total 0.004180 # mshr miss rate for demand accesses 1225system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.004180 # mshr miss rate for overall accesses 1226system.cpu1.dcache.overall_mshr_miss_rate::total 0.004180 # mshr miss rate for overall accesses 1227system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 6901.636364 # average ReadReq mshr miss latency 1228system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 6901.636364 # average ReadReq mshr miss latency 1229system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 12907.390000 # average WriteReq mshr miss latency 1230system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 12907.390000 # average WriteReq mshr miss latency 1231system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 7141.600000 # average SwapReq mshr miss latency 1232system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 7141.600000 # average SwapReq mshr miss latency 1233system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 9167.958491 # average overall mshr miss latency 1234system.cpu1.dcache.demand_avg_mshr_miss_latency::total 9167.958491 # average overall mshr miss latency 1235system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 9167.958491 # average overall mshr miss latency 1236system.cpu1.dcache.overall_avg_mshr_miss_latency::total 9167.958491 # average overall mshr miss latency 1237system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1238system.cpu2.branchPred.lookups 51236 # Number of BP lookups 1239system.cpu2.branchPred.condPredicted 48519 # Number of conditional branches predicted 1240system.cpu2.branchPred.condIncorrect 1308 # Number of conditional branches incorrect 1241system.cpu2.branchPred.BTBLookups 45052 # Number of BTB lookups 1242system.cpu2.branchPred.BTBHits 44357 # Number of BTB hits 1243system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 1244system.cpu2.branchPred.BTBHitPct 98.457338 # BTB Hit Percentage 1245system.cpu2.branchPred.usedRAS 684 # Number of times the RAS was used to get a target. 1246system.cpu2.branchPred.RASInCorrect 232 # Number of incorrect RAS predictions. 1247system.cpu2.numCycles 177316 # number of cpu cycles simulated 1248system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started 1249system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed 1250system.cpu2.fetch.icacheStallCycles 28846 # Number of cycles fetch is stalled on an Icache miss 1251system.cpu2.fetch.Insts 286216 # Number of instructions fetch has processed 1252system.cpu2.fetch.Branches 51236 # Number of branches that fetch encountered 1253system.cpu2.fetch.predictedBranches 45041 # Number of branches that fetch has predicted taken 1254system.cpu2.fetch.Cycles 100902 # Number of cycles fetch has run and was not squashing or blocked 1255system.cpu2.fetch.SquashCycles 3805 # Number of cycles fetch has spent squashing 1256system.cpu2.fetch.BlockedCycles 31210 # Number of cycles fetch has spent blocked 1257system.cpu2.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 1258system.cpu2.fetch.NoActiveThreadStallCycles 7739 # Number of stall cycles due to no active thread to fetch from 1259system.cpu2.fetch.PendingTrapStallCycles 775 # Number of stall cycles due to pending traps 1260system.cpu2.fetch.CacheLines 19767 # Number of cache lines fetched 1261system.cpu2.fetch.IcacheSquashes 276 # Number of outstanding Icache misses that were squashed 1262system.cpu2.fetch.rateDist::samples 171898 # Number of instructions fetched each cycle (Total) 1263system.cpu2.fetch.rateDist::mean 1.665034 # Number of instructions fetched each cycle (Total) 1264system.cpu2.fetch.rateDist::stdev 2.139289 # Number of instructions fetched each cycle (Total) 1265system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 1266system.cpu2.fetch.rateDist::0 70996 41.30% 41.30% # Number of instructions fetched each cycle (Total) 1267system.cpu2.fetch.rateDist::1 51338 29.87% 71.17% # Number of instructions fetched each cycle (Total) 1268system.cpu2.fetch.rateDist::2 6125 3.56% 74.73% # Number of instructions fetched each cycle (Total) 1269system.cpu2.fetch.rateDist::3 3190 1.86% 76.59% # Number of instructions fetched each cycle (Total) 1270system.cpu2.fetch.rateDist::4 695 0.40% 76.99% # Number of instructions fetched each cycle (Total) 1271system.cpu2.fetch.rateDist::5 34353 19.98% 96.97% # Number of instructions fetched each cycle (Total) 1272system.cpu2.fetch.rateDist::6 1162 0.68% 97.65% # Number of instructions fetched each cycle (Total) 1273system.cpu2.fetch.rateDist::7 771 0.45% 98.10% # Number of instructions fetched each cycle (Total) 1274system.cpu2.fetch.rateDist::8 3268 1.90% 100.00% # Number of instructions fetched each cycle (Total) 1275system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 1276system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1277system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 1278system.cpu2.fetch.rateDist::total 171898 # Number of instructions fetched each cycle (Total) 1279system.cpu2.fetch.branchRate 0.288953 # Number of branch fetches per cycle 1280system.cpu2.fetch.rate 1.614158 # Number of inst fetches per cycle 1281system.cpu2.decode.IdleCycles 33770 # Number of cycles decode is idle 1282system.cpu2.decode.BlockedCycles 27924 # Number of cycles decode is blocked 1283system.cpu2.decode.RunCycles 94988 # Number of cycles decode is running 1284system.cpu2.decode.UnblockCycles 5055 # Number of cycles decode is unblocking 1285system.cpu2.decode.SquashCycles 2422 # Number of cycles decode is squashing 1286system.cpu2.decode.DecodedInsts 282690 # Number of instructions handled by decode 1287system.cpu2.rename.SquashCycles 2422 # Number of cycles rename is squashing 1288system.cpu2.rename.IdleCycles 34480 # Number of cycles rename is idle 1289system.cpu2.rename.BlockCycles 14885 # Number of cycles rename is blocking 1290system.cpu2.rename.serializeStallCycles 12280 # count of cycles rename stalled for serializing inst 1291system.cpu2.rename.RunCycles 90190 # Number of cycles rename is running 1292system.cpu2.rename.UnblockCycles 9902 # Number of cycles rename is unblocking 1293system.cpu2.rename.RenamedInsts 280450 # Number of instructions processed by rename 1294system.cpu2.rename.IQFullEvents 4 # Number of times rename has blocked due to IQ full 1295system.cpu2.rename.LSQFullEvents 24 # Number of times rename has blocked due to LSQ full 1296system.cpu2.rename.RenamedOperands 196553 # Number of destination operands rename has renamed 1297system.cpu2.rename.RenameLookups 537620 # Number of register rename lookups that rename has made 1298system.cpu2.rename.int_rename_lookups 537620 # Number of integer rename lookups 1299system.cpu2.rename.CommittedMaps 183508 # Number of HB maps that are committed 1300system.cpu2.rename.UndoneMaps 13045 # Number of HB maps that are undone due to squashing 1301system.cpu2.rename.serializingInsts 1112 # count of serializing insts renamed 1302system.cpu2.rename.tempSerializingInsts 1237 # count of temporary serializing insts renamed 1303system.cpu2.rename.skidInsts 12513 # count of insts added to the skid buffer 1304system.cpu2.memDep0.insertedLoads 79191 # Number of loads inserted to the mem dependence unit. 1305system.cpu2.memDep0.insertedStores 37564 # Number of stores inserted to the mem dependence unit. 1306system.cpu2.memDep0.conflictingLoads 37796 # Number of conflicting loads. 1307system.cpu2.memDep0.conflictingStores 32512 # Number of conflicting stores. 1308system.cpu2.iq.iqInstsAdded 232563 # Number of instructions added to the IQ (excludes non-spec) 1309system.cpu2.iq.iqNonSpecInstsAdded 6341 # Number of non-speculative instructions added to the IQ 1310system.cpu2.iq.iqInstsIssued 234561 # Number of instructions issued 1311system.cpu2.iq.iqSquashedInstsIssued 83 # Number of squashed instructions issued 1312system.cpu2.iq.iqSquashedInstsExamined 11040 # Number of squashed instructions iterated over during squash; mainly for profiling 1313system.cpu2.iq.iqSquashedOperandsExamined 10888 # Number of squashed operands that are examined and possibly removed from graph 1314system.cpu2.iq.iqSquashedNonSpecRemoved 602 # Number of squashed non-spec instructions that were removed 1315system.cpu2.iq.issued_per_cycle::samples 171898 # Number of insts issued each cycle 1316system.cpu2.iq.issued_per_cycle::mean 1.364536 # Number of insts issued each cycle 1317system.cpu2.iq.issued_per_cycle::stdev 1.313534 # Number of insts issued each cycle 1318system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 1319system.cpu2.iq.issued_per_cycle::0 68441 39.81% 39.81% # Number of insts issued each cycle 1320system.cpu2.iq.issued_per_cycle::1 22472 13.07% 52.89% # Number of insts issued each cycle 1321system.cpu2.iq.issued_per_cycle::2 37788 21.98% 74.87% # Number of insts issued each cycle 1322system.cpu2.iq.issued_per_cycle::3 38389 22.33% 97.20% # Number of insts issued each cycle 1323system.cpu2.iq.issued_per_cycle::4 3254 1.89% 99.10% # Number of insts issued each cycle 1324system.cpu2.iq.issued_per_cycle::5 1164 0.68% 99.77% # Number of insts issued each cycle 1325system.cpu2.iq.issued_per_cycle::6 277 0.16% 99.93% # Number of insts issued each cycle 1326system.cpu2.iq.issued_per_cycle::7 56 0.03% 99.97% # Number of insts issued each cycle 1327system.cpu2.iq.issued_per_cycle::8 57 0.03% 100.00% # Number of insts issued each cycle 1328system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1329system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1330system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 1331system.cpu2.iq.issued_per_cycle::total 171898 # Number of insts issued each cycle 1332system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 1333system.cpu2.iq.fu_full::IntAlu 17 6.14% 6.14% # attempts to use FU when none available 1334system.cpu2.iq.fu_full::IntMult 0 0.00% 6.14% # attempts to use FU when none available 1335system.cpu2.iq.fu_full::IntDiv 0 0.00% 6.14% # attempts to use FU when none available 1336system.cpu2.iq.fu_full::FloatAdd 0 0.00% 6.14% # attempts to use FU when none available 1337system.cpu2.iq.fu_full::FloatCmp 0 0.00% 6.14% # attempts to use FU when none available 1338system.cpu2.iq.fu_full::FloatCvt 0 0.00% 6.14% # attempts to use FU when none available 1339system.cpu2.iq.fu_full::FloatMult 0 0.00% 6.14% # attempts to use FU when none available 1340system.cpu2.iq.fu_full::FloatDiv 0 0.00% 6.14% # attempts to use FU when none available 1341system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 6.14% # attempts to use FU when none available 1342system.cpu2.iq.fu_full::SimdAdd 0 0.00% 6.14% # attempts to use FU when none available 1343system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 6.14% # attempts to use FU when none available 1344system.cpu2.iq.fu_full::SimdAlu 0 0.00% 6.14% # attempts to use FU when none available 1345system.cpu2.iq.fu_full::SimdCmp 0 0.00% 6.14% # attempts to use FU when none available 1346system.cpu2.iq.fu_full::SimdCvt 0 0.00% 6.14% # attempts to use FU when none available 1347system.cpu2.iq.fu_full::SimdMisc 0 0.00% 6.14% # attempts to use FU when none available 1348system.cpu2.iq.fu_full::SimdMult 0 0.00% 6.14% # attempts to use FU when none available 1349system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 6.14% # attempts to use FU when none available 1350system.cpu2.iq.fu_full::SimdShift 0 0.00% 6.14% # attempts to use FU when none available 1351system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 6.14% # attempts to use FU when none available 1352system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 6.14% # attempts to use FU when none available 1353system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 6.14% # attempts to use FU when none available 1354system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 6.14% # attempts to use FU when none available 1355system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 6.14% # attempts to use FU when none available 1356system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 6.14% # attempts to use FU when none available 1357system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 6.14% # attempts to use FU when none available 1358system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 6.14% # attempts to use FU when none available 1359system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 6.14% # attempts to use FU when none available 1360system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.14% # attempts to use FU when none available 1361system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 6.14% # attempts to use FU when none available 1362system.cpu2.iq.fu_full::MemRead 50 18.05% 24.19% # attempts to use FU when none available 1363system.cpu2.iq.fu_full::MemWrite 210 75.81% 100.00% # attempts to use FU when none available 1364system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 1365system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 1366system.cpu2.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 1367system.cpu2.iq.FU_type_0::IntAlu 114217 48.69% 48.69% # Type of FU issued 1368system.cpu2.iq.FU_type_0::IntMult 0 0.00% 48.69% # Type of FU issued 1369system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 48.69% # Type of FU issued 1370system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 48.69% # Type of FU issued 1371system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 48.69% # Type of FU issued 1372system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 48.69% # Type of FU issued 1373system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 48.69% # Type of FU issued 1374system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 48.69% # Type of FU issued 1375system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 48.69% # Type of FU issued 1376system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 48.69% # Type of FU issued 1377system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 48.69% # Type of FU issued 1378system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 48.69% # Type of FU issued 1379system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 48.69% # Type of FU issued 1380system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 48.69% # Type of FU issued 1381system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 48.69% # Type of FU issued 1382system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 48.69% # Type of FU issued 1383system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 48.69% # Type of FU issued 1384system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 48.69% # Type of FU issued 1385system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.69% # Type of FU issued 1386system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 48.69% # Type of FU issued 1387system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.69% # Type of FU issued 1388system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.69% # Type of FU issued 1389system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.69% # Type of FU issued 1390system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.69% # Type of FU issued 1391system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.69% # Type of FU issued 1392system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.69% # Type of FU issued 1393system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 48.69% # Type of FU issued 1394system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.69% # Type of FU issued 1395system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.69% # Type of FU issued 1396system.cpu2.iq.FU_type_0::MemRead 83468 35.58% 84.28% # Type of FU issued 1397system.cpu2.iq.FU_type_0::MemWrite 36876 15.72% 100.00% # Type of FU issued 1398system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 1399system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 1400system.cpu2.iq.FU_type_0::total 234561 # Type of FU issued 1401system.cpu2.iq.rate 1.322842 # Inst issue rate 1402system.cpu2.iq.fu_busy_cnt 277 # FU busy when requested 1403system.cpu2.iq.fu_busy_rate 0.001181 # FU busy rate (busy events/executed inst) 1404system.cpu2.iq.int_inst_queue_reads 641380 # Number of integer instruction queue reads 1405system.cpu2.iq.int_inst_queue_writes 249989 # Number of integer instruction queue writes 1406system.cpu2.iq.int_inst_queue_wakeup_accesses 232740 # Number of integer instruction queue wakeup accesses 1407system.cpu2.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads 1408system.cpu2.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes 1409system.cpu2.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses 1410system.cpu2.iq.int_alu_accesses 234838 # Number of integer alu accesses 1411system.cpu2.iq.fp_alu_accesses 0 # Number of floating point alu accesses 1412system.cpu2.iew.lsq.thread0.forwLoads 32248 # Number of loads that had data forwarded from stores 1413system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 1414system.cpu2.iew.lsq.thread0.squashedLoads 2484 # Number of loads squashed 1415system.cpu2.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed 1416system.cpu2.iew.lsq.thread0.memOrderViolation 45 # Number of memory ordering violations 1417system.cpu2.iew.lsq.thread0.squashedStores 1465 # Number of stores squashed 1418system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 1419system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 1420system.cpu2.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 1421system.cpu2.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked 1422system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle 1423system.cpu2.iew.iewSquashCycles 2422 # Number of cycles IEW is squashing 1424system.cpu2.iew.iewBlockCycles 851 # Number of cycles IEW is blocking 1425system.cpu2.iew.iewUnblockCycles 46 # Number of cycles IEW is unblocking 1426system.cpu2.iew.iewDispatchedInsts 277610 # Number of instructions dispatched to IQ 1427system.cpu2.iew.iewDispSquashedInsts 365 # Number of squashed instructions skipped by dispatch 1428system.cpu2.iew.iewDispLoadInsts 79191 # Number of dispatched load instructions 1429system.cpu2.iew.iewDispStoreInsts 37564 # Number of dispatched store instructions 1430system.cpu2.iew.iewDispNonSpecInsts 1068 # Number of dispatched non-speculative instructions 1431system.cpu2.iew.iewIQFullEvents 46 # Number of times the IQ has become full, causing a stall 1432system.cpu2.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 1433system.cpu2.iew.memOrderViolationEvents 45 # Number of memory order violations 1434system.cpu2.iew.predictedTakenIncorrect 466 # Number of branches that were predicted taken incorrectly 1435system.cpu2.iew.predictedNotTakenIncorrect 970 # Number of branches that were predicted not taken incorrectly 1436system.cpu2.iew.branchMispredicts 1436 # Number of branch mispredicts detected at execute 1437system.cpu2.iew.iewExecutedInsts 233403 # Number of executed instructions 1438system.cpu2.iew.iewExecLoadInsts 78158 # Number of load instructions executed 1439system.cpu2.iew.iewExecSquashedInsts 1158 # Number of squashed instructions skipped in execute 1440system.cpu2.iew.exec_swp 0 # number of swp insts executed 1441system.cpu2.iew.exec_nop 38706 # number of nop insts executed 1442system.cpu2.iew.exec_refs 114950 # number of memory reference insts executed 1443system.cpu2.iew.exec_branches 47927 # Number of branches executed 1444system.cpu2.iew.exec_stores 36792 # Number of stores executed 1445system.cpu2.iew.exec_rate 1.316311 # Inst execution rate 1446system.cpu2.iew.wb_sent 233070 # cumulative count of insts sent to commit 1447system.cpu2.iew.wb_count 232740 # cumulative count of insts written-back 1448system.cpu2.iew.wb_producers 131730 # num instructions producing a value 1449system.cpu2.iew.wb_consumers 136434 # num instructions consuming a value 1450system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 1451system.cpu2.iew.wb_rate 1.312572 # insts written-back per cycle 1452system.cpu2.iew.wb_fanout 0.965522 # average fanout of values written-back 1453system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 1454system.cpu2.commit.commitSquashedInsts 12692 # The number of squashed insts skipped by commit 1455system.cpu2.commit.commitNonSpecStalls 5739 # The number of times commit has been forced to stall to communicate backwards 1456system.cpu2.commit.branchMispredicts 1308 # The number of times a branch was mispredicted 1457system.cpu2.commit.committed_per_cycle::samples 161737 # Number of insts commited each cycle 1458system.cpu2.commit.committed_per_cycle::mean 1.637943 # Number of insts commited each cycle 1459system.cpu2.commit.committed_per_cycle::stdev 2.020354 # Number of insts commited each cycle 1460system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 1461system.cpu2.commit.committed_per_cycle::0 66243 40.96% 40.96% # Number of insts commited each cycle 1462system.cpu2.commit.committed_per_cycle::1 46082 28.49% 69.45% # Number of insts commited each cycle 1463system.cpu2.commit.committed_per_cycle::2 6100 3.77% 73.22% # Number of insts commited each cycle 1464system.cpu2.commit.committed_per_cycle::3 6659 4.12% 77.34% # Number of insts commited each cycle 1465system.cpu2.commit.committed_per_cycle::4 1556 0.96% 78.30% # Number of insts commited each cycle 1466system.cpu2.commit.committed_per_cycle::5 32794 20.28% 98.58% # Number of insts commited each cycle 1467system.cpu2.commit.committed_per_cycle::6 480 0.30% 98.87% # Number of insts commited each cycle 1468system.cpu2.commit.committed_per_cycle::7 1001 0.62% 99.49% # Number of insts commited each cycle 1469system.cpu2.commit.committed_per_cycle::8 822 0.51% 100.00% # Number of insts commited each cycle 1470system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 1471system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 1472system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 1473system.cpu2.commit.committed_per_cycle::total 161737 # Number of insts commited each cycle 1474system.cpu2.commit.committedInsts 264916 # Number of instructions committed 1475system.cpu2.commit.committedOps 264916 # Number of ops (including micro ops) committed 1476system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed 1477system.cpu2.commit.refs 112806 # Number of memory references committed 1478system.cpu2.commit.loads 76707 # Number of loads committed 1479system.cpu2.commit.membars 5024 # Number of memory barriers committed 1480system.cpu2.commit.branches 47088 # Number of branches committed 1481system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions. 1482system.cpu2.commit.int_insts 182014 # Number of committed integer instructions. 1483system.cpu2.commit.function_calls 322 # Number of function calls committed. 1484system.cpu2.commit.bw_lim_events 822 # number cycles where commit BW limit reached 1485system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits 1486system.cpu2.rob.rob_reads 437936 # The number of ROB reads 1487system.cpu2.rob.rob_writes 557643 # The number of ROB writes 1488system.cpu2.timesIdled 224 # Number of times that the entire CPU went into an idle state and unscheduled itself 1489system.cpu2.idleCycles 5418 # Total number of cycles that the CPU has spent unscheduled due to idling 1490system.cpu2.quiesceCycles 44292 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1491system.cpu2.committedInsts 222015 # Number of Instructions Simulated 1492system.cpu2.committedOps 222015 # Number of Ops (including micro ops) Simulated 1493system.cpu2.committedInsts_total 222015 # Number of Instructions Simulated 1494system.cpu2.cpi 0.798667 # CPI: Cycles Per Instruction 1495system.cpu2.cpi_total 0.798667 # CPI: Total CPI of All Threads 1496system.cpu2.ipc 1.252087 # IPC: Instructions Per Cycle 1497system.cpu2.ipc_total 1.252087 # IPC: Total IPC of All Threads 1498system.cpu2.int_regfile_reads 403571 # number of integer regfile reads 1499system.cpu2.int_regfile_writes 188531 # number of integer regfile writes 1500system.cpu2.fp_regfile_writes 64 # number of floating regfile writes 1501system.cpu2.misc_regfile_reads 116514 # number of misc regfile reads 1502system.cpu2.misc_regfile_writes 648 # number of misc regfile writes 1503system.cpu2.icache.tags.replacements 317 # number of replacements 1504system.cpu2.icache.tags.tagsinuse 82.351710 # Cycle average of tags in use 1505system.cpu2.icache.tags.total_refs 19274 # Total number of references to valid blocks. 1506system.cpu2.icache.tags.sampled_refs 425 # Sample count of references to valid blocks. 1507system.cpu2.icache.tags.avg_refs 45.350588 # Average number of references to valid blocks. 1508system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1509system.cpu2.icache.tags.occ_blocks::cpu2.inst 82.351710 # Average occupied blocks per requestor 1510system.cpu2.icache.tags.occ_percent::cpu2.inst 0.160843 # Average percentage of cache occupancy 1511system.cpu2.icache.tags.occ_percent::total 0.160843 # Average percentage of cache occupancy 1512system.cpu2.icache.ReadReq_hits::cpu2.inst 19274 # number of ReadReq hits 1513system.cpu2.icache.ReadReq_hits::total 19274 # number of ReadReq hits 1514system.cpu2.icache.demand_hits::cpu2.inst 19274 # number of demand (read+write) hits 1515system.cpu2.icache.demand_hits::total 19274 # number of demand (read+write) hits 1516system.cpu2.icache.overall_hits::cpu2.inst 19274 # number of overall hits 1517system.cpu2.icache.overall_hits::total 19274 # number of overall hits 1518system.cpu2.icache.ReadReq_misses::cpu2.inst 493 # number of ReadReq misses 1519system.cpu2.icache.ReadReq_misses::total 493 # number of ReadReq misses 1520system.cpu2.icache.demand_misses::cpu2.inst 493 # number of demand (read+write) misses 1521system.cpu2.icache.demand_misses::total 493 # number of demand (read+write) misses 1522system.cpu2.icache.overall_misses::cpu2.inst 493 # number of overall misses 1523system.cpu2.icache.overall_misses::total 493 # number of overall misses 1524system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 11521742 # number of ReadReq miss cycles 1525system.cpu2.icache.ReadReq_miss_latency::total 11521742 # number of ReadReq miss cycles 1526system.cpu2.icache.demand_miss_latency::cpu2.inst 11521742 # number of demand (read+write) miss cycles 1527system.cpu2.icache.demand_miss_latency::total 11521742 # number of demand (read+write) miss cycles 1528system.cpu2.icache.overall_miss_latency::cpu2.inst 11521742 # number of overall miss cycles 1529system.cpu2.icache.overall_miss_latency::total 11521742 # number of overall miss cycles 1530system.cpu2.icache.ReadReq_accesses::cpu2.inst 19767 # number of ReadReq accesses(hits+misses) 1531system.cpu2.icache.ReadReq_accesses::total 19767 # number of ReadReq accesses(hits+misses) 1532system.cpu2.icache.demand_accesses::cpu2.inst 19767 # number of demand (read+write) accesses 1533system.cpu2.icache.demand_accesses::total 19767 # number of demand (read+write) accesses 1534system.cpu2.icache.overall_accesses::cpu2.inst 19767 # number of overall (read+write) accesses 1535system.cpu2.icache.overall_accesses::total 19767 # number of overall (read+write) accesses 1536system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.024941 # miss rate for ReadReq accesses 1537system.cpu2.icache.ReadReq_miss_rate::total 0.024941 # miss rate for ReadReq accesses 1538system.cpu2.icache.demand_miss_rate::cpu2.inst 0.024941 # miss rate for demand accesses 1539system.cpu2.icache.demand_miss_rate::total 0.024941 # miss rate for demand accesses 1540system.cpu2.icache.overall_miss_rate::cpu2.inst 0.024941 # miss rate for overall accesses 1541system.cpu2.icache.overall_miss_rate::total 0.024941 # miss rate for overall accesses 1542system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 23370.673428 # average ReadReq miss latency 1543system.cpu2.icache.ReadReq_avg_miss_latency::total 23370.673428 # average ReadReq miss latency 1544system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 23370.673428 # average overall miss latency 1545system.cpu2.icache.demand_avg_miss_latency::total 23370.673428 # average overall miss latency 1546system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 23370.673428 # average overall miss latency 1547system.cpu2.icache.overall_avg_miss_latency::total 23370.673428 # average overall miss latency 1548system.cpu2.icache.blocked_cycles::no_mshrs 85 # number of cycles access was blocked 1549system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1550system.cpu2.icache.blocked::no_mshrs 1 # number of cycles access was blocked 1551system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked 1552system.cpu2.icache.avg_blocked_cycles::no_mshrs 85 # average number of cycles each access was blocked 1553system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1554system.cpu2.icache.fast_writes 0 # number of fast writes performed 1555system.cpu2.icache.cache_copies 0 # number of cache copies performed 1556system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 68 # number of ReadReq MSHR hits 1557system.cpu2.icache.ReadReq_mshr_hits::total 68 # number of ReadReq MSHR hits 1558system.cpu2.icache.demand_mshr_hits::cpu2.inst 68 # number of demand (read+write) MSHR hits 1559system.cpu2.icache.demand_mshr_hits::total 68 # number of demand (read+write) MSHR hits 1560system.cpu2.icache.overall_mshr_hits::cpu2.inst 68 # number of overall MSHR hits 1561system.cpu2.icache.overall_mshr_hits::total 68 # number of overall MSHR hits 1562system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 425 # number of ReadReq MSHR misses 1563system.cpu2.icache.ReadReq_mshr_misses::total 425 # number of ReadReq MSHR misses 1564system.cpu2.icache.demand_mshr_misses::cpu2.inst 425 # number of demand (read+write) MSHR misses 1565system.cpu2.icache.demand_mshr_misses::total 425 # number of demand (read+write) MSHR misses 1566system.cpu2.icache.overall_mshr_misses::cpu2.inst 425 # number of overall MSHR misses 1567system.cpu2.icache.overall_mshr_misses::total 425 # number of overall MSHR misses 1568system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 9201754 # number of ReadReq MSHR miss cycles 1569system.cpu2.icache.ReadReq_mshr_miss_latency::total 9201754 # number of ReadReq MSHR miss cycles 1570system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 9201754 # number of demand (read+write) MSHR miss cycles 1571system.cpu2.icache.demand_mshr_miss_latency::total 9201754 # number of demand (read+write) MSHR miss cycles 1572system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 9201754 # number of overall MSHR miss cycles 1573system.cpu2.icache.overall_mshr_miss_latency::total 9201754 # number of overall MSHR miss cycles 1574system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.021500 # mshr miss rate for ReadReq accesses 1575system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.021500 # mshr miss rate for ReadReq accesses 1576system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.021500 # mshr miss rate for demand accesses 1577system.cpu2.icache.demand_mshr_miss_rate::total 0.021500 # mshr miss rate for demand accesses 1578system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.021500 # mshr miss rate for overall accesses 1579system.cpu2.icache.overall_mshr_miss_rate::total 0.021500 # mshr miss rate for overall accesses 1580system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 21651.185882 # average ReadReq mshr miss latency 1581system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 21651.185882 # average ReadReq mshr miss latency 1582system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 21651.185882 # average overall mshr miss latency 1583system.cpu2.icache.demand_avg_mshr_miss_latency::total 21651.185882 # average overall mshr miss latency 1584system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 21651.185882 # average overall mshr miss latency 1585system.cpu2.icache.overall_avg_mshr_miss_latency::total 21651.185882 # average overall mshr miss latency 1586system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1587system.cpu2.dcache.tags.replacements 0 # number of replacements 1588system.cpu2.dcache.tags.tagsinuse 26.191522 # Cycle average of tags in use 1589system.cpu2.dcache.tags.total_refs 42135 # Total number of references to valid blocks. 1590system.cpu2.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks. 1591system.cpu2.dcache.tags.avg_refs 1504.821429 # Average number of references to valid blocks. 1592system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1593system.cpu2.dcache.tags.occ_blocks::cpu2.data 26.191522 # Average occupied blocks per requestor 1594system.cpu2.dcache.tags.occ_percent::cpu2.data 0.051155 # Average percentage of cache occupancy 1595system.cpu2.dcache.tags.occ_percent::total 0.051155 # Average percentage of cache occupancy 1596system.cpu2.dcache.ReadReq_hits::cpu2.data 45549 # number of ReadReq hits 1597system.cpu2.dcache.ReadReq_hits::total 45549 # number of ReadReq hits 1598system.cpu2.dcache.WriteReq_hits::cpu2.data 35887 # number of WriteReq hits 1599system.cpu2.dcache.WriteReq_hits::total 35887 # number of WriteReq hits 1600system.cpu2.dcache.SwapReq_hits::cpu2.data 12 # number of SwapReq hits 1601system.cpu2.dcache.SwapReq_hits::total 12 # number of SwapReq hits 1602system.cpu2.dcache.demand_hits::cpu2.data 81436 # number of demand (read+write) hits 1603system.cpu2.dcache.demand_hits::total 81436 # number of demand (read+write) hits 1604system.cpu2.dcache.overall_hits::cpu2.data 81436 # number of overall hits 1605system.cpu2.dcache.overall_hits::total 81436 # number of overall hits 1606system.cpu2.dcache.ReadReq_misses::cpu2.data 344 # number of ReadReq misses 1607system.cpu2.dcache.ReadReq_misses::total 344 # number of ReadReq misses 1608system.cpu2.dcache.WriteReq_misses::cpu2.data 143 # number of WriteReq misses 1609system.cpu2.dcache.WriteReq_misses::total 143 # number of WriteReq misses 1610system.cpu2.dcache.SwapReq_misses::cpu2.data 57 # number of SwapReq misses 1611system.cpu2.dcache.SwapReq_misses::total 57 # number of SwapReq misses 1612system.cpu2.dcache.demand_misses::cpu2.data 487 # number of demand (read+write) misses 1613system.cpu2.dcache.demand_misses::total 487 # number of demand (read+write) misses 1614system.cpu2.dcache.overall_misses::cpu2.data 487 # number of overall misses 1615system.cpu2.dcache.overall_misses::total 487 # number of overall misses 1616system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 5599802 # number of ReadReq miss cycles 1617system.cpu2.dcache.ReadReq_miss_latency::total 5599802 # number of ReadReq miss cycles 1618system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 3105260 # number of WriteReq miss cycles 1619system.cpu2.dcache.WriteReq_miss_latency::total 3105260 # number of WriteReq miss cycles 1620system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 575007 # number of SwapReq miss cycles 1621system.cpu2.dcache.SwapReq_miss_latency::total 575007 # number of SwapReq miss cycles 1622system.cpu2.dcache.demand_miss_latency::cpu2.data 8705062 # number of demand (read+write) miss cycles 1623system.cpu2.dcache.demand_miss_latency::total 8705062 # number of demand (read+write) miss cycles 1624system.cpu2.dcache.overall_miss_latency::cpu2.data 8705062 # number of overall miss cycles 1625system.cpu2.dcache.overall_miss_latency::total 8705062 # number of overall miss cycles 1626system.cpu2.dcache.ReadReq_accesses::cpu2.data 45893 # number of ReadReq accesses(hits+misses) 1627system.cpu2.dcache.ReadReq_accesses::total 45893 # number of ReadReq accesses(hits+misses) 1628system.cpu2.dcache.WriteReq_accesses::cpu2.data 36030 # number of WriteReq accesses(hits+misses) 1629system.cpu2.dcache.WriteReq_accesses::total 36030 # number of WriteReq accesses(hits+misses) 1630system.cpu2.dcache.SwapReq_accesses::cpu2.data 69 # number of SwapReq accesses(hits+misses) 1631system.cpu2.dcache.SwapReq_accesses::total 69 # number of SwapReq accesses(hits+misses) 1632system.cpu2.dcache.demand_accesses::cpu2.data 81923 # number of demand (read+write) accesses 1633system.cpu2.dcache.demand_accesses::total 81923 # number of demand (read+write) accesses 1634system.cpu2.dcache.overall_accesses::cpu2.data 81923 # number of overall (read+write) accesses 1635system.cpu2.dcache.overall_accesses::total 81923 # number of overall (read+write) accesses 1636system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.007496 # miss rate for ReadReq accesses 1637system.cpu2.dcache.ReadReq_miss_rate::total 0.007496 # miss rate for ReadReq accesses 1638system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.003969 # miss rate for WriteReq accesses 1639system.cpu2.dcache.WriteReq_miss_rate::total 0.003969 # miss rate for WriteReq accesses 1640system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.826087 # miss rate for SwapReq accesses 1641system.cpu2.dcache.SwapReq_miss_rate::total 0.826087 # miss rate for SwapReq accesses 1642system.cpu2.dcache.demand_miss_rate::cpu2.data 0.005945 # miss rate for demand accesses 1643system.cpu2.dcache.demand_miss_rate::total 0.005945 # miss rate for demand accesses 1644system.cpu2.dcache.overall_miss_rate::cpu2.data 0.005945 # miss rate for overall accesses 1645system.cpu2.dcache.overall_miss_rate::total 0.005945 # miss rate for overall accesses 1646system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 16278.494186 # average ReadReq miss latency 1647system.cpu2.dcache.ReadReq_avg_miss_latency::total 16278.494186 # average ReadReq miss latency 1648system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 21715.104895 # average WriteReq miss latency 1649system.cpu2.dcache.WriteReq_avg_miss_latency::total 21715.104895 # average WriteReq miss latency 1650system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 10087.842105 # average SwapReq miss latency 1651system.cpu2.dcache.SwapReq_avg_miss_latency::total 10087.842105 # average SwapReq miss latency 1652system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 17874.870637 # average overall miss latency 1653system.cpu2.dcache.demand_avg_miss_latency::total 17874.870637 # average overall miss latency 1654system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 17874.870637 # average overall miss latency 1655system.cpu2.dcache.overall_avg_miss_latency::total 17874.870637 # average overall miss latency 1656system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1657system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1658system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1659system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked 1660system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1661system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1662system.cpu2.dcache.fast_writes 0 # number of fast writes performed 1663system.cpu2.dcache.cache_copies 0 # number of cache copies performed 1664system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 182 # number of ReadReq MSHR hits 1665system.cpu2.dcache.ReadReq_mshr_hits::total 182 # number of ReadReq MSHR hits 1666system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 34 # number of WriteReq MSHR hits 1667system.cpu2.dcache.WriteReq_mshr_hits::total 34 # number of WriteReq MSHR hits 1668system.cpu2.dcache.demand_mshr_hits::cpu2.data 216 # number of demand (read+write) MSHR hits 1669system.cpu2.dcache.demand_mshr_hits::total 216 # number of demand (read+write) MSHR hits 1670system.cpu2.dcache.overall_mshr_hits::cpu2.data 216 # number of overall MSHR hits 1671system.cpu2.dcache.overall_mshr_hits::total 216 # number of overall MSHR hits 1672system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 162 # number of ReadReq MSHR misses 1673system.cpu2.dcache.ReadReq_mshr_misses::total 162 # number of ReadReq MSHR misses 1674system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 109 # number of WriteReq MSHR misses 1675system.cpu2.dcache.WriteReq_mshr_misses::total 109 # number of WriteReq MSHR misses 1676system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 57 # number of SwapReq MSHR misses 1677system.cpu2.dcache.SwapReq_mshr_misses::total 57 # number of SwapReq MSHR misses 1678system.cpu2.dcache.demand_mshr_misses::cpu2.data 271 # number of demand (read+write) MSHR misses 1679system.cpu2.dcache.demand_mshr_misses::total 271 # number of demand (read+write) MSHR misses 1680system.cpu2.dcache.overall_mshr_misses::cpu2.data 271 # number of overall MSHR misses 1681system.cpu2.dcache.overall_mshr_misses::total 271 # number of overall MSHR misses 1682system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1526780 # number of ReadReq MSHR miss cycles 1683system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1526780 # number of ReadReq MSHR miss cycles 1684system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1514240 # number of WriteReq MSHR miss cycles 1685system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1514240 # number of WriteReq MSHR miss cycles 1686system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 460993 # number of SwapReq MSHR miss cycles 1687system.cpu2.dcache.SwapReq_mshr_miss_latency::total 460993 # number of SwapReq MSHR miss cycles 1688system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3041020 # number of demand (read+write) MSHR miss cycles 1689system.cpu2.dcache.demand_mshr_miss_latency::total 3041020 # number of demand (read+write) MSHR miss cycles 1690system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3041020 # number of overall MSHR miss cycles 1691system.cpu2.dcache.overall_mshr_miss_latency::total 3041020 # number of overall MSHR miss cycles 1692system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003530 # mshr miss rate for ReadReq accesses 1693system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003530 # mshr miss rate for ReadReq accesses 1694system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.003025 # mshr miss rate for WriteReq accesses 1695system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.003025 # mshr miss rate for WriteReq accesses 1696system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.826087 # mshr miss rate for SwapReq accesses 1697system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.826087 # mshr miss rate for SwapReq accesses 1698system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.003308 # mshr miss rate for demand accesses 1699system.cpu2.dcache.demand_mshr_miss_rate::total 0.003308 # mshr miss rate for demand accesses 1700system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.003308 # mshr miss rate for overall accesses 1701system.cpu2.dcache.overall_mshr_miss_rate::total 0.003308 # mshr miss rate for overall accesses 1702system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 9424.567901 # average ReadReq mshr miss latency 1703system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 9424.567901 # average ReadReq mshr miss latency 1704system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 13892.110092 # average WriteReq mshr miss latency 1705system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 13892.110092 # average WriteReq mshr miss latency 1706system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 8087.596491 # average SwapReq mshr miss latency 1707system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 8087.596491 # average SwapReq mshr miss latency 1708system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 11221.476015 # average overall mshr miss latency 1709system.cpu2.dcache.demand_avg_mshr_miss_latency::total 11221.476015 # average overall mshr miss latency 1710system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 11221.476015 # average overall mshr miss latency 1711system.cpu2.dcache.overall_avg_mshr_miss_latency::total 11221.476015 # average overall mshr miss latency 1712system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1713system.cpu3.branchPred.lookups 56317 # Number of BP lookups 1714system.cpu3.branchPred.condPredicted 53592 # Number of conditional branches predicted 1715system.cpu3.branchPred.condIncorrect 1257 # Number of conditional branches incorrect 1716system.cpu3.branchPred.BTBLookups 50318 # Number of BTB lookups 1717system.cpu3.branchPred.BTBHits 49441 # Number of BTB hits 1718system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 1719system.cpu3.branchPred.BTBHitPct 98.257085 # BTB Hit Percentage 1720system.cpu3.branchPred.usedRAS 649 # Number of times the RAS was used to get a target. 1721system.cpu3.branchPred.RASInCorrect 232 # Number of incorrect RAS predictions. 1722system.cpu3.numCycles 176970 # number of cpu cycles simulated 1723system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started 1724system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed 1725system.cpu3.fetch.icacheStallCycles 26467 # Number of cycles fetch is stalled on an Icache miss 1726system.cpu3.fetch.Insts 318235 # Number of instructions fetch has processed 1727system.cpu3.fetch.Branches 56317 # Number of branches that fetch encountered 1728system.cpu3.fetch.predictedBranches 50090 # Number of branches that fetch has predicted taken 1729system.cpu3.fetch.Cycles 110248 # Number of cycles fetch has run and was not squashing or blocked 1730system.cpu3.fetch.SquashCycles 3629 # Number of cycles fetch has spent squashing 1731system.cpu3.fetch.BlockedCycles 28039 # Number of cycles fetch has spent blocked 1732system.cpu3.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 1733system.cpu3.fetch.NoActiveThreadStallCycles 7739 # Number of stall cycles due to no active thread to fetch from 1734system.cpu3.fetch.PendingTrapStallCycles 790 # Number of stall cycles due to pending traps 1735system.cpu3.fetch.CacheLines 18199 # Number of cache lines fetched 1736system.cpu3.fetch.IcacheSquashes 258 # Number of outstanding Icache misses that were squashed 1737system.cpu3.fetch.rateDist::samples 175582 # Number of instructions fetched each cycle (Total) 1738system.cpu3.fetch.rateDist::mean 1.812458 # Number of instructions fetched each cycle (Total) 1739system.cpu3.fetch.rateDist::stdev 2.180606 # Number of instructions fetched each cycle (Total) 1740system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 1741system.cpu3.fetch.rateDist::0 65334 37.21% 37.21% # Number of instructions fetched each cycle (Total) 1742system.cpu3.fetch.rateDist::1 55610 31.67% 68.88% # Number of instructions fetched each cycle (Total) 1743system.cpu3.fetch.rateDist::2 5389 3.07% 71.95% # Number of instructions fetched each cycle (Total) 1744system.cpu3.fetch.rateDist::3 3177 1.81% 73.76% # Number of instructions fetched each cycle (Total) 1745system.cpu3.fetch.rateDist::4 669 0.38% 74.14% # Number of instructions fetched each cycle (Total) 1746system.cpu3.fetch.rateDist::5 40119 22.85% 96.99% # Number of instructions fetched each cycle (Total) 1747system.cpu3.fetch.rateDist::6 1237 0.70% 97.70% # Number of instructions fetched each cycle (Total) 1748system.cpu3.fetch.rateDist::7 753 0.43% 98.12% # Number of instructions fetched each cycle (Total) 1749system.cpu3.fetch.rateDist::8 3294 1.88% 100.00% # Number of instructions fetched each cycle (Total) 1750system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 1751system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1752system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 1753system.cpu3.fetch.rateDist::total 175582 # Number of instructions fetched each cycle (Total) 1754system.cpu3.fetch.branchRate 0.318229 # Number of branch fetches per cycle 1755system.cpu3.fetch.rate 1.798243 # Number of inst fetches per cycle 1756system.cpu3.decode.IdleCycles 31057 # Number of cycles decode is idle 1757system.cpu3.decode.BlockedCycles 25106 # Number of cycles decode is blocked 1758system.cpu3.decode.RunCycles 104911 # Number of cycles decode is running 1759system.cpu3.decode.UnblockCycles 4475 # Number of cycles decode is unblocking 1760system.cpu3.decode.SquashCycles 2294 # Number of cycles decode is squashing 1761system.cpu3.decode.DecodedInsts 314540 # Number of instructions handled by decode 1762system.cpu3.rename.SquashCycles 2294 # Number of cycles rename is squashing 1763system.cpu3.rename.IdleCycles 31713 # Number of cycles rename is idle 1764system.cpu3.rename.BlockCycles 12844 # Number of cycles rename is blocking 1765system.cpu3.rename.serializeStallCycles 11527 # count of cycles rename stalled for serializing inst 1766system.cpu3.rename.RunCycles 100723 # Number of cycles rename is running 1767system.cpu3.rename.UnblockCycles 8742 # Number of cycles rename is unblocking 1768system.cpu3.rename.RenamedInsts 312369 # Number of instructions processed by rename 1769system.cpu3.rename.IQFullEvents 1 # Number of times rename has blocked due to IQ full 1770system.cpu3.rename.LSQFullEvents 22 # Number of times rename has blocked due to LSQ full 1771system.cpu3.rename.RenamedOperands 219058 # Number of destination operands rename has renamed 1772system.cpu3.rename.RenameLookups 604346 # Number of register rename lookups that rename has made 1773system.cpu3.rename.int_rename_lookups 604346 # Number of integer rename lookups 1774system.cpu3.rename.CommittedMaps 206290 # Number of HB maps that are committed 1775system.cpu3.rename.UndoneMaps 12768 # Number of HB maps that are undone due to squashing 1776system.cpu3.rename.serializingInsts 1082 # count of serializing insts renamed 1777system.cpu3.rename.tempSerializingInsts 1202 # count of temporary serializing insts renamed 1778system.cpu3.rename.skidInsts 11332 # count of insts added to the skid buffer 1779system.cpu3.memDep0.insertedLoads 90084 # Number of loads inserted to the mem dependence unit. 1780system.cpu3.memDep0.insertedStores 43367 # Number of stores inserted to the mem dependence unit. 1781system.cpu3.memDep0.conflictingLoads 42837 # Number of conflicting loads. 1782system.cpu3.memDep0.conflictingStores 38342 # Number of conflicting stores. 1783system.cpu3.iq.iqInstsAdded 260031 # Number of instructions added to the IQ (excludes non-spec) 1784system.cpu3.iq.iqNonSpecInstsAdded 5573 # Number of non-speculative instructions added to the IQ 1785system.cpu3.iq.iqInstsIssued 261645 # Number of instructions issued 1786system.cpu3.iq.iqSquashedInstsIssued 62 # Number of squashed instructions issued 1787system.cpu3.iq.iqSquashedInstsExamined 10424 # Number of squashed instructions iterated over during squash; mainly for profiling 1788system.cpu3.iq.iqSquashedOperandsExamined 10297 # Number of squashed operands that are examined and possibly removed from graph 1789system.cpu3.iq.iqSquashedNonSpecRemoved 498 # Number of squashed non-spec instructions that were removed 1790system.cpu3.iq.issued_per_cycle::samples 175582 # Number of insts issued each cycle 1791system.cpu3.iq.issued_per_cycle::mean 1.490158 # Number of insts issued each cycle 1792system.cpu3.iq.issued_per_cycle::stdev 1.307816 # Number of insts issued each cycle 1793system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 1794system.cpu3.iq.issued_per_cycle::0 62519 35.61% 35.61% # Number of insts issued each cycle 1795system.cpu3.iq.issued_per_cycle::1 20435 11.64% 47.25% # Number of insts issued each cycle 1796system.cpu3.iq.issued_per_cycle::2 43580 24.82% 72.07% # Number of insts issued each cycle 1797system.cpu3.iq.issued_per_cycle::3 44218 25.18% 97.25% # Number of insts issued each cycle 1798system.cpu3.iq.issued_per_cycle::4 3288 1.87% 99.12% # Number of insts issued each cycle 1799system.cpu3.iq.issued_per_cycle::5 1176 0.67% 99.79% # Number of insts issued each cycle 1800system.cpu3.iq.issued_per_cycle::6 257 0.15% 99.94% # Number of insts issued each cycle 1801system.cpu3.iq.issued_per_cycle::7 50 0.03% 99.97% # Number of insts issued each cycle 1802system.cpu3.iq.issued_per_cycle::8 59 0.03% 100.00% # Number of insts issued each cycle 1803system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1804system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1805system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 1806system.cpu3.iq.issued_per_cycle::total 175582 # Number of insts issued each cycle 1807system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 1808system.cpu3.iq.fu_full::IntAlu 17 6.25% 6.25% # attempts to use FU when none available 1809system.cpu3.iq.fu_full::IntMult 0 0.00% 6.25% # attempts to use FU when none available 1810system.cpu3.iq.fu_full::IntDiv 0 0.00% 6.25% # attempts to use FU when none available 1811system.cpu3.iq.fu_full::FloatAdd 0 0.00% 6.25% # attempts to use FU when none available 1812system.cpu3.iq.fu_full::FloatCmp 0 0.00% 6.25% # attempts to use FU when none available 1813system.cpu3.iq.fu_full::FloatCvt 0 0.00% 6.25% # attempts to use FU when none available 1814system.cpu3.iq.fu_full::FloatMult 0 0.00% 6.25% # attempts to use FU when none available 1815system.cpu3.iq.fu_full::FloatDiv 0 0.00% 6.25% # attempts to use FU when none available 1816system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 6.25% # attempts to use FU when none available 1817system.cpu3.iq.fu_full::SimdAdd 0 0.00% 6.25% # attempts to use FU when none available 1818system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 6.25% # attempts to use FU when none available 1819system.cpu3.iq.fu_full::SimdAlu 0 0.00% 6.25% # attempts to use FU when none available 1820system.cpu3.iq.fu_full::SimdCmp 0 0.00% 6.25% # attempts to use FU when none available 1821system.cpu3.iq.fu_full::SimdCvt 0 0.00% 6.25% # attempts to use FU when none available 1822system.cpu3.iq.fu_full::SimdMisc 0 0.00% 6.25% # attempts to use FU when none available 1823system.cpu3.iq.fu_full::SimdMult 0 0.00% 6.25% # attempts to use FU when none available 1824system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 6.25% # attempts to use FU when none available 1825system.cpu3.iq.fu_full::SimdShift 0 0.00% 6.25% # attempts to use FU when none available 1826system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 6.25% # attempts to use FU when none available 1827system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 6.25% # attempts to use FU when none available 1828system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 6.25% # attempts to use FU when none available 1829system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 6.25% # attempts to use FU when none available 1830system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 6.25% # attempts to use FU when none available 1831system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 6.25% # attempts to use FU when none available 1832system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 6.25% # attempts to use FU when none available 1833system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 6.25% # attempts to use FU when none available 1834system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 6.25% # attempts to use FU when none available 1835system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.25% # attempts to use FU when none available 1836system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 6.25% # attempts to use FU when none available 1837system.cpu3.iq.fu_full::MemRead 45 16.54% 22.79% # attempts to use FU when none available 1838system.cpu3.iq.fu_full::MemWrite 210 77.21% 100.00% # attempts to use FU when none available 1839system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 1840system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 1841system.cpu3.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 1842system.cpu3.iq.FU_type_0::IntAlu 125105 47.81% 47.81% # Type of FU issued 1843system.cpu3.iq.FU_type_0::IntMult 0 0.00% 47.81% # Type of FU issued 1844system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 47.81% # Type of FU issued 1845system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 47.81% # Type of FU issued 1846system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 47.81% # Type of FU issued 1847system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 47.81% # Type of FU issued 1848system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 47.81% # Type of FU issued 1849system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 47.81% # Type of FU issued 1850system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 47.81% # Type of FU issued 1851system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 47.81% # Type of FU issued 1852system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 47.81% # Type of FU issued 1853system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 47.81% # Type of FU issued 1854system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 47.81% # Type of FU issued 1855system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 47.81% # Type of FU issued 1856system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 47.81% # Type of FU issued 1857system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 47.81% # Type of FU issued 1858system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 47.81% # Type of FU issued 1859system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 47.81% # Type of FU issued 1860system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 47.81% # Type of FU issued 1861system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 47.81% # Type of FU issued 1862system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.81% # Type of FU issued 1863system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.81% # Type of FU issued 1864system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.81% # Type of FU issued 1865system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.81% # Type of FU issued 1866system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.81% # Type of FU issued 1867system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 47.81% # Type of FU issued 1868system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 47.81% # Type of FU issued 1869system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.81% # Type of FU issued 1870system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.81% # Type of FU issued 1871system.cpu3.iq.FU_type_0::MemRead 93850 35.87% 83.68% # Type of FU issued 1872system.cpu3.iq.FU_type_0::MemWrite 42690 16.32% 100.00% # Type of FU issued 1873system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 1874system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 1875system.cpu3.iq.FU_type_0::total 261645 # Type of FU issued 1876system.cpu3.iq.rate 1.478471 # Inst issue rate 1877system.cpu3.iq.fu_busy_cnt 272 # FU busy when requested 1878system.cpu3.iq.fu_busy_rate 0.001040 # FU busy rate (busy events/executed inst) 1879system.cpu3.iq.int_inst_queue_reads 699206 # Number of integer instruction queue reads 1880system.cpu3.iq.int_inst_queue_writes 276071 # Number of integer instruction queue writes 1881system.cpu3.iq.int_inst_queue_wakeup_accesses 259793 # Number of integer instruction queue wakeup accesses 1882system.cpu3.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads 1883system.cpu3.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes 1884system.cpu3.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses 1885system.cpu3.iq.int_alu_accesses 261917 # Number of integer alu accesses 1886system.cpu3.iq.fp_alu_accesses 0 # Number of floating point alu accesses 1887system.cpu3.iew.lsq.thread0.forwLoads 38112 # Number of loads that had data forwarded from stores 1888system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 1889system.cpu3.iew.lsq.thread0.squashedLoads 2309 # Number of loads squashed 1890system.cpu3.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed 1891system.cpu3.iew.lsq.thread0.memOrderViolation 43 # Number of memory ordering violations 1892system.cpu3.iew.lsq.thread0.squashedStores 1414 # Number of stores squashed 1893system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 1894system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 1895system.cpu3.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 1896system.cpu3.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked 1897system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle 1898system.cpu3.iew.iewSquashCycles 2294 # Number of cycles IEW is squashing 1899system.cpu3.iew.iewBlockCycles 580 # Number of cycles IEW is blocking 1900system.cpu3.iew.iewUnblockCycles 36 # Number of cycles IEW is unblocking 1901system.cpu3.iew.iewDispatchedInsts 309373 # Number of instructions dispatched to IQ 1902system.cpu3.iew.iewDispSquashedInsts 369 # Number of squashed instructions skipped by dispatch 1903system.cpu3.iew.iewDispLoadInsts 90084 # Number of dispatched load instructions 1904system.cpu3.iew.iewDispStoreInsts 43367 # Number of dispatched store instructions 1905system.cpu3.iew.iewDispNonSpecInsts 1034 # Number of dispatched non-speculative instructions 1906system.cpu3.iew.iewIQFullEvents 36 # Number of times the IQ has become full, causing a stall 1907system.cpu3.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 1908system.cpu3.iew.memOrderViolationEvents 43 # Number of memory order violations 1909system.cpu3.iew.predictedTakenIncorrect 465 # Number of branches that were predicted taken incorrectly 1910system.cpu3.iew.predictedNotTakenIncorrect 904 # Number of branches that were predicted not taken incorrectly 1911system.cpu3.iew.branchMispredicts 1369 # Number of branch mispredicts detected at execute 1912system.cpu3.iew.iewExecutedInsts 260458 # Number of executed instructions 1913system.cpu3.iew.iewExecLoadInsts 89199 # Number of load instructions executed 1914system.cpu3.iew.iewExecSquashedInsts 1187 # Number of squashed instructions skipped in execute 1915system.cpu3.iew.exec_swp 0 # number of swp insts executed 1916system.cpu3.iew.exec_nop 43769 # number of nop insts executed 1917system.cpu3.iew.exec_refs 131812 # number of memory reference insts executed 1918system.cpu3.iew.exec_branches 53091 # Number of branches executed 1919system.cpu3.iew.exec_stores 42613 # Number of stores executed 1920system.cpu3.iew.exec_rate 1.471764 # Inst execution rate 1921system.cpu3.iew.wb_sent 260118 # cumulative count of insts sent to commit 1922system.cpu3.iew.wb_count 259793 # cumulative count of insts written-back 1923system.cpu3.iew.wb_producers 148532 # num instructions producing a value 1924system.cpu3.iew.wb_consumers 153197 # num instructions consuming a value 1925system.cpu3.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 1926system.cpu3.iew.wb_rate 1.468006 # insts written-back per cycle 1927system.cpu3.iew.wb_fanout 0.969549 # average fanout of values written-back 1928system.cpu3.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 1929system.cpu3.commit.commitSquashedInsts 11915 # The number of squashed insts skipped by commit 1930system.cpu3.commit.commitNonSpecStalls 5075 # The number of times commit has been forced to stall to communicate backwards 1931system.cpu3.commit.branchMispredicts 1257 # The number of times a branch was mispredicted 1932system.cpu3.commit.committed_per_cycle::samples 165549 # Number of insts commited each cycle 1933system.cpu3.commit.committed_per_cycle::mean 1.796677 # Number of insts commited each cycle 1934system.cpu3.commit.committed_per_cycle::stdev 2.064793 # Number of insts commited each cycle 1935system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 1936system.cpu3.commit.committed_per_cycle::0 59727 36.08% 36.08% # Number of insts commited each cycle 1937system.cpu3.commit.committed_per_cycle::1 51190 30.92% 67.00% # Number of insts commited each cycle 1938system.cpu3.commit.committed_per_cycle::2 6085 3.68% 70.68% # Number of insts commited each cycle 1939system.cpu3.commit.committed_per_cycle::3 6030 3.64% 74.32% # Number of insts commited each cycle 1940system.cpu3.commit.committed_per_cycle::4 1572 0.95% 75.27% # Number of insts commited each cycle 1941system.cpu3.commit.committed_per_cycle::5 38600 23.32% 98.58% # Number of insts commited each cycle 1942system.cpu3.commit.committed_per_cycle::6 530 0.32% 98.90% # Number of insts commited each cycle 1943system.cpu3.commit.committed_per_cycle::7 1000 0.60% 99.51% # Number of insts commited each cycle 1944system.cpu3.commit.committed_per_cycle::8 815 0.49% 100.00% # Number of insts commited each cycle 1945system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 1946system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 1947system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 1948system.cpu3.commit.committed_per_cycle::total 165549 # Number of insts commited each cycle 1949system.cpu3.commit.committedInsts 297438 # Number of instructions committed 1950system.cpu3.commit.committedOps 297438 # Number of ops (including micro ops) committed 1951system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed 1952system.cpu3.commit.refs 129728 # Number of memory references committed 1953system.cpu3.commit.loads 87775 # Number of loads committed 1954system.cpu3.commit.membars 4366 # Number of memory barriers committed 1955system.cpu3.commit.branches 52284 # Number of branches committed 1956system.cpu3.commit.fp_insts 0 # Number of committed floating point instructions. 1957system.cpu3.commit.int_insts 204138 # Number of committed integer instructions. 1958system.cpu3.commit.function_calls 322 # Number of function calls committed. 1959system.cpu3.commit.bw_lim_events 815 # number cycles where commit BW limit reached 1960system.cpu3.commit.bw_limited 0 # number of insts not committed due to BW limits 1961system.cpu3.rob.rob_reads 473500 # The number of ROB reads 1962system.cpu3.rob.rob_writes 621006 # The number of ROB writes 1963system.cpu3.timesIdled 209 # Number of times that the entire CPU went into an idle state and unscheduled itself 1964system.cpu3.idleCycles 1388 # Total number of cycles that the CPU has spent unscheduled due to idling 1965system.cpu3.quiesceCycles 44638 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1966system.cpu3.committedInsts 249993 # Number of Instructions Simulated 1967system.cpu3.committedOps 249993 # Number of Ops (including micro ops) Simulated 1968system.cpu3.committedInsts_total 249993 # Number of Instructions Simulated 1969system.cpu3.cpi 0.707900 # CPI: Cycles Per Instruction 1970system.cpu3.cpi_total 0.707900 # CPI: Total CPI of All Threads 1971system.cpu3.ipc 1.412629 # IPC: Instructions Per Cycle 1972system.cpu3.ipc_total 1.412629 # IPC: Total IPC of All Threads 1973system.cpu3.int_regfile_reads 453881 # number of integer regfile reads 1974system.cpu3.int_regfile_writes 211087 # number of integer regfile writes 1975system.cpu3.fp_regfile_writes 64 # number of floating regfile writes 1976system.cpu3.misc_regfile_reads 133368 # number of misc regfile reads 1977system.cpu3.misc_regfile_writes 648 # number of misc regfile writes 1978system.cpu3.icache.tags.replacements 319 # number of replacements 1979system.cpu3.icache.tags.tagsinuse 77.348761 # Cycle average of tags in use 1980system.cpu3.icache.tags.total_refs 17724 # Total number of references to valid blocks. 1981system.cpu3.icache.tags.sampled_refs 430 # Sample count of references to valid blocks. 1982system.cpu3.icache.tags.avg_refs 41.218605 # Average number of references to valid blocks. 1983system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1984system.cpu3.icache.tags.occ_blocks::cpu3.inst 77.348761 # Average occupied blocks per requestor 1985system.cpu3.icache.tags.occ_percent::cpu3.inst 0.151072 # Average percentage of cache occupancy 1986system.cpu3.icache.tags.occ_percent::total 0.151072 # Average percentage of cache occupancy 1987system.cpu3.icache.ReadReq_hits::cpu3.inst 17724 # number of ReadReq hits 1988system.cpu3.icache.ReadReq_hits::total 17724 # number of ReadReq hits 1989system.cpu3.icache.demand_hits::cpu3.inst 17724 # number of demand (read+write) hits 1990system.cpu3.icache.demand_hits::total 17724 # number of demand (read+write) hits 1991system.cpu3.icache.overall_hits::cpu3.inst 17724 # number of overall hits 1992system.cpu3.icache.overall_hits::total 17724 # number of overall hits 1993system.cpu3.icache.ReadReq_misses::cpu3.inst 475 # number of ReadReq misses 1994system.cpu3.icache.ReadReq_misses::total 475 # number of ReadReq misses 1995system.cpu3.icache.demand_misses::cpu3.inst 475 # number of demand (read+write) misses 1996system.cpu3.icache.demand_misses::total 475 # number of demand (read+write) misses 1997system.cpu3.icache.overall_misses::cpu3.inst 475 # number of overall misses 1998system.cpu3.icache.overall_misses::total 475 # number of overall misses 1999system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 6467995 # number of ReadReq miss cycles 2000system.cpu3.icache.ReadReq_miss_latency::total 6467995 # number of ReadReq miss cycles 2001system.cpu3.icache.demand_miss_latency::cpu3.inst 6467995 # number of demand (read+write) miss cycles 2002system.cpu3.icache.demand_miss_latency::total 6467995 # number of demand (read+write) miss cycles 2003system.cpu3.icache.overall_miss_latency::cpu3.inst 6467995 # number of overall miss cycles 2004system.cpu3.icache.overall_miss_latency::total 6467995 # number of overall miss cycles 2005system.cpu3.icache.ReadReq_accesses::cpu3.inst 18199 # number of ReadReq accesses(hits+misses) 2006system.cpu3.icache.ReadReq_accesses::total 18199 # number of ReadReq accesses(hits+misses) 2007system.cpu3.icache.demand_accesses::cpu3.inst 18199 # number of demand (read+write) accesses 2008system.cpu3.icache.demand_accesses::total 18199 # number of demand (read+write) accesses 2009system.cpu3.icache.overall_accesses::cpu3.inst 18199 # number of overall (read+write) accesses 2010system.cpu3.icache.overall_accesses::total 18199 # number of overall (read+write) accesses 2011system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.026100 # miss rate for ReadReq accesses 2012system.cpu3.icache.ReadReq_miss_rate::total 0.026100 # miss rate for ReadReq accesses 2013system.cpu3.icache.demand_miss_rate::cpu3.inst 0.026100 # miss rate for demand accesses 2014system.cpu3.icache.demand_miss_rate::total 0.026100 # miss rate for demand accesses 2015system.cpu3.icache.overall_miss_rate::cpu3.inst 0.026100 # miss rate for overall accesses 2016system.cpu3.icache.overall_miss_rate::total 0.026100 # miss rate for overall accesses 2017system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13616.831579 # average ReadReq miss latency 2018system.cpu3.icache.ReadReq_avg_miss_latency::total 13616.831579 # average ReadReq miss latency 2019system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13616.831579 # average overall miss latency 2020system.cpu3.icache.demand_avg_miss_latency::total 13616.831579 # average overall miss latency 2021system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13616.831579 # average overall miss latency 2022system.cpu3.icache.overall_avg_miss_latency::total 13616.831579 # average overall miss latency 2023system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2024system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2025system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked 2026system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked 2027system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2028system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2029system.cpu3.icache.fast_writes 0 # number of fast writes performed 2030system.cpu3.icache.cache_copies 0 # number of cache copies performed 2031system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 45 # number of ReadReq MSHR hits 2032system.cpu3.icache.ReadReq_mshr_hits::total 45 # number of ReadReq MSHR hits 2033system.cpu3.icache.demand_mshr_hits::cpu3.inst 45 # number of demand (read+write) MSHR hits 2034system.cpu3.icache.demand_mshr_hits::total 45 # number of demand (read+write) MSHR hits 2035system.cpu3.icache.overall_mshr_hits::cpu3.inst 45 # number of overall MSHR hits 2036system.cpu3.icache.overall_mshr_hits::total 45 # number of overall MSHR hits 2037system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 430 # number of ReadReq MSHR misses 2038system.cpu3.icache.ReadReq_mshr_misses::total 430 # number of ReadReq MSHR misses 2039system.cpu3.icache.demand_mshr_misses::cpu3.inst 430 # number of demand (read+write) MSHR misses 2040system.cpu3.icache.demand_mshr_misses::total 430 # number of demand (read+write) MSHR misses 2041system.cpu3.icache.overall_mshr_misses::cpu3.inst 430 # number of overall MSHR misses 2042system.cpu3.icache.overall_mshr_misses::total 430 # number of overall MSHR misses 2043system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 5219755 # number of ReadReq MSHR miss cycles 2044system.cpu3.icache.ReadReq_mshr_miss_latency::total 5219755 # number of ReadReq MSHR miss cycles 2045system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 5219755 # number of demand (read+write) MSHR miss cycles 2046system.cpu3.icache.demand_mshr_miss_latency::total 5219755 # number of demand (read+write) MSHR miss cycles 2047system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 5219755 # number of overall MSHR miss cycles 2048system.cpu3.icache.overall_mshr_miss_latency::total 5219755 # number of overall MSHR miss cycles 2049system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.023628 # mshr miss rate for ReadReq accesses 2050system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.023628 # mshr miss rate for ReadReq accesses 2051system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.023628 # mshr miss rate for demand accesses 2052system.cpu3.icache.demand_mshr_miss_rate::total 0.023628 # mshr miss rate for demand accesses 2053system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.023628 # mshr miss rate for overall accesses 2054system.cpu3.icache.overall_mshr_miss_rate::total 0.023628 # mshr miss rate for overall accesses 2055system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12138.965116 # average ReadReq mshr miss latency 2056system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 12138.965116 # average ReadReq mshr miss latency 2057system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12138.965116 # average overall mshr miss latency 2058system.cpu3.icache.demand_avg_mshr_miss_latency::total 12138.965116 # average overall mshr miss latency 2059system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12138.965116 # average overall mshr miss latency 2060system.cpu3.icache.overall_avg_mshr_miss_latency::total 12138.965116 # average overall mshr miss latency 2061system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate 2062system.cpu3.dcache.tags.replacements 0 # number of replacements 2063system.cpu3.dcache.tags.tagsinuse 23.659946 # Cycle average of tags in use 2064system.cpu3.dcache.tags.total_refs 47957 # Total number of references to valid blocks. 2065system.cpu3.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks. 2066system.cpu3.dcache.tags.avg_refs 1712.750000 # Average number of references to valid blocks. 2067system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 2068system.cpu3.dcache.tags.occ_blocks::cpu3.data 23.659946 # Average occupied blocks per requestor 2069system.cpu3.dcache.tags.occ_percent::cpu3.data 0.046211 # Average percentage of cache occupancy 2070system.cpu3.dcache.tags.occ_percent::total 0.046211 # Average percentage of cache occupancy 2071system.cpu3.dcache.ReadReq_hits::cpu3.data 50723 # number of ReadReq hits 2072system.cpu3.dcache.ReadReq_hits::total 50723 # number of ReadReq hits 2073system.cpu3.dcache.WriteReq_hits::cpu3.data 41752 # number of WriteReq hits 2074system.cpu3.dcache.WriteReq_hits::total 41752 # number of WriteReq hits 2075system.cpu3.dcache.SwapReq_hits::cpu3.data 12 # number of SwapReq hits 2076system.cpu3.dcache.SwapReq_hits::total 12 # number of SwapReq hits 2077system.cpu3.dcache.demand_hits::cpu3.data 92475 # number of demand (read+write) hits 2078system.cpu3.dcache.demand_hits::total 92475 # number of demand (read+write) hits 2079system.cpu3.dcache.overall_hits::cpu3.data 92475 # number of overall hits 2080system.cpu3.dcache.overall_hits::total 92475 # number of overall hits 2081system.cpu3.dcache.ReadReq_misses::cpu3.data 346 # number of ReadReq misses 2082system.cpu3.dcache.ReadReq_misses::total 346 # number of ReadReq misses 2083system.cpu3.dcache.WriteReq_misses::cpu3.data 138 # number of WriteReq misses 2084system.cpu3.dcache.WriteReq_misses::total 138 # number of WriteReq misses 2085system.cpu3.dcache.SwapReq_misses::cpu3.data 51 # number of SwapReq misses 2086system.cpu3.dcache.SwapReq_misses::total 51 # number of SwapReq misses 2087system.cpu3.dcache.demand_misses::cpu3.data 484 # number of demand (read+write) misses 2088system.cpu3.dcache.demand_misses::total 484 # number of demand (read+write) misses 2089system.cpu3.dcache.overall_misses::cpu3.data 484 # number of overall misses 2090system.cpu3.dcache.overall_misses::total 484 # number of overall misses 2091system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 4449419 # number of ReadReq miss cycles 2092system.cpu3.dcache.ReadReq_miss_latency::total 4449419 # number of ReadReq miss cycles 2093system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 2879011 # number of WriteReq miss cycles 2094system.cpu3.dcache.WriteReq_miss_latency::total 2879011 # number of WriteReq miss cycles 2095system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 478509 # number of SwapReq miss cycles 2096system.cpu3.dcache.SwapReq_miss_latency::total 478509 # number of SwapReq miss cycles 2097system.cpu3.dcache.demand_miss_latency::cpu3.data 7328430 # number of demand (read+write) miss cycles 2098system.cpu3.dcache.demand_miss_latency::total 7328430 # number of demand (read+write) miss cycles 2099system.cpu3.dcache.overall_miss_latency::cpu3.data 7328430 # number of overall miss cycles 2100system.cpu3.dcache.overall_miss_latency::total 7328430 # number of overall miss cycles 2101system.cpu3.dcache.ReadReq_accesses::cpu3.data 51069 # number of ReadReq accesses(hits+misses) 2102system.cpu3.dcache.ReadReq_accesses::total 51069 # number of ReadReq accesses(hits+misses) 2103system.cpu3.dcache.WriteReq_accesses::cpu3.data 41890 # number of WriteReq accesses(hits+misses) 2104system.cpu3.dcache.WriteReq_accesses::total 41890 # number of WriteReq accesses(hits+misses) 2105system.cpu3.dcache.SwapReq_accesses::cpu3.data 63 # number of SwapReq accesses(hits+misses) 2106system.cpu3.dcache.SwapReq_accesses::total 63 # number of SwapReq accesses(hits+misses) 2107system.cpu3.dcache.demand_accesses::cpu3.data 92959 # number of demand (read+write) accesses 2108system.cpu3.dcache.demand_accesses::total 92959 # number of demand (read+write) accesses 2109system.cpu3.dcache.overall_accesses::cpu3.data 92959 # number of overall (read+write) accesses 2110system.cpu3.dcache.overall_accesses::total 92959 # number of overall (read+write) accesses 2111system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.006775 # miss rate for ReadReq accesses 2112system.cpu3.dcache.ReadReq_miss_rate::total 0.006775 # miss rate for ReadReq accesses 2113system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.003294 # miss rate for WriteReq accesses 2114system.cpu3.dcache.WriteReq_miss_rate::total 0.003294 # miss rate for WriteReq accesses 2115system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.809524 # miss rate for SwapReq accesses 2116system.cpu3.dcache.SwapReq_miss_rate::total 0.809524 # miss rate for SwapReq accesses 2117system.cpu3.dcache.demand_miss_rate::cpu3.data 0.005207 # miss rate for demand accesses 2118system.cpu3.dcache.demand_miss_rate::total 0.005207 # miss rate for demand accesses 2119system.cpu3.dcache.overall_miss_rate::cpu3.data 0.005207 # miss rate for overall accesses 2120system.cpu3.dcache.overall_miss_rate::total 0.005207 # miss rate for overall accesses 2121system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 12859.592486 # average ReadReq miss latency 2122system.cpu3.dcache.ReadReq_avg_miss_latency::total 12859.592486 # average ReadReq miss latency 2123system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 20862.398551 # average WriteReq miss latency 2124system.cpu3.dcache.WriteReq_avg_miss_latency::total 20862.398551 # average WriteReq miss latency 2125system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 9382.529412 # average SwapReq miss latency 2126system.cpu3.dcache.SwapReq_avg_miss_latency::total 9382.529412 # average SwapReq miss latency 2127system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 15141.384298 # average overall miss latency 2128system.cpu3.dcache.demand_avg_miss_latency::total 15141.384298 # average overall miss latency 2129system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 15141.384298 # average overall miss latency 2130system.cpu3.dcache.overall_avg_miss_latency::total 15141.384298 # average overall miss latency 2131system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2132system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2133system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 2134system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked 2135system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2136system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2137system.cpu3.dcache.fast_writes 0 # number of fast writes performed 2138system.cpu3.dcache.cache_copies 0 # number of cache copies performed 2139system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 195 # number of ReadReq MSHR hits 2140system.cpu3.dcache.ReadReq_mshr_hits::total 195 # number of ReadReq MSHR hits 2141system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 32 # number of WriteReq MSHR hits 2142system.cpu3.dcache.WriteReq_mshr_hits::total 32 # number of WriteReq MSHR hits 2143system.cpu3.dcache.demand_mshr_hits::cpu3.data 227 # number of demand (read+write) MSHR hits 2144system.cpu3.dcache.demand_mshr_hits::total 227 # number of demand (read+write) MSHR hits 2145system.cpu3.dcache.overall_mshr_hits::cpu3.data 227 # number of overall MSHR hits 2146system.cpu3.dcache.overall_mshr_hits::total 227 # number of overall MSHR hits 2147system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 151 # number of ReadReq MSHR misses 2148system.cpu3.dcache.ReadReq_mshr_misses::total 151 # number of ReadReq MSHR misses 2149system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 106 # number of WriteReq MSHR misses 2150system.cpu3.dcache.WriteReq_mshr_misses::total 106 # number of WriteReq MSHR misses 2151system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 51 # number of SwapReq MSHR misses 2152system.cpu3.dcache.SwapReq_mshr_misses::total 51 # number of SwapReq MSHR misses 2153system.cpu3.dcache.demand_mshr_misses::cpu3.data 257 # number of demand (read+write) MSHR misses 2154system.cpu3.dcache.demand_mshr_misses::total 257 # number of demand (read+write) MSHR misses 2155system.cpu3.dcache.overall_mshr_misses::cpu3.data 257 # number of overall MSHR misses 2156system.cpu3.dcache.overall_mshr_misses::total 257 # number of overall MSHR misses 2157system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1003763 # number of ReadReq MSHR miss cycles 2158system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1003763 # number of ReadReq MSHR miss cycles 2159system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1322239 # number of WriteReq MSHR miss cycles 2160system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1322239 # number of WriteReq MSHR miss cycles 2161system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 376491 # number of SwapReq MSHR miss cycles 2162system.cpu3.dcache.SwapReq_mshr_miss_latency::total 376491 # number of SwapReq MSHR miss cycles 2163system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 2326002 # number of demand (read+write) MSHR miss cycles 2164system.cpu3.dcache.demand_mshr_miss_latency::total 2326002 # number of demand (read+write) MSHR miss cycles 2165system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 2326002 # number of overall MSHR miss cycles 2166system.cpu3.dcache.overall_mshr_miss_latency::total 2326002 # number of overall MSHR miss cycles 2167system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.002957 # mshr miss rate for ReadReq accesses 2168system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.002957 # mshr miss rate for ReadReq accesses 2169system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.002530 # mshr miss rate for WriteReq accesses 2170system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.002530 # mshr miss rate for WriteReq accesses 2171system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.809524 # mshr miss rate for SwapReq accesses 2172system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.809524 # mshr miss rate for SwapReq accesses 2173system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.002765 # mshr miss rate for demand accesses 2174system.cpu3.dcache.demand_mshr_miss_rate::total 0.002765 # mshr miss rate for demand accesses 2175system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.002765 # mshr miss rate for overall accesses 2176system.cpu3.dcache.overall_mshr_miss_rate::total 0.002765 # mshr miss rate for overall accesses 2177system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 6647.437086 # average ReadReq mshr miss latency 2178system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 6647.437086 # average ReadReq mshr miss latency 2179system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 12473.952830 # average WriteReq mshr miss latency 2180system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 12473.952830 # average WriteReq mshr miss latency 2181system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 7382.176471 # average SwapReq mshr miss latency 2182system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 7382.176471 # average SwapReq mshr miss latency 2183system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 9050.591440 # average overall mshr miss latency 2184system.cpu3.dcache.demand_avg_mshr_miss_latency::total 9050.591440 # average overall mshr miss latency 2185system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 9050.591440 # average overall mshr miss latency 2186system.cpu3.dcache.overall_avg_mshr_miss_latency::total 9050.591440 # average overall mshr miss latency 2187system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 2188system.l2c.tags.replacements 0 # number of replacements 2189system.l2c.tags.tagsinuse 416.979851 # Cycle average of tags in use 2190system.l2c.tags.total_refs 1443 # Total number of references to valid blocks. 2191system.l2c.tags.sampled_refs 526 # Sample count of references to valid blocks. 2192system.l2c.tags.avg_refs 2.743346 # Average number of references to valid blocks. 2193system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 2194system.l2c.tags.occ_blocks::writebacks 0.800256 # Average occupied blocks per requestor 2195system.l2c.tags.occ_blocks::cpu0.inst 284.888559 # Average occupied blocks per requestor 2196system.l2c.tags.occ_blocks::cpu0.data 58.382327 # Average occupied blocks per requestor 2197system.l2c.tags.occ_blocks::cpu1.inst 7.813679 # Average occupied blocks per requestor 2198system.l2c.tags.occ_blocks::cpu1.data 0.733163 # Average occupied blocks per requestor 2199system.l2c.tags.occ_blocks::cpu2.inst 55.504569 # Average occupied blocks per requestor 2200system.l2c.tags.occ_blocks::cpu2.data 5.417548 # Average occupied blocks per requestor 2201system.l2c.tags.occ_blocks::cpu3.inst 2.743977 # Average occupied blocks per requestor 2202system.l2c.tags.occ_blocks::cpu3.data 0.695773 # Average occupied blocks per requestor 2203system.l2c.tags.occ_percent::writebacks 0.000012 # Average percentage of cache occupancy 2204system.l2c.tags.occ_percent::cpu0.inst 0.004347 # Average percentage of cache occupancy 2205system.l2c.tags.occ_percent::cpu0.data 0.000891 # Average percentage of cache occupancy 2206system.l2c.tags.occ_percent::cpu1.inst 0.000119 # Average percentage of cache occupancy 2207system.l2c.tags.occ_percent::cpu1.data 0.000011 # Average percentage of cache occupancy 2208system.l2c.tags.occ_percent::cpu2.inst 0.000847 # Average percentage of cache occupancy 2209system.l2c.tags.occ_percent::cpu2.data 0.000083 # Average percentage of cache occupancy 2210system.l2c.tags.occ_percent::cpu3.inst 0.000042 # Average percentage of cache occupancy 2211system.l2c.tags.occ_percent::cpu3.data 0.000011 # Average percentage of cache occupancy 2212system.l2c.tags.occ_percent::total 0.006363 # Average percentage of cache occupancy 2213system.l2c.ReadReq_hits::cpu0.inst 229 # number of ReadReq hits 2214system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits 2215system.l2c.ReadReq_hits::cpu1.inst 412 # number of ReadReq hits 2216system.l2c.ReadReq_hits::cpu1.data 11 # number of ReadReq hits 2217system.l2c.ReadReq_hits::cpu2.inst 349 # number of ReadReq hits 2218system.l2c.ReadReq_hits::cpu2.data 5 # number of ReadReq hits 2219system.l2c.ReadReq_hits::cpu3.inst 421 # number of ReadReq hits 2220system.l2c.ReadReq_hits::cpu3.data 11 # number of ReadReq hits 2221system.l2c.ReadReq_hits::total 1443 # number of ReadReq hits 2222system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits 2223system.l2c.Writeback_hits::total 1 # number of Writeback hits 2224system.l2c.UpgradeReq_hits::cpu0.data 3 # number of UpgradeReq hits 2225system.l2c.UpgradeReq_hits::total 3 # number of UpgradeReq hits 2226system.l2c.demand_hits::cpu0.inst 229 # number of demand (read+write) hits 2227system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits 2228system.l2c.demand_hits::cpu1.inst 412 # number of demand (read+write) hits 2229system.l2c.demand_hits::cpu1.data 11 # number of demand (read+write) hits 2230system.l2c.demand_hits::cpu2.inst 349 # number of demand (read+write) hits 2231system.l2c.demand_hits::cpu2.data 5 # number of demand (read+write) hits 2232system.l2c.demand_hits::cpu3.inst 421 # number of demand (read+write) hits 2233system.l2c.demand_hits::cpu3.data 11 # number of demand (read+write) hits 2234system.l2c.demand_hits::total 1443 # number of demand (read+write) hits 2235system.l2c.overall_hits::cpu0.inst 229 # number of overall hits 2236system.l2c.overall_hits::cpu0.data 5 # number of overall hits 2237system.l2c.overall_hits::cpu1.inst 412 # number of overall hits 2238system.l2c.overall_hits::cpu1.data 11 # number of overall hits 2239system.l2c.overall_hits::cpu2.inst 349 # number of overall hits 2240system.l2c.overall_hits::cpu2.data 5 # number of overall hits 2241system.l2c.overall_hits::cpu3.inst 421 # number of overall hits 2242system.l2c.overall_hits::cpu3.data 11 # number of overall hits 2243system.l2c.overall_hits::total 1443 # number of overall hits 2244system.l2c.ReadReq_misses::cpu0.inst 359 # number of ReadReq misses 2245system.l2c.ReadReq_misses::cpu0.data 74 # number of ReadReq misses 2246system.l2c.ReadReq_misses::cpu1.inst 16 # number of ReadReq misses 2247system.l2c.ReadReq_misses::cpu1.data 1 # number of ReadReq misses 2248system.l2c.ReadReq_misses::cpu2.inst 76 # number of ReadReq misses 2249system.l2c.ReadReq_misses::cpu2.data 7 # number of ReadReq misses 2250system.l2c.ReadReq_misses::cpu3.inst 9 # number of ReadReq misses 2251system.l2c.ReadReq_misses::cpu3.data 1 # number of ReadReq misses 2252system.l2c.ReadReq_misses::total 543 # number of ReadReq misses 2253system.l2c.UpgradeReq_misses::cpu0.data 22 # number of UpgradeReq misses 2254system.l2c.UpgradeReq_misses::cpu1.data 16 # number of UpgradeReq misses 2255system.l2c.UpgradeReq_misses::cpu2.data 18 # number of UpgradeReq misses 2256system.l2c.UpgradeReq_misses::cpu3.data 20 # number of UpgradeReq misses 2257system.l2c.UpgradeReq_misses::total 76 # number of UpgradeReq misses 2258system.l2c.ReadExReq_misses::cpu0.data 94 # number of ReadExReq misses 2259system.l2c.ReadExReq_misses::cpu1.data 12 # number of ReadExReq misses 2260system.l2c.ReadExReq_misses::cpu2.data 13 # number of ReadExReq misses 2261system.l2c.ReadExReq_misses::cpu3.data 12 # number of ReadExReq misses 2262system.l2c.ReadExReq_misses::total 131 # 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number of ReadExReq MSHR miss cycles 2500system.l2c.demand_mshr_miss_latency::cpu0.inst 19789750 # number of demand (read+write) MSHR miss cycles 2501system.l2c.demand_mshr_miss_latency::cpu0.data 10909000 # number of demand (read+write) MSHR miss cycles 2502system.l2c.demand_mshr_miss_latency::cpu1.inst 695750 # number of demand (read+write) MSHR miss cycles 2503system.l2c.demand_mshr_miss_latency::cpu1.data 748500 # number of demand (read+write) MSHR miss cycles 2504system.l2c.demand_mshr_miss_latency::cpu2.inst 4180000 # number of demand (read+write) MSHR miss cycles 2505system.l2c.demand_mshr_miss_latency::cpu2.data 1343499 # number of demand (read+write) MSHR miss cycles 2506system.l2c.demand_mshr_miss_latency::cpu3.inst 327500 # number of demand (read+write) MSHR miss cycles 2507system.l2c.demand_mshr_miss_latency::cpu3.data 807500 # number of demand (read+write) MSHR miss cycles 2508system.l2c.demand_mshr_miss_latency::total 38801499 # number of demand (read+write) MSHR miss cycles 2509system.l2c.overall_mshr_miss_latency::cpu0.inst 19789750 # number of overall MSHR miss cycles 2510system.l2c.overall_mshr_miss_latency::cpu0.data 10909000 # number of overall MSHR miss cycles 2511system.l2c.overall_mshr_miss_latency::cpu1.inst 695750 # number of overall MSHR miss cycles 2512system.l2c.overall_mshr_miss_latency::cpu1.data 748500 # number of overall MSHR miss cycles 2513system.l2c.overall_mshr_miss_latency::cpu2.inst 4180000 # number of overall MSHR miss cycles 2514system.l2c.overall_mshr_miss_latency::cpu2.data 1343499 # number of overall MSHR miss cycles 2515system.l2c.overall_mshr_miss_latency::cpu3.inst 327500 # number of overall MSHR miss cycles 2516system.l2c.overall_mshr_miss_latency::cpu3.data 807500 # number of overall MSHR miss cycles 2517system.l2c.overall_mshr_miss_latency::total 38801499 # number of overall MSHR miss cycles 2518system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.607143 # mshr miss rate for ReadReq accesses 2519system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.936709 # mshr miss rate for ReadReq accesses 2520system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.023364 # mshr miss rate for ReadReq accesses 2521system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.083333 # mshr miss rate for ReadReq accesses 2522system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.171765 # mshr miss rate for ReadReq accesses 2523system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.583333 # mshr miss rate for ReadReq accesses 2524system.l2c.ReadReq_mshr_miss_rate::cpu3.inst 0.013953 # mshr miss rate for ReadReq accesses 2525system.l2c.ReadReq_mshr_miss_rate::cpu3.data 0.083333 # mshr miss rate for ReadReq accesses 2526system.l2c.ReadReq_mshr_miss_rate::total 0.266365 # mshr miss rate for ReadReq accesses 2527system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.880000 # mshr miss rate for UpgradeReq accesses 2528system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses 2529system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for UpgradeReq accesses 2530system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for UpgradeReq accesses 2531system.l2c.UpgradeReq_mshr_miss_rate::total 0.962025 # mshr miss rate for UpgradeReq accesses 2532system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses 2533system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses 2534system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses 2535system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for ReadExReq accesses 2536system.l2c.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 2537system.l2c.demand_mshr_miss_rate::cpu0.inst 0.607143 # mshr miss rate for demand accesses 2538system.l2c.demand_mshr_miss_rate::cpu0.data 0.971098 # mshr miss rate for demand accesses 2539system.l2c.demand_mshr_miss_rate::cpu1.inst 0.023364 # mshr miss rate for demand accesses 2540system.l2c.demand_mshr_miss_rate::cpu1.data 0.541667 # mshr miss rate for demand accesses 2541system.l2c.demand_mshr_miss_rate::cpu2.inst 0.171765 # mshr miss rate for demand accesses 2542system.l2c.demand_mshr_miss_rate::cpu2.data 0.800000 # mshr miss rate for demand accesses 2543system.l2c.demand_mshr_miss_rate::cpu3.inst 0.013953 # mshr miss rate for demand accesses 2544system.l2c.demand_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for demand accesses 2545system.l2c.demand_mshr_miss_rate::total 0.311762 # mshr miss rate for demand accesses 2546system.l2c.overall_mshr_miss_rate::cpu0.inst 0.607143 # mshr miss rate for overall accesses 2547system.l2c.overall_mshr_miss_rate::cpu0.data 0.971098 # mshr miss rate for overall accesses 2548system.l2c.overall_mshr_miss_rate::cpu1.inst 0.023364 # mshr miss rate for overall accesses 2549system.l2c.overall_mshr_miss_rate::cpu1.data 0.541667 # mshr miss rate for overall accesses 2550system.l2c.overall_mshr_miss_rate::cpu2.inst 0.171765 # mshr miss rate for overall accesses 2551system.l2c.overall_mshr_miss_rate::cpu2.data 0.800000 # mshr miss rate for overall accesses 2552system.l2c.overall_mshr_miss_rate::cpu3.inst 0.013953 # mshr miss rate for overall accesses 2553system.l2c.overall_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for overall accesses 2554system.l2c.overall_mshr_miss_rate::total 0.311762 # mshr miss rate for overall accesses 2555system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 55433.473389 # average ReadReq mshr miss latency 2556system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 64331.081081 # average ReadReq mshr miss latency 2557system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 69575 # average ReadReq mshr miss latency 2558system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 76250 # average ReadReq mshr miss latency 2559system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 57260.273973 # average ReadReq mshr miss latency 2560system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 62321.428571 # average ReadReq mshr miss latency 2561system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 54583.333333 # average ReadReq mshr miss latency 2562system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 76250 # average ReadReq mshr miss latency 2563system.l2c.ReadReq_avg_mshr_miss_latency::total 57357.750473 # average ReadReq mshr miss latency 2564system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average UpgradeReq mshr miss latency 2565system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 11094.687500 # average UpgradeReq mshr miss latency 2566system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10001 # average UpgradeReq mshr miss latency 2567system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 10001 # average UpgradeReq mshr miss latency 2568system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10231.250000 # average UpgradeReq mshr miss latency 2569system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 65409.574468 # average ReadExReq mshr miss latency 2570system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 56020.833333 # average ReadExReq mshr miss latency 2571system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 69788.384615 # average ReadExReq mshr miss latency 2572system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 60937.500000 # average ReadExReq mshr miss latency 2573system.l2c.ReadExReq_avg_mshr_miss_latency::total 64574.419847 # average ReadExReq mshr miss latency 2574system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 55433.473389 # average overall mshr miss latency 2575system.l2c.demand_avg_mshr_miss_latency::cpu0.data 64934.523810 # average overall mshr miss latency 2576system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 69575 # average overall mshr miss latency 2577system.l2c.demand_avg_mshr_miss_latency::cpu1.data 57576.923077 # average overall mshr miss latency 2578system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 57260.273973 # average overall mshr miss latency 2579system.l2c.demand_avg_mshr_miss_latency::cpu2.data 67174.950000 # average overall mshr miss latency 2580system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 54583.333333 # average overall mshr miss latency 2581system.l2c.demand_avg_mshr_miss_latency::cpu3.data 62115.384615 # average overall mshr miss latency 2582system.l2c.demand_avg_mshr_miss_latency::total 58790.150000 # average overall mshr miss latency 2583system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 55433.473389 # average overall mshr miss latency 2584system.l2c.overall_avg_mshr_miss_latency::cpu0.data 64934.523810 # average overall mshr miss latency 2585system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 69575 # average overall mshr miss latency 2586system.l2c.overall_avg_mshr_miss_latency::cpu1.data 57576.923077 # average overall mshr miss latency 2587system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 57260.273973 # average overall mshr miss latency 2588system.l2c.overall_avg_mshr_miss_latency::cpu2.data 67174.950000 # average overall mshr miss latency 2589system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 54583.333333 # average overall mshr miss latency 2590system.l2c.overall_avg_mshr_miss_latency::cpu3.data 62115.384615 # average overall mshr miss latency 2591system.l2c.overall_avg_mshr_miss_latency::total 58790.150000 # average overall mshr miss latency 2592system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 2593 2594---------- End Simulation Statistics ---------- 2595