stats.txt revision 9378:36ed6d4654bb
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000105 # Number of seconds simulated 4sim_ticks 104830500 # Number of ticks simulated 5final_tick 104830500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 112424 # Simulator instruction rate (inst/s) 8host_op_rate 112424 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 11388036 # Simulator tick rate (ticks/s) 10host_mem_usage 275264 # Number of bytes of host memory used 11host_seconds 9.21 # Real time elapsed on the host 12sim_insts 1034897 # Number of instructions simulated 13sim_ops 1034897 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu0.inst 22784 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu0.data 10752 # Number of bytes read from this memory 16system.physmem.bytes_read::cpu1.inst 5184 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu1.data 1280 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu2.inst 192 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu2.data 832 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu3.inst 256 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu3.data 832 # Number of bytes read from this memory 22system.physmem.bytes_read::total 42112 # Number of bytes read from this memory 23system.physmem.bytes_inst_read::cpu0.inst 22784 # Number of instructions bytes read from this memory 24system.physmem.bytes_inst_read::cpu1.inst 5184 # Number of instructions bytes read from this memory 25system.physmem.bytes_inst_read::cpu2.inst 192 # Number of instructions bytes read from this memory 26system.physmem.bytes_inst_read::cpu3.inst 256 # Number of instructions bytes read from this memory 27system.physmem.bytes_inst_read::total 28416 # Number of instructions bytes read from this memory 28system.physmem.num_reads::cpu0.inst 356 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu0.data 168 # Number of read requests responded to by this memory 30system.physmem.num_reads::cpu1.inst 81 # Number of read requests responded to by this memory 31system.physmem.num_reads::cpu1.data 20 # Number of read requests responded to by this memory 32system.physmem.num_reads::cpu2.inst 3 # Number of read requests responded to by this memory 33system.physmem.num_reads::cpu2.data 13 # Number of read requests responded to by this memory 34system.physmem.num_reads::cpu3.inst 4 # Number of read requests responded to by this memory 35system.physmem.num_reads::cpu3.data 13 # Number of read requests responded to by this memory 36system.physmem.num_reads::total 658 # Number of read requests responded to by this memory 37system.physmem.bw_read::cpu0.inst 217341327 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu0.data 102565570 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::cpu1.inst 49451257 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::cpu1.data 12210187 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::cpu2.inst 1831528 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_read::cpu2.data 7936621 # Total read bandwidth from this memory (bytes/s) 43system.physmem.bw_read::cpu3.inst 2442037 # Total read bandwidth from this memory (bytes/s) 44system.physmem.bw_read::cpu3.data 7936621 # Total read bandwidth from this memory (bytes/s) 45system.physmem.bw_read::total 401715150 # Total read bandwidth from this memory (bytes/s) 46system.physmem.bw_inst_read::cpu0.inst 217341327 # Instruction read bandwidth from this memory (bytes/s) 47system.physmem.bw_inst_read::cpu1.inst 49451257 # Instruction read bandwidth from this memory (bytes/s) 48system.physmem.bw_inst_read::cpu2.inst 1831528 # Instruction read bandwidth from this memory (bytes/s) 49system.physmem.bw_inst_read::cpu3.inst 2442037 # Instruction read bandwidth from this memory (bytes/s) 50system.physmem.bw_inst_read::total 271066150 # Instruction read bandwidth from this memory (bytes/s) 51system.physmem.bw_total::cpu0.inst 217341327 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::cpu0.data 102565570 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.bw_total::cpu1.inst 49451257 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.bw_total::cpu1.data 12210187 # Total bandwidth to/from this memory (bytes/s) 55system.physmem.bw_total::cpu2.inst 1831528 # Total bandwidth to/from this memory (bytes/s) 56system.physmem.bw_total::cpu2.data 7936621 # Total bandwidth to/from this memory (bytes/s) 57system.physmem.bw_total::cpu3.inst 2442037 # Total bandwidth to/from this memory (bytes/s) 58system.physmem.bw_total::cpu3.data 7936621 # Total bandwidth to/from this memory (bytes/s) 59system.physmem.bw_total::total 401715150 # Total bandwidth to/from this memory (bytes/s) 60system.physmem.readReqs 659 # Total number of read requests seen 61system.physmem.writeReqs 0 # Total number of write requests seen 62system.physmem.cpureqs 980 # Reqs generatd by CPU via cache - shady 63system.physmem.bytesRead 42112 # Total number of bytes read from memory 64system.physmem.bytesWritten 0 # Total number of bytes written to memory 65system.physmem.bytesConsumedRd 42112 # bytesRead derated as per pkt->getSize() 66system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() 67system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q 68system.physmem.neitherReadNorWrite 72 # Reqs where no action is needed 69system.physmem.perBankRdReqs::0 50 # Track reads on a per bank basis 70system.physmem.perBankRdReqs::1 71 # Track reads on a per bank basis 71system.physmem.perBankRdReqs::2 36 # Track reads on a per bank basis 72system.physmem.perBankRdReqs::3 31 # Track reads on a per bank basis 73system.physmem.perBankRdReqs::4 29 # Track reads on a per bank basis 74system.physmem.perBankRdReqs::5 23 # Track reads on a per bank basis 75system.physmem.perBankRdReqs::6 19 # Track reads on a per bank basis 76system.physmem.perBankRdReqs::7 53 # Track reads on a per bank basis 77system.physmem.perBankRdReqs::8 54 # Track reads on a per bank basis 78system.physmem.perBankRdReqs::9 71 # Track reads on a per bank basis 79system.physmem.perBankRdReqs::10 60 # Track reads on a per bank basis 80system.physmem.perBankRdReqs::11 5 # Track reads on a per bank basis 81system.physmem.perBankRdReqs::12 15 # Track reads on a per bank basis 82system.physmem.perBankRdReqs::13 20 # Track reads on a per bank basis 83system.physmem.perBankRdReqs::14 78 # Track reads on a per bank basis 84system.physmem.perBankRdReqs::15 44 # Track reads on a per bank basis 85system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis 86system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis 87system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis 88system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis 89system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis 90system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis 91system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis 92system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis 93system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis 94system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis 95system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis 96system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis 97system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis 98system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis 99system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis 100system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis 101system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 102system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry 103system.physmem.totGap 104802500 # Total gap between requests 104system.physmem.readPktSize::0 0 # Categorize read packet sizes 105system.physmem.readPktSize::1 0 # Categorize read packet sizes 106system.physmem.readPktSize::2 0 # Categorize read packet sizes 107system.physmem.readPktSize::3 0 # Categorize read packet sizes 108system.physmem.readPktSize::4 0 # Categorize read packet sizes 109system.physmem.readPktSize::5 0 # Categorize read packet sizes 110system.physmem.readPktSize::6 659 # Categorize read packet sizes 111system.physmem.readPktSize::7 0 # Categorize read packet sizes 112system.physmem.readPktSize::8 0 # Categorize read packet sizes 113system.physmem.writePktSize::0 0 # categorize write packet sizes 114system.physmem.writePktSize::1 0 # categorize write packet sizes 115system.physmem.writePktSize::2 0 # categorize write packet sizes 116system.physmem.writePktSize::3 0 # categorize write packet sizes 117system.physmem.writePktSize::4 0 # categorize write packet sizes 118system.physmem.writePktSize::5 0 # categorize write packet sizes 119system.physmem.writePktSize::6 0 # categorize write packet sizes 120system.physmem.writePktSize::7 0 # categorize write packet sizes 121system.physmem.writePktSize::8 0 # categorize write packet sizes 122system.physmem.neitherpktsize::0 0 # categorize neither packet sizes 123system.physmem.neitherpktsize::1 0 # categorize neither packet sizes 124system.physmem.neitherpktsize::2 0 # categorize neither packet sizes 125system.physmem.neitherpktsize::3 0 # categorize neither packet sizes 126system.physmem.neitherpktsize::4 0 # categorize neither packet sizes 127system.physmem.neitherpktsize::5 0 # categorize neither packet sizes 128system.physmem.neitherpktsize::6 72 # categorize neither packet sizes 129system.physmem.neitherpktsize::7 0 # categorize neither packet sizes 130system.physmem.neitherpktsize::8 0 # categorize neither packet sizes 131system.physmem.rdQLenPdf::0 390 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::1 195 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::2 60 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::3 11 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 159system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 160system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 161system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 162system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 163system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see 164system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 197system.physmem.totQLat 2987155 # Total cycles spent in queuing delays 198system.physmem.totMemAccLat 17761155 # Sum of mem lat for all requests 199system.physmem.totBusLat 2636000 # Total cycles spent in databus access 200system.physmem.totBankLat 12138000 # Total cycles spent in bank access 201system.physmem.avgQLat 4532.86 # Average queueing delay per request 202system.physmem.avgBankLat 18418.82 # Average bank access latency per request 203system.physmem.avgBusLat 4000.00 # Average bus latency per request 204system.physmem.avgMemAccLat 26951.68 # Average memory access latency 205system.physmem.avgRdBW 401.72 # Average achieved read bandwidth in MB/s 206system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s 207system.physmem.avgConsumedRdBW 401.72 # Average consumed read bandwidth in MB/s 208system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s 209system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s 210system.physmem.busUtil 2.51 # Data bus utilization in percentage 211system.physmem.avgRdQLen 0.17 # Average read queue length over time 212system.physmem.avgWrQLen 0.00 # Average write queue length over time 213system.physmem.readRowHits 506 # Number of row buffer hits during reads 214system.physmem.writeRowHits 0 # Number of row buffer hits during writes 215system.physmem.readRowHitRate 76.78 # Row buffer hit rate for reads 216system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 217system.physmem.avgGap 159032.63 # Average gap between requests 218system.cpu0.workload.num_syscalls 89 # Number of system calls 219system.cpu0.numCycles 209662 # number of cpu cycles simulated 220system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 221system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 222system.cpu0.BPredUnit.lookups 82004 # Number of BP lookups 223system.cpu0.BPredUnit.condPredicted 79765 # Number of conditional branches predicted 224system.cpu0.BPredUnit.condIncorrect 1218 # Number of conditional branches incorrect 225system.cpu0.BPredUnit.BTBLookups 79291 # Number of BTB lookups 226system.cpu0.BPredUnit.BTBHits 77227 # Number of BTB hits 227system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 228system.cpu0.BPredUnit.usedRAS 516 # Number of times the RAS was used to get a target. 229system.cpu0.BPredUnit.RASInCorrect 132 # Number of incorrect RAS predictions. 230system.cpu0.fetch.icacheStallCycles 16907 # Number of cycles fetch is stalled on an Icache miss 231system.cpu0.fetch.Insts 486703 # Number of instructions fetch has processed 232system.cpu0.fetch.Branches 82004 # Number of branches that fetch encountered 233system.cpu0.fetch.predictedBranches 77743 # Number of branches that fetch has predicted taken 234system.cpu0.fetch.Cycles 159637 # Number of cycles fetch has run and was not squashing or blocked 235system.cpu0.fetch.SquashCycles 3804 # Number of cycles fetch has spent squashing 236system.cpu0.fetch.BlockedCycles 12545 # Number of cycles fetch has spent blocked 237system.cpu0.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 238system.cpu0.fetch.PendingTrapStallCycles 1361 # Number of stall cycles due to pending traps 239system.cpu0.fetch.CacheLines 5871 # Number of cache lines fetched 240system.cpu0.fetch.IcacheSquashes 484 # Number of outstanding Icache misses that were squashed 241system.cpu0.fetch.rateDist::samples 192893 # Number of instructions fetched each cycle (Total) 242system.cpu0.fetch.rateDist::mean 2.523176 # Number of instructions fetched each cycle (Total) 243system.cpu0.fetch.rateDist::stdev 2.215866 # Number of instructions fetched each cycle (Total) 244system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 245system.cpu0.fetch.rateDist::0 33256 17.24% 17.24% # Number of instructions fetched each cycle (Total) 246system.cpu0.fetch.rateDist::1 79042 40.98% 58.22% # Number of instructions fetched each cycle (Total) 247system.cpu0.fetch.rateDist::2 584 0.30% 58.52% # Number of instructions fetched each cycle (Total) 248system.cpu0.fetch.rateDist::3 987 0.51% 59.03% # Number of instructions fetched each cycle (Total) 249system.cpu0.fetch.rateDist::4 454 0.24% 59.27% # Number of instructions fetched each cycle (Total) 250system.cpu0.fetch.rateDist::5 75108 38.94% 98.21% # Number of instructions fetched each cycle (Total) 251system.cpu0.fetch.rateDist::6 578 0.30% 98.50% # Number of instructions fetched each cycle (Total) 252system.cpu0.fetch.rateDist::7 364 0.19% 98.69% # Number of instructions fetched each cycle (Total) 253system.cpu0.fetch.rateDist::8 2520 1.31% 100.00% # Number of instructions fetched each cycle (Total) 254system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 255system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 256system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 257system.cpu0.fetch.rateDist::total 192893 # Number of instructions fetched each cycle (Total) 258system.cpu0.fetch.branchRate 0.391125 # Number of branch fetches per cycle 259system.cpu0.fetch.rate 2.321370 # Number of inst fetches per cycle 260system.cpu0.decode.IdleCycles 17503 # Number of cycles decode is idle 261system.cpu0.decode.BlockedCycles 14000 # Number of cycles decode is blocked 262system.cpu0.decode.RunCycles 158668 # Number of cycles decode is running 263system.cpu0.decode.UnblockCycles 284 # Number of cycles decode is unblocking 264system.cpu0.decode.SquashCycles 2438 # Number of cycles decode is squashing 265system.cpu0.decode.DecodedInsts 483730 # Number of instructions handled by decode 266system.cpu0.rename.SquashCycles 2438 # Number of cycles rename is squashing 267system.cpu0.rename.IdleCycles 18159 # Number of cycles rename is idle 268system.cpu0.rename.BlockCycles 648 # Number of cycles rename is blocking 269system.cpu0.rename.serializeStallCycles 12765 # count of cycles rename stalled for serializing inst 270system.cpu0.rename.RunCycles 158332 # Number of cycles rename is running 271system.cpu0.rename.UnblockCycles 551 # Number of cycles rename is unblocking 272system.cpu0.rename.RenamedInsts 480873 # Number of instructions processed by rename 273system.cpu0.rename.IQFullEvents 4 # Number of times rename has blocked due to IQ full 274system.cpu0.rename.LSQFullEvents 153 # Number of times rename has blocked due to LSQ full 275system.cpu0.rename.RenamedOperands 329027 # Number of destination operands rename has renamed 276system.cpu0.rename.RenameLookups 958899 # Number of register rename lookups that rename has made 277system.cpu0.rename.int_rename_lookups 958899 # Number of integer rename lookups 278system.cpu0.rename.CommittedMaps 315995 # Number of HB maps that are committed 279system.cpu0.rename.UndoneMaps 13032 # Number of HB maps that are undone due to squashing 280system.cpu0.rename.serializingInsts 877 # count of serializing insts renamed 281system.cpu0.rename.tempSerializingInsts 903 # count of temporary serializing insts renamed 282system.cpu0.rename.skidInsts 3587 # count of insts added to the skid buffer 283system.cpu0.memDep0.insertedLoads 153720 # Number of loads inserted to the mem dependence unit. 284system.cpu0.memDep0.insertedStores 77689 # Number of stores inserted to the mem dependence unit. 285system.cpu0.memDep0.conflictingLoads 74928 # Number of conflicting loads. 286system.cpu0.memDep0.conflictingStores 74758 # Number of conflicting stores. 287system.cpu0.iq.iqInstsAdded 402151 # Number of instructions added to the IQ (excludes non-spec) 288system.cpu0.iq.iqNonSpecInstsAdded 922 # Number of non-speculative instructions added to the IQ 289system.cpu0.iq.iqInstsIssued 399521 # Number of instructions issued 290system.cpu0.iq.iqSquashedInstsIssued 164 # Number of squashed instructions issued 291system.cpu0.iq.iqSquashedInstsExamined 10786 # Number of squashed instructions iterated over during squash; mainly for profiling 292system.cpu0.iq.iqSquashedOperandsExamined 9496 # Number of squashed operands that are examined and possibly removed from graph 293system.cpu0.iq.iqSquashedNonSpecRemoved 363 # Number of squashed non-spec instructions that were removed 294system.cpu0.iq.issued_per_cycle::samples 192893 # Number of insts issued each cycle 295system.cpu0.iq.issued_per_cycle::mean 2.071205 # Number of insts issued each cycle 296system.cpu0.iq.issued_per_cycle::stdev 1.088777 # Number of insts issued each cycle 297system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 298system.cpu0.iq.issued_per_cycle::0 32269 16.73% 16.73% # Number of insts issued each cycle 299system.cpu0.iq.issued_per_cycle::1 4844 2.51% 19.24% # Number of insts issued each cycle 300system.cpu0.iq.issued_per_cycle::2 76822 39.83% 59.07% # Number of insts issued each cycle 301system.cpu0.iq.issued_per_cycle::3 76327 39.57% 98.64% # Number of insts issued each cycle 302system.cpu0.iq.issued_per_cycle::4 1582 0.82% 99.46% # Number of insts issued each cycle 303system.cpu0.iq.issued_per_cycle::5 687 0.36% 99.81% # Number of insts issued each cycle 304system.cpu0.iq.issued_per_cycle::6 263 0.14% 99.95% # Number of insts issued each cycle 305system.cpu0.iq.issued_per_cycle::7 81 0.04% 99.99% # Number of insts issued each cycle 306system.cpu0.iq.issued_per_cycle::8 18 0.01% 100.00% # Number of insts issued each cycle 307system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 308system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 309system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 310system.cpu0.iq.issued_per_cycle::total 192893 # Number of insts issued each cycle 311system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 312system.cpu0.iq.fu_full::IntAlu 57 25.45% 25.45% # attempts to use FU when none available 313system.cpu0.iq.fu_full::IntMult 0 0.00% 25.45% # attempts to use FU when none available 314system.cpu0.iq.fu_full::IntDiv 0 0.00% 25.45% # attempts to use FU when none available 315system.cpu0.iq.fu_full::FloatAdd 0 0.00% 25.45% # attempts to use FU when none available 316system.cpu0.iq.fu_full::FloatCmp 0 0.00% 25.45% # attempts to use FU when none available 317system.cpu0.iq.fu_full::FloatCvt 0 0.00% 25.45% # attempts to use FU when none available 318system.cpu0.iq.fu_full::FloatMult 0 0.00% 25.45% # attempts to use FU when none available 319system.cpu0.iq.fu_full::FloatDiv 0 0.00% 25.45% # attempts to use FU when none available 320system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 25.45% # attempts to use FU when none available 321system.cpu0.iq.fu_full::SimdAdd 0 0.00% 25.45% # attempts to use FU when none available 322system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 25.45% # attempts to use FU when none available 323system.cpu0.iq.fu_full::SimdAlu 0 0.00% 25.45% # attempts to use FU when none available 324system.cpu0.iq.fu_full::SimdCmp 0 0.00% 25.45% # attempts to use FU when none available 325system.cpu0.iq.fu_full::SimdCvt 0 0.00% 25.45% # attempts to use FU when none available 326system.cpu0.iq.fu_full::SimdMisc 0 0.00% 25.45% # attempts to use FU when none available 327system.cpu0.iq.fu_full::SimdMult 0 0.00% 25.45% # attempts to use FU when none available 328system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 25.45% # attempts to use FU when none available 329system.cpu0.iq.fu_full::SimdShift 0 0.00% 25.45% # attempts to use FU when none available 330system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 25.45% # attempts to use FU when none available 331system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 25.45% # attempts to use FU when none available 332system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 25.45% # attempts to use FU when none available 333system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 25.45% # attempts to use FU when none available 334system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 25.45% # attempts to use FU when none available 335system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 25.45% # attempts to use FU when none available 336system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 25.45% # attempts to use FU when none available 337system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 25.45% # attempts to use FU when none available 338system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 25.45% # attempts to use FU when none available 339system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.45% # attempts to use FU when none available 340system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 25.45% # attempts to use FU when none available 341system.cpu0.iq.fu_full::MemRead 53 23.66% 49.11% # attempts to use FU when none available 342system.cpu0.iq.fu_full::MemWrite 114 50.89% 100.00% # attempts to use FU when none available 343system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 344system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 345system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 346system.cpu0.iq.FU_type_0::IntAlu 169105 42.33% 42.33% # Type of FU issued 347system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.33% # Type of FU issued 348system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.33% # Type of FU issued 349system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.33% # Type of FU issued 350system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.33% # Type of FU issued 351system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.33% # Type of FU issued 352system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.33% # Type of FU issued 353system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.33% # Type of FU issued 354system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.33% # Type of FU issued 355system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.33% # Type of FU issued 356system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.33% # Type of FU issued 357system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.33% # Type of FU issued 358system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.33% # Type of FU issued 359system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.33% # Type of FU issued 360system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.33% # Type of FU issued 361system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.33% # Type of FU issued 362system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.33% # Type of FU issued 363system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.33% # Type of FU issued 364system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.33% # Type of FU issued 365system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.33% # Type of FU issued 366system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.33% # Type of FU issued 367system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.33% # Type of FU issued 368system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.33% # Type of FU issued 369system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.33% # Type of FU issued 370system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.33% # Type of FU issued 371system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.33% # Type of FU issued 372system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.33% # Type of FU issued 373system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.33% # Type of FU issued 374system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.33% # Type of FU issued 375system.cpu0.iq.FU_type_0::MemRead 153283 38.37% 80.69% # Type of FU issued 376system.cpu0.iq.FU_type_0::MemWrite 77133 19.31% 100.00% # Type of FU issued 377system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 378system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 379system.cpu0.iq.FU_type_0::total 399521 # Type of FU issued 380system.cpu0.iq.rate 1.905548 # Inst issue rate 381system.cpu0.iq.fu_busy_cnt 224 # FU busy when requested 382system.cpu0.iq.fu_busy_rate 0.000561 # FU busy rate (busy events/executed inst) 383system.cpu0.iq.int_inst_queue_reads 992323 # Number of integer instruction queue reads 384system.cpu0.iq.int_inst_queue_writes 413903 # Number of integer instruction queue writes 385system.cpu0.iq.int_inst_queue_wakeup_accesses 397700 # Number of integer instruction queue wakeup accesses 386system.cpu0.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads 387system.cpu0.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes 388system.cpu0.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses 389system.cpu0.iq.int_alu_accesses 399745 # Number of integer alu accesses 390system.cpu0.iq.fp_alu_accesses 0 # Number of floating point alu accesses 391system.cpu0.iew.lsq.thread0.forwLoads 74515 # Number of loads that had data forwarded from stores 392system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 393system.cpu0.iew.lsq.thread0.squashedLoads 2133 # Number of loads squashed 394system.cpu0.iew.lsq.thread0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed 395system.cpu0.iew.lsq.thread0.memOrderViolation 44 # Number of memory ordering violations 396system.cpu0.iew.lsq.thread0.squashedStores 1389 # Number of stores squashed 397system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 398system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 399system.cpu0.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 400system.cpu0.iew.lsq.thread0.cacheBlocked 4 # Number of times an access to memory failed due to the cache being blocked 401system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle 402system.cpu0.iew.iewSquashCycles 2438 # Number of cycles IEW is squashing 403system.cpu0.iew.iewBlockCycles 389 # Number of cycles IEW is blocking 404system.cpu0.iew.iewUnblockCycles 34 # Number of cycles IEW is unblocking 405system.cpu0.iew.iewDispatchedInsts 478542 # Number of instructions dispatched to IQ 406system.cpu0.iew.iewDispSquashedInsts 300 # Number of squashed instructions skipped by dispatch 407system.cpu0.iew.iewDispLoadInsts 153720 # Number of dispatched load instructions 408system.cpu0.iew.iewDispStoreInsts 77689 # Number of dispatched store instructions 409system.cpu0.iew.iewDispNonSpecInsts 806 # Number of dispatched non-speculative instructions 410system.cpu0.iew.iewIQFullEvents 35 # Number of times the IQ has become full, causing a stall 411system.cpu0.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 412system.cpu0.iew.memOrderViolationEvents 44 # Number of memory order violations 413system.cpu0.iew.predictedTakenIncorrect 327 # Number of branches that were predicted taken incorrectly 414system.cpu0.iew.predictedNotTakenIncorrect 1115 # Number of branches that were predicted not taken incorrectly 415system.cpu0.iew.branchMispredicts 1442 # Number of branch mispredicts detected at execute 416system.cpu0.iew.iewExecutedInsts 398429 # Number of executed instructions 417system.cpu0.iew.iewExecLoadInsts 152970 # Number of load instructions executed 418system.cpu0.iew.iewExecSquashedInsts 1092 # Number of squashed instructions skipped in execute 419system.cpu0.iew.exec_swp 0 # number of swp insts executed 420system.cpu0.iew.exec_nop 75469 # number of nop insts executed 421system.cpu0.iew.exec_refs 229968 # number of memory reference insts executed 422system.cpu0.iew.exec_branches 79152 # Number of branches executed 423system.cpu0.iew.exec_stores 76998 # Number of stores executed 424system.cpu0.iew.exec_rate 1.900340 # Inst execution rate 425system.cpu0.iew.wb_sent 398024 # cumulative count of insts sent to commit 426system.cpu0.iew.wb_count 397700 # cumulative count of insts written-back 427system.cpu0.iew.wb_producers 235727 # num instructions producing a value 428system.cpu0.iew.wb_consumers 238246 # num instructions consuming a value 429system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 430system.cpu0.iew.wb_rate 1.896863 # insts written-back per cycle 431system.cpu0.iew.wb_fanout 0.989427 # average fanout of values written-back 432system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 433system.cpu0.commit.commitSquashedInsts 12164 # The number of squashed insts skipped by commit 434system.cpu0.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards 435system.cpu0.commit.branchMispredicts 1218 # The number of times a branch was mispredicted 436system.cpu0.commit.committed_per_cycle::samples 190472 # Number of insts commited each cycle 437system.cpu0.commit.committed_per_cycle::mean 2.448360 # Number of insts commited each cycle 438system.cpu0.commit.committed_per_cycle::stdev 2.135276 # Number of insts commited each cycle 439system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 440system.cpu0.commit.committed_per_cycle::0 32802 17.22% 17.22% # Number of insts commited each cycle 441system.cpu0.commit.committed_per_cycle::1 78740 41.34% 58.56% # Number of insts commited each cycle 442system.cpu0.commit.committed_per_cycle::2 2340 1.23% 59.79% # Number of insts commited each cycle 443system.cpu0.commit.committed_per_cycle::3 693 0.36% 60.15% # Number of insts commited each cycle 444system.cpu0.commit.committed_per_cycle::4 545 0.29% 60.44% # Number of insts commited each cycle 445system.cpu0.commit.committed_per_cycle::5 74330 39.02% 99.46% # Number of insts commited each cycle 446system.cpu0.commit.committed_per_cycle::6 456 0.24% 99.70% # Number of insts commited each cycle 447system.cpu0.commit.committed_per_cycle::7 249 0.13% 99.83% # Number of insts commited each cycle 448system.cpu0.commit.committed_per_cycle::8 317 0.17% 100.00% # Number of insts commited each cycle 449system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 450system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 451system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 452system.cpu0.commit.committed_per_cycle::total 190472 # Number of insts commited each cycle 453system.cpu0.commit.committedInsts 466344 # Number of instructions committed 454system.cpu0.commit.committedOps 466344 # Number of ops (including micro ops) committed 455system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed 456system.cpu0.commit.refs 227887 # Number of memory references committed 457system.cpu0.commit.loads 151587 # Number of loads committed 458system.cpu0.commit.membars 84 # Number of memory barriers committed 459system.cpu0.commit.branches 78187 # Number of branches committed 460system.cpu0.commit.fp_insts 0 # Number of committed floating point instructions. 461system.cpu0.commit.int_insts 314326 # Number of committed integer instructions. 462system.cpu0.commit.function_calls 223 # Number of function calls committed. 463system.cpu0.commit.bw_lim_events 317 # number cycles where commit BW limit reached 464system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits 465system.cpu0.rob.rob_reads 667502 # The number of ROB reads 466system.cpu0.rob.rob_writes 959472 # The number of ROB writes 467system.cpu0.timesIdled 316 # Number of times that the entire CPU went into an idle state and unscheduled itself 468system.cpu0.idleCycles 16769 # Total number of cycles that the CPU has spent unscheduled due to idling 469system.cpu0.committedInsts 391341 # Number of Instructions Simulated 470system.cpu0.committedOps 391341 # Number of Ops (including micro ops) Simulated 471system.cpu0.committedInsts_total 391341 # Number of Instructions Simulated 472system.cpu0.cpi 0.535753 # CPI: Cycles Per Instruction 473system.cpu0.cpi_total 0.535753 # CPI: Total CPI of All Threads 474system.cpu0.ipc 1.866533 # IPC: Instructions Per Cycle 475system.cpu0.ipc_total 1.866533 # IPC: Total IPC of All Threads 476system.cpu0.int_regfile_reads 712669 # number of integer regfile reads 477system.cpu0.int_regfile_writes 321346 # number of integer regfile writes 478system.cpu0.fp_regfile_reads 192 # number of floating regfile reads 479system.cpu0.misc_regfile_reads 231752 # number of misc regfile reads 480system.cpu0.misc_regfile_writes 564 # number of misc regfile writes 481system.cpu0.icache.replacements 297 # number of replacements 482system.cpu0.icache.tagsinuse 245.466325 # Cycle average of tags in use 483system.cpu0.icache.total_refs 5129 # Total number of references to valid blocks. 484system.cpu0.icache.sampled_refs 587 # Sample count of references to valid blocks. 485system.cpu0.icache.avg_refs 8.737649 # Average number of references to valid blocks. 486system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 487system.cpu0.icache.occ_blocks::cpu0.inst 245.466325 # Average occupied blocks per requestor 488system.cpu0.icache.occ_percent::cpu0.inst 0.479426 # Average percentage of cache occupancy 489system.cpu0.icache.occ_percent::total 0.479426 # Average percentage of cache occupancy 490system.cpu0.icache.ReadReq_hits::cpu0.inst 5129 # number of ReadReq hits 491system.cpu0.icache.ReadReq_hits::total 5129 # number of ReadReq hits 492system.cpu0.icache.demand_hits::cpu0.inst 5129 # number of demand (read+write) hits 493system.cpu0.icache.demand_hits::total 5129 # number of demand (read+write) hits 494system.cpu0.icache.overall_hits::cpu0.inst 5129 # number of overall hits 495system.cpu0.icache.overall_hits::total 5129 # number of overall hits 496system.cpu0.icache.ReadReq_misses::cpu0.inst 742 # number of ReadReq misses 497system.cpu0.icache.ReadReq_misses::total 742 # number of ReadReq misses 498system.cpu0.icache.demand_misses::cpu0.inst 742 # number of demand (read+write) misses 499system.cpu0.icache.demand_misses::total 742 # number of demand (read+write) misses 500system.cpu0.icache.overall_misses::cpu0.inst 742 # number of overall misses 501system.cpu0.icache.overall_misses::total 742 # number of overall misses 502system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 25612000 # number of ReadReq miss cycles 503system.cpu0.icache.ReadReq_miss_latency::total 25612000 # number of ReadReq miss cycles 504system.cpu0.icache.demand_miss_latency::cpu0.inst 25612000 # number of demand (read+write) miss cycles 505system.cpu0.icache.demand_miss_latency::total 25612000 # number of demand (read+write) miss cycles 506system.cpu0.icache.overall_miss_latency::cpu0.inst 25612000 # number of overall miss cycles 507system.cpu0.icache.overall_miss_latency::total 25612000 # number of overall miss cycles 508system.cpu0.icache.ReadReq_accesses::cpu0.inst 5871 # number of ReadReq accesses(hits+misses) 509system.cpu0.icache.ReadReq_accesses::total 5871 # number of ReadReq accesses(hits+misses) 510system.cpu0.icache.demand_accesses::cpu0.inst 5871 # number of demand (read+write) accesses 511system.cpu0.icache.demand_accesses::total 5871 # number of demand (read+write) accesses 512system.cpu0.icache.overall_accesses::cpu0.inst 5871 # number of overall (read+write) accesses 513system.cpu0.icache.overall_accesses::total 5871 # number of overall (read+write) accesses 514system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.126384 # miss rate for ReadReq accesses 515system.cpu0.icache.ReadReq_miss_rate::total 0.126384 # miss rate for ReadReq accesses 516system.cpu0.icache.demand_miss_rate::cpu0.inst 0.126384 # miss rate for demand accesses 517system.cpu0.icache.demand_miss_rate::total 0.126384 # miss rate for demand accesses 518system.cpu0.icache.overall_miss_rate::cpu0.inst 0.126384 # miss rate for overall accesses 519system.cpu0.icache.overall_miss_rate::total 0.126384 # miss rate for overall accesses 520system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 34517.520216 # average ReadReq miss latency 521system.cpu0.icache.ReadReq_avg_miss_latency::total 34517.520216 # average ReadReq miss latency 522system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 34517.520216 # average overall miss latency 523system.cpu0.icache.demand_avg_miss_latency::total 34517.520216 # average overall miss latency 524system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 34517.520216 # average overall miss latency 525system.cpu0.icache.overall_avg_miss_latency::total 34517.520216 # average overall miss latency 526system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 527system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 528system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 529system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 530system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 531system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 532system.cpu0.icache.fast_writes 0 # number of fast writes performed 533system.cpu0.icache.cache_copies 0 # number of cache copies performed 534system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 154 # number of ReadReq MSHR hits 535system.cpu0.icache.ReadReq_mshr_hits::total 154 # number of ReadReq MSHR hits 536system.cpu0.icache.demand_mshr_hits::cpu0.inst 154 # number of demand (read+write) MSHR hits 537system.cpu0.icache.demand_mshr_hits::total 154 # number of demand (read+write) MSHR hits 538system.cpu0.icache.overall_mshr_hits::cpu0.inst 154 # number of overall MSHR hits 539system.cpu0.icache.overall_mshr_hits::total 154 # number of overall MSHR hits 540system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 588 # number of ReadReq MSHR misses 541system.cpu0.icache.ReadReq_mshr_misses::total 588 # number of ReadReq MSHR misses 542system.cpu0.icache.demand_mshr_misses::cpu0.inst 588 # number of demand (read+write) MSHR misses 543system.cpu0.icache.demand_mshr_misses::total 588 # number of demand (read+write) MSHR misses 544system.cpu0.icache.overall_mshr_misses::cpu0.inst 588 # number of overall MSHR misses 545system.cpu0.icache.overall_mshr_misses::total 588 # number of overall MSHR misses 546system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 20478500 # number of ReadReq MSHR miss cycles 547system.cpu0.icache.ReadReq_mshr_miss_latency::total 20478500 # number of ReadReq MSHR miss cycles 548system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 20478500 # number of demand (read+write) MSHR miss cycles 549system.cpu0.icache.demand_mshr_miss_latency::total 20478500 # number of demand (read+write) MSHR miss cycles 550system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 20478500 # number of overall MSHR miss cycles 551system.cpu0.icache.overall_mshr_miss_latency::total 20478500 # number of overall MSHR miss cycles 552system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.100153 # mshr miss rate for ReadReq accesses 553system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.100153 # mshr miss rate for ReadReq accesses 554system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.100153 # mshr miss rate for demand accesses 555system.cpu0.icache.demand_mshr_miss_rate::total 0.100153 # mshr miss rate for demand accesses 556system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.100153 # mshr miss rate for overall accesses 557system.cpu0.icache.overall_mshr_miss_rate::total 0.100153 # mshr miss rate for overall accesses 558system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 34827.380952 # average ReadReq mshr miss latency 559system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 34827.380952 # average ReadReq mshr miss latency 560system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 34827.380952 # average overall mshr miss latency 561system.cpu0.icache.demand_avg_mshr_miss_latency::total 34827.380952 # average overall mshr miss latency 562system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 34827.380952 # average overall mshr miss latency 563system.cpu0.icache.overall_avg_mshr_miss_latency::total 34827.380952 # average overall mshr miss latency 564system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 565system.cpu0.dcache.replacements 2 # number of replacements 566system.cpu0.dcache.tagsinuse 143.868426 # Cycle average of tags in use 567system.cpu0.dcache.total_refs 153554 # Total number of references to valid blocks. 568system.cpu0.dcache.sampled_refs 170 # Sample count of references to valid blocks. 569system.cpu0.dcache.avg_refs 903.258824 # Average number of references to valid blocks. 570system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 571system.cpu0.dcache.occ_blocks::cpu0.data 143.868426 # Average occupied blocks per requestor 572system.cpu0.dcache.occ_percent::cpu0.data 0.280993 # Average percentage of cache occupancy 573system.cpu0.dcache.occ_percent::total 0.280993 # Average percentage of cache occupancy 574system.cpu0.dcache.ReadReq_hits::cpu0.data 77923 # number of ReadReq hits 575system.cpu0.dcache.ReadReq_hits::total 77923 # number of ReadReq hits 576system.cpu0.dcache.WriteReq_hits::cpu0.data 75708 # number of WriteReq hits 577system.cpu0.dcache.WriteReq_hits::total 75708 # number of WriteReq hits 578system.cpu0.dcache.SwapReq_hits::cpu0.data 22 # number of SwapReq hits 579system.cpu0.dcache.SwapReq_hits::total 22 # number of SwapReq hits 580system.cpu0.dcache.demand_hits::cpu0.data 153631 # number of demand (read+write) hits 581system.cpu0.dcache.demand_hits::total 153631 # number of demand (read+write) hits 582system.cpu0.dcache.overall_hits::cpu0.data 153631 # number of overall hits 583system.cpu0.dcache.overall_hits::total 153631 # number of overall hits 584system.cpu0.dcache.ReadReq_misses::cpu0.data 471 # number of ReadReq misses 585system.cpu0.dcache.ReadReq_misses::total 471 # number of ReadReq misses 586system.cpu0.dcache.WriteReq_misses::cpu0.data 550 # number of WriteReq misses 587system.cpu0.dcache.WriteReq_misses::total 550 # number of WriteReq misses 588system.cpu0.dcache.SwapReq_misses::cpu0.data 20 # number of SwapReq misses 589system.cpu0.dcache.SwapReq_misses::total 20 # number of SwapReq misses 590system.cpu0.dcache.demand_misses::cpu0.data 1021 # number of demand (read+write) misses 591system.cpu0.dcache.demand_misses::total 1021 # number of demand (read+write) misses 592system.cpu0.dcache.overall_misses::cpu0.data 1021 # number of overall misses 593system.cpu0.dcache.overall_misses::total 1021 # number of overall misses 594system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 11085500 # number of ReadReq miss cycles 595system.cpu0.dcache.ReadReq_miss_latency::total 11085500 # number of ReadReq miss cycles 596system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 22991498 # number of WriteReq miss cycles 597system.cpu0.dcache.WriteReq_miss_latency::total 22991498 # number of WriteReq miss cycles 598system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 390000 # number of SwapReq miss cycles 599system.cpu0.dcache.SwapReq_miss_latency::total 390000 # number of SwapReq miss cycles 600system.cpu0.dcache.demand_miss_latency::cpu0.data 34076998 # number of demand (read+write) miss cycles 601system.cpu0.dcache.demand_miss_latency::total 34076998 # number of demand (read+write) miss cycles 602system.cpu0.dcache.overall_miss_latency::cpu0.data 34076998 # number of overall miss cycles 603system.cpu0.dcache.overall_miss_latency::total 34076998 # number of overall miss cycles 604system.cpu0.dcache.ReadReq_accesses::cpu0.data 78394 # number of ReadReq accesses(hits+misses) 605system.cpu0.dcache.ReadReq_accesses::total 78394 # number of ReadReq accesses(hits+misses) 606system.cpu0.dcache.WriteReq_accesses::cpu0.data 76258 # number of WriteReq accesses(hits+misses) 607system.cpu0.dcache.WriteReq_accesses::total 76258 # number of WriteReq accesses(hits+misses) 608system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) 609system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) 610system.cpu0.dcache.demand_accesses::cpu0.data 154652 # number of demand (read+write) accesses 611system.cpu0.dcache.demand_accesses::total 154652 # number of demand (read+write) accesses 612system.cpu0.dcache.overall_accesses::cpu0.data 154652 # number of overall (read+write) accesses 613system.cpu0.dcache.overall_accesses::total 154652 # number of overall (read+write) accesses 614system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.006008 # miss rate for ReadReq accesses 615system.cpu0.dcache.ReadReq_miss_rate::total 0.006008 # miss rate for ReadReq accesses 616system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007212 # miss rate for WriteReq accesses 617system.cpu0.dcache.WriteReq_miss_rate::total 0.007212 # miss rate for WriteReq accesses 618system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.476190 # miss rate for SwapReq accesses 619system.cpu0.dcache.SwapReq_miss_rate::total 0.476190 # miss rate for SwapReq accesses 620system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006602 # miss rate for demand accesses 621system.cpu0.dcache.demand_miss_rate::total 0.006602 # miss rate for demand accesses 622system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006602 # miss rate for overall accesses 623system.cpu0.dcache.overall_miss_rate::total 0.006602 # miss rate for overall accesses 624system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 23536.093418 # average ReadReq miss latency 625system.cpu0.dcache.ReadReq_avg_miss_latency::total 23536.093418 # average ReadReq miss latency 626system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 41802.723636 # average WriteReq miss latency 627system.cpu0.dcache.WriteReq_avg_miss_latency::total 41802.723636 # average WriteReq miss latency 628system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 19500 # average SwapReq miss latency 629system.cpu0.dcache.SwapReq_avg_miss_latency::total 19500 # average SwapReq miss latency 630system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33376.099902 # average overall miss latency 631system.cpu0.dcache.demand_avg_miss_latency::total 33376.099902 # average overall miss latency 632system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33376.099902 # average overall miss latency 633system.cpu0.dcache.overall_avg_miss_latency::total 33376.099902 # average overall miss latency 634system.cpu0.dcache.blocked_cycles::no_mshrs 196 # number of cycles access was blocked 635system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 636system.cpu0.dcache.blocked::no_mshrs 14 # number of cycles access was blocked 637system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 638system.cpu0.dcache.avg_blocked_cycles::no_mshrs 14 # average number of cycles each access was blocked 639system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 640system.cpu0.dcache.fast_writes 0 # number of fast writes performed 641system.cpu0.dcache.cache_copies 0 # number of cache copies performed 642system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks 643system.cpu0.dcache.writebacks::total 1 # number of writebacks 644system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 277 # number of ReadReq MSHR hits 645system.cpu0.dcache.ReadReq_mshr_hits::total 277 # number of ReadReq MSHR hits 646system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 384 # number of WriteReq MSHR hits 647system.cpu0.dcache.WriteReq_mshr_hits::total 384 # number of WriteReq MSHR hits 648system.cpu0.dcache.demand_mshr_hits::cpu0.data 661 # number of demand (read+write) MSHR hits 649system.cpu0.dcache.demand_mshr_hits::total 661 # number of demand (read+write) MSHR hits 650system.cpu0.dcache.overall_mshr_hits::cpu0.data 661 # number of overall MSHR hits 651system.cpu0.dcache.overall_mshr_hits::total 661 # number of overall MSHR hits 652system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 194 # number of ReadReq MSHR misses 653system.cpu0.dcache.ReadReq_mshr_misses::total 194 # number of ReadReq MSHR misses 654system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 166 # number of WriteReq MSHR misses 655system.cpu0.dcache.WriteReq_mshr_misses::total 166 # number of WriteReq MSHR misses 656system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 20 # number of SwapReq MSHR misses 657system.cpu0.dcache.SwapReq_mshr_misses::total 20 # number of SwapReq MSHR misses 658system.cpu0.dcache.demand_mshr_misses::cpu0.data 360 # number of demand (read+write) MSHR misses 659system.cpu0.dcache.demand_mshr_misses::total 360 # number of demand (read+write) MSHR misses 660system.cpu0.dcache.overall_mshr_misses::cpu0.data 360 # number of overall MSHR misses 661system.cpu0.dcache.overall_mshr_misses::total 360 # number of overall MSHR misses 662system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4894000 # number of ReadReq MSHR miss cycles 663system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4894000 # number of ReadReq MSHR miss cycles 664system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5605500 # number of WriteReq MSHR miss cycles 665system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5605500 # number of WriteReq MSHR miss cycles 666system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 350000 # number of SwapReq MSHR miss cycles 667system.cpu0.dcache.SwapReq_mshr_miss_latency::total 350000 # number of SwapReq MSHR miss cycles 668system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10499500 # number of demand (read+write) MSHR miss cycles 669system.cpu0.dcache.demand_mshr_miss_latency::total 10499500 # number of demand (read+write) MSHR miss cycles 670system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10499500 # number of overall MSHR miss cycles 671system.cpu0.dcache.overall_mshr_miss_latency::total 10499500 # number of overall MSHR miss cycles 672system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002475 # mshr miss rate for ReadReq accesses 673system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002475 # mshr miss rate for ReadReq accesses 674system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002177 # mshr miss rate for WriteReq accesses 675system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002177 # mshr miss rate for WriteReq accesses 676system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.476190 # mshr miss rate for SwapReq accesses 677system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.476190 # mshr miss rate for SwapReq accesses 678system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002328 # mshr miss rate for demand accesses 679system.cpu0.dcache.demand_mshr_miss_rate::total 0.002328 # mshr miss rate for demand accesses 680system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002328 # mshr miss rate for overall accesses 681system.cpu0.dcache.overall_mshr_miss_rate::total 0.002328 # mshr miss rate for overall accesses 682system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 25226.804124 # average ReadReq mshr miss latency 683system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 25226.804124 # average ReadReq mshr miss latency 684system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 33768.072289 # average WriteReq mshr miss latency 685system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33768.072289 # average WriteReq mshr miss latency 686system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 17500 # average SwapReq mshr miss latency 687system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 17500 # average SwapReq mshr miss latency 688system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 29165.277778 # average overall mshr miss latency 689system.cpu0.dcache.demand_avg_mshr_miss_latency::total 29165.277778 # average overall mshr miss latency 690system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 29165.277778 # average overall mshr miss latency 691system.cpu0.dcache.overall_avg_mshr_miss_latency::total 29165.277778 # average overall mshr miss latency 692system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 693system.cpu1.numCycles 174084 # number of cpu cycles simulated 694system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 695system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 696system.cpu1.BPredUnit.lookups 52904 # Number of BP lookups 697system.cpu1.BPredUnit.condPredicted 50238 # Number of conditional branches predicted 698system.cpu1.BPredUnit.condIncorrect 1268 # Number of conditional branches incorrect 699system.cpu1.BPredUnit.BTBLookups 46828 # Number of BTB lookups 700system.cpu1.BPredUnit.BTBHits 46138 # Number of BTB hits 701system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 702system.cpu1.BPredUnit.usedRAS 659 # Number of times the RAS was used to get a target. 703system.cpu1.BPredUnit.RASInCorrect 232 # Number of incorrect RAS predictions. 704system.cpu1.fetch.icacheStallCycles 27344 # Number of cycles fetch is stalled on an Icache miss 705system.cpu1.fetch.Insts 297398 # Number of instructions fetch has processed 706system.cpu1.fetch.Branches 52904 # Number of branches that fetch encountered 707system.cpu1.fetch.predictedBranches 46797 # Number of branches that fetch has predicted taken 708system.cpu1.fetch.Cycles 103835 # Number of cycles fetch has run and was not squashing or blocked 709system.cpu1.fetch.SquashCycles 3694 # Number of cycles fetch has spent squashing 710system.cpu1.fetch.BlockedCycles 29305 # Number of cycles fetch has spent blocked 711system.cpu1.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 712system.cpu1.fetch.NoActiveThreadStallCycles 6116 # Number of stall cycles due to no active thread to fetch from 713system.cpu1.fetch.PendingTrapStallCycles 727 # Number of stall cycles due to pending traps 714system.cpu1.fetch.CacheLines 18660 # Number of cache lines fetched 715system.cpu1.fetch.IcacheSquashes 267 # Number of outstanding Icache misses that were squashed 716system.cpu1.fetch.rateDist::samples 169680 # Number of instructions fetched each cycle (Total) 717system.cpu1.fetch.rateDist::mean 1.752699 # Number of instructions fetched each cycle (Total) 718system.cpu1.fetch.rateDist::stdev 2.165176 # Number of instructions fetched each cycle (Total) 719system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 720system.cpu1.fetch.rateDist::0 65845 38.81% 38.81% # Number of instructions fetched each cycle (Total) 721system.cpu1.fetch.rateDist::1 52566 30.98% 69.78% # Number of instructions fetched each cycle (Total) 722system.cpu1.fetch.rateDist::2 5632 3.32% 73.10% # Number of instructions fetched each cycle (Total) 723system.cpu1.fetch.rateDist::3 3204 1.89% 74.99% # Number of instructions fetched each cycle (Total) 724system.cpu1.fetch.rateDist::4 655 0.39% 75.38% # Number of instructions fetched each cycle (Total) 725system.cpu1.fetch.rateDist::5 36566 21.55% 96.93% # Number of instructions fetched each cycle (Total) 726system.cpu1.fetch.rateDist::6 1212 0.71% 97.64% # Number of instructions fetched each cycle (Total) 727system.cpu1.fetch.rateDist::7 766 0.45% 98.09% # Number of instructions fetched each cycle (Total) 728system.cpu1.fetch.rateDist::8 3234 1.91% 100.00% # Number of instructions fetched each cycle (Total) 729system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 730system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 731system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 732system.cpu1.fetch.rateDist::total 169680 # Number of instructions fetched each cycle (Total) 733system.cpu1.fetch.branchRate 0.303899 # Number of branch fetches per cycle 734system.cpu1.fetch.rate 1.708359 # Number of inst fetches per cycle 735system.cpu1.decode.IdleCycles 31981 # Number of cycles decode is idle 736system.cpu1.decode.BlockedCycles 26240 # Number of cycles decode is blocked 737system.cpu1.decode.RunCycles 98388 # Number of cycles decode is running 738system.cpu1.decode.UnblockCycles 4607 # Number of cycles decode is unblocking 739system.cpu1.decode.SquashCycles 2348 # Number of cycles decode is squashing 740system.cpu1.decode.DecodedInsts 293925 # Number of instructions handled by decode 741system.cpu1.rename.SquashCycles 2348 # Number of cycles rename is squashing 742system.cpu1.rename.IdleCycles 32683 # Number of cycles rename is idle 743system.cpu1.rename.BlockCycles 13600 # Number of cycles rename is blocking 744system.cpu1.rename.serializeStallCycles 11858 # count of cycles rename stalled for serializing inst 745system.cpu1.rename.RunCycles 94082 # Number of cycles rename is running 746system.cpu1.rename.UnblockCycles 8993 # Number of cycles rename is unblocking 747system.cpu1.rename.RenamedInsts 291891 # Number of instructions processed by rename 748system.cpu1.rename.LSQFullEvents 40 # Number of times rename has blocked due to LSQ full 749system.cpu1.rename.RenamedOperands 205019 # Number of destination operands rename has renamed 750system.cpu1.rename.RenameLookups 562522 # Number of register rename lookups that rename has made 751system.cpu1.rename.int_rename_lookups 562522 # Number of integer rename lookups 752system.cpu1.rename.CommittedMaps 192184 # Number of HB maps that are committed 753system.cpu1.rename.UndoneMaps 12835 # Number of HB maps that are undone due to squashing 754system.cpu1.rename.serializingInsts 1091 # count of serializing insts renamed 755system.cpu1.rename.tempSerializingInsts 1214 # count of temporary serializing insts renamed 756system.cpu1.rename.skidInsts 11554 # count of insts added to the skid buffer 757system.cpu1.memDep0.insertedLoads 83196 # Number of loads inserted to the mem dependence unit. 758system.cpu1.memDep0.insertedStores 39822 # Number of stores inserted to the mem dependence unit. 759system.cpu1.memDep0.conflictingLoads 39557 # Number of conflicting loads. 760system.cpu1.memDep0.conflictingStores 34785 # Number of conflicting stores. 761system.cpu1.iq.iqInstsAdded 242788 # Number of instructions added to the IQ (excludes non-spec) 762system.cpu1.iq.iqNonSpecInstsAdded 5818 # Number of non-speculative instructions added to the IQ 763system.cpu1.iq.iqInstsIssued 244431 # Number of instructions issued 764system.cpu1.iq.iqSquashedInstsIssued 88 # Number of squashed instructions issued 765system.cpu1.iq.iqSquashedInstsExamined 10770 # Number of squashed instructions iterated over during squash; mainly for profiling 766system.cpu1.iq.iqSquashedOperandsExamined 10393 # Number of squashed operands that are examined and possibly removed from graph 767system.cpu1.iq.iqSquashedNonSpecRemoved 573 # Number of squashed non-spec instructions that were removed 768system.cpu1.iq.issued_per_cycle::samples 169680 # Number of insts issued each cycle 769system.cpu1.iq.issued_per_cycle::mean 1.440541 # Number of insts issued each cycle 770system.cpu1.iq.issued_per_cycle::stdev 1.314007 # Number of insts issued each cycle 771system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 772system.cpu1.iq.issued_per_cycle::0 63213 37.25% 37.25% # Number of insts issued each cycle 773system.cpu1.iq.issued_per_cycle::1 21011 12.38% 49.64% # Number of insts issued each cycle 774system.cpu1.iq.issued_per_cycle::2 39930 23.53% 73.17% # Number of insts issued each cycle 775system.cpu1.iq.issued_per_cycle::3 40650 23.96% 97.13% # Number of insts issued each cycle 776system.cpu1.iq.issued_per_cycle::4 3306 1.95% 99.07% # Number of insts issued each cycle 777system.cpu1.iq.issued_per_cycle::5 1205 0.71% 99.78% # Number of insts issued each cycle 778system.cpu1.iq.issued_per_cycle::6 253 0.15% 99.93% # Number of insts issued each cycle 779system.cpu1.iq.issued_per_cycle::7 53 0.03% 99.97% # Number of insts issued each cycle 780system.cpu1.iq.issued_per_cycle::8 59 0.03% 100.00% # Number of insts issued each cycle 781system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 782system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 783system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 784system.cpu1.iq.issued_per_cycle::total 169680 # Number of insts issued each cycle 785system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 786system.cpu1.iq.fu_full::IntAlu 17 5.76% 5.76% # attempts to use FU when none available 787system.cpu1.iq.fu_full::IntMult 0 0.00% 5.76% # attempts to use FU when none available 788system.cpu1.iq.fu_full::IntDiv 0 0.00% 5.76% # attempts to use FU when none available 789system.cpu1.iq.fu_full::FloatAdd 0 0.00% 5.76% # attempts to use FU when none available 790system.cpu1.iq.fu_full::FloatCmp 0 0.00% 5.76% # attempts to use FU when none available 791system.cpu1.iq.fu_full::FloatCvt 0 0.00% 5.76% # attempts to use FU when none available 792system.cpu1.iq.fu_full::FloatMult 0 0.00% 5.76% # attempts to use FU when none available 793system.cpu1.iq.fu_full::FloatDiv 0 0.00% 5.76% # attempts to use FU when none available 794system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 5.76% # attempts to use FU when none available 795system.cpu1.iq.fu_full::SimdAdd 0 0.00% 5.76% # attempts to use FU when none available 796system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 5.76% # attempts to use FU when none available 797system.cpu1.iq.fu_full::SimdAlu 0 0.00% 5.76% # attempts to use FU when none available 798system.cpu1.iq.fu_full::SimdCmp 0 0.00% 5.76% # attempts to use FU when none available 799system.cpu1.iq.fu_full::SimdCvt 0 0.00% 5.76% # attempts to use FU when none available 800system.cpu1.iq.fu_full::SimdMisc 0 0.00% 5.76% # attempts to use FU when none available 801system.cpu1.iq.fu_full::SimdMult 0 0.00% 5.76% # attempts to use FU when none available 802system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 5.76% # attempts to use FU when none available 803system.cpu1.iq.fu_full::SimdShift 0 0.00% 5.76% # attempts to use FU when none available 804system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 5.76% # attempts to use FU when none available 805system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 5.76% # attempts to use FU when none available 806system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 5.76% # attempts to use FU when none available 807system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 5.76% # attempts to use FU when none available 808system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 5.76% # attempts to use FU when none available 809system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 5.76% # attempts to use FU when none available 810system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 5.76% # attempts to use FU when none available 811system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 5.76% # attempts to use FU when none available 812system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 5.76% # attempts to use FU when none available 813system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.76% # attempts to use FU when none available 814system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 5.76% # attempts to use FU when none available 815system.cpu1.iq.fu_full::MemRead 68 23.05% 28.81% # attempts to use FU when none available 816system.cpu1.iq.fu_full::MemWrite 210 71.19% 100.00% # attempts to use FU when none available 817system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 818system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 819system.cpu1.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 820system.cpu1.iq.FU_type_0::IntAlu 118248 48.38% 48.38% # Type of FU issued 821system.cpu1.iq.FU_type_0::IntMult 0 0.00% 48.38% # Type of FU issued 822system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 48.38% # Type of FU issued 823system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 48.38% # Type of FU issued 824system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 48.38% # Type of FU issued 825system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 48.38% # Type of FU issued 826system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 48.38% # Type of FU issued 827system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 48.38% # Type of FU issued 828system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 48.38% # Type of FU issued 829system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 48.38% # Type of FU issued 830system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 48.38% # Type of FU issued 831system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 48.38% # Type of FU issued 832system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 48.38% # Type of FU issued 833system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 48.38% # Type of FU issued 834system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 48.38% # Type of FU issued 835system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 48.38% # Type of FU issued 836system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 48.38% # Type of FU issued 837system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 48.38% # Type of FU issued 838system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.38% # Type of FU issued 839system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 48.38% # Type of FU issued 840system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.38% # Type of FU issued 841system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.38% # Type of FU issued 842system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.38% # Type of FU issued 843system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.38% # Type of FU issued 844system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.38% # Type of FU issued 845system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.38% # Type of FU issued 846system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 48.38% # Type of FU issued 847system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.38% # Type of FU issued 848system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.38% # Type of FU issued 849system.cpu1.iq.FU_type_0::MemRead 87044 35.61% 83.99% # Type of FU issued 850system.cpu1.iq.FU_type_0::MemWrite 39139 16.01% 100.00% # Type of FU issued 851system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 852system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 853system.cpu1.iq.FU_type_0::total 244431 # Type of FU issued 854system.cpu1.iq.rate 1.404098 # Inst issue rate 855system.cpu1.iq.fu_busy_cnt 295 # FU busy when requested 856system.cpu1.iq.fu_busy_rate 0.001207 # FU busy rate (busy events/executed inst) 857system.cpu1.iq.int_inst_queue_reads 658925 # Number of integer instruction queue reads 858system.cpu1.iq.int_inst_queue_writes 259421 # Number of integer instruction queue writes 859system.cpu1.iq.int_inst_queue_wakeup_accesses 242675 # Number of integer instruction queue wakeup accesses 860system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads 861system.cpu1.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes 862system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses 863system.cpu1.iq.int_alu_accesses 244726 # Number of integer alu accesses 864system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses 865system.cpu1.iew.lsq.thread0.forwLoads 34549 # Number of loads that had data forwarded from stores 866system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 867system.cpu1.iew.lsq.thread0.squashedLoads 2395 # Number of loads squashed 868system.cpu1.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed 869system.cpu1.iew.lsq.thread0.memOrderViolation 45 # Number of memory ordering violations 870system.cpu1.iew.lsq.thread0.squashedStores 1432 # Number of stores squashed 871system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 872system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 873system.cpu1.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 874system.cpu1.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked 875system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle 876system.cpu1.iew.iewSquashCycles 2348 # Number of cycles IEW is squashing 877system.cpu1.iew.iewBlockCycles 954 # Number of cycles IEW is blocking 878system.cpu1.iew.iewUnblockCycles 69 # Number of cycles IEW is unblocking 879system.cpu1.iew.iewDispatchedInsts 289058 # Number of instructions dispatched to IQ 880system.cpu1.iew.iewDispSquashedInsts 345 # Number of squashed instructions skipped by dispatch 881system.cpu1.iew.iewDispLoadInsts 83196 # Number of dispatched load instructions 882system.cpu1.iew.iewDispStoreInsts 39822 # Number of dispatched store instructions 883system.cpu1.iew.iewDispNonSpecInsts 1054 # Number of dispatched non-speculative instructions 884system.cpu1.iew.iewIQFullEvents 70 # Number of times the IQ has become full, causing a stall 885system.cpu1.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 886system.cpu1.iew.memOrderViolationEvents 45 # Number of memory order violations 887system.cpu1.iew.predictedTakenIncorrect 455 # Number of branches that were predicted taken incorrectly 888system.cpu1.iew.predictedNotTakenIncorrect 930 # Number of branches that were predicted not taken incorrectly 889system.cpu1.iew.branchMispredicts 1385 # Number of branch mispredicts detected at execute 890system.cpu1.iew.iewExecutedInsts 243269 # Number of executed instructions 891system.cpu1.iew.iewExecLoadInsts 82226 # Number of load instructions executed 892system.cpu1.iew.iewExecSquashedInsts 1162 # Number of squashed instructions skipped in execute 893system.cpu1.iew.exec_swp 0 # number of swp insts executed 894system.cpu1.iew.exec_nop 40452 # number of nop insts executed 895system.cpu1.iew.exec_refs 121286 # number of memory reference insts executed 896system.cpu1.iew.exec_branches 49717 # Number of branches executed 897system.cpu1.iew.exec_stores 39060 # Number of stores executed 898system.cpu1.iew.exec_rate 1.397423 # Inst execution rate 899system.cpu1.iew.wb_sent 242942 # cumulative count of insts sent to commit 900system.cpu1.iew.wb_count 242675 # cumulative count of insts written-back 901system.cpu1.iew.wb_producers 138073 # num instructions producing a value 902system.cpu1.iew.wb_consumers 142763 # num instructions consuming a value 903system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 904system.cpu1.iew.wb_rate 1.394011 # insts written-back per cycle 905system.cpu1.iew.wb_fanout 0.967148 # average fanout of values written-back 906system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 907system.cpu1.commit.commitSquashedInsts 12362 # The number of squashed insts skipped by commit 908system.cpu1.commit.commitNonSpecStalls 5245 # The number of times commit has been forced to stall to communicate backwards 909system.cpu1.commit.branchMispredicts 1268 # The number of times a branch was mispredicted 910system.cpu1.commit.committed_per_cycle::samples 161217 # Number of insts commited each cycle 911system.cpu1.commit.committed_per_cycle::mean 1.716302 # Number of insts commited each cycle 912system.cpu1.commit.committed_per_cycle::stdev 2.045846 # Number of insts commited each cycle 913system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 914system.cpu1.commit.committed_per_cycle::0 62248 38.61% 38.61% # Number of insts commited each cycle 915system.cpu1.commit.committed_per_cycle::1 47764 29.63% 68.24% # Number of insts commited each cycle 916system.cpu1.commit.committed_per_cycle::2 6052 3.75% 71.99% # Number of insts commited each cycle 917system.cpu1.commit.committed_per_cycle::3 6179 3.83% 75.83% # Number of insts commited each cycle 918system.cpu1.commit.committed_per_cycle::4 1571 0.97% 76.80% # Number of insts commited each cycle 919system.cpu1.commit.committed_per_cycle::5 35062 21.75% 98.55% # Number of insts commited each cycle 920system.cpu1.commit.committed_per_cycle::6 510 0.32% 98.86% # Number of insts commited each cycle 921system.cpu1.commit.committed_per_cycle::7 1010 0.63% 99.49% # Number of insts commited each cycle 922system.cpu1.commit.committed_per_cycle::8 821 0.51% 100.00% # Number of insts commited each cycle 923system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 924system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 925system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 926system.cpu1.commit.committed_per_cycle::total 161217 # Number of insts commited each cycle 927system.cpu1.commit.committedInsts 276697 # Number of instructions committed 928system.cpu1.commit.committedOps 276697 # Number of ops (including micro ops) committed 929system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed 930system.cpu1.commit.refs 119191 # Number of memory references committed 931system.cpu1.commit.loads 80801 # Number of loads committed 932system.cpu1.commit.membars 4532 # Number of memory barriers committed 933system.cpu1.commit.branches 48885 # Number of branches committed 934system.cpu1.commit.fp_insts 0 # Number of committed floating point instructions. 935system.cpu1.commit.int_insts 190199 # Number of committed integer instructions. 936system.cpu1.commit.function_calls 322 # Number of function calls committed. 937system.cpu1.commit.bw_lim_events 821 # number cycles where commit BW limit reached 938system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits 939system.cpu1.rob.rob_reads 448868 # The number of ROB reads 940system.cpu1.rob.rob_writes 580470 # The number of ROB writes 941system.cpu1.timesIdled 225 # Number of times that the entire CPU went into an idle state and unscheduled itself 942system.cpu1.idleCycles 4404 # Total number of cycles that the CPU has spent unscheduled due to idling 943system.cpu1.quiesceCycles 35576 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 944system.cpu1.committedInsts 232489 # Number of Instructions Simulated 945system.cpu1.committedOps 232489 # Number of Ops (including micro ops) Simulated 946system.cpu1.committedInsts_total 232489 # Number of Instructions Simulated 947system.cpu1.cpi 0.748784 # CPI: Cycles Per Instruction 948system.cpu1.cpi_total 0.748784 # CPI: Total CPI of All Threads 949system.cpu1.ipc 1.335499 # IPC: Instructions Per Cycle 950system.cpu1.ipc_total 1.335499 # IPC: Total IPC of All Threads 951system.cpu1.int_regfile_reads 422509 # number of integer regfile reads 952system.cpu1.int_regfile_writes 197149 # number of integer regfile writes 953system.cpu1.fp_regfile_writes 64 # number of floating regfile writes 954system.cpu1.misc_regfile_reads 122869 # number of misc regfile reads 955system.cpu1.misc_regfile_writes 648 # number of misc regfile writes 956system.cpu1.icache.replacements 317 # number of replacements 957system.cpu1.icache.tagsinuse 85.783317 # Cycle average of tags in use 958system.cpu1.icache.total_refs 18178 # Total number of references to valid blocks. 959system.cpu1.icache.sampled_refs 425 # Sample count of references to valid blocks. 960system.cpu1.icache.avg_refs 42.771765 # Average number of references to valid blocks. 961system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 962system.cpu1.icache.occ_blocks::cpu1.inst 85.783317 # Average occupied blocks per requestor 963system.cpu1.icache.occ_percent::cpu1.inst 0.167546 # Average percentage of cache occupancy 964system.cpu1.icache.occ_percent::total 0.167546 # Average percentage of cache occupancy 965system.cpu1.icache.ReadReq_hits::cpu1.inst 18178 # number of ReadReq hits 966system.cpu1.icache.ReadReq_hits::total 18178 # number of ReadReq hits 967system.cpu1.icache.demand_hits::cpu1.inst 18178 # number of demand (read+write) hits 968system.cpu1.icache.demand_hits::total 18178 # number of demand (read+write) hits 969system.cpu1.icache.overall_hits::cpu1.inst 18178 # number of overall hits 970system.cpu1.icache.overall_hits::total 18178 # number of overall hits 971system.cpu1.icache.ReadReq_misses::cpu1.inst 482 # number of ReadReq misses 972system.cpu1.icache.ReadReq_misses::total 482 # number of ReadReq misses 973system.cpu1.icache.demand_misses::cpu1.inst 482 # number of demand (read+write) misses 974system.cpu1.icache.demand_misses::total 482 # number of demand (read+write) misses 975system.cpu1.icache.overall_misses::cpu1.inst 482 # number of overall misses 976system.cpu1.icache.overall_misses::total 482 # number of overall misses 977system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 9898500 # number of ReadReq miss cycles 978system.cpu1.icache.ReadReq_miss_latency::total 9898500 # number of ReadReq miss cycles 979system.cpu1.icache.demand_miss_latency::cpu1.inst 9898500 # number of demand (read+write) miss cycles 980system.cpu1.icache.demand_miss_latency::total 9898500 # number of demand (read+write) miss cycles 981system.cpu1.icache.overall_miss_latency::cpu1.inst 9898500 # number of overall miss cycles 982system.cpu1.icache.overall_miss_latency::total 9898500 # number of overall miss cycles 983system.cpu1.icache.ReadReq_accesses::cpu1.inst 18660 # number of ReadReq accesses(hits+misses) 984system.cpu1.icache.ReadReq_accesses::total 18660 # number of ReadReq accesses(hits+misses) 985system.cpu1.icache.demand_accesses::cpu1.inst 18660 # number of demand (read+write) accesses 986system.cpu1.icache.demand_accesses::total 18660 # number of demand (read+write) accesses 987system.cpu1.icache.overall_accesses::cpu1.inst 18660 # number of overall (read+write) accesses 988system.cpu1.icache.overall_accesses::total 18660 # number of overall (read+write) accesses 989system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.025831 # miss rate for ReadReq accesses 990system.cpu1.icache.ReadReq_miss_rate::total 0.025831 # miss rate for ReadReq accesses 991system.cpu1.icache.demand_miss_rate::cpu1.inst 0.025831 # miss rate for demand accesses 992system.cpu1.icache.demand_miss_rate::total 0.025831 # miss rate for demand accesses 993system.cpu1.icache.overall_miss_rate::cpu1.inst 0.025831 # miss rate for overall accesses 994system.cpu1.icache.overall_miss_rate::total 0.025831 # miss rate for overall accesses 995system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 20536.307054 # average ReadReq miss latency 996system.cpu1.icache.ReadReq_avg_miss_latency::total 20536.307054 # average ReadReq miss latency 997system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 20536.307054 # average overall miss latency 998system.cpu1.icache.demand_avg_miss_latency::total 20536.307054 # average overall miss latency 999system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 20536.307054 # average overall miss latency 1000system.cpu1.icache.overall_avg_miss_latency::total 20536.307054 # average overall miss latency 1001system.cpu1.icache.blocked_cycles::no_mshrs 44 # number of cycles access was blocked 1002system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1003system.cpu1.icache.blocked::no_mshrs 1 # number of cycles access was blocked 1004system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1005system.cpu1.icache.avg_blocked_cycles::no_mshrs 44 # average number of cycles each access was blocked 1006system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1007system.cpu1.icache.fast_writes 0 # number of fast writes performed 1008system.cpu1.icache.cache_copies 0 # number of cache copies performed 1009system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 57 # number of ReadReq MSHR hits 1010system.cpu1.icache.ReadReq_mshr_hits::total 57 # number of ReadReq MSHR hits 1011system.cpu1.icache.demand_mshr_hits::cpu1.inst 57 # number of demand (read+write) MSHR hits 1012system.cpu1.icache.demand_mshr_hits::total 57 # number of demand (read+write) MSHR hits 1013system.cpu1.icache.overall_mshr_hits::cpu1.inst 57 # number of overall MSHR hits 1014system.cpu1.icache.overall_mshr_hits::total 57 # number of overall MSHR hits 1015system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 425 # number of ReadReq MSHR misses 1016system.cpu1.icache.ReadReq_mshr_misses::total 425 # number of ReadReq MSHR misses 1017system.cpu1.icache.demand_mshr_misses::cpu1.inst 425 # number of demand (read+write) MSHR misses 1018system.cpu1.icache.demand_mshr_misses::total 425 # number of demand (read+write) MSHR misses 1019system.cpu1.icache.overall_mshr_misses::cpu1.inst 425 # number of overall MSHR misses 1020system.cpu1.icache.overall_mshr_misses::total 425 # number of overall MSHR misses 1021system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 8055000 # number of ReadReq MSHR miss cycles 1022system.cpu1.icache.ReadReq_mshr_miss_latency::total 8055000 # number of ReadReq MSHR miss cycles 1023system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 8055000 # number of demand (read+write) MSHR miss cycles 1024system.cpu1.icache.demand_mshr_miss_latency::total 8055000 # number of demand (read+write) MSHR miss cycles 1025system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 8055000 # number of overall MSHR miss cycles 1026system.cpu1.icache.overall_mshr_miss_latency::total 8055000 # number of overall MSHR miss cycles 1027system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.022776 # mshr miss rate for ReadReq accesses 1028system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.022776 # mshr miss rate for ReadReq accesses 1029system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.022776 # mshr miss rate for demand accesses 1030system.cpu1.icache.demand_mshr_miss_rate::total 0.022776 # mshr miss rate for demand accesses 1031system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.022776 # mshr miss rate for overall accesses 1032system.cpu1.icache.overall_mshr_miss_rate::total 0.022776 # mshr miss rate for overall accesses 1033system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 18952.941176 # average ReadReq mshr miss latency 1034system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 18952.941176 # average ReadReq mshr miss latency 1035system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 18952.941176 # average overall mshr miss latency 1036system.cpu1.icache.demand_avg_mshr_miss_latency::total 18952.941176 # average overall mshr miss latency 1037system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 18952.941176 # average overall mshr miss latency 1038system.cpu1.icache.overall_avg_mshr_miss_latency::total 18952.941176 # average overall mshr miss latency 1039system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1040system.cpu1.dcache.replacements 0 # number of replacements 1041system.cpu1.dcache.tagsinuse 27.224773 # Cycle average of tags in use 1042system.cpu1.dcache.total_refs 44406 # Total number of references to valid blocks. 1043system.cpu1.dcache.sampled_refs 28 # Sample count of references to valid blocks. 1044system.cpu1.dcache.avg_refs 1585.928571 # Average number of references to valid blocks. 1045system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1046system.cpu1.dcache.occ_blocks::cpu1.data 27.224773 # Average occupied blocks per requestor 1047system.cpu1.dcache.occ_percent::cpu1.data 0.053173 # Average percentage of cache occupancy 1048system.cpu1.dcache.occ_percent::total 0.053173 # Average percentage of cache occupancy 1049system.cpu1.dcache.ReadReq_hits::cpu1.data 47254 # number of ReadReq hits 1050system.cpu1.dcache.ReadReq_hits::total 47254 # number of ReadReq hits 1051system.cpu1.dcache.WriteReq_hits::cpu1.data 38186 # number of WriteReq hits 1052system.cpu1.dcache.WriteReq_hits::total 38186 # number of WriteReq hits 1053system.cpu1.dcache.SwapReq_hits::cpu1.data 14 # number of SwapReq hits 1054system.cpu1.dcache.SwapReq_hits::total 14 # number of SwapReq hits 1055system.cpu1.dcache.demand_hits::cpu1.data 85440 # number of demand (read+write) hits 1056system.cpu1.dcache.demand_hits::total 85440 # number of demand (read+write) hits 1057system.cpu1.dcache.overall_hits::cpu1.data 85440 # number of overall hits 1058system.cpu1.dcache.overall_hits::total 85440 # number of overall hits 1059system.cpu1.dcache.ReadReq_misses::cpu1.data 407 # number of ReadReq misses 1060system.cpu1.dcache.ReadReq_misses::total 407 # number of ReadReq misses 1061system.cpu1.dcache.WriteReq_misses::cpu1.data 137 # number of WriteReq misses 1062system.cpu1.dcache.WriteReq_misses::total 137 # number of WriteReq misses 1063system.cpu1.dcache.SwapReq_misses::cpu1.data 53 # number of SwapReq misses 1064system.cpu1.dcache.SwapReq_misses::total 53 # number of SwapReq misses 1065system.cpu1.dcache.demand_misses::cpu1.data 544 # number of demand (read+write) misses 1066system.cpu1.dcache.demand_misses::total 544 # number of demand (read+write) misses 1067system.cpu1.dcache.overall_misses::cpu1.data 544 # number of overall misses 1068system.cpu1.dcache.overall_misses::total 544 # number of overall misses 1069system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 6159500 # number of ReadReq miss cycles 1070system.cpu1.dcache.ReadReq_miss_latency::total 6159500 # number of ReadReq miss cycles 1071system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2649500 # number of WriteReq miss cycles 1072system.cpu1.dcache.WriteReq_miss_latency::total 2649500 # number of WriteReq miss cycles 1073system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 528500 # number of SwapReq miss cycles 1074system.cpu1.dcache.SwapReq_miss_latency::total 528500 # number of SwapReq miss cycles 1075system.cpu1.dcache.demand_miss_latency::cpu1.data 8809000 # number of demand (read+write) miss cycles 1076system.cpu1.dcache.demand_miss_latency::total 8809000 # number of demand (read+write) miss cycles 1077system.cpu1.dcache.overall_miss_latency::cpu1.data 8809000 # number of overall miss cycles 1078system.cpu1.dcache.overall_miss_latency::total 8809000 # number of overall miss cycles 1079system.cpu1.dcache.ReadReq_accesses::cpu1.data 47661 # number of ReadReq accesses(hits+misses) 1080system.cpu1.dcache.ReadReq_accesses::total 47661 # number of ReadReq accesses(hits+misses) 1081system.cpu1.dcache.WriteReq_accesses::cpu1.data 38323 # number of WriteReq accesses(hits+misses) 1082system.cpu1.dcache.WriteReq_accesses::total 38323 # number of WriteReq accesses(hits+misses) 1083system.cpu1.dcache.SwapReq_accesses::cpu1.data 67 # number of SwapReq accesses(hits+misses) 1084system.cpu1.dcache.SwapReq_accesses::total 67 # number of SwapReq accesses(hits+misses) 1085system.cpu1.dcache.demand_accesses::cpu1.data 85984 # number of demand (read+write) accesses 1086system.cpu1.dcache.demand_accesses::total 85984 # number of demand (read+write) accesses 1087system.cpu1.dcache.overall_accesses::cpu1.data 85984 # number of overall (read+write) accesses 1088system.cpu1.dcache.overall_accesses::total 85984 # number of overall (read+write) accesses 1089system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.008539 # miss rate for ReadReq accesses 1090system.cpu1.dcache.ReadReq_miss_rate::total 0.008539 # miss rate for ReadReq accesses 1091system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.003575 # miss rate for WriteReq accesses 1092system.cpu1.dcache.WriteReq_miss_rate::total 0.003575 # miss rate for WriteReq accesses 1093system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.791045 # miss rate for SwapReq accesses 1094system.cpu1.dcache.SwapReq_miss_rate::total 0.791045 # miss rate for SwapReq accesses 1095system.cpu1.dcache.demand_miss_rate::cpu1.data 0.006327 # miss rate for demand accesses 1096system.cpu1.dcache.demand_miss_rate::total 0.006327 # miss rate for demand accesses 1097system.cpu1.dcache.overall_miss_rate::cpu1.data 0.006327 # miss rate for overall accesses 1098system.cpu1.dcache.overall_miss_rate::total 0.006327 # miss rate for overall accesses 1099system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15133.906634 # average ReadReq miss latency 1100system.cpu1.dcache.ReadReq_avg_miss_latency::total 15133.906634 # average ReadReq miss latency 1101system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 19339.416058 # average WriteReq miss latency 1102system.cpu1.dcache.WriteReq_avg_miss_latency::total 19339.416058 # average WriteReq miss latency 1103system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 9971.698113 # average SwapReq miss latency 1104system.cpu1.dcache.SwapReq_avg_miss_latency::total 9971.698113 # average SwapReq miss latency 1105system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 16193.014706 # average overall miss latency 1106system.cpu1.dcache.demand_avg_miss_latency::total 16193.014706 # average overall miss latency 1107system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16193.014706 # average overall miss latency 1108system.cpu1.dcache.overall_avg_miss_latency::total 16193.014706 # average overall miss latency 1109system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1110system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1111system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1112system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1113system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1114system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1115system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1116system.cpu1.dcache.cache_copies 0 # number of cache copies performed 1117system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 252 # number of ReadReq MSHR hits 1118system.cpu1.dcache.ReadReq_mshr_hits::total 252 # number of ReadReq MSHR hits 1119system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 32 # number of WriteReq MSHR hits 1120system.cpu1.dcache.WriteReq_mshr_hits::total 32 # number of WriteReq MSHR hits 1121system.cpu1.dcache.demand_mshr_hits::cpu1.data 284 # number of demand (read+write) MSHR hits 1122system.cpu1.dcache.demand_mshr_hits::total 284 # number of demand (read+write) MSHR hits 1123system.cpu1.dcache.overall_mshr_hits::cpu1.data 284 # number of overall MSHR hits 1124system.cpu1.dcache.overall_mshr_hits::total 284 # number of overall MSHR hits 1125system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 155 # number of ReadReq MSHR misses 1126system.cpu1.dcache.ReadReq_mshr_misses::total 155 # number of ReadReq MSHR misses 1127system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 105 # number of WriteReq MSHR misses 1128system.cpu1.dcache.WriteReq_mshr_misses::total 105 # number of WriteReq MSHR misses 1129system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 53 # number of SwapReq MSHR misses 1130system.cpu1.dcache.SwapReq_mshr_misses::total 53 # number of SwapReq MSHR misses 1131system.cpu1.dcache.demand_mshr_misses::cpu1.data 260 # number of demand (read+write) MSHR misses 1132system.cpu1.dcache.demand_mshr_misses::total 260 # number of demand (read+write) MSHR misses 1133system.cpu1.dcache.overall_mshr_misses::cpu1.data 260 # number of overall MSHR misses 1134system.cpu1.dcache.overall_mshr_misses::total 260 # number of overall MSHR misses 1135system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1530000 # number of ReadReq MSHR miss cycles 1136system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1530000 # number of ReadReq MSHR miss cycles 1137system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1383500 # number of WriteReq MSHR miss cycles 1138system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1383500 # number of WriteReq MSHR miss cycles 1139system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 422500 # number of SwapReq MSHR miss cycles 1140system.cpu1.dcache.SwapReq_mshr_miss_latency::total 422500 # number of SwapReq MSHR miss cycles 1141system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2913500 # number of demand (read+write) MSHR miss cycles 1142system.cpu1.dcache.demand_mshr_miss_latency::total 2913500 # number of demand (read+write) MSHR miss cycles 1143system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2913500 # number of overall MSHR miss cycles 1144system.cpu1.dcache.overall_mshr_miss_latency::total 2913500 # number of overall MSHR miss cycles 1145system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003252 # mshr miss rate for ReadReq accesses 1146system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003252 # mshr miss rate for ReadReq accesses 1147system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.002740 # mshr miss rate for WriteReq accesses 1148system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.002740 # mshr miss rate for WriteReq accesses 1149system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.791045 # mshr miss rate for SwapReq accesses 1150system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.791045 # mshr miss rate for SwapReq accesses 1151system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.003024 # mshr miss rate for demand accesses 1152system.cpu1.dcache.demand_mshr_miss_rate::total 0.003024 # mshr miss rate for demand accesses 1153system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.003024 # mshr miss rate for overall accesses 1154system.cpu1.dcache.overall_mshr_miss_rate::total 0.003024 # mshr miss rate for overall accesses 1155system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 9870.967742 # average ReadReq mshr miss latency 1156system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 9870.967742 # average ReadReq mshr miss latency 1157system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 13176.190476 # average WriteReq mshr miss latency 1158system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 13176.190476 # average WriteReq mshr miss latency 1159system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 7971.698113 # average SwapReq mshr miss latency 1160system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 7971.698113 # average SwapReq mshr miss latency 1161system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 11205.769231 # average overall mshr miss latency 1162system.cpu1.dcache.demand_avg_mshr_miss_latency::total 11205.769231 # average overall mshr miss latency 1163system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 11205.769231 # average overall mshr miss latency 1164system.cpu1.dcache.overall_avg_mshr_miss_latency::total 11205.769231 # average overall mshr miss latency 1165system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1166system.cpu2.numCycles 173759 # number of cpu cycles simulated 1167system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started 1168system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed 1169system.cpu2.BPredUnit.lookups 43658 # Number of BP lookups 1170system.cpu2.BPredUnit.condPredicted 40905 # Number of conditional branches predicted 1171system.cpu2.BPredUnit.condIncorrect 1282 # Number of conditional branches incorrect 1172system.cpu2.BPredUnit.BTBLookups 37514 # Number of BTB lookups 1173system.cpu2.BPredUnit.BTBHits 36718 # Number of BTB hits 1174system.cpu2.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 1175system.cpu2.BPredUnit.usedRAS 654 # Number of times the RAS was used to get a target. 1176system.cpu2.BPredUnit.RASInCorrect 232 # Number of incorrect RAS predictions. 1177system.cpu2.fetch.icacheStallCycles 33388 # Number of cycles fetch is stalled on an Icache miss 1178system.cpu2.fetch.Insts 235313 # Number of instructions fetch has processed 1179system.cpu2.fetch.Branches 43658 # Number of branches that fetch encountered 1180system.cpu2.fetch.predictedBranches 37372 # Number of branches that fetch has predicted taken 1181system.cpu2.fetch.Cycles 88227 # Number of cycles fetch has run and was not squashing or blocked 1182system.cpu2.fetch.SquashCycles 3786 # Number of cycles fetch has spent squashing 1183system.cpu2.fetch.BlockedCycles 41179 # Number of cycles fetch has spent blocked 1184system.cpu2.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 1185system.cpu2.fetch.NoActiveThreadStallCycles 6107 # Number of stall cycles due to no active thread to fetch from 1186system.cpu2.fetch.PendingTrapStallCycles 690 # Number of stall cycles due to pending traps 1187system.cpu2.fetch.CacheLines 25041 # Number of cache lines fetched 1188system.cpu2.fetch.IcacheSquashes 268 # Number of outstanding Icache misses that were squashed 1189system.cpu2.fetch.rateDist::samples 172022 # Number of instructions fetched each cycle (Total) 1190system.cpu2.fetch.rateDist::mean 1.367924 # Number of instructions fetched each cycle (Total) 1191system.cpu2.fetch.rateDist::stdev 2.005612 # Number of instructions fetched each cycle (Total) 1192system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 1193system.cpu2.fetch.rateDist::0 83795 48.71% 48.71% # Number of instructions fetched each cycle (Total) 1194system.cpu2.fetch.rateDist::1 46271 26.90% 75.61% # Number of instructions fetched each cycle (Total) 1195system.cpu2.fetch.rateDist::2 8744 5.08% 80.69% # Number of instructions fetched each cycle (Total) 1196system.cpu2.fetch.rateDist::3 3171 1.84% 82.54% # Number of instructions fetched each cycle (Total) 1197system.cpu2.fetch.rateDist::4 732 0.43% 82.96% # Number of instructions fetched each cycle (Total) 1198system.cpu2.fetch.rateDist::5 24119 14.02% 96.98% # Number of instructions fetched each cycle (Total) 1199system.cpu2.fetch.rateDist::6 1119 0.65% 97.63% # Number of instructions fetched each cycle (Total) 1200system.cpu2.fetch.rateDist::7 764 0.44% 98.08% # Number of instructions fetched each cycle (Total) 1201system.cpu2.fetch.rateDist::8 3307 1.92% 100.00% # Number of instructions fetched each cycle (Total) 1202system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 1203system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1204system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 1205system.cpu2.fetch.rateDist::total 172022 # Number of instructions fetched each cycle (Total) 1206system.cpu2.fetch.branchRate 0.251256 # Number of branch fetches per cycle 1207system.cpu2.fetch.rate 1.354249 # Number of inst fetches per cycle 1208system.cpu2.decode.IdleCycles 40935 # Number of cycles decode is idle 1209system.cpu2.decode.BlockedCycles 35177 # Number of cycles decode is blocked 1210system.cpu2.decode.RunCycles 79843 # Number of cycles decode is running 1211system.cpu2.decode.UnblockCycles 7534 # Number of cycles decode is unblocking 1212system.cpu2.decode.SquashCycles 2426 # Number of cycles decode is squashing 1213system.cpu2.decode.DecodedInsts 231751 # Number of instructions handled by decode 1214system.cpu2.rename.SquashCycles 2426 # Number of cycles rename is squashing 1215system.cpu2.rename.IdleCycles 41648 # Number of cycles rename is idle 1216system.cpu2.rename.BlockCycles 22387 # Number of cycles rename is blocking 1217system.cpu2.rename.serializeStallCycles 11999 # count of cycles rename stalled for serializing inst 1218system.cpu2.rename.RunCycles 72579 # Number of cycles rename is running 1219system.cpu2.rename.UnblockCycles 14876 # Number of cycles rename is unblocking 1220system.cpu2.rename.RenamedInsts 229374 # Number of instructions processed by rename 1221system.cpu2.rename.IQFullEvents 1 # Number of times rename has blocked due to IQ full 1222system.cpu2.rename.LSQFullEvents 35 # Number of times rename has blocked due to LSQ full 1223system.cpu2.rename.RenamedOperands 158064 # Number of destination operands rename has renamed 1224system.cpu2.rename.RenameLookups 425055 # Number of register rename lookups that rename has made 1225system.cpu2.rename.int_rename_lookups 425055 # Number of integer rename lookups 1226system.cpu2.rename.CommittedMaps 145196 # Number of HB maps that are committed 1227system.cpu2.rename.UndoneMaps 12868 # Number of HB maps that are undone due to squashing 1228system.cpu2.rename.serializingInsts 1106 # count of serializing insts renamed 1229system.cpu2.rename.tempSerializingInsts 1225 # count of temporary serializing insts renamed 1230system.cpu2.rename.skidInsts 17601 # count of insts added to the skid buffer 1231system.cpu2.memDep0.insertedLoads 61347 # Number of loads inserted to the mem dependence unit. 1232system.cpu2.memDep0.insertedStores 27349 # Number of stores inserted to the mem dependence unit. 1233system.cpu2.memDep0.conflictingLoads 30218 # Number of conflicting loads. 1234system.cpu2.memDep0.conflictingStores 22307 # Number of conflicting stores. 1235system.cpu2.iq.iqInstsAdded 186544 # Number of instructions added to the IQ (excludes non-spec) 1236system.cpu2.iq.iqNonSpecInstsAdded 8963 # Number of non-speculative instructions added to the IQ 1237system.cpu2.iq.iqInstsIssued 190992 # Number of instructions issued 1238system.cpu2.iq.iqSquashedInstsIssued 109 # Number of squashed instructions issued 1239system.cpu2.iq.iqSquashedInstsExamined 11074 # Number of squashed instructions iterated over during squash; mainly for profiling 1240system.cpu2.iq.iqSquashedOperandsExamined 10969 # Number of squashed operands that are examined and possibly removed from graph 1241system.cpu2.iq.iqSquashedNonSpecRemoved 650 # Number of squashed non-spec instructions that were removed 1242system.cpu2.iq.issued_per_cycle::samples 172022 # Number of insts issued each cycle 1243system.cpu2.iq.issued_per_cycle::mean 1.110277 # Number of insts issued each cycle 1244system.cpu2.iq.issued_per_cycle::stdev 1.273783 # Number of insts issued each cycle 1245system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 1246system.cpu2.iq.issued_per_cycle::0 81441 47.34% 47.34% # Number of insts issued each cycle 1247system.cpu2.iq.issued_per_cycle::1 30126 17.51% 64.86% # Number of insts issued each cycle 1248system.cpu2.iq.issued_per_cycle::2 27409 15.93% 80.79% # Number of insts issued each cycle 1249system.cpu2.iq.issued_per_cycle::3 28202 16.39% 97.18% # Number of insts issued each cycle 1250system.cpu2.iq.issued_per_cycle::4 3303 1.92% 99.10% # Number of insts issued each cycle 1251system.cpu2.iq.issued_per_cycle::5 1178 0.68% 99.79% # Number of insts issued each cycle 1252system.cpu2.iq.issued_per_cycle::6 256 0.15% 99.94% # Number of insts issued each cycle 1253system.cpu2.iq.issued_per_cycle::7 52 0.03% 99.97% # Number of insts issued each cycle 1254system.cpu2.iq.issued_per_cycle::8 55 0.03% 100.00% # Number of insts issued each cycle 1255system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1256system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1257system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 1258system.cpu2.iq.issued_per_cycle::total 172022 # Number of insts issued each cycle 1259system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 1260system.cpu2.iq.fu_full::IntAlu 11 3.83% 3.83% # attempts to use FU when none available 1261system.cpu2.iq.fu_full::IntMult 0 0.00% 3.83% # attempts to use FU when none available 1262system.cpu2.iq.fu_full::IntDiv 0 0.00% 3.83% # attempts to use FU when none available 1263system.cpu2.iq.fu_full::FloatAdd 0 0.00% 3.83% # attempts to use FU when none available 1264system.cpu2.iq.fu_full::FloatCmp 0 0.00% 3.83% # attempts to use FU when none available 1265system.cpu2.iq.fu_full::FloatCvt 0 0.00% 3.83% # attempts to use FU when none available 1266system.cpu2.iq.fu_full::FloatMult 0 0.00% 3.83% # attempts to use FU when none available 1267system.cpu2.iq.fu_full::FloatDiv 0 0.00% 3.83% # attempts to use FU when none available 1268system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 3.83% # attempts to use FU when none available 1269system.cpu2.iq.fu_full::SimdAdd 0 0.00% 3.83% # attempts to use FU when none available 1270system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 3.83% # attempts to use FU when none available 1271system.cpu2.iq.fu_full::SimdAlu 0 0.00% 3.83% # attempts to use FU when none available 1272system.cpu2.iq.fu_full::SimdCmp 0 0.00% 3.83% # attempts to use FU when none available 1273system.cpu2.iq.fu_full::SimdCvt 0 0.00% 3.83% # attempts to use FU when none available 1274system.cpu2.iq.fu_full::SimdMisc 0 0.00% 3.83% # attempts to use FU when none available 1275system.cpu2.iq.fu_full::SimdMult 0 0.00% 3.83% # attempts to use FU when none available 1276system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 3.83% # attempts to use FU when none available 1277system.cpu2.iq.fu_full::SimdShift 0 0.00% 3.83% # attempts to use FU when none available 1278system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 3.83% # attempts to use FU when none available 1279system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 3.83% # attempts to use FU when none available 1280system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 3.83% # attempts to use FU when none available 1281system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 3.83% # attempts to use FU when none available 1282system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 3.83% # attempts to use FU when none available 1283system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 3.83% # attempts to use FU when none available 1284system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 3.83% # attempts to use FU when none available 1285system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 3.83% # attempts to use FU when none available 1286system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 3.83% # attempts to use FU when none available 1287system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.83% # attempts to use FU when none available 1288system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 3.83% # attempts to use FU when none available 1289system.cpu2.iq.fu_full::MemRead 66 23.00% 26.83% # attempts to use FU when none available 1290system.cpu2.iq.fu_full::MemWrite 210 73.17% 100.00% # attempts to use FU when none available 1291system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 1292system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 1293system.cpu2.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 1294system.cpu2.iq.FU_type_0::IntAlu 96218 50.38% 50.38% # Type of FU issued 1295system.cpu2.iq.FU_type_0::IntMult 0 0.00% 50.38% # Type of FU issued 1296system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 50.38% # Type of FU issued 1297system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 50.38% # Type of FU issued 1298system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 50.38% # Type of FU issued 1299system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 50.38% # Type of FU issued 1300system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 50.38% # Type of FU issued 1301system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 50.38% # Type of FU issued 1302system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 50.38% # Type of FU issued 1303system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 50.38% # Type of FU issued 1304system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 50.38% # Type of FU issued 1305system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 50.38% # Type of FU issued 1306system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 50.38% # Type of FU issued 1307system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 50.38% # Type of FU issued 1308system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 50.38% # Type of FU issued 1309system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 50.38% # Type of FU issued 1310system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 50.38% # Type of FU issued 1311system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 50.38% # Type of FU issued 1312system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 50.38% # Type of FU issued 1313system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 50.38% # Type of FU issued 1314system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 50.38% # Type of FU issued 1315system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 50.38% # Type of FU issued 1316system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 50.38% # Type of FU issued 1317system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 50.38% # Type of FU issued 1318system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 50.38% # Type of FU issued 1319system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 50.38% # Type of FU issued 1320system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 50.38% # Type of FU issued 1321system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 50.38% # Type of FU issued 1322system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 50.38% # Type of FU issued 1323system.cpu2.iq.FU_type_0::MemRead 68109 35.66% 86.04% # Type of FU issued 1324system.cpu2.iq.FU_type_0::MemWrite 26665 13.96% 100.00% # Type of FU issued 1325system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 1326system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 1327system.cpu2.iq.FU_type_0::total 190992 # Type of FU issued 1328system.cpu2.iq.rate 1.099178 # Inst issue rate 1329system.cpu2.iq.fu_busy_cnt 287 # FU busy when requested 1330system.cpu2.iq.fu_busy_rate 0.001503 # FU busy rate (busy events/executed inst) 1331system.cpu2.iq.int_inst_queue_reads 554402 # Number of integer instruction queue reads 1332system.cpu2.iq.int_inst_queue_writes 206628 # Number of integer instruction queue writes 1333system.cpu2.iq.int_inst_queue_wakeup_accesses 189208 # Number of integer instruction queue wakeup accesses 1334system.cpu2.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads 1335system.cpu2.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes 1336system.cpu2.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses 1337system.cpu2.iq.int_alu_accesses 191279 # Number of integer alu accesses 1338system.cpu2.iq.fp_alu_accesses 0 # Number of floating point alu accesses 1339system.cpu2.iew.lsq.thread0.forwLoads 22028 # Number of loads that had data forwarded from stores 1340system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 1341system.cpu2.iew.lsq.thread0.squashedLoads 2518 # Number of loads squashed 1342system.cpu2.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed 1343system.cpu2.iew.lsq.thread0.memOrderViolation 47 # Number of memory ordering violations 1344system.cpu2.iew.lsq.thread0.squashedStores 1460 # Number of stores squashed 1345system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 1346system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 1347system.cpu2.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 1348system.cpu2.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked 1349system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle 1350system.cpu2.iew.iewSquashCycles 2426 # Number of cycles IEW is squashing 1351system.cpu2.iew.iewBlockCycles 904 # Number of cycles IEW is blocking 1352system.cpu2.iew.iewUnblockCycles 54 # Number of cycles IEW is unblocking 1353system.cpu2.iew.iewDispatchedInsts 226591 # Number of instructions dispatched to IQ 1354system.cpu2.iew.iewDispSquashedInsts 328 # Number of squashed instructions skipped by dispatch 1355system.cpu2.iew.iewDispLoadInsts 61347 # Number of dispatched load instructions 1356system.cpu2.iew.iewDispStoreInsts 27349 # Number of dispatched store instructions 1357system.cpu2.iew.iewDispNonSpecInsts 1066 # Number of dispatched non-speculative instructions 1358system.cpu2.iew.iewIQFullEvents 54 # Number of times the IQ has become full, causing a stall 1359system.cpu2.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 1360system.cpu2.iew.memOrderViolationEvents 47 # Number of memory order violations 1361system.cpu2.iew.predictedTakenIncorrect 465 # Number of branches that were predicted taken incorrectly 1362system.cpu2.iew.predictedNotTakenIncorrect 929 # Number of branches that were predicted not taken incorrectly 1363system.cpu2.iew.branchMispredicts 1394 # Number of branch mispredicts detected at execute 1364system.cpu2.iew.iewExecutedInsts 189816 # Number of executed instructions 1365system.cpu2.iew.iewExecLoadInsts 60231 # Number of load instructions executed 1366system.cpu2.iew.iewExecSquashedInsts 1176 # Number of squashed instructions skipped in execute 1367system.cpu2.iew.exec_swp 0 # number of swp insts executed 1368system.cpu2.iew.exec_nop 31084 # number of nop insts executed 1369system.cpu2.iew.exec_refs 86812 # number of memory reference insts executed 1370system.cpu2.iew.exec_branches 40244 # Number of branches executed 1371system.cpu2.iew.exec_stores 26581 # Number of stores executed 1372system.cpu2.iew.exec_rate 1.092410 # Inst execution rate 1373system.cpu2.iew.wb_sent 189478 # cumulative count of insts sent to commit 1374system.cpu2.iew.wb_count 189208 # cumulative count of insts written-back 1375system.cpu2.iew.wb_producers 103581 # num instructions producing a value 1376system.cpu2.iew.wb_consumers 108246 # num instructions consuming a value 1377system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 1378system.cpu2.iew.wb_rate 1.088911 # insts written-back per cycle 1379system.cpu2.iew.wb_fanout 0.956904 # average fanout of values written-back 1380system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 1381system.cpu2.commit.commitSquashedInsts 12701 # The number of squashed insts skipped by commit 1382system.cpu2.commit.commitNonSpecStalls 8313 # The number of times commit has been forced to stall to communicate backwards 1383system.cpu2.commit.branchMispredicts 1282 # The number of times a branch was mispredicted 1384system.cpu2.commit.committed_per_cycle::samples 163490 # Number of insts commited each cycle 1385system.cpu2.commit.committed_per_cycle::mean 1.308153 # Number of insts commited each cycle 1386system.cpu2.commit.committed_per_cycle::stdev 1.875243 # Number of insts commited each cycle 1387system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 1388system.cpu2.commit.committed_per_cycle::0 83402 51.01% 51.01% # Number of insts commited each cycle 1389system.cpu2.commit.committed_per_cycle::1 38322 23.44% 74.45% # Number of insts commited each cycle 1390system.cpu2.commit.committed_per_cycle::2 6091 3.73% 78.18% # Number of insts commited each cycle 1391system.cpu2.commit.committed_per_cycle::3 9201 5.63% 83.81% # Number of insts commited each cycle 1392system.cpu2.commit.committed_per_cycle::4 1555 0.95% 84.76% # Number of insts commited each cycle 1393system.cpu2.commit.committed_per_cycle::5 22612 13.83% 98.59% # Number of insts commited each cycle 1394system.cpu2.commit.committed_per_cycle::6 481 0.29% 98.88% # Number of insts commited each cycle 1395system.cpu2.commit.committed_per_cycle::7 1011 0.62% 99.50% # Number of insts commited each cycle 1396system.cpu2.commit.committed_per_cycle::8 815 0.50% 100.00% # Number of insts commited each cycle 1397system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 1398system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 1399system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 1400system.cpu2.commit.committed_per_cycle::total 163490 # Number of insts commited each cycle 1401system.cpu2.commit.committedInsts 213870 # Number of instructions committed 1402system.cpu2.commit.committedOps 213870 # Number of ops (including micro ops) committed 1403system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed 1404system.cpu2.commit.refs 84718 # Number of memory references committed 1405system.cpu2.commit.loads 58829 # Number of loads committed 1406system.cpu2.commit.membars 7592 # Number of memory barriers committed 1407system.cpu2.commit.branches 39438 # Number of branches committed 1408system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions. 1409system.cpu2.commit.int_insts 146274 # Number of committed integer instructions. 1410system.cpu2.commit.function_calls 322 # Number of function calls committed. 1411system.cpu2.commit.bw_lim_events 815 # number cycles where commit BW limit reached 1412system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits 1413system.cpu2.rob.rob_reads 388659 # The number of ROB reads 1414system.cpu2.rob.rob_writes 455572 # The number of ROB writes 1415system.cpu2.timesIdled 220 # Number of times that the entire CPU went into an idle state and unscheduled itself 1416system.cpu2.idleCycles 1737 # Total number of cycles that the CPU has spent unscheduled due to idling 1417system.cpu2.quiesceCycles 35901 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1418system.cpu2.committedInsts 176057 # Number of Instructions Simulated 1419system.cpu2.committedOps 176057 # Number of Ops (including micro ops) Simulated 1420system.cpu2.committedInsts_total 176057 # Number of Instructions Simulated 1421system.cpu2.cpi 0.986947 # CPI: Cycles Per Instruction 1422system.cpu2.cpi_total 0.986947 # CPI: Total CPI of All Threads 1423system.cpu2.ipc 1.013225 # IPC: Instructions Per Cycle 1424system.cpu2.ipc_total 1.013225 # IPC: Total IPC of All Threads 1425system.cpu2.int_regfile_reads 319017 # number of integer regfile reads 1426system.cpu2.int_regfile_writes 150022 # number of integer regfile writes 1427system.cpu2.fp_regfile_writes 64 # number of floating regfile writes 1428system.cpu2.misc_regfile_reads 88362 # number of misc regfile reads 1429system.cpu2.misc_regfile_writes 648 # number of misc regfile writes 1430system.cpu2.icache.replacements 319 # number of replacements 1431system.cpu2.icache.tagsinuse 80.119670 # Cycle average of tags in use 1432system.cpu2.icache.total_refs 24566 # Total number of references to valid blocks. 1433system.cpu2.icache.sampled_refs 429 # Sample count of references to valid blocks. 1434system.cpu2.icache.avg_refs 57.263403 # Average number of references to valid blocks. 1435system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1436system.cpu2.icache.occ_blocks::cpu2.inst 80.119670 # Average occupied blocks per requestor 1437system.cpu2.icache.occ_percent::cpu2.inst 0.156484 # Average percentage of cache occupancy 1438system.cpu2.icache.occ_percent::total 0.156484 # Average percentage of cache occupancy 1439system.cpu2.icache.ReadReq_hits::cpu2.inst 24566 # number of ReadReq hits 1440system.cpu2.icache.ReadReq_hits::total 24566 # number of ReadReq hits 1441system.cpu2.icache.demand_hits::cpu2.inst 24566 # number of demand (read+write) hits 1442system.cpu2.icache.demand_hits::total 24566 # number of demand (read+write) hits 1443system.cpu2.icache.overall_hits::cpu2.inst 24566 # number of overall hits 1444system.cpu2.icache.overall_hits::total 24566 # number of overall hits 1445system.cpu2.icache.ReadReq_misses::cpu2.inst 475 # number of ReadReq misses 1446system.cpu2.icache.ReadReq_misses::total 475 # number of ReadReq misses 1447system.cpu2.icache.demand_misses::cpu2.inst 475 # number of demand (read+write) misses 1448system.cpu2.icache.demand_misses::total 475 # number of demand (read+write) misses 1449system.cpu2.icache.overall_misses::cpu2.inst 475 # number of overall misses 1450system.cpu2.icache.overall_misses::total 475 # number of overall misses 1451system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 6356500 # number of ReadReq miss cycles 1452system.cpu2.icache.ReadReq_miss_latency::total 6356500 # number of ReadReq miss cycles 1453system.cpu2.icache.demand_miss_latency::cpu2.inst 6356500 # number of demand (read+write) miss cycles 1454system.cpu2.icache.demand_miss_latency::total 6356500 # number of demand (read+write) miss cycles 1455system.cpu2.icache.overall_miss_latency::cpu2.inst 6356500 # number of overall miss cycles 1456system.cpu2.icache.overall_miss_latency::total 6356500 # number of overall miss cycles 1457system.cpu2.icache.ReadReq_accesses::cpu2.inst 25041 # number of ReadReq accesses(hits+misses) 1458system.cpu2.icache.ReadReq_accesses::total 25041 # number of ReadReq accesses(hits+misses) 1459system.cpu2.icache.demand_accesses::cpu2.inst 25041 # number of demand (read+write) accesses 1460system.cpu2.icache.demand_accesses::total 25041 # number of demand (read+write) accesses 1461system.cpu2.icache.overall_accesses::cpu2.inst 25041 # number of overall (read+write) accesses 1462system.cpu2.icache.overall_accesses::total 25041 # number of overall (read+write) accesses 1463system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.018969 # miss rate for ReadReq accesses 1464system.cpu2.icache.ReadReq_miss_rate::total 0.018969 # miss rate for ReadReq accesses 1465system.cpu2.icache.demand_miss_rate::cpu2.inst 0.018969 # miss rate for demand accesses 1466system.cpu2.icache.demand_miss_rate::total 0.018969 # miss rate for demand accesses 1467system.cpu2.icache.overall_miss_rate::cpu2.inst 0.018969 # miss rate for overall accesses 1468system.cpu2.icache.overall_miss_rate::total 0.018969 # miss rate for overall accesses 1469system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 13382.105263 # average ReadReq miss latency 1470system.cpu2.icache.ReadReq_avg_miss_latency::total 13382.105263 # average ReadReq miss latency 1471system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 13382.105263 # average overall miss latency 1472system.cpu2.icache.demand_avg_miss_latency::total 13382.105263 # average overall miss latency 1473system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 13382.105263 # average overall miss latency 1474system.cpu2.icache.overall_avg_miss_latency::total 13382.105263 # average overall miss latency 1475system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1476system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1477system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1478system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked 1479system.cpu2.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1480system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1481system.cpu2.icache.fast_writes 0 # number of fast writes performed 1482system.cpu2.icache.cache_copies 0 # number of cache copies performed 1483system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 46 # number of ReadReq MSHR hits 1484system.cpu2.icache.ReadReq_mshr_hits::total 46 # number of ReadReq MSHR hits 1485system.cpu2.icache.demand_mshr_hits::cpu2.inst 46 # number of demand (read+write) MSHR hits 1486system.cpu2.icache.demand_mshr_hits::total 46 # number of demand (read+write) MSHR hits 1487system.cpu2.icache.overall_mshr_hits::cpu2.inst 46 # number of overall MSHR hits 1488system.cpu2.icache.overall_mshr_hits::total 46 # number of overall MSHR hits 1489system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 429 # number of ReadReq MSHR misses 1490system.cpu2.icache.ReadReq_mshr_misses::total 429 # number of ReadReq MSHR misses 1491system.cpu2.icache.demand_mshr_misses::cpu2.inst 429 # number of demand (read+write) MSHR misses 1492system.cpu2.icache.demand_mshr_misses::total 429 # number of demand (read+write) MSHR misses 1493system.cpu2.icache.overall_mshr_misses::cpu2.inst 429 # number of overall MSHR misses 1494system.cpu2.icache.overall_mshr_misses::total 429 # number of overall MSHR misses 1495system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 5130000 # number of ReadReq MSHR miss cycles 1496system.cpu2.icache.ReadReq_mshr_miss_latency::total 5130000 # number of ReadReq MSHR miss cycles 1497system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 5130000 # number of demand (read+write) MSHR miss cycles 1498system.cpu2.icache.demand_mshr_miss_latency::total 5130000 # number of demand (read+write) MSHR miss cycles 1499system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 5130000 # number of overall MSHR miss cycles 1500system.cpu2.icache.overall_mshr_miss_latency::total 5130000 # number of overall MSHR miss cycles 1501system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.017132 # mshr miss rate for ReadReq accesses 1502system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.017132 # mshr miss rate for ReadReq accesses 1503system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.017132 # mshr miss rate for demand accesses 1504system.cpu2.icache.demand_mshr_miss_rate::total 0.017132 # mshr miss rate for demand accesses 1505system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.017132 # mshr miss rate for overall accesses 1506system.cpu2.icache.overall_mshr_miss_rate::total 0.017132 # mshr miss rate for overall accesses 1507system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 11958.041958 # average ReadReq mshr miss latency 1508system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 11958.041958 # average ReadReq mshr miss latency 1509system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 11958.041958 # average overall mshr miss latency 1510system.cpu2.icache.demand_avg_mshr_miss_latency::total 11958.041958 # average overall mshr miss latency 1511system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 11958.041958 # average overall mshr miss latency 1512system.cpu2.icache.overall_avg_mshr_miss_latency::total 11958.041958 # average overall mshr miss latency 1513system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1514system.cpu2.dcache.replacements 0 # number of replacements 1515system.cpu2.dcache.tagsinuse 24.750979 # Cycle average of tags in use 1516system.cpu2.dcache.total_refs 32016 # Total number of references to valid blocks. 1517system.cpu2.dcache.sampled_refs 29 # Sample count of references to valid blocks. 1518system.cpu2.dcache.avg_refs 1104 # Average number of references to valid blocks. 1519system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1520system.cpu2.dcache.occ_blocks::cpu2.data 24.750979 # Average occupied blocks per requestor 1521system.cpu2.dcache.occ_percent::cpu2.data 0.048342 # Average percentage of cache occupancy 1522system.cpu2.dcache.occ_percent::total 0.048342 # Average percentage of cache occupancy 1523system.cpu2.dcache.ReadReq_hits::cpu2.data 37788 # number of ReadReq hits 1524system.cpu2.dcache.ReadReq_hits::total 37788 # number of ReadReq hits 1525system.cpu2.dcache.WriteReq_hits::cpu2.data 25681 # number of WriteReq hits 1526system.cpu2.dcache.WriteReq_hits::total 25681 # number of WriteReq hits 1527system.cpu2.dcache.SwapReq_hits::cpu2.data 16 # number of SwapReq hits 1528system.cpu2.dcache.SwapReq_hits::total 16 # number of SwapReq hits 1529system.cpu2.dcache.demand_hits::cpu2.data 63469 # number of demand (read+write) hits 1530system.cpu2.dcache.demand_hits::total 63469 # number of demand (read+write) hits 1531system.cpu2.dcache.overall_hits::cpu2.data 63469 # number of overall hits 1532system.cpu2.dcache.overall_hits::total 63469 # number of overall hits 1533system.cpu2.dcache.ReadReq_misses::cpu2.data 397 # number of ReadReq misses 1534system.cpu2.dcache.ReadReq_misses::total 397 # number of ReadReq misses 1535system.cpu2.dcache.WriteReq_misses::cpu2.data 133 # number of WriteReq misses 1536system.cpu2.dcache.WriteReq_misses::total 133 # number of WriteReq misses 1537system.cpu2.dcache.SwapReq_misses::cpu2.data 59 # number of SwapReq misses 1538system.cpu2.dcache.SwapReq_misses::total 59 # number of SwapReq misses 1539system.cpu2.dcache.demand_misses::cpu2.data 530 # number of demand (read+write) misses 1540system.cpu2.dcache.demand_misses::total 530 # number of demand (read+write) misses 1541system.cpu2.dcache.overall_misses::cpu2.data 530 # number of overall misses 1542system.cpu2.dcache.overall_misses::total 530 # number of overall misses 1543system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 5135500 # number of ReadReq miss cycles 1544system.cpu2.dcache.ReadReq_miss_latency::total 5135500 # number of ReadReq miss cycles 1545system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 2343500 # number of WriteReq miss cycles 1546system.cpu2.dcache.WriteReq_miss_latency::total 2343500 # number of WriteReq miss cycles 1547system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 565000 # number of SwapReq miss cycles 1548system.cpu2.dcache.SwapReq_miss_latency::total 565000 # number of SwapReq miss cycles 1549system.cpu2.dcache.demand_miss_latency::cpu2.data 7479000 # number of demand (read+write) miss cycles 1550system.cpu2.dcache.demand_miss_latency::total 7479000 # number of demand (read+write) miss cycles 1551system.cpu2.dcache.overall_miss_latency::cpu2.data 7479000 # number of overall miss cycles 1552system.cpu2.dcache.overall_miss_latency::total 7479000 # number of overall miss cycles 1553system.cpu2.dcache.ReadReq_accesses::cpu2.data 38185 # number of ReadReq accesses(hits+misses) 1554system.cpu2.dcache.ReadReq_accesses::total 38185 # number of ReadReq accesses(hits+misses) 1555system.cpu2.dcache.WriteReq_accesses::cpu2.data 25814 # number of WriteReq accesses(hits+misses) 1556system.cpu2.dcache.WriteReq_accesses::total 25814 # number of WriteReq accesses(hits+misses) 1557system.cpu2.dcache.SwapReq_accesses::cpu2.data 75 # number of SwapReq accesses(hits+misses) 1558system.cpu2.dcache.SwapReq_accesses::total 75 # number of SwapReq accesses(hits+misses) 1559system.cpu2.dcache.demand_accesses::cpu2.data 63999 # number of demand (read+write) accesses 1560system.cpu2.dcache.demand_accesses::total 63999 # number of demand (read+write) accesses 1561system.cpu2.dcache.overall_accesses::cpu2.data 63999 # number of overall (read+write) accesses 1562system.cpu2.dcache.overall_accesses::total 63999 # number of overall (read+write) accesses 1563system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.010397 # miss rate for ReadReq accesses 1564system.cpu2.dcache.ReadReq_miss_rate::total 0.010397 # miss rate for ReadReq accesses 1565system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.005152 # miss rate for WriteReq accesses 1566system.cpu2.dcache.WriteReq_miss_rate::total 0.005152 # miss rate for WriteReq accesses 1567system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.786667 # miss rate for SwapReq accesses 1568system.cpu2.dcache.SwapReq_miss_rate::total 0.786667 # miss rate for SwapReq accesses 1569system.cpu2.dcache.demand_miss_rate::cpu2.data 0.008281 # miss rate for demand accesses 1570system.cpu2.dcache.demand_miss_rate::total 0.008281 # miss rate for demand accesses 1571system.cpu2.dcache.overall_miss_rate::cpu2.data 0.008281 # miss rate for overall accesses 1572system.cpu2.dcache.overall_miss_rate::total 0.008281 # miss rate for overall accesses 1573system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 12935.768262 # average ReadReq miss latency 1574system.cpu2.dcache.ReadReq_avg_miss_latency::total 12935.768262 # average ReadReq miss latency 1575system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 17620.300752 # average WriteReq miss latency 1576system.cpu2.dcache.WriteReq_avg_miss_latency::total 17620.300752 # average WriteReq miss latency 1577system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 9576.271186 # average SwapReq miss latency 1578system.cpu2.dcache.SwapReq_avg_miss_latency::total 9576.271186 # average SwapReq miss latency 1579system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 14111.320755 # average overall miss latency 1580system.cpu2.dcache.demand_avg_miss_latency::total 14111.320755 # average overall miss latency 1581system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 14111.320755 # average overall miss latency 1582system.cpu2.dcache.overall_avg_miss_latency::total 14111.320755 # average overall miss latency 1583system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1584system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1585system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1586system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked 1587system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1588system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1589system.cpu2.dcache.fast_writes 0 # number of fast writes performed 1590system.cpu2.dcache.cache_copies 0 # number of cache copies performed 1591system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 227 # number of ReadReq MSHR hits 1592system.cpu2.dcache.ReadReq_mshr_hits::total 227 # number of ReadReq MSHR hits 1593system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 32 # number of WriteReq MSHR hits 1594system.cpu2.dcache.WriteReq_mshr_hits::total 32 # number of WriteReq MSHR hits 1595system.cpu2.dcache.demand_mshr_hits::cpu2.data 259 # number of demand (read+write) MSHR hits 1596system.cpu2.dcache.demand_mshr_hits::total 259 # number of demand (read+write) MSHR hits 1597system.cpu2.dcache.overall_mshr_hits::cpu2.data 259 # number of overall MSHR hits 1598system.cpu2.dcache.overall_mshr_hits::total 259 # number of overall MSHR hits 1599system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 170 # number of ReadReq MSHR misses 1600system.cpu2.dcache.ReadReq_mshr_misses::total 170 # number of ReadReq MSHR misses 1601system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 101 # number of WriteReq MSHR misses 1602system.cpu2.dcache.WriteReq_mshr_misses::total 101 # number of WriteReq MSHR misses 1603system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 59 # number of SwapReq MSHR misses 1604system.cpu2.dcache.SwapReq_mshr_misses::total 59 # number of SwapReq MSHR misses 1605system.cpu2.dcache.demand_mshr_misses::cpu2.data 271 # number of demand (read+write) MSHR misses 1606system.cpu2.dcache.demand_mshr_misses::total 271 # number of demand (read+write) MSHR misses 1607system.cpu2.dcache.overall_mshr_misses::cpu2.data 271 # number of overall MSHR misses 1608system.cpu2.dcache.overall_mshr_misses::total 271 # number of overall MSHR misses 1609system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1409000 # number of ReadReq MSHR miss cycles 1610system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1409000 # number of ReadReq MSHR miss cycles 1611system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1142500 # number of WriteReq MSHR miss cycles 1612system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1142500 # number of WriteReq MSHR miss cycles 1613system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 447000 # number of SwapReq MSHR miss cycles 1614system.cpu2.dcache.SwapReq_mshr_miss_latency::total 447000 # number of SwapReq MSHR miss cycles 1615system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 2551500 # number of demand (read+write) MSHR miss cycles 1616system.cpu2.dcache.demand_mshr_miss_latency::total 2551500 # number of demand (read+write) MSHR miss cycles 1617system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 2551500 # number of overall MSHR miss cycles 1618system.cpu2.dcache.overall_mshr_miss_latency::total 2551500 # number of overall MSHR miss cycles 1619system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.004452 # mshr miss rate for ReadReq accesses 1620system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.004452 # mshr miss rate for ReadReq accesses 1621system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.003913 # mshr miss rate for WriteReq accesses 1622system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.003913 # mshr miss rate for WriteReq accesses 1623system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.786667 # mshr miss rate for SwapReq accesses 1624system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.786667 # mshr miss rate for SwapReq accesses 1625system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.004234 # mshr miss rate for demand accesses 1626system.cpu2.dcache.demand_mshr_miss_rate::total 0.004234 # mshr miss rate for demand accesses 1627system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.004234 # mshr miss rate for overall accesses 1628system.cpu2.dcache.overall_mshr_miss_rate::total 0.004234 # mshr miss rate for overall accesses 1629system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 8288.235294 # average ReadReq mshr miss latency 1630system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 8288.235294 # average ReadReq mshr miss latency 1631system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 11311.881188 # average WriteReq mshr miss latency 1632system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 11311.881188 # average WriteReq mshr miss latency 1633system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 7576.271186 # average SwapReq mshr miss latency 1634system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 7576.271186 # average SwapReq mshr miss latency 1635system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 9415.129151 # average overall mshr miss latency 1636system.cpu2.dcache.demand_avg_mshr_miss_latency::total 9415.129151 # average overall mshr miss latency 1637system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 9415.129151 # average overall mshr miss latency 1638system.cpu2.dcache.overall_avg_mshr_miss_latency::total 9415.129151 # average overall mshr miss latency 1639system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1640system.cpu3.numCycles 173449 # number of cpu cycles simulated 1641system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started 1642system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed 1643system.cpu3.BPredUnit.lookups 53688 # Number of BP lookups 1644system.cpu3.BPredUnit.condPredicted 50962 # Number of conditional branches predicted 1645system.cpu3.BPredUnit.condIncorrect 1276 # Number of conditional branches incorrect 1646system.cpu3.BPredUnit.BTBLookups 47521 # Number of BTB lookups 1647system.cpu3.BPredUnit.BTBHits 46771 # Number of BTB hits 1648system.cpu3.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 1649system.cpu3.BPredUnit.usedRAS 661 # Number of times the RAS was used to get a target. 1650system.cpu3.BPredUnit.RASInCorrect 232 # Number of incorrect RAS predictions. 1651system.cpu3.fetch.icacheStallCycles 27478 # Number of cycles fetch is stalled on an Icache miss 1652system.cpu3.fetch.Insts 301358 # Number of instructions fetch has processed 1653system.cpu3.fetch.Branches 53688 # Number of branches that fetch encountered 1654system.cpu3.fetch.predictedBranches 47432 # Number of branches that fetch has predicted taken 1655system.cpu3.fetch.Cycles 105431 # Number of cycles fetch has run and was not squashing or blocked 1656system.cpu3.fetch.SquashCycles 3739 # Number of cycles fetch has spent squashing 1657system.cpu3.fetch.BlockedCycles 29902 # Number of cycles fetch has spent blocked 1658system.cpu3.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 1659system.cpu3.fetch.NoActiveThreadStallCycles 6125 # Number of stall cycles due to no active thread to fetch from 1660system.cpu3.fetch.PendingTrapStallCycles 699 # Number of stall cycles due to pending traps 1661system.cpu3.fetch.CacheLines 19205 # Number of cache lines fetched 1662system.cpu3.fetch.IcacheSquashes 263 # Number of outstanding Icache misses that were squashed 1663system.cpu3.fetch.rateDist::samples 172027 # Number of instructions fetched each cycle (Total) 1664system.cpu3.fetch.rateDist::mean 1.751806 # Number of instructions fetched each cycle (Total) 1665system.cpu3.fetch.rateDist::stdev 2.162661 # Number of instructions fetched each cycle (Total) 1666system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 1667system.cpu3.fetch.rateDist::0 66596 38.71% 38.71% # Number of instructions fetched each cycle (Total) 1668system.cpu3.fetch.rateDist::1 53420 31.05% 69.77% # Number of instructions fetched each cycle (Total) 1669system.cpu3.fetch.rateDist::2 5840 3.39% 73.16% # Number of instructions fetched each cycle (Total) 1670system.cpu3.fetch.rateDist::3 3208 1.86% 75.03% # Number of instructions fetched each cycle (Total) 1671system.cpu3.fetch.rateDist::4 724 0.42% 75.45% # Number of instructions fetched each cycle (Total) 1672system.cpu3.fetch.rateDist::5 37059 21.54% 96.99% # Number of instructions fetched each cycle (Total) 1673system.cpu3.fetch.rateDist::6 1114 0.65% 97.64% # Number of instructions fetched each cycle (Total) 1674system.cpu3.fetch.rateDist::7 769 0.45% 98.08% # Number of instructions fetched each cycle (Total) 1675system.cpu3.fetch.rateDist::8 3297 1.92% 100.00% # Number of instructions fetched each cycle (Total) 1676system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 1677system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1678system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 1679system.cpu3.fetch.rateDist::total 172027 # Number of instructions fetched each cycle (Total) 1680system.cpu3.fetch.branchRate 0.309532 # Number of branch fetches per cycle 1681system.cpu3.fetch.rate 1.737444 # Number of inst fetches per cycle 1682system.cpu3.decode.IdleCycles 32330 # Number of cycles decode is idle 1683system.cpu3.decode.BlockedCycles 26595 # Number of cycles decode is blocked 1684system.cpu3.decode.RunCycles 99738 # Number of cycles decode is running 1685system.cpu3.decode.UnblockCycles 4852 # Number of cycles decode is unblocking 1686system.cpu3.decode.SquashCycles 2387 # Number of cycles decode is squashing 1687system.cpu3.decode.DecodedInsts 297869 # Number of instructions handled by decode 1688system.cpu3.rename.SquashCycles 2387 # Number of cycles rename is squashing 1689system.cpu3.rename.IdleCycles 33042 # Number of cycles rename is idle 1690system.cpu3.rename.BlockCycles 14161 # Number of cycles rename is blocking 1691system.cpu3.rename.serializeStallCycles 11648 # count of cycles rename stalled for serializing inst 1692system.cpu3.rename.RunCycles 95158 # Number of cycles rename is running 1693system.cpu3.rename.UnblockCycles 9506 # Number of cycles rename is unblocking 1694system.cpu3.rename.RenamedInsts 295495 # Number of instructions processed by rename 1695system.cpu3.rename.IQFullEvents 6 # Number of times rename has blocked due to IQ full 1696system.cpu3.rename.LSQFullEvents 42 # Number of times rename has blocked due to LSQ full 1697system.cpu3.rename.RenamedOperands 206972 # Number of destination operands rename has renamed 1698system.cpu3.rename.RenameLookups 568769 # Number of register rename lookups that rename has made 1699system.cpu3.rename.int_rename_lookups 568769 # Number of integer rename lookups 1700system.cpu3.rename.CommittedMaps 194051 # Number of HB maps that are committed 1701system.cpu3.rename.UndoneMaps 12921 # Number of HB maps that are undone due to squashing 1702system.cpu3.rename.serializingInsts 1094 # count of serializing insts renamed 1703system.cpu3.rename.tempSerializingInsts 1213 # count of temporary serializing insts renamed 1704system.cpu3.rename.skidInsts 12164 # count of insts added to the skid buffer 1705system.cpu3.memDep0.insertedLoads 84321 # Number of loads inserted to the mem dependence unit. 1706system.cpu3.memDep0.insertedStores 40263 # Number of stores inserted to the mem dependence unit. 1707system.cpu3.memDep0.conflictingLoads 40233 # Number of conflicting loads. 1708system.cpu3.memDep0.conflictingStores 35230 # Number of conflicting stores. 1709system.cpu3.iq.iqInstsAdded 245462 # Number of instructions added to the IQ (excludes non-spec) 1710system.cpu3.iq.iqNonSpecInstsAdded 6061 # Number of non-speculative instructions added to the IQ 1711system.cpu3.iq.iqInstsIssued 247263 # Number of instructions issued 1712system.cpu3.iq.iqSquashedInstsIssued 84 # Number of squashed instructions issued 1713system.cpu3.iq.iqSquashedInstsExamined 10948 # Number of squashed instructions iterated over during squash; mainly for profiling 1714system.cpu3.iq.iqSquashedOperandsExamined 10583 # Number of squashed operands that are examined and possibly removed from graph 1715system.cpu3.iq.iqSquashedNonSpecRemoved 569 # Number of squashed non-spec instructions that were removed 1716system.cpu3.iq.issued_per_cycle::samples 172027 # Number of insts issued each cycle 1717system.cpu3.iq.issued_per_cycle::mean 1.437350 # Number of insts issued each cycle 1718system.cpu3.iq.issued_per_cycle::stdev 1.311410 # Number of insts issued each cycle 1719system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 1720system.cpu3.iq.issued_per_cycle::0 63993 37.20% 37.20% # Number of insts issued each cycle 1721system.cpu3.iq.issued_per_cycle::1 21775 12.66% 49.86% # Number of insts issued each cycle 1722system.cpu3.iq.issued_per_cycle::2 40281 23.42% 73.27% # Number of insts issued each cycle 1723system.cpu3.iq.issued_per_cycle::3 41063 23.87% 97.14% # Number of insts issued each cycle 1724system.cpu3.iq.issued_per_cycle::4 3352 1.95% 99.09% # Number of insts issued each cycle 1725system.cpu3.iq.issued_per_cycle::5 1207 0.70% 99.79% # Number of insts issued each cycle 1726system.cpu3.iq.issued_per_cycle::6 253 0.15% 99.94% # Number of insts issued each cycle 1727system.cpu3.iq.issued_per_cycle::7 48 0.03% 99.97% # Number of insts issued each cycle 1728system.cpu3.iq.issued_per_cycle::8 55 0.03% 100.00% # Number of insts issued each cycle 1729system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1730system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1731system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 1732system.cpu3.iq.issued_per_cycle::total 172027 # Number of insts issued each cycle 1733system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 1734system.cpu3.iq.fu_full::IntAlu 11 3.83% 3.83% # attempts to use FU when none available 1735system.cpu3.iq.fu_full::IntMult 0 0.00% 3.83% # attempts to use FU when none available 1736system.cpu3.iq.fu_full::IntDiv 0 0.00% 3.83% # attempts to use FU when none available 1737system.cpu3.iq.fu_full::FloatAdd 0 0.00% 3.83% # attempts to use FU when none available 1738system.cpu3.iq.fu_full::FloatCmp 0 0.00% 3.83% # attempts to use FU when none available 1739system.cpu3.iq.fu_full::FloatCvt 0 0.00% 3.83% # attempts to use FU when none available 1740system.cpu3.iq.fu_full::FloatMult 0 0.00% 3.83% # attempts to use FU when none available 1741system.cpu3.iq.fu_full::FloatDiv 0 0.00% 3.83% # attempts to use FU when none available 1742system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 3.83% # attempts to use FU when none available 1743system.cpu3.iq.fu_full::SimdAdd 0 0.00% 3.83% # attempts to use FU when none available 1744system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 3.83% # attempts to use FU when none available 1745system.cpu3.iq.fu_full::SimdAlu 0 0.00% 3.83% # attempts to use FU when none available 1746system.cpu3.iq.fu_full::SimdCmp 0 0.00% 3.83% # attempts to use FU when none available 1747system.cpu3.iq.fu_full::SimdCvt 0 0.00% 3.83% # attempts to use FU when none available 1748system.cpu3.iq.fu_full::SimdMisc 0 0.00% 3.83% # attempts to use FU when none available 1749system.cpu3.iq.fu_full::SimdMult 0 0.00% 3.83% # attempts to use FU when none available 1750system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 3.83% # attempts to use FU when none available 1751system.cpu3.iq.fu_full::SimdShift 0 0.00% 3.83% # attempts to use FU when none available 1752system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 3.83% # attempts to use FU when none available 1753system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 3.83% # attempts to use FU when none available 1754system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 3.83% # attempts to use FU when none available 1755system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 3.83% # attempts to use FU when none available 1756system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 3.83% # attempts to use FU when none available 1757system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 3.83% # attempts to use FU when none available 1758system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 3.83% # attempts to use FU when none available 1759system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 3.83% # attempts to use FU when none available 1760system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 3.83% # attempts to use FU when none available 1761system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.83% # attempts to use FU when none available 1762system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 3.83% # attempts to use FU when none available 1763system.cpu3.iq.fu_full::MemRead 66 23.00% 26.83% # attempts to use FU when none available 1764system.cpu3.iq.fu_full::MemWrite 210 73.17% 100.00% # attempts to use FU when none available 1765system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 1766system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 1767system.cpu3.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 1768system.cpu3.iq.FU_type_0::IntAlu 119304 48.25% 48.25% # Type of FU issued 1769system.cpu3.iq.FU_type_0::IntMult 0 0.00% 48.25% # Type of FU issued 1770system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 48.25% # Type of FU issued 1771system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 48.25% # Type of FU issued 1772system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 48.25% # Type of FU issued 1773system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 48.25% # Type of FU issued 1774system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 48.25% # Type of FU issued 1775system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 48.25% # Type of FU issued 1776system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 48.25% # Type of FU issued 1777system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 48.25% # Type of FU issued 1778system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 48.25% # Type of FU issued 1779system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 48.25% # Type of FU issued 1780system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 48.25% # Type of FU issued 1781system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 48.25% # Type of FU issued 1782system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 48.25% # Type of FU issued 1783system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 48.25% # Type of FU issued 1784system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 48.25% # Type of FU issued 1785system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 48.25% # Type of FU issued 1786system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.25% # Type of FU issued 1787system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 48.25% # Type of FU issued 1788system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.25% # Type of FU issued 1789system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.25% # Type of FU issued 1790system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.25% # Type of FU issued 1791system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.25% # Type of FU issued 1792system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.25% # Type of FU issued 1793system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.25% # Type of FU issued 1794system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 48.25% # Type of FU issued 1795system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.25% # Type of FU issued 1796system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.25% # Type of FU issued 1797system.cpu3.iq.FU_type_0::MemRead 88373 35.74% 83.99% # Type of FU issued 1798system.cpu3.iq.FU_type_0::MemWrite 39586 16.01% 100.00% # Type of FU issued 1799system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 1800system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 1801system.cpu3.iq.FU_type_0::total 247263 # Type of FU issued 1802system.cpu3.iq.rate 1.425566 # Inst issue rate 1803system.cpu3.iq.fu_busy_cnt 287 # FU busy when requested 1804system.cpu3.iq.fu_busy_rate 0.001161 # FU busy rate (busy events/executed inst) 1805system.cpu3.iq.int_inst_queue_reads 666924 # Number of integer instruction queue reads 1806system.cpu3.iq.int_inst_queue_writes 262516 # Number of integer instruction queue writes 1807system.cpu3.iq.int_inst_queue_wakeup_accesses 245480 # Number of integer instruction queue wakeup accesses 1808system.cpu3.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads 1809system.cpu3.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes 1810system.cpu3.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses 1811system.cpu3.iq.int_alu_accesses 247550 # Number of integer alu accesses 1812system.cpu3.iq.fp_alu_accesses 0 # Number of floating point alu accesses 1813system.cpu3.iew.lsq.thread0.forwLoads 34961 # Number of loads that had data forwarded from stores 1814system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 1815system.cpu3.iew.lsq.thread0.squashedLoads 2463 # Number of loads squashed 1816system.cpu3.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed 1817system.cpu3.iew.lsq.thread0.memOrderViolation 45 # Number of memory ordering violations 1818system.cpu3.iew.lsq.thread0.squashedStores 1469 # Number of stores squashed 1819system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 1820system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 1821system.cpu3.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 1822system.cpu3.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked 1823system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle 1824system.cpu3.iew.iewSquashCycles 2387 # Number of cycles IEW is squashing 1825system.cpu3.iew.iewBlockCycles 786 # Number of cycles IEW is blocking 1826system.cpu3.iew.iewUnblockCycles 47 # Number of cycles IEW is unblocking 1827system.cpu3.iew.iewDispatchedInsts 292666 # Number of instructions dispatched to IQ 1828system.cpu3.iew.iewDispSquashedInsts 339 # Number of squashed instructions skipped by dispatch 1829system.cpu3.iew.iewDispLoadInsts 84321 # Number of dispatched load instructions 1830system.cpu3.iew.iewDispStoreInsts 40263 # Number of dispatched store instructions 1831system.cpu3.iew.iewDispNonSpecInsts 1055 # Number of dispatched non-speculative instructions 1832system.cpu3.iew.iewIQFullEvents 46 # Number of times the IQ has become full, causing a stall 1833system.cpu3.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 1834system.cpu3.iew.memOrderViolationEvents 45 # Number of memory order violations 1835system.cpu3.iew.predictedTakenIncorrect 463 # Number of branches that were predicted taken incorrectly 1836system.cpu3.iew.predictedNotTakenIncorrect 932 # Number of branches that were predicted not taken incorrectly 1837system.cpu3.iew.branchMispredicts 1395 # Number of branch mispredicts detected at execute 1838system.cpu3.iew.iewExecutedInsts 246084 # Number of executed instructions 1839system.cpu3.iew.iewExecLoadInsts 83306 # Number of load instructions executed 1840system.cpu3.iew.iewExecSquashedInsts 1179 # Number of squashed instructions skipped in execute 1841system.cpu3.iew.exec_swp 0 # number of swp insts executed 1842system.cpu3.iew.exec_nop 41143 # number of nop insts executed 1843system.cpu3.iew.exec_refs 122808 # number of memory reference insts executed 1844system.cpu3.iew.exec_branches 50377 # Number of branches executed 1845system.cpu3.iew.exec_stores 39502 # Number of stores executed 1846system.cpu3.iew.exec_rate 1.418769 # Inst execution rate 1847system.cpu3.iew.wb_sent 245746 # cumulative count of insts sent to commit 1848system.cpu3.iew.wb_count 245480 # cumulative count of insts written-back 1849system.cpu3.iew.wb_producers 139608 # num instructions producing a value 1850system.cpu3.iew.wb_consumers 144273 # num instructions consuming a value 1851system.cpu3.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 1852system.cpu3.iew.wb_rate 1.415286 # insts written-back per cycle 1853system.cpu3.iew.wb_fanout 0.967665 # average fanout of values written-back 1854system.cpu3.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 1855system.cpu3.commit.commitSquashedInsts 12526 # The number of squashed insts skipped by commit 1856system.cpu3.commit.commitNonSpecStalls 5492 # The number of times commit has been forced to stall to communicate backwards 1857system.cpu3.commit.branchMispredicts 1276 # The number of times a branch was mispredicted 1858system.cpu3.commit.committed_per_cycle::samples 163516 # Number of insts commited each cycle 1859system.cpu3.commit.committed_per_cycle::mean 1.713105 # Number of insts commited each cycle 1860system.cpu3.commit.committed_per_cycle::stdev 2.043722 # Number of insts commited each cycle 1861system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 1862system.cpu3.commit.committed_per_cycle::0 63247 38.68% 38.68% # Number of insts commited each cycle 1863system.cpu3.commit.committed_per_cycle::1 48404 29.60% 68.28% # Number of insts commited each cycle 1864system.cpu3.commit.committed_per_cycle::2 6092 3.73% 72.01% # Number of insts commited each cycle 1865system.cpu3.commit.committed_per_cycle::3 6399 3.91% 75.92% # Number of insts commited each cycle 1866system.cpu3.commit.committed_per_cycle::4 1556 0.95% 76.87% # Number of insts commited each cycle 1867system.cpu3.commit.committed_per_cycle::5 35437 21.67% 98.54% # Number of insts commited each cycle 1868system.cpu3.commit.committed_per_cycle::6 553 0.34% 98.88% # Number of insts commited each cycle 1869system.cpu3.commit.committed_per_cycle::7 1016 0.62% 99.50% # Number of insts commited each cycle 1870system.cpu3.commit.committed_per_cycle::8 812 0.50% 100.00% # Number of insts commited each cycle 1871system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 1872system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 1873system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 1874system.cpu3.commit.committed_per_cycle::total 163516 # Number of insts commited each cycle 1875system.cpu3.commit.committedInsts 280120 # Number of instructions committed 1876system.cpu3.commit.committedOps 280120 # Number of ops (including micro ops) committed 1877system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed 1878system.cpu3.commit.refs 120652 # Number of memory references committed 1879system.cpu3.commit.loads 81858 # Number of loads committed 1880system.cpu3.commit.membars 4779 # Number of memory barriers committed 1881system.cpu3.commit.branches 49540 # Number of branches committed 1882system.cpu3.commit.fp_insts 0 # Number of committed floating point instructions. 1883system.cpu3.commit.int_insts 192312 # Number of committed integer instructions. 1884system.cpu3.commit.function_calls 322 # Number of function calls committed. 1885system.cpu3.commit.bw_lim_events 812 # number cycles where commit BW limit reached 1886system.cpu3.commit.bw_limited 0 # number of insts not committed due to BW limits 1887system.cpu3.rob.rob_reads 454763 # The number of ROB reads 1888system.cpu3.rob.rob_writes 587684 # The number of ROB writes 1889system.cpu3.timesIdled 212 # Number of times that the entire CPU went into an idle state and unscheduled itself 1890system.cpu3.idleCycles 1422 # Total number of cycles that the CPU has spent unscheduled due to idling 1891system.cpu3.quiesceCycles 36211 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1892system.cpu3.committedInsts 235010 # Number of Instructions Simulated 1893system.cpu3.committedOps 235010 # Number of Ops (including micro ops) Simulated 1894system.cpu3.committedInsts_total 235010 # Number of Instructions Simulated 1895system.cpu3.cpi 0.738049 # CPI: Cycles Per Instruction 1896system.cpu3.cpi_total 0.738049 # CPI: Total CPI of All Threads 1897system.cpu3.ipc 1.354923 # IPC: Instructions Per Cycle 1898system.cpu3.ipc_total 1.354923 # IPC: Total IPC of All Threads 1899system.cpu3.int_regfile_reads 427031 # number of integer regfile reads 1900system.cpu3.int_regfile_writes 198982 # number of integer regfile writes 1901system.cpu3.fp_regfile_writes 64 # number of floating regfile writes 1902system.cpu3.misc_regfile_reads 124365 # number of misc regfile reads 1903system.cpu3.misc_regfile_writes 648 # number of misc regfile writes 1904system.cpu3.icache.replacements 318 # number of replacements 1905system.cpu3.icache.tagsinuse 83.493816 # Cycle average of tags in use 1906system.cpu3.icache.total_refs 18731 # Total number of references to valid blocks. 1907system.cpu3.icache.sampled_refs 428 # Sample count of references to valid blocks. 1908system.cpu3.icache.avg_refs 43.764019 # Average number of references to valid blocks. 1909system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1910system.cpu3.icache.occ_blocks::cpu3.inst 83.493816 # Average occupied blocks per requestor 1911system.cpu3.icache.occ_percent::cpu3.inst 0.163074 # Average percentage of cache occupancy 1912system.cpu3.icache.occ_percent::total 0.163074 # Average percentage of cache occupancy 1913system.cpu3.icache.ReadReq_hits::cpu3.inst 18731 # number of ReadReq hits 1914system.cpu3.icache.ReadReq_hits::total 18731 # number of ReadReq hits 1915system.cpu3.icache.demand_hits::cpu3.inst 18731 # number of demand (read+write) hits 1916system.cpu3.icache.demand_hits::total 18731 # number of demand (read+write) hits 1917system.cpu3.icache.overall_hits::cpu3.inst 18731 # number of overall hits 1918system.cpu3.icache.overall_hits::total 18731 # number of overall hits 1919system.cpu3.icache.ReadReq_misses::cpu3.inst 474 # number of ReadReq misses 1920system.cpu3.icache.ReadReq_misses::total 474 # number of ReadReq misses 1921system.cpu3.icache.demand_misses::cpu3.inst 474 # number of demand (read+write) misses 1922system.cpu3.icache.demand_misses::total 474 # number of demand (read+write) misses 1923system.cpu3.icache.overall_misses::cpu3.inst 474 # number of overall misses 1924system.cpu3.icache.overall_misses::total 474 # number of overall misses 1925system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 6191000 # number of ReadReq miss cycles 1926system.cpu3.icache.ReadReq_miss_latency::total 6191000 # number of ReadReq miss cycles 1927system.cpu3.icache.demand_miss_latency::cpu3.inst 6191000 # number of demand (read+write) miss cycles 1928system.cpu3.icache.demand_miss_latency::total 6191000 # number of demand (read+write) miss cycles 1929system.cpu3.icache.overall_miss_latency::cpu3.inst 6191000 # number of overall miss cycles 1930system.cpu3.icache.overall_miss_latency::total 6191000 # number of overall miss cycles 1931system.cpu3.icache.ReadReq_accesses::cpu3.inst 19205 # number of ReadReq accesses(hits+misses) 1932system.cpu3.icache.ReadReq_accesses::total 19205 # number of ReadReq accesses(hits+misses) 1933system.cpu3.icache.demand_accesses::cpu3.inst 19205 # number of demand (read+write) accesses 1934system.cpu3.icache.demand_accesses::total 19205 # number of demand (read+write) accesses 1935system.cpu3.icache.overall_accesses::cpu3.inst 19205 # number of overall (read+write) accesses 1936system.cpu3.icache.overall_accesses::total 19205 # number of overall (read+write) accesses 1937system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.024681 # miss rate for ReadReq accesses 1938system.cpu3.icache.ReadReq_miss_rate::total 0.024681 # miss rate for ReadReq accesses 1939system.cpu3.icache.demand_miss_rate::cpu3.inst 0.024681 # miss rate for demand accesses 1940system.cpu3.icache.demand_miss_rate::total 0.024681 # miss rate for demand accesses 1941system.cpu3.icache.overall_miss_rate::cpu3.inst 0.024681 # miss rate for overall accesses 1942system.cpu3.icache.overall_miss_rate::total 0.024681 # miss rate for overall accesses 1943system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13061.181435 # average ReadReq miss latency 1944system.cpu3.icache.ReadReq_avg_miss_latency::total 13061.181435 # average ReadReq miss latency 1945system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13061.181435 # average overall miss latency 1946system.cpu3.icache.demand_avg_miss_latency::total 13061.181435 # average overall miss latency 1947system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13061.181435 # average overall miss latency 1948system.cpu3.icache.overall_avg_miss_latency::total 13061.181435 # average overall miss latency 1949system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1950system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1951system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1952system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked 1953system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1954system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1955system.cpu3.icache.fast_writes 0 # number of fast writes performed 1956system.cpu3.icache.cache_copies 0 # number of cache copies performed 1957system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 46 # number of ReadReq MSHR hits 1958system.cpu3.icache.ReadReq_mshr_hits::total 46 # number of ReadReq MSHR hits 1959system.cpu3.icache.demand_mshr_hits::cpu3.inst 46 # number of demand (read+write) MSHR hits 1960system.cpu3.icache.demand_mshr_hits::total 46 # number of demand (read+write) MSHR hits 1961system.cpu3.icache.overall_mshr_hits::cpu3.inst 46 # number of overall MSHR hits 1962system.cpu3.icache.overall_mshr_hits::total 46 # number of overall MSHR hits 1963system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 428 # number of ReadReq MSHR misses 1964system.cpu3.icache.ReadReq_mshr_misses::total 428 # number of ReadReq MSHR misses 1965system.cpu3.icache.demand_mshr_misses::cpu3.inst 428 # number of demand (read+write) MSHR misses 1966system.cpu3.icache.demand_mshr_misses::total 428 # number of demand (read+write) MSHR misses 1967system.cpu3.icache.overall_mshr_misses::cpu3.inst 428 # number of overall MSHR misses 1968system.cpu3.icache.overall_mshr_misses::total 428 # number of overall MSHR misses 1969system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 4970500 # number of ReadReq MSHR miss cycles 1970system.cpu3.icache.ReadReq_mshr_miss_latency::total 4970500 # number of ReadReq MSHR miss cycles 1971system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 4970500 # number of demand (read+write) MSHR miss cycles 1972system.cpu3.icache.demand_mshr_miss_latency::total 4970500 # number of demand (read+write) MSHR miss cycles 1973system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 4970500 # number of overall MSHR miss cycles 1974system.cpu3.icache.overall_mshr_miss_latency::total 4970500 # number of overall MSHR miss cycles 1975system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.022286 # mshr miss rate for ReadReq accesses 1976system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.022286 # mshr miss rate for ReadReq accesses 1977system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.022286 # mshr miss rate for demand accesses 1978system.cpu3.icache.demand_mshr_miss_rate::total 0.022286 # mshr miss rate for demand accesses 1979system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.022286 # mshr miss rate for overall accesses 1980system.cpu3.icache.overall_mshr_miss_rate::total 0.022286 # mshr miss rate for overall accesses 1981system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 11613.317757 # average ReadReq mshr miss latency 1982system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 11613.317757 # average ReadReq mshr miss latency 1983system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 11613.317757 # average overall mshr miss latency 1984system.cpu3.icache.demand_avg_mshr_miss_latency::total 11613.317757 # average overall mshr miss latency 1985system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 11613.317757 # average overall mshr miss latency 1986system.cpu3.icache.overall_avg_mshr_miss_latency::total 11613.317757 # average overall mshr miss latency 1987system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1988system.cpu3.dcache.replacements 0 # number of replacements 1989system.cpu3.dcache.tagsinuse 25.854093 # Cycle average of tags in use 1990system.cpu3.dcache.total_refs 44811 # Total number of references to valid blocks. 1991system.cpu3.dcache.sampled_refs 28 # Sample count of references to valid blocks. 1992system.cpu3.dcache.avg_refs 1600.392857 # Average number of references to valid blocks. 1993system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1994system.cpu3.dcache.occ_blocks::cpu3.data 25.854093 # Average occupied blocks per requestor 1995system.cpu3.dcache.occ_percent::cpu3.data 0.050496 # Average percentage of cache occupancy 1996system.cpu3.dcache.occ_percent::total 0.050496 # Average percentage of cache occupancy 1997system.cpu3.dcache.ReadReq_hits::cpu3.data 47901 # number of ReadReq hits 1998system.cpu3.dcache.ReadReq_hits::total 47901 # number of ReadReq hits 1999system.cpu3.dcache.WriteReq_hits::cpu3.data 38585 # number of WriteReq hits 2000system.cpu3.dcache.WriteReq_hits::total 38585 # number of WriteReq hits 2001system.cpu3.dcache.SwapReq_hits::cpu3.data 11 # number of SwapReq hits 2002system.cpu3.dcache.SwapReq_hits::total 11 # number of SwapReq hits 2003system.cpu3.dcache.demand_hits::cpu3.data 86486 # number of demand (read+write) hits 2004system.cpu3.dcache.demand_hits::total 86486 # number of demand (read+write) hits 2005system.cpu3.dcache.overall_hits::cpu3.data 86486 # number of overall hits 2006system.cpu3.dcache.overall_hits::total 86486 # number of overall hits 2007system.cpu3.dcache.ReadReq_misses::cpu3.data 426 # number of ReadReq misses 2008system.cpu3.dcache.ReadReq_misses::total 426 # number of ReadReq misses 2009system.cpu3.dcache.WriteReq_misses::cpu3.data 142 # number of WriteReq misses 2010system.cpu3.dcache.WriteReq_misses::total 142 # number of WriteReq misses 2011system.cpu3.dcache.SwapReq_misses::cpu3.data 56 # number of SwapReq misses 2012system.cpu3.dcache.SwapReq_misses::total 56 # number of SwapReq misses 2013system.cpu3.dcache.demand_misses::cpu3.data 568 # number of demand (read+write) misses 2014system.cpu3.dcache.demand_misses::total 568 # number of demand (read+write) misses 2015system.cpu3.dcache.overall_misses::cpu3.data 568 # number of overall misses 2016system.cpu3.dcache.overall_misses::total 568 # number of overall misses 2017system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 5342000 # number of ReadReq miss cycles 2018system.cpu3.dcache.ReadReq_miss_latency::total 5342000 # number of ReadReq miss cycles 2019system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 2332500 # number of WriteReq miss cycles 2020system.cpu3.dcache.WriteReq_miss_latency::total 2332500 # number of WriteReq miss cycles 2021system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 555000 # number of SwapReq miss cycles 2022system.cpu3.dcache.SwapReq_miss_latency::total 555000 # number of SwapReq miss cycles 2023system.cpu3.dcache.demand_miss_latency::cpu3.data 7674500 # number of demand (read+write) miss cycles 2024system.cpu3.dcache.demand_miss_latency::total 7674500 # number of demand (read+write) miss cycles 2025system.cpu3.dcache.overall_miss_latency::cpu3.data 7674500 # number of overall miss cycles 2026system.cpu3.dcache.overall_miss_latency::total 7674500 # number of overall miss cycles 2027system.cpu3.dcache.ReadReq_accesses::cpu3.data 48327 # number of ReadReq accesses(hits+misses) 2028system.cpu3.dcache.ReadReq_accesses::total 48327 # number of ReadReq accesses(hits+misses) 2029system.cpu3.dcache.WriteReq_accesses::cpu3.data 38727 # number of WriteReq accesses(hits+misses) 2030system.cpu3.dcache.WriteReq_accesses::total 38727 # number of WriteReq accesses(hits+misses) 2031system.cpu3.dcache.SwapReq_accesses::cpu3.data 67 # number of SwapReq accesses(hits+misses) 2032system.cpu3.dcache.SwapReq_accesses::total 67 # number of SwapReq accesses(hits+misses) 2033system.cpu3.dcache.demand_accesses::cpu3.data 87054 # number of demand (read+write) accesses 2034system.cpu3.dcache.demand_accesses::total 87054 # number of demand (read+write) accesses 2035system.cpu3.dcache.overall_accesses::cpu3.data 87054 # number of overall (read+write) accesses 2036system.cpu3.dcache.overall_accesses::total 87054 # number of overall (read+write) accesses 2037system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.008815 # miss rate for ReadReq accesses 2038system.cpu3.dcache.ReadReq_miss_rate::total 0.008815 # miss rate for ReadReq accesses 2039system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.003667 # miss rate for WriteReq accesses 2040system.cpu3.dcache.WriteReq_miss_rate::total 0.003667 # miss rate for WriteReq accesses 2041system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.835821 # miss rate for SwapReq accesses 2042system.cpu3.dcache.SwapReq_miss_rate::total 0.835821 # miss rate for SwapReq accesses 2043system.cpu3.dcache.demand_miss_rate::cpu3.data 0.006525 # miss rate for demand accesses 2044system.cpu3.dcache.demand_miss_rate::total 0.006525 # miss rate for demand accesses 2045system.cpu3.dcache.overall_miss_rate::cpu3.data 0.006525 # miss rate for overall accesses 2046system.cpu3.dcache.overall_miss_rate::total 0.006525 # miss rate for overall accesses 2047system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 12539.906103 # average ReadReq miss latency 2048system.cpu3.dcache.ReadReq_avg_miss_latency::total 12539.906103 # average ReadReq miss latency 2049system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 16426.056338 # average WriteReq miss latency 2050system.cpu3.dcache.WriteReq_avg_miss_latency::total 16426.056338 # average WriteReq miss latency 2051system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 9910.714286 # average SwapReq miss latency 2052system.cpu3.dcache.SwapReq_avg_miss_latency::total 9910.714286 # average SwapReq miss latency 2053system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 13511.443662 # average overall miss latency 2054system.cpu3.dcache.demand_avg_miss_latency::total 13511.443662 # average overall miss latency 2055system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 13511.443662 # average overall miss latency 2056system.cpu3.dcache.overall_avg_miss_latency::total 13511.443662 # average overall miss latency 2057system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2058system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2059system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 2060system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked 2061system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2062system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2063system.cpu3.dcache.fast_writes 0 # number of fast writes performed 2064system.cpu3.dcache.cache_copies 0 # number of cache copies performed 2065system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 273 # number of ReadReq MSHR hits 2066system.cpu3.dcache.ReadReq_mshr_hits::total 273 # number of ReadReq MSHR hits 2067system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 33 # number of WriteReq MSHR hits 2068system.cpu3.dcache.WriteReq_mshr_hits::total 33 # number of WriteReq MSHR hits 2069system.cpu3.dcache.demand_mshr_hits::cpu3.data 306 # number of demand (read+write) MSHR hits 2070system.cpu3.dcache.demand_mshr_hits::total 306 # number of demand (read+write) MSHR hits 2071system.cpu3.dcache.overall_mshr_hits::cpu3.data 306 # number of overall MSHR hits 2072system.cpu3.dcache.overall_mshr_hits::total 306 # number of overall MSHR hits 2073system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 153 # number of ReadReq MSHR misses 2074system.cpu3.dcache.ReadReq_mshr_misses::total 153 # number of ReadReq MSHR misses 2075system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 109 # number of WriteReq MSHR misses 2076system.cpu3.dcache.WriteReq_mshr_misses::total 109 # number of WriteReq MSHR misses 2077system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 56 # number of SwapReq MSHR misses 2078system.cpu3.dcache.SwapReq_mshr_misses::total 56 # number of SwapReq MSHR misses 2079system.cpu3.dcache.demand_mshr_misses::cpu3.data 262 # number of demand (read+write) MSHR misses 2080system.cpu3.dcache.demand_mshr_misses::total 262 # number of demand (read+write) MSHR misses 2081system.cpu3.dcache.overall_mshr_misses::cpu3.data 262 # number of overall MSHR misses 2082system.cpu3.dcache.overall_mshr_misses::total 262 # number of overall MSHR misses 2083system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1265000 # number of ReadReq MSHR miss cycles 2084system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1265000 # number of ReadReq MSHR miss cycles 2085system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1159500 # number of WriteReq MSHR miss cycles 2086system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1159500 # number of WriteReq MSHR miss cycles 2087system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 443000 # number of SwapReq MSHR miss cycles 2088system.cpu3.dcache.SwapReq_mshr_miss_latency::total 443000 # number of SwapReq MSHR miss cycles 2089system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 2424500 # number of demand (read+write) MSHR miss cycles 2090system.cpu3.dcache.demand_mshr_miss_latency::total 2424500 # number of demand (read+write) MSHR miss cycles 2091system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 2424500 # number of overall MSHR miss cycles 2092system.cpu3.dcache.overall_mshr_miss_latency::total 2424500 # number of overall MSHR miss cycles 2093system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003166 # mshr miss rate for ReadReq accesses 2094system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003166 # mshr miss rate for ReadReq accesses 2095system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.002815 # mshr miss rate for WriteReq accesses 2096system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.002815 # mshr miss rate for WriteReq accesses 2097system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.835821 # mshr miss rate for SwapReq accesses 2098system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.835821 # mshr miss rate for SwapReq accesses 2099system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.003010 # mshr miss rate for demand accesses 2100system.cpu3.dcache.demand_mshr_miss_rate::total 0.003010 # mshr miss rate for demand accesses 2101system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.003010 # mshr miss rate for overall accesses 2102system.cpu3.dcache.overall_mshr_miss_rate::total 0.003010 # mshr miss rate for overall accesses 2103system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 8267.973856 # average ReadReq mshr miss latency 2104system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 8267.973856 # average ReadReq mshr miss latency 2105system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 10637.614679 # average WriteReq mshr miss latency 2106system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 10637.614679 # average WriteReq mshr miss latency 2107system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 7910.714286 # average SwapReq mshr miss latency 2108system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 7910.714286 # average SwapReq mshr miss latency 2109system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 9253.816794 # average overall mshr miss latency 2110system.cpu3.dcache.demand_avg_mshr_miss_latency::total 9253.816794 # average overall mshr miss latency 2111system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 9253.816794 # average overall mshr miss latency 2112system.cpu3.dcache.overall_avg_mshr_miss_latency::total 9253.816794 # average overall mshr miss latency 2113system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 2114system.l2c.replacements 0 # number of replacements 2115system.l2c.tagsinuse 425.296596 # Cycle average of tags in use 2116system.l2c.total_refs 1448 # Total number of references to valid blocks. 2117system.l2c.sampled_refs 525 # Sample count of references to valid blocks. 2118system.l2c.avg_refs 2.758095 # Average number of references to valid blocks. 2119system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. 2120system.l2c.occ_blocks::writebacks 0.828895 # Average occupied blocks per requestor 2121system.l2c.occ_blocks::cpu0.inst 289.891501 # Average occupied blocks per requestor 2122system.l2c.occ_blocks::cpu0.data 59.268437 # Average occupied blocks per requestor 2123system.l2c.occ_blocks::cpu1.inst 63.508816 # Average occupied blocks per requestor 2124system.l2c.occ_blocks::cpu1.data 5.639642 # Average occupied blocks per requestor 2125system.l2c.occ_blocks::cpu2.inst 2.310248 # Average occupied blocks per requestor 2126system.l2c.occ_blocks::cpu2.data 0.728233 # Average occupied blocks per requestor 2127system.l2c.occ_blocks::cpu3.inst 2.354110 # Average occupied blocks per requestor 2128system.l2c.occ_blocks::cpu3.data 0.766714 # Average occupied blocks per requestor 2129system.l2c.occ_percent::writebacks 0.000013 # Average percentage of cache occupancy 2130system.l2c.occ_percent::cpu0.inst 0.004423 # Average percentage of cache occupancy 2131system.l2c.occ_percent::cpu0.data 0.000904 # Average percentage of cache occupancy 2132system.l2c.occ_percent::cpu1.inst 0.000969 # Average percentage of cache occupancy 2133system.l2c.occ_percent::cpu1.data 0.000086 # Average percentage of cache occupancy 2134system.l2c.occ_percent::cpu2.inst 0.000035 # Average percentage of cache occupancy 2135system.l2c.occ_percent::cpu2.data 0.000011 # Average percentage of cache occupancy 2136system.l2c.occ_percent::cpu3.inst 0.000036 # Average percentage of cache occupancy 2137system.l2c.occ_percent::cpu3.data 0.000012 # Average percentage of cache occupancy 2138system.l2c.occ_percent::total 0.006490 # Average percentage of cache occupancy 2139system.l2c.ReadReq_hits::cpu0.inst 229 # number of ReadReq hits 2140system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits 2141system.l2c.ReadReq_hits::cpu1.inst 342 # number of ReadReq hits 2142system.l2c.ReadReq_hits::cpu1.data 5 # number of ReadReq hits 2143system.l2c.ReadReq_hits::cpu2.inst 421 # number of ReadReq hits 2144system.l2c.ReadReq_hits::cpu2.data 11 # number of ReadReq hits 2145system.l2c.ReadReq_hits::cpu3.inst 424 # number of ReadReq hits 2146system.l2c.ReadReq_hits::cpu3.data 11 # number of ReadReq hits 2147system.l2c.ReadReq_hits::total 1448 # number of ReadReq hits 2148system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits 2149system.l2c.Writeback_hits::total 1 # number of Writeback hits 2150system.l2c.UpgradeReq_hits::cpu0.data 3 # number of UpgradeReq hits 2151system.l2c.UpgradeReq_hits::total 3 # number of UpgradeReq hits 2152system.l2c.demand_hits::cpu0.inst 229 # number of demand (read+write) hits 2153system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits 2154system.l2c.demand_hits::cpu1.inst 342 # number of demand (read+write) hits 2155system.l2c.demand_hits::cpu1.data 5 # number of demand (read+write) hits 2156system.l2c.demand_hits::cpu2.inst 421 # number of demand (read+write) hits 2157system.l2c.demand_hits::cpu2.data 11 # number of demand (read+write) hits 2158system.l2c.demand_hits::cpu3.inst 424 # number of demand (read+write) hits 2159system.l2c.demand_hits::cpu3.data 11 # number of demand (read+write) hits 2160system.l2c.demand_hits::total 1448 # number of demand (read+write) hits 2161system.l2c.overall_hits::cpu0.inst 229 # number of overall hits 2162system.l2c.overall_hits::cpu0.data 5 # number of overall hits 2163system.l2c.overall_hits::cpu1.inst 342 # number of overall hits 2164system.l2c.overall_hits::cpu1.data 5 # number of overall hits 2165system.l2c.overall_hits::cpu2.inst 421 # number of overall hits 2166system.l2c.overall_hits::cpu2.data 11 # number of overall hits 2167system.l2c.overall_hits::cpu3.inst 424 # number of overall hits 2168system.l2c.overall_hits::cpu3.data 11 # number of overall hits 2169system.l2c.overall_hits::total 1448 # number of overall hits 2170system.l2c.ReadReq_misses::cpu0.inst 359 # number of ReadReq misses 2171system.l2c.ReadReq_misses::cpu0.data 74 # number of ReadReq misses 2172system.l2c.ReadReq_misses::cpu1.inst 83 # number of ReadReq misses 2173system.l2c.ReadReq_misses::cpu1.data 7 # number of ReadReq misses 2174system.l2c.ReadReq_misses::cpu2.inst 8 # number of ReadReq misses 2175system.l2c.ReadReq_misses::cpu2.data 1 # number of ReadReq misses 2176system.l2c.ReadReq_misses::cpu3.inst 4 # number of ReadReq misses 2177system.l2c.ReadReq_misses::cpu3.data 1 # number of ReadReq misses 2178system.l2c.ReadReq_misses::total 537 # number of ReadReq misses 2179system.l2c.UpgradeReq_misses::cpu0.data 19 # number of UpgradeReq misses 2180system.l2c.UpgradeReq_misses::cpu1.data 18 # number of UpgradeReq misses 2181system.l2c.UpgradeReq_misses::cpu2.data 15 # number of UpgradeReq misses 2182system.l2c.UpgradeReq_misses::cpu3.data 20 # number of UpgradeReq misses 2183system.l2c.UpgradeReq_misses::total 72 # number of UpgradeReq misses 2184system.l2c.ReadExReq_misses::cpu0.data 94 # number of ReadExReq misses 2185system.l2c.ReadExReq_misses::cpu1.data 13 # number of ReadExReq misses 2186system.l2c.ReadExReq_misses::cpu2.data 12 # number of ReadExReq misses 2187system.l2c.ReadExReq_misses::cpu3.data 12 # number of ReadExReq misses 2188system.l2c.ReadExReq_misses::total 131 # number of ReadExReq misses 2189system.l2c.demand_misses::cpu0.inst 359 # number of demand (read+write) misses 2190system.l2c.demand_misses::cpu0.data 168 # number of demand (read+write) misses 2191system.l2c.demand_misses::cpu1.inst 83 # number of demand (read+write) misses 2192system.l2c.demand_misses::cpu1.data 20 # number of demand (read+write) misses 2193system.l2c.demand_misses::cpu2.inst 8 # number of demand (read+write) misses 2194system.l2c.demand_misses::cpu2.data 13 # number of demand (read+write) misses 2195system.l2c.demand_misses::cpu3.inst 4 # number of demand (read+write) misses 2196system.l2c.demand_misses::cpu3.data 13 # number of demand (read+write) misses 2197system.l2c.demand_misses::total 668 # number of demand (read+write) misses 2198system.l2c.overall_misses::cpu0.inst 359 # number of overall misses 2199system.l2c.overall_misses::cpu0.data 168 # number of overall misses 2200system.l2c.overall_misses::cpu1.inst 83 # number of overall misses 2201system.l2c.overall_misses::cpu1.data 20 # number of overall misses 2202system.l2c.overall_misses::cpu2.inst 8 # number of overall misses 2203system.l2c.overall_misses::cpu2.data 13 # number of overall misses 2204system.l2c.overall_misses::cpu3.inst 4 # number of overall misses 2205system.l2c.overall_misses::cpu3.data 13 # number of overall misses 2206system.l2c.overall_misses::total 668 # number of overall misses 2207system.l2c.ReadReq_miss_latency::cpu0.inst 17565000 # number of ReadReq miss cycles 2208system.l2c.ReadReq_miss_latency::cpu0.data 4069000 # number of ReadReq miss cycles 2209system.l2c.ReadReq_miss_latency::cpu1.inst 4146500 # number of ReadReq miss cycles 2210system.l2c.ReadReq_miss_latency::cpu1.data 381000 # number of ReadReq miss cycles 2211system.l2c.ReadReq_miss_latency::cpu2.inst 396000 # number of ReadReq miss cycles 2212system.l2c.ReadReq_miss_latency::cpu2.data 68500 # number of ReadReq miss cycles 2213system.l2c.ReadReq_miss_latency::cpu3.inst 233000 # number of ReadReq miss cycles 2214system.l2c.ReadReq_miss_latency::cpu3.data 68500 # number of ReadReq miss cycles 2215system.l2c.ReadReq_miss_latency::total 26927500 # number of ReadReq miss cycles 2216system.l2c.ReadExReq_miss_latency::cpu0.data 5000500 # number of ReadExReq miss cycles 2217system.l2c.ReadExReq_miss_latency::cpu1.data 881000 # number of ReadExReq miss cycles 2218system.l2c.ReadExReq_miss_latency::cpu2.data 699500 # number of ReadExReq miss cycles 2219system.l2c.ReadExReq_miss_latency::cpu3.data 661500 # number of ReadExReq miss cycles 2220system.l2c.ReadExReq_miss_latency::total 7242500 # number of ReadExReq miss cycles 2221system.l2c.demand_miss_latency::cpu0.inst 17565000 # number of demand (read+write) miss cycles 2222system.l2c.demand_miss_latency::cpu0.data 9069500 # number of demand (read+write) miss cycles 2223system.l2c.demand_miss_latency::cpu1.inst 4146500 # number of demand (read+write) miss cycles 2224system.l2c.demand_miss_latency::cpu1.data 1262000 # number of demand (read+write) miss cycles 2225system.l2c.demand_miss_latency::cpu2.inst 396000 # number of demand (read+write) miss cycles 2226system.l2c.demand_miss_latency::cpu2.data 768000 # number of demand (read+write) miss cycles 2227system.l2c.demand_miss_latency::cpu3.inst 233000 # number of demand (read+write) miss cycles 2228system.l2c.demand_miss_latency::cpu3.data 730000 # number of demand (read+write) miss cycles 2229system.l2c.demand_miss_latency::total 34170000 # number of demand (read+write) miss cycles 2230system.l2c.overall_miss_latency::cpu0.inst 17565000 # number of overall miss cycles 2231system.l2c.overall_miss_latency::cpu0.data 9069500 # number of overall miss cycles 2232system.l2c.overall_miss_latency::cpu1.inst 4146500 # number of overall miss cycles 2233system.l2c.overall_miss_latency::cpu1.data 1262000 # number of overall miss cycles 2234system.l2c.overall_miss_latency::cpu2.inst 396000 # number of overall miss cycles 2235system.l2c.overall_miss_latency::cpu2.data 768000 # number of overall miss cycles 2236system.l2c.overall_miss_latency::cpu3.inst 233000 # number of overall miss cycles 2237system.l2c.overall_miss_latency::cpu3.data 730000 # number of overall miss cycles 2238system.l2c.overall_miss_latency::total 34170000 # number of overall miss cycles 2239system.l2c.ReadReq_accesses::cpu0.inst 588 # number of ReadReq accesses(hits+misses) 2240system.l2c.ReadReq_accesses::cpu0.data 79 # number of ReadReq accesses(hits+misses) 2241system.l2c.ReadReq_accesses::cpu1.inst 425 # number of ReadReq accesses(hits+misses) 2242system.l2c.ReadReq_accesses::cpu1.data 12 # number of ReadReq accesses(hits+misses) 2243system.l2c.ReadReq_accesses::cpu2.inst 429 # number of ReadReq accesses(hits+misses) 2244system.l2c.ReadReq_accesses::cpu2.data 12 # number of ReadReq accesses(hits+misses) 2245system.l2c.ReadReq_accesses::cpu3.inst 428 # number of ReadReq accesses(hits+misses) 2246system.l2c.ReadReq_accesses::cpu3.data 12 # number of ReadReq accesses(hits+misses) 2247system.l2c.ReadReq_accesses::total 1985 # number of ReadReq accesses(hits+misses) 2248system.l2c.Writeback_accesses::writebacks 1 # number of Writeback accesses(hits+misses) 2249system.l2c.Writeback_accesses::total 1 # number of Writeback accesses(hits+misses) 2250system.l2c.UpgradeReq_accesses::cpu0.data 22 # number of UpgradeReq accesses(hits+misses) 2251system.l2c.UpgradeReq_accesses::cpu1.data 18 # number of UpgradeReq accesses(hits+misses) 2252system.l2c.UpgradeReq_accesses::cpu2.data 15 # number of UpgradeReq accesses(hits+misses) 2253system.l2c.UpgradeReq_accesses::cpu3.data 20 # number of UpgradeReq accesses(hits+misses) 2254system.l2c.UpgradeReq_accesses::total 75 # number of UpgradeReq accesses(hits+misses) 2255system.l2c.ReadExReq_accesses::cpu0.data 94 # number of ReadExReq accesses(hits+misses) 2256system.l2c.ReadExReq_accesses::cpu1.data 13 # number of ReadExReq accesses(hits+misses) 2257system.l2c.ReadExReq_accesses::cpu2.data 12 # number of ReadExReq accesses(hits+misses) 2258system.l2c.ReadExReq_accesses::cpu3.data 12 # number of ReadExReq accesses(hits+misses) 2259system.l2c.ReadExReq_accesses::total 131 # number of ReadExReq accesses(hits+misses) 2260system.l2c.demand_accesses::cpu0.inst 588 # number of demand (read+write) accesses 2261system.l2c.demand_accesses::cpu0.data 173 # number of demand (read+write) accesses 2262system.l2c.demand_accesses::cpu1.inst 425 # number of demand (read+write) accesses 2263system.l2c.demand_accesses::cpu1.data 25 # number of demand (read+write) accesses 2264system.l2c.demand_accesses::cpu2.inst 429 # number of demand (read+write) accesses 2265system.l2c.demand_accesses::cpu2.data 24 # number of demand (read+write) accesses 2266system.l2c.demand_accesses::cpu3.inst 428 # number of demand (read+write) accesses 2267system.l2c.demand_accesses::cpu3.data 24 # number of demand (read+write) accesses 2268system.l2c.demand_accesses::total 2116 # number of demand (read+write) accesses 2269system.l2c.overall_accesses::cpu0.inst 588 # number of overall (read+write) accesses 2270system.l2c.overall_accesses::cpu0.data 173 # number of overall (read+write) accesses 2271system.l2c.overall_accesses::cpu1.inst 425 # number of overall (read+write) accesses 2272system.l2c.overall_accesses::cpu1.data 25 # number of overall (read+write) accesses 2273system.l2c.overall_accesses::cpu2.inst 429 # number of overall (read+write) accesses 2274system.l2c.overall_accesses::cpu2.data 24 # number of overall (read+write) accesses 2275system.l2c.overall_accesses::cpu3.inst 428 # number of overall (read+write) accesses 2276system.l2c.overall_accesses::cpu3.data 24 # number of overall (read+write) accesses 2277system.l2c.overall_accesses::total 2116 # number of overall (read+write) accesses 2278system.l2c.ReadReq_miss_rate::cpu0.inst 0.610544 # miss rate for ReadReq accesses 2279system.l2c.ReadReq_miss_rate::cpu0.data 0.936709 # miss rate for ReadReq accesses 2280system.l2c.ReadReq_miss_rate::cpu1.inst 0.195294 # miss rate for ReadReq accesses 2281system.l2c.ReadReq_miss_rate::cpu1.data 0.583333 # miss rate for ReadReq accesses 2282system.l2c.ReadReq_miss_rate::cpu2.inst 0.018648 # miss rate for ReadReq accesses 2283system.l2c.ReadReq_miss_rate::cpu2.data 0.083333 # miss rate for ReadReq accesses 2284system.l2c.ReadReq_miss_rate::cpu3.inst 0.009346 # miss rate for ReadReq accesses 2285system.l2c.ReadReq_miss_rate::cpu3.data 0.083333 # miss rate for ReadReq accesses 2286system.l2c.ReadReq_miss_rate::total 0.270529 # miss rate for ReadReq accesses 2287system.l2c.UpgradeReq_miss_rate::cpu0.data 0.863636 # miss rate for UpgradeReq accesses 2288system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses 2289system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses 2290system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses 2291system.l2c.UpgradeReq_miss_rate::total 0.960000 # miss rate for UpgradeReq accesses 2292system.l2c.ReadExReq_miss_rate::cpu0.data 1 # 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miss rate for demand accesses 2305system.l2c.demand_miss_rate::total 0.315690 # miss rate for demand accesses 2306system.l2c.overall_miss_rate::cpu0.inst 0.610544 # miss rate for overall accesses 2307system.l2c.overall_miss_rate::cpu0.data 0.971098 # miss rate for overall accesses 2308system.l2c.overall_miss_rate::cpu1.inst 0.195294 # miss rate for overall accesses 2309system.l2c.overall_miss_rate::cpu1.data 0.800000 # miss rate for overall accesses 2310system.l2c.overall_miss_rate::cpu2.inst 0.018648 # miss rate for overall accesses 2311system.l2c.overall_miss_rate::cpu2.data 0.541667 # miss rate for overall accesses 2312system.l2c.overall_miss_rate::cpu3.inst 0.009346 # miss rate for overall accesses 2313system.l2c.overall_miss_rate::cpu3.data 0.541667 # miss rate for overall accesses 2314system.l2c.overall_miss_rate::total 0.315690 # miss rate for overall accesses 2315system.l2c.ReadReq_avg_miss_latency::cpu0.inst 48927.576602 # average ReadReq miss latency 2316system.l2c.ReadReq_avg_miss_latency::cpu0.data 54986.486486 # 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average overall miss latency 2339system.l2c.overall_avg_miss_latency::cpu0.data 53985.119048 # average overall miss latency 2340system.l2c.overall_avg_miss_latency::cpu1.inst 49957.831325 # average overall miss latency 2341system.l2c.overall_avg_miss_latency::cpu1.data 63100 # average overall miss latency 2342system.l2c.overall_avg_miss_latency::cpu2.inst 49500 # average overall miss latency 2343system.l2c.overall_avg_miss_latency::cpu2.data 59076.923077 # average overall miss latency 2344system.l2c.overall_avg_miss_latency::cpu3.inst 58250 # average overall miss latency 2345system.l2c.overall_avg_miss_latency::cpu3.data 56153.846154 # average overall miss latency 2346system.l2c.overall_avg_miss_latency::total 51152.694611 # average overall miss latency 2347system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2348system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 2349system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 2350system.l2c.blocked::no_targets 0 # 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number of demand (read+write) MSHR misses 2389system.l2c.demand_mshr_misses::cpu1.data 20 # number of demand (read+write) MSHR misses 2390system.l2c.demand_mshr_misses::cpu2.inst 3 # number of demand (read+write) MSHR misses 2391system.l2c.demand_mshr_misses::cpu2.data 13 # number of demand (read+write) MSHR misses 2392system.l2c.demand_mshr_misses::cpu3.inst 4 # number of demand (read+write) MSHR misses 2393system.l2c.demand_mshr_misses::cpu3.data 13 # number of demand (read+write) MSHR misses 2394system.l2c.demand_mshr_misses::total 659 # number of demand (read+write) MSHR misses 2395system.l2c.overall_mshr_misses::cpu0.inst 357 # number of overall MSHR misses 2396system.l2c.overall_mshr_misses::cpu0.data 168 # number of overall MSHR misses 2397system.l2c.overall_mshr_misses::cpu1.inst 81 # number of overall MSHR misses 2398system.l2c.overall_mshr_misses::cpu1.data 20 # number of overall MSHR misses 2399system.l2c.overall_mshr_misses::cpu2.inst 3 # number of overall MSHR misses 2400system.l2c.overall_mshr_misses::cpu2.data 13 # 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number of ReadExReq MSHR miss cycles 2423system.l2c.demand_mshr_miss_latency::cpu0.inst 13017059 # number of demand (read+write) MSHR miss cycles 2424system.l2c.demand_mshr_miss_latency::cpu0.data 6980186 # number of demand (read+write) MSHR miss cycles 2425system.l2c.demand_mshr_miss_latency::cpu1.inst 3026126 # number of demand (read+write) MSHR miss cycles 2426system.l2c.demand_mshr_miss_latency::cpu1.data 1012523 # number of demand (read+write) MSHR miss cycles 2427system.l2c.demand_mshr_miss_latency::cpu2.inst 103002 # number of demand (read+write) MSHR miss cycles 2428system.l2c.demand_mshr_miss_latency::cpu2.data 605020 # number of demand (read+write) MSHR miss cycles 2429system.l2c.demand_mshr_miss_latency::cpu3.inst 181507 # number of demand (read+write) MSHR miss cycles 2430system.l2c.demand_mshr_miss_latency::cpu3.data 567020 # number of demand (read+write) MSHR miss cycles 2431system.l2c.demand_mshr_miss_latency::total 25492443 # number of demand (read+write) MSHR miss cycles 2432system.l2c.overall_mshr_miss_latency::cpu0.inst 13017059 # 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mshr miss rate for ReadReq accesses 2444system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.583333 # mshr miss rate for ReadReq accesses 2445system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.006993 # mshr miss rate for ReadReq accesses 2446system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.083333 # mshr miss rate for ReadReq accesses 2447system.l2c.ReadReq_mshr_miss_rate::cpu3.inst 0.009346 # mshr miss rate for ReadReq accesses 2448system.l2c.ReadReq_mshr_miss_rate::cpu3.data 0.083333 # mshr miss rate for ReadReq accesses 2449system.l2c.ReadReq_mshr_miss_rate::total 0.265995 # mshr miss rate for ReadReq accesses 2450system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.863636 # mshr miss rate for UpgradeReq accesses 2451system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses 2452system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for UpgradeReq accesses 2453system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for UpgradeReq accesses 2454system.l2c.UpgradeReq_mshr_miss_rate::total 0.960000 # mshr miss rate for UpgradeReq accesses 2455system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses 2456system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses 2457system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses 2458system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for ReadExReq accesses 2459system.l2c.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 2460system.l2c.demand_mshr_miss_rate::cpu0.inst 0.607143 # mshr miss rate for demand accesses 2461system.l2c.demand_mshr_miss_rate::cpu0.data 0.971098 # mshr miss rate for demand accesses 2462system.l2c.demand_mshr_miss_rate::cpu1.inst 0.190588 # mshr miss rate for demand accesses 2463system.l2c.demand_mshr_miss_rate::cpu1.data 0.800000 # mshr miss rate for demand accesses 2464system.l2c.demand_mshr_miss_rate::cpu2.inst 0.006993 # mshr miss rate for demand accesses 2465system.l2c.demand_mshr_miss_rate::cpu2.data 0.541667 # mshr miss rate for demand accesses 2466system.l2c.demand_mshr_miss_rate::cpu3.inst 0.009346 # mshr miss rate for demand accesses 2467system.l2c.demand_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for demand accesses 2468system.l2c.demand_mshr_miss_rate::total 0.311437 # mshr miss rate for demand accesses 2469system.l2c.overall_mshr_miss_rate::cpu0.inst 0.607143 # mshr miss rate for overall accesses 2470system.l2c.overall_mshr_miss_rate::cpu0.data 0.971098 # mshr miss rate for overall accesses 2471system.l2c.overall_mshr_miss_rate::cpu1.inst 0.190588 # mshr miss rate for overall accesses 2472system.l2c.overall_mshr_miss_rate::cpu1.data 0.800000 # mshr miss rate for overall accesses 2473system.l2c.overall_mshr_miss_rate::cpu2.inst 0.006993 # mshr miss rate for overall accesses 2474system.l2c.overall_mshr_miss_rate::cpu2.data 0.541667 # mshr miss rate for overall accesses 2475system.l2c.overall_mshr_miss_rate::cpu3.inst 0.009346 # mshr miss rate for overall accesses 2476system.l2c.overall_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for overall accesses 2477system.l2c.overall_mshr_miss_rate::total 0.311437 # mshr miss rate for overall accesses 2478system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 36462.350140 # average ReadReq mshr miss latency 2479system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 42575.351351 # average ReadReq mshr miss latency 2480system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 37359.580247 # average ReadReq mshr miss latency 2481system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 41858.571429 # average ReadReq mshr miss latency 2482system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 34334 # average ReadReq mshr miss latency 2483system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 56002 # average ReadReq mshr miss latency 2484system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 45376.750000 # average ReadReq mshr miss latency 2485system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 56002 # average ReadReq mshr miss latency 2486system.l2c.ReadReq_avg_mshr_miss_latency::total 37657.734848 # average ReadReq mshr miss latency 2487system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10158.578947 # average UpgradeReq mshr miss latency 2488system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10084.166667 # average UpgradeReq mshr miss latency 2489system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10200.600000 # average UpgradeReq mshr miss latency 2490system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 10025.950000 # average UpgradeReq mshr miss latency 2491system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10111.888889 # average UpgradeReq mshr miss latency 2492system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40740.531915 # average ReadExReq mshr miss latency 2493system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 55347.153846 # average ReadExReq mshr miss latency 2494system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 45751.500000 # average ReadExReq mshr miss latency 2495system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 42584.833333 # average ReadExReq mshr miss latency 2496system.l2c.ReadExReq_avg_mshr_miss_latency::total 42818.007634 # average ReadExReq mshr miss latency 2497system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 36462.350140 # average overall mshr miss latency 2498system.l2c.demand_avg_mshr_miss_latency::cpu0.data 41548.726190 # average overall mshr miss latency 2499system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 37359.580247 # average overall mshr miss latency 2500system.l2c.demand_avg_mshr_miss_latency::cpu1.data 50626.150000 # average overall mshr miss latency 2501system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 34334 # average overall mshr miss latency 2502system.l2c.demand_avg_mshr_miss_latency::cpu2.data 46540 # average overall mshr miss latency 2503system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 45376.750000 # average overall mshr miss latency 2504system.l2c.demand_avg_mshr_miss_latency::cpu3.data 43616.923077 # average overall mshr miss latency 2505system.l2c.demand_avg_mshr_miss_latency::total 38683.525038 # average overall mshr miss latency 2506system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 36462.350140 # average overall mshr miss latency 2507system.l2c.overall_avg_mshr_miss_latency::cpu0.data 41548.726190 # average overall mshr miss latency 2508system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 37359.580247 # average overall mshr miss latency 2509system.l2c.overall_avg_mshr_miss_latency::cpu1.data 50626.150000 # average overall mshr miss latency 2510system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 34334 # average overall mshr miss latency 2511system.l2c.overall_avg_mshr_miss_latency::cpu2.data 46540 # average overall mshr miss latency 2512system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 45376.750000 # average overall mshr miss latency 2513system.l2c.overall_avg_mshr_miss_latency::cpu3.data 43616.923077 # average overall mshr miss latency 2514system.l2c.overall_avg_mshr_miss_latency::total 38683.525038 # average overall mshr miss latency 2515system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 2516 2517---------- End Simulation Statistics ---------- 2518