stats.txt revision 11312:3d7a85d71bd1
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000108 # Number of seconds simulated 4sim_ticks 107836000 # Number of ticks simulated 5final_tick 107836000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 68965 # Simulator instruction rate (inst/s) 8host_op_rate 68965 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 7480497 # Simulator tick rate (ticks/s) 10host_mem_usage 247424 # Number of bytes of host memory used 11host_seconds 14.42 # Real time elapsed on the host 12sim_insts 994171 # Number of instructions simulated 13sim_ops 994171 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu0.inst 23040 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.data 10816 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu1.inst 5120 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu1.data 1280 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu2.inst 192 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu2.data 832 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu3.inst 448 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu3.data 832 # Number of bytes read from this memory 24system.physmem.bytes_read::total 42560 # Number of bytes read from this memory 25system.physmem.bytes_inst_read::cpu0.inst 23040 # Number of instructions bytes read from this memory 26system.physmem.bytes_inst_read::cpu1.inst 5120 # Number of instructions bytes read from this memory 27system.physmem.bytes_inst_read::cpu2.inst 192 # Number of instructions bytes read from this memory 28system.physmem.bytes_inst_read::cpu3.inst 448 # Number of instructions bytes read from this memory 29system.physmem.bytes_inst_read::total 28800 # Number of instructions bytes read from this memory 30system.physmem.num_reads::cpu0.inst 360 # Number of read requests responded to by this memory 31system.physmem.num_reads::cpu0.data 169 # Number of read requests responded to by this memory 32system.physmem.num_reads::cpu1.inst 80 # Number of read requests responded to by this memory 33system.physmem.num_reads::cpu1.data 20 # Number of read requests responded to by this memory 34system.physmem.num_reads::cpu2.inst 3 # Number of read requests responded to by this memory 35system.physmem.num_reads::cpu2.data 13 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu3.inst 7 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu3.data 13 # Number of read requests responded to by this memory 38system.physmem.num_reads::total 665 # Number of read requests responded to by this memory 39system.physmem.bw_read::cpu0.inst 213657777 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::cpu0.data 100300456 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::cpu1.inst 47479506 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_read::cpu1.data 11869876 # Total read bandwidth from this memory (bytes/s) 43system.physmem.bw_read::cpu2.inst 1780481 # Total read bandwidth from this memory (bytes/s) 44system.physmem.bw_read::cpu2.data 7715420 # Total read bandwidth from this memory (bytes/s) 45system.physmem.bw_read::cpu3.inst 4154457 # Total read bandwidth from this memory (bytes/s) 46system.physmem.bw_read::cpu3.data 7715420 # Total read bandwidth from this memory (bytes/s) 47system.physmem.bw_read::total 394673393 # Total read bandwidth from this memory (bytes/s) 48system.physmem.bw_inst_read::cpu0.inst 213657777 # Instruction read bandwidth from this memory (bytes/s) 49system.physmem.bw_inst_read::cpu1.inst 47479506 # Instruction read bandwidth from this memory (bytes/s) 50system.physmem.bw_inst_read::cpu2.inst 1780481 # Instruction read bandwidth from this memory (bytes/s) 51system.physmem.bw_inst_read::cpu3.inst 4154457 # Instruction read bandwidth from this memory (bytes/s) 52system.physmem.bw_inst_read::total 267072221 # Instruction read bandwidth from this memory (bytes/s) 53system.physmem.bw_total::cpu0.inst 213657777 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.bw_total::cpu0.data 100300456 # Total bandwidth to/from this memory (bytes/s) 55system.physmem.bw_total::cpu1.inst 47479506 # Total bandwidth to/from this memory (bytes/s) 56system.physmem.bw_total::cpu1.data 11869876 # Total bandwidth to/from this memory (bytes/s) 57system.physmem.bw_total::cpu2.inst 1780481 # Total bandwidth to/from this memory (bytes/s) 58system.physmem.bw_total::cpu2.data 7715420 # Total bandwidth to/from this memory (bytes/s) 59system.physmem.bw_total::cpu3.inst 4154457 # Total bandwidth to/from this memory (bytes/s) 60system.physmem.bw_total::cpu3.data 7715420 # Total bandwidth to/from this memory (bytes/s) 61system.physmem.bw_total::total 394673393 # Total bandwidth to/from this memory (bytes/s) 62system.physmem.readReqs 666 # Number of read requests accepted 63system.physmem.writeReqs 0 # Number of write requests accepted 64system.physmem.readBursts 666 # Number of DRAM read bursts, including those serviced by the write queue 65system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 66system.physmem.bytesReadDRAM 42624 # Total number of bytes read from DRAM 67system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 68system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 69system.physmem.bytesReadSys 42624 # Total read bytes from the system interface side 70system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 71system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 72system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 73system.physmem.neitherReadNorWriteReqs 89 # Number of requests that are neither read nor write 74system.physmem.perBankRdBursts::0 114 # Per bank write bursts 75system.physmem.perBankRdBursts::1 42 # Per bank write bursts 76system.physmem.perBankRdBursts::2 30 # Per bank write bursts 77system.physmem.perBankRdBursts::3 60 # Per bank write bursts 78system.physmem.perBankRdBursts::4 66 # Per bank write bursts 79system.physmem.perBankRdBursts::5 27 # Per bank write bursts 80system.physmem.perBankRdBursts::6 18 # Per bank write bursts 81system.physmem.perBankRdBursts::7 24 # Per bank write bursts 82system.physmem.perBankRdBursts::8 7 # Per bank write bursts 83system.physmem.perBankRdBursts::9 28 # Per bank write bursts 84system.physmem.perBankRdBursts::10 23 # Per bank write bursts 85system.physmem.perBankRdBursts::11 13 # Per bank write bursts 86system.physmem.perBankRdBursts::12 61 # Per bank write bursts 87system.physmem.perBankRdBursts::13 38 # Per bank write bursts 88system.physmem.perBankRdBursts::14 18 # Per bank write bursts 89system.physmem.perBankRdBursts::15 97 # Per bank write bursts 90system.physmem.perBankWrBursts::0 0 # Per bank write bursts 91system.physmem.perBankWrBursts::1 0 # Per bank write bursts 92system.physmem.perBankWrBursts::2 0 # Per bank write bursts 93system.physmem.perBankWrBursts::3 0 # Per bank write bursts 94system.physmem.perBankWrBursts::4 0 # Per bank write bursts 95system.physmem.perBankWrBursts::5 0 # Per bank write bursts 96system.physmem.perBankWrBursts::6 0 # Per bank write bursts 97system.physmem.perBankWrBursts::7 0 # Per bank write bursts 98system.physmem.perBankWrBursts::8 0 # Per bank write bursts 99system.physmem.perBankWrBursts::9 0 # Per bank write bursts 100system.physmem.perBankWrBursts::10 0 # Per bank write bursts 101system.physmem.perBankWrBursts::11 0 # Per bank write bursts 102system.physmem.perBankWrBursts::12 0 # Per bank write bursts 103system.physmem.perBankWrBursts::13 0 # Per bank write bursts 104system.physmem.perBankWrBursts::14 0 # Per bank write bursts 105system.physmem.perBankWrBursts::15 0 # Per bank write bursts 106system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 107system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 108system.physmem.totGap 107808000 # Total gap between requests 109system.physmem.readPktSize::0 0 # Read request sizes (log2) 110system.physmem.readPktSize::1 0 # Read request sizes (log2) 111system.physmem.readPktSize::2 0 # Read request sizes (log2) 112system.physmem.readPktSize::3 0 # Read request sizes (log2) 113system.physmem.readPktSize::4 0 # Read request sizes (log2) 114system.physmem.readPktSize::5 0 # Read request sizes (log2) 115system.physmem.readPktSize::6 666 # Read request sizes (log2) 116system.physmem.writePktSize::0 0 # Write request sizes (log2) 117system.physmem.writePktSize::1 0 # Write request sizes (log2) 118system.physmem.writePktSize::2 0 # Write request sizes (log2) 119system.physmem.writePktSize::3 0 # Write request sizes (log2) 120system.physmem.writePktSize::4 0 # Write request sizes (log2) 121system.physmem.writePktSize::5 0 # Write request sizes (log2) 122system.physmem.writePktSize::6 0 # Write request sizes (log2) 123system.physmem.rdQLenPdf::0 396 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::1 199 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::2 54 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::3 13 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 155system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 218system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 219system.physmem.bytesPerActivate::samples 145 # Bytes accessed per row activation 220system.physmem.bytesPerActivate::mean 274.537931 # Bytes accessed per row activation 221system.physmem.bytesPerActivate::gmean 187.244268 # Bytes accessed per row activation 222system.physmem.bytesPerActivate::stdev 251.506931 # Bytes accessed per row activation 223system.physmem.bytesPerActivate::0-127 44 30.34% 30.34% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::128-255 37 25.52% 55.86% # Bytes accessed per row activation 225system.physmem.bytesPerActivate::256-383 28 19.31% 75.17% # Bytes accessed per row activation 226system.physmem.bytesPerActivate::384-511 11 7.59% 82.76% # Bytes accessed per row activation 227system.physmem.bytesPerActivate::512-639 7 4.83% 87.59% # Bytes accessed per row activation 228system.physmem.bytesPerActivate::640-767 8 5.52% 93.10% # Bytes accessed per row activation 229system.physmem.bytesPerActivate::768-895 2 1.38% 94.48% # Bytes accessed per row activation 230system.physmem.bytesPerActivate::896-1023 3 2.07% 96.55% # Bytes accessed per row activation 231system.physmem.bytesPerActivate::1024-1151 5 3.45% 100.00% # Bytes accessed per row activation 232system.physmem.bytesPerActivate::total 145 # Bytes accessed per row activation 233system.physmem.totQLat 6565250 # Total ticks spent queuing 234system.physmem.totMemAccLat 19052750 # Total ticks spent from burst creation until serviced by the DRAM 235system.physmem.totBusLat 3330000 # Total ticks spent in databus transfers 236system.physmem.avgQLat 9857.73 # Average queueing delay per DRAM burst 237system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 238system.physmem.avgMemAccLat 28607.73 # Average memory access latency per DRAM burst 239system.physmem.avgRdBW 395.27 # Average DRAM read bandwidth in MiByte/s 240system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 241system.physmem.avgRdBWSys 395.27 # Average system read bandwidth in MiByte/s 242system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 243system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 244system.physmem.busUtil 3.09 # Data bus utilization in percentage 245system.physmem.busUtilRead 3.09 # Data bus utilization in percentage for reads 246system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 247system.physmem.avgRdQLen 1.29 # Average read queue length when enqueuing 248system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 249system.physmem.readRowHits 510 # Number of row buffer hits during reads 250system.physmem.writeRowHits 0 # Number of row buffer hits during writes 251system.physmem.readRowHitRate 76.58 # Row buffer hit rate for reads 252system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 253system.physmem.avgGap 161873.87 # Average gap between requests 254system.physmem.pageHitRate 76.58 # Row buffer hit rate, read and write combined 255system.physmem_0.actEnergy 710640 # Energy for activate commands per rank (pJ) 256system.physmem_0.preEnergy 387750 # Energy for precharge commands per rank (pJ) 257system.physmem_0.readEnergy 2769000 # Energy for read commands per rank (pJ) 258system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 259system.physmem_0.refreshEnergy 6611280 # Energy for refresh commands per rank (pJ) 260system.physmem_0.actBackEnergy 38088540 # Energy for active background per rank (pJ) 261system.physmem_0.preBackEnergy 27477750 # Energy for precharge background per rank (pJ) 262system.physmem_0.totalEnergy 76044960 # Total energy per rank (pJ) 263system.physmem_0.averagePower 749.349855 # Core power per rank (mW) 264system.physmem_0.memoryStateTime::IDLE 47969250 # Time in different power states 265system.physmem_0.memoryStateTime::REF 3380000 # Time in different power states 266system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 267system.physmem_0.memoryStateTime::ACT 52649750 # Time in different power states 268system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 269system.physmem_1.actEnergy 355320 # Energy for activate commands per rank (pJ) 270system.physmem_1.preEnergy 193875 # Energy for precharge commands per rank (pJ) 271system.physmem_1.readEnergy 2028000 # Energy for read commands per rank (pJ) 272system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 273system.physmem_1.refreshEnergy 6611280 # Energy for refresh commands per rank (pJ) 274system.physmem_1.actBackEnergy 32065065 # Energy for active background per rank (pJ) 275system.physmem_1.preBackEnergy 32761500 # Energy for precharge background per rank (pJ) 276system.physmem_1.totalEnergy 74015040 # Total energy per rank (pJ) 277system.physmem_1.averagePower 729.346948 # Core power per rank (mW) 278system.physmem_1.memoryStateTime::IDLE 57811250 # Time in different power states 279system.physmem_1.memoryStateTime::REF 3380000 # Time in different power states 280system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 281system.physmem_1.memoryStateTime::ACT 43803750 # Time in different power states 282system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 283system.cpu0.branchPred.lookups 81652 # Number of BP lookups 284system.cpu0.branchPred.condPredicted 79008 # Number of conditional branches predicted 285system.cpu0.branchPred.condIncorrect 1100 # Number of conditional branches incorrect 286system.cpu0.branchPred.BTBLookups 78985 # Number of BTB lookups 287system.cpu0.branchPred.BTBHits 76270 # Number of BTB hits 288system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 289system.cpu0.branchPred.BTBHitPct 96.562638 # BTB Hit Percentage 290system.cpu0.branchPred.usedRAS 645 # Number of times the RAS was used to get a target. 291system.cpu0.branchPred.RASInCorrect 128 # Number of incorrect RAS predictions. 292system.cpu_clk_domain.clock 500 # Clock period in ticks 293system.cpu0.workload.num_syscalls 89 # Number of system calls 294system.cpu0.numCycles 215673 # number of cpu cycles simulated 295system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 296system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 297system.cpu0.fetch.icacheStallCycles 19729 # Number of cycles fetch is stalled on an Icache miss 298system.cpu0.fetch.Insts 482689 # Number of instructions fetch has processed 299system.cpu0.fetch.Branches 81652 # Number of branches that fetch encountered 300system.cpu0.fetch.predictedBranches 76915 # Number of branches that fetch has predicted taken 301system.cpu0.fetch.Cycles 165939 # Number of cycles fetch has run and was not squashing or blocked 302system.cpu0.fetch.SquashCycles 2501 # Number of cycles fetch has spent squashing 303system.cpu0.fetch.TlbCycles 96 # Number of cycles fetch has spent waiting for tlb 304system.cpu0.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 305system.cpu0.fetch.PendingTrapStallCycles 1994 # Number of stall cycles due to pending traps 306system.cpu0.fetch.CacheLines 6734 # Number of cache lines fetched 307system.cpu0.fetch.IcacheSquashes 621 # Number of outstanding Icache misses that were squashed 308system.cpu0.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed 309system.cpu0.fetch.rateDist::samples 189011 # Number of instructions fetched each cycle (Total) 310system.cpu0.fetch.rateDist::mean 2.553761 # Number of instructions fetched each cycle (Total) 311system.cpu0.fetch.rateDist::stdev 2.213837 # Number of instructions fetched each cycle (Total) 312system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 313system.cpu0.fetch.rateDist::0 30617 16.20% 16.20% # Number of instructions fetched each cycle (Total) 314system.cpu0.fetch.rateDist::1 78326 41.44% 57.64% # Number of instructions fetched each cycle (Total) 315system.cpu0.fetch.rateDist::2 798 0.42% 58.06% # Number of instructions fetched each cycle (Total) 316system.cpu0.fetch.rateDist::3 1203 0.64% 58.70% # Number of instructions fetched each cycle (Total) 317system.cpu0.fetch.rateDist::4 614 0.32% 59.02% # Number of instructions fetched each cycle (Total) 318system.cpu0.fetch.rateDist::5 73725 39.01% 98.03% # Number of instructions fetched each cycle (Total) 319system.cpu0.fetch.rateDist::6 672 0.36% 98.38% # Number of instructions fetched each cycle (Total) 320system.cpu0.fetch.rateDist::7 403 0.21% 98.60% # Number of instructions fetched each cycle (Total) 321system.cpu0.fetch.rateDist::8 2653 1.40% 100.00% # Number of instructions fetched each cycle (Total) 322system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 323system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 324system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 325system.cpu0.fetch.rateDist::total 189011 # Number of instructions fetched each cycle (Total) 326system.cpu0.fetch.branchRate 0.378592 # Number of branch fetches per cycle 327system.cpu0.fetch.rate 2.238059 # Number of inst fetches per cycle 328system.cpu0.decode.IdleCycles 15475 # Number of cycles decode is idle 329system.cpu0.decode.BlockedCycles 18570 # Number of cycles decode is blocked 330system.cpu0.decode.RunCycles 153063 # Number of cycles decode is running 331system.cpu0.decode.UnblockCycles 653 # Number of cycles decode is unblocking 332system.cpu0.decode.SquashCycles 1250 # Number of cycles decode is squashing 333system.cpu0.decode.DecodedInsts 472193 # Number of instructions handled by decode 334system.cpu0.rename.SquashCycles 1250 # Number of cycles rename is squashing 335system.cpu0.rename.IdleCycles 16079 # Number of cycles rename is idle 336system.cpu0.rename.BlockCycles 2117 # Number of cycles rename is blocking 337system.cpu0.rename.serializeStallCycles 15116 # count of cycles rename stalled for serializing inst 338system.cpu0.rename.RunCycles 153063 # Number of cycles rename is running 339system.cpu0.rename.UnblockCycles 1386 # Number of cycles rename is unblocking 340system.cpu0.rename.RenamedInsts 469016 # Number of instructions processed by rename 341system.cpu0.rename.IQFullEvents 11 # Number of times rename has blocked due to IQ full 342system.cpu0.rename.LQFullEvents 11 # Number of times rename has blocked due to LQ full 343system.cpu0.rename.SQFullEvents 883 # Number of times rename has blocked due to SQ full 344system.cpu0.rename.RenamedOperands 320676 # Number of destination operands rename has renamed 345system.cpu0.rename.RenameLookups 935403 # Number of register rename lookups that rename has made 346system.cpu0.rename.int_rename_lookups 706479 # Number of integer rename lookups 347system.cpu0.rename.CommittedMaps 307583 # Number of HB maps that are committed 348system.cpu0.rename.UndoneMaps 13093 # Number of HB maps that are undone due to squashing 349system.cpu0.rename.serializingInsts 822 # count of serializing insts renamed 350system.cpu0.rename.tempSerializingInsts 832 # count of temporary serializing insts renamed 351system.cpu0.rename.skidInsts 4383 # count of insts added to the skid buffer 352system.cpu0.memDep0.insertedLoads 150037 # Number of loads inserted to the mem dependence unit. 353system.cpu0.memDep0.insertedStores 75873 # Number of stores inserted to the mem dependence unit. 354system.cpu0.memDep0.conflictingLoads 73364 # Number of conflicting loads. 355system.cpu0.memDep0.conflictingStores 72959 # Number of conflicting stores. 356system.cpu0.iq.iqInstsAdded 392343 # Number of instructions added to the IQ (excludes non-spec) 357system.cpu0.iq.iqNonSpecInstsAdded 889 # Number of non-speculative instructions added to the IQ 358system.cpu0.iq.iqInstsIssued 388906 # Number of instructions issued 359system.cpu0.iq.iqSquashedInstsIssued 31 # Number of squashed instructions issued 360system.cpu0.iq.iqSquashedInstsExamined 12322 # Number of squashed instructions iterated over during squash; mainly for profiling 361system.cpu0.iq.iqSquashedOperandsExamined 11733 # Number of squashed operands that are examined and possibly removed from graph 362system.cpu0.iq.iqSquashedNonSpecRemoved 330 # Number of squashed non-spec instructions that were removed 363system.cpu0.iq.issued_per_cycle::samples 189011 # Number of insts issued each cycle 364system.cpu0.iq.issued_per_cycle::mean 2.057584 # Number of insts issued each cycle 365system.cpu0.iq.issued_per_cycle::stdev 1.125737 # Number of insts issued each cycle 366system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 367system.cpu0.iq.issued_per_cycle::0 33687 17.82% 17.82% # Number of insts issued each cycle 368system.cpu0.iq.issued_per_cycle::1 4243 2.24% 20.07% # Number of insts issued each cycle 369system.cpu0.iq.issued_per_cycle::2 74165 39.24% 59.31% # Number of insts issued each cycle 370system.cpu0.iq.issued_per_cycle::3 73776 39.03% 98.34% # Number of insts issued each cycle 371system.cpu0.iq.issued_per_cycle::4 1622 0.86% 99.20% # Number of insts issued each cycle 372system.cpu0.iq.issued_per_cycle::5 890 0.47% 99.67% # Number of insts issued each cycle 373system.cpu0.iq.issued_per_cycle::6 405 0.21% 99.88% # Number of insts issued each cycle 374system.cpu0.iq.issued_per_cycle::7 147 0.08% 99.96% # Number of insts issued each cycle 375system.cpu0.iq.issued_per_cycle::8 76 0.04% 100.00% # Number of insts issued each cycle 376system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 377system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 378system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 379system.cpu0.iq.issued_per_cycle::total 189011 # Number of insts issued each cycle 380system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 381system.cpu0.iq.fu_full::IntAlu 62 21.45% 21.45% # attempts to use FU when none available 382system.cpu0.iq.fu_full::IntMult 0 0.00% 21.45% # attempts to use FU when none available 383system.cpu0.iq.fu_full::IntDiv 0 0.00% 21.45% # attempts to use FU when none available 384system.cpu0.iq.fu_full::FloatAdd 0 0.00% 21.45% # attempts to use FU when none available 385system.cpu0.iq.fu_full::FloatCmp 0 0.00% 21.45% # attempts to use FU when none available 386system.cpu0.iq.fu_full::FloatCvt 0 0.00% 21.45% # attempts to use FU when none available 387system.cpu0.iq.fu_full::FloatMult 0 0.00% 21.45% # attempts to use FU when none available 388system.cpu0.iq.fu_full::FloatDiv 0 0.00% 21.45% # attempts to use FU when none available 389system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 21.45% # attempts to use FU when none available 390system.cpu0.iq.fu_full::SimdAdd 0 0.00% 21.45% # attempts to use FU when none available 391system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 21.45% # attempts to use FU when none available 392system.cpu0.iq.fu_full::SimdAlu 0 0.00% 21.45% # attempts to use FU when none available 393system.cpu0.iq.fu_full::SimdCmp 0 0.00% 21.45% # attempts to use FU when none available 394system.cpu0.iq.fu_full::SimdCvt 0 0.00% 21.45% # attempts to use FU when none available 395system.cpu0.iq.fu_full::SimdMisc 0 0.00% 21.45% # attempts to use FU when none available 396system.cpu0.iq.fu_full::SimdMult 0 0.00% 21.45% # attempts to use FU when none available 397system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 21.45% # attempts to use FU when none available 398system.cpu0.iq.fu_full::SimdShift 0 0.00% 21.45% # attempts to use FU when none available 399system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 21.45% # attempts to use FU when none available 400system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 21.45% # attempts to use FU when none available 401system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 21.45% # attempts to use FU when none available 402system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 21.45% # attempts to use FU when none available 403system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 21.45% # attempts to use FU when none available 404system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 21.45% # attempts to use FU when none available 405system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 21.45% # attempts to use FU when none available 406system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 21.45% # attempts to use FU when none available 407system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 21.45% # attempts to use FU when none available 408system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 21.45% # attempts to use FU when none available 409system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 21.45% # attempts to use FU when none available 410system.cpu0.iq.fu_full::MemRead 124 42.91% 64.36% # attempts to use FU when none available 411system.cpu0.iq.fu_full::MemWrite 103 35.64% 100.00% # attempts to use FU when none available 412system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 413system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 414system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 415system.cpu0.iq.FU_type_0::IntAlu 164396 42.27% 42.27% # Type of FU issued 416system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.27% # Type of FU issued 417system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.27% # Type of FU issued 418system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.27% # Type of FU issued 419system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.27% # Type of FU issued 420system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.27% # Type of FU issued 421system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.27% # Type of FU issued 422system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.27% # Type of FU issued 423system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.27% # Type of FU issued 424system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.27% # Type of FU issued 425system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.27% # Type of FU issued 426system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.27% # Type of FU issued 427system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.27% # Type of FU issued 428system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.27% # Type of FU issued 429system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.27% # Type of FU issued 430system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.27% # Type of FU issued 431system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.27% # Type of FU issued 432system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.27% # Type of FU issued 433system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.27% # Type of FU issued 434system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.27% # Type of FU issued 435system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.27% # Type of FU issued 436system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.27% # Type of FU issued 437system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.27% # Type of FU issued 438system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.27% # Type of FU issued 439system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.27% # Type of FU issued 440system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.27% # Type of FU issued 441system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.27% # Type of FU issued 442system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.27% # Type of FU issued 443system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.27% # Type of FU issued 444system.cpu0.iq.FU_type_0::MemRead 149390 38.41% 80.68% # Type of FU issued 445system.cpu0.iq.FU_type_0::MemWrite 75120 19.32% 100.00% # Type of FU issued 446system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 447system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 448system.cpu0.iq.FU_type_0::total 388906 # Type of FU issued 449system.cpu0.iq.rate 1.803221 # Inst issue rate 450system.cpu0.iq.fu_busy_cnt 289 # FU busy when requested 451system.cpu0.iq.fu_busy_rate 0.000743 # FU busy rate (busy events/executed inst) 452system.cpu0.iq.int_inst_queue_reads 967143 # Number of integer instruction queue reads 453system.cpu0.iq.int_inst_queue_writes 405616 # Number of integer instruction queue writes 454system.cpu0.iq.int_inst_queue_wakeup_accesses 387054 # Number of integer instruction queue wakeup accesses 455system.cpu0.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads 456system.cpu0.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes 457system.cpu0.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses 458system.cpu0.iq.int_alu_accesses 389195 # Number of integer alu accesses 459system.cpu0.iq.fp_alu_accesses 0 # Number of floating point alu accesses 460system.cpu0.iew.lsq.thread0.forwLoads 72474 # Number of loads that had data forwarded from stores 461system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 462system.cpu0.iew.lsq.thread0.squashedLoads 2656 # Number of loads squashed 463system.cpu0.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed 464system.cpu0.iew.lsq.thread0.memOrderViolation 63 # Number of memory ordering violations 465system.cpu0.iew.lsq.thread0.squashedStores 1676 # Number of stores squashed 466system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 467system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 468system.cpu0.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 469system.cpu0.iew.lsq.thread0.cacheBlocked 22 # Number of times an access to memory failed due to the cache being blocked 470system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle 471system.cpu0.iew.iewSquashCycles 1250 # Number of cycles IEW is squashing 472system.cpu0.iew.iewBlockCycles 2081 # Number of cycles IEW is blocking 473system.cpu0.iew.iewUnblockCycles 38 # Number of cycles IEW is unblocking 474system.cpu0.iew.iewDispatchedInsts 466895 # Number of instructions dispatched to IQ 475system.cpu0.iew.iewDispSquashedInsts 243 # Number of squashed instructions skipped by dispatch 476system.cpu0.iew.iewDispLoadInsts 150037 # Number of dispatched load instructions 477system.cpu0.iew.iewDispStoreInsts 75873 # Number of dispatched store instructions 478system.cpu0.iew.iewDispNonSpecInsts 770 # Number of dispatched non-speculative instructions 479system.cpu0.iew.iewIQFullEvents 46 # Number of times the IQ has become full, causing a stall 480system.cpu0.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 481system.cpu0.iew.memOrderViolationEvents 63 # Number of memory order violations 482system.cpu0.iew.predictedTakenIncorrect 318 # Number of branches that were predicted taken incorrectly 483system.cpu0.iew.predictedNotTakenIncorrect 991 # Number of branches that were predicted not taken incorrectly 484system.cpu0.iew.branchMispredicts 1309 # Number of branch mispredicts detected at execute 485system.cpu0.iew.iewExecutedInsts 387894 # Number of executed instructions 486system.cpu0.iew.iewExecLoadInsts 149051 # Number of load instructions executed 487system.cpu0.iew.iewExecSquashedInsts 1012 # Number of squashed instructions skipped in execute 488system.cpu0.iew.exec_swp 0 # number of swp insts executed 489system.cpu0.iew.exec_nop 73663 # number of nop insts executed 490system.cpu0.iew.exec_refs 224021 # number of memory reference insts executed 491system.cpu0.iew.exec_branches 76988 # Number of branches executed 492system.cpu0.iew.exec_stores 74970 # Number of stores executed 493system.cpu0.iew.exec_rate 1.798528 # Inst execution rate 494system.cpu0.iew.wb_sent 387462 # cumulative count of insts sent to commit 495system.cpu0.iew.wb_count 387054 # cumulative count of insts written-back 496system.cpu0.iew.wb_producers 229603 # num instructions producing a value 497system.cpu0.iew.wb_consumers 232649 # num instructions consuming a value 498system.cpu0.iew.wb_rate 1.794634 # insts written-back per cycle 499system.cpu0.iew.wb_fanout 0.986907 # average fanout of values written-back 500system.cpu0.commit.commitSquashedInsts 13111 # The number of squashed insts skipped by commit 501system.cpu0.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards 502system.cpu0.commit.branchMispredicts 1100 # The number of times a branch was mispredicted 503system.cpu0.commit.committed_per_cycle::samples 186547 # Number of insts commited each cycle 504system.cpu0.commit.committed_per_cycle::mean 2.432234 # Number of insts commited each cycle 505system.cpu0.commit.committed_per_cycle::stdev 2.149146 # Number of insts commited each cycle 506system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 507system.cpu0.commit.committed_per_cycle::0 33930 18.19% 18.19% # Number of insts commited each cycle 508system.cpu0.commit.committed_per_cycle::1 76047 40.77% 58.95% # Number of insts commited each cycle 509system.cpu0.commit.committed_per_cycle::2 1940 1.04% 59.99% # Number of insts commited each cycle 510system.cpu0.commit.committed_per_cycle::3 670 0.36% 60.35% # Number of insts commited each cycle 511system.cpu0.commit.committed_per_cycle::4 524 0.28% 60.63% # Number of insts commited each cycle 512system.cpu0.commit.committed_per_cycle::5 72154 38.68% 99.31% # Number of insts commited each cycle 513system.cpu0.commit.committed_per_cycle::6 534 0.29% 99.60% # Number of insts commited each cycle 514system.cpu0.commit.committed_per_cycle::7 265 0.14% 99.74% # Number of insts commited each cycle 515system.cpu0.commit.committed_per_cycle::8 483 0.26% 100.00% # Number of insts commited each cycle 516system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 517system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 518system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 519system.cpu0.commit.committed_per_cycle::total 186547 # Number of insts commited each cycle 520system.cpu0.commit.committedInsts 453726 # Number of instructions committed 521system.cpu0.commit.committedOps 453726 # Number of ops (including micro ops) committed 522system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed 523system.cpu0.commit.refs 221578 # Number of memory references committed 524system.cpu0.commit.loads 147381 # Number of loads committed 525system.cpu0.commit.membars 84 # Number of memory barriers committed 526system.cpu0.commit.branches 76084 # Number of branches committed 527system.cpu0.commit.fp_insts 0 # Number of committed floating point instructions. 528system.cpu0.commit.int_insts 305914 # Number of committed integer instructions. 529system.cpu0.commit.function_calls 223 # Number of function calls committed. 530system.cpu0.commit.op_class_0::No_OpClass 72816 16.05% 16.05% # Class of committed instruction 531system.cpu0.commit.op_class_0::IntAlu 159248 35.10% 51.15% # Class of committed instruction 532system.cpu0.commit.op_class_0::IntMult 0 0.00% 51.15% # Class of committed instruction 533system.cpu0.commit.op_class_0::IntDiv 0 0.00% 51.15% # Class of committed instruction 534system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 51.15% # Class of committed instruction 535system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 51.15% # Class of committed instruction 536system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 51.15% # Class of committed instruction 537system.cpu0.commit.op_class_0::FloatMult 0 0.00% 51.15% # Class of committed instruction 538system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 51.15% # Class of committed instruction 539system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 51.15% # Class of committed instruction 540system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 51.15% # Class of committed instruction 541system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 51.15% # Class of committed instruction 542system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 51.15% # Class of committed instruction 543system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 51.15% # Class of committed instruction 544system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 51.15% # Class of committed instruction 545system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 51.15% # Class of committed instruction 546system.cpu0.commit.op_class_0::SimdMult 0 0.00% 51.15% # Class of committed instruction 547system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 51.15% # Class of committed instruction 548system.cpu0.commit.op_class_0::SimdShift 0 0.00% 51.15% # Class of committed instruction 549system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 51.15% # Class of committed instruction 550system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 51.15% # Class of committed instruction 551system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 51.15% # Class of committed instruction 552system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 51.15% # Class of committed instruction 553system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 51.15% # Class of committed instruction 554system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 51.15% # Class of committed instruction 555system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 51.15% # Class of committed instruction 556system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 51.15% # Class of committed instruction 557system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 51.15% # Class of committed instruction 558system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 51.15% # Class of committed instruction 559system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 51.15% # Class of committed instruction 560system.cpu0.commit.op_class_0::MemRead 147465 32.50% 83.65% # Class of committed instruction 561system.cpu0.commit.op_class_0::MemWrite 74197 16.35% 100.00% # Class of committed instruction 562system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 563system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 564system.cpu0.commit.op_class_0::total 453726 # Class of committed instruction 565system.cpu0.commit.bw_lim_events 483 # number cycles where commit BW limit reached 566system.cpu0.rob.rob_reads 651740 # The number of ROB reads 567system.cpu0.rob.rob_writes 936154 # The number of ROB writes 568system.cpu0.timesIdled 313 # Number of times that the entire CPU went into an idle state and unscheduled itself 569system.cpu0.idleCycles 26662 # Total number of cycles that the CPU has spent unscheduled due to idling 570system.cpu0.committedInsts 380826 # Number of Instructions Simulated 571system.cpu0.committedOps 380826 # Number of Ops (including micro ops) Simulated 572system.cpu0.cpi 0.566330 # CPI: Cycles Per Instruction 573system.cpu0.cpi_total 0.566330 # CPI: Total CPI of All Threads 574system.cpu0.ipc 1.765756 # IPC: Instructions Per Cycle 575system.cpu0.ipc_total 1.765756 # IPC: Total IPC of All Threads 576system.cpu0.int_regfile_reads 693989 # number of integer regfile reads 577system.cpu0.int_regfile_writes 312909 # number of integer regfile writes 578system.cpu0.fp_regfile_reads 192 # number of floating regfile reads 579system.cpu0.misc_regfile_reads 225890 # number of misc regfile reads 580system.cpu0.misc_regfile_writes 564 # number of misc regfile writes 581system.cpu0.dcache.tags.replacements 2 # number of replacements 582system.cpu0.dcache.tags.tagsinuse 141.137199 # Cycle average of tags in use 583system.cpu0.dcache.tags.total_refs 149509 # Total number of references to valid blocks. 584system.cpu0.dcache.tags.sampled_refs 171 # Sample count of references to valid blocks. 585system.cpu0.dcache.tags.avg_refs 874.321637 # Average number of references to valid blocks. 586system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 587system.cpu0.dcache.tags.occ_blocks::cpu0.data 141.137199 # Average occupied blocks per requestor 588system.cpu0.dcache.tags.occ_percent::cpu0.data 0.275659 # Average percentage of cache occupancy 589system.cpu0.dcache.tags.occ_percent::total 0.275659 # Average percentage of cache occupancy 590system.cpu0.dcache.tags.occ_task_id_blocks::1024 169 # Occupied blocks per task id 591system.cpu0.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id 592system.cpu0.dcache.tags.age_task_id_blocks_1024::1 67 # Occupied blocks per task id 593system.cpu0.dcache.tags.age_task_id_blocks_1024::2 84 # Occupied blocks per task id 594system.cpu0.dcache.tags.occ_task_id_percent::1024 0.330078 # Percentage of cache occupancy per task id 595system.cpu0.dcache.tags.tag_accesses 603167 # Number of tag accesses 596system.cpu0.dcache.tags.data_accesses 603167 # Number of data accesses 597system.cpu0.dcache.ReadReq_hits::cpu0.data 75961 # number of ReadReq hits 598system.cpu0.dcache.ReadReq_hits::total 75961 # number of ReadReq hits 599system.cpu0.dcache.WriteReq_hits::cpu0.data 73598 # number of WriteReq hits 600system.cpu0.dcache.WriteReq_hits::total 73598 # number of WriteReq hits 601system.cpu0.dcache.SwapReq_hits::cpu0.data 16 # number of SwapReq hits 602system.cpu0.dcache.SwapReq_hits::total 16 # number of SwapReq hits 603system.cpu0.dcache.demand_hits::cpu0.data 149559 # number of demand (read+write) hits 604system.cpu0.dcache.demand_hits::total 149559 # number of demand (read+write) hits 605system.cpu0.dcache.overall_hits::cpu0.data 149559 # number of overall hits 606system.cpu0.dcache.overall_hits::total 149559 # number of overall hits 607system.cpu0.dcache.ReadReq_misses::cpu0.data 557 # number of ReadReq misses 608system.cpu0.dcache.ReadReq_misses::total 557 # number of ReadReq misses 609system.cpu0.dcache.WriteReq_misses::cpu0.data 557 # number of WriteReq misses 610system.cpu0.dcache.WriteReq_misses::total 557 # number of WriteReq misses 611system.cpu0.dcache.SwapReq_misses::cpu0.data 26 # number of SwapReq misses 612system.cpu0.dcache.SwapReq_misses::total 26 # number of SwapReq misses 613system.cpu0.dcache.demand_misses::cpu0.data 1114 # number of demand (read+write) misses 614system.cpu0.dcache.demand_misses::total 1114 # number of demand (read+write) misses 615system.cpu0.dcache.overall_misses::cpu0.data 1114 # number of overall misses 616system.cpu0.dcache.overall_misses::total 1114 # number of overall misses 617system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 17293500 # number of ReadReq miss cycles 618system.cpu0.dcache.ReadReq_miss_latency::total 17293500 # number of ReadReq miss cycles 619system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 34774980 # number of WriteReq miss cycles 620system.cpu0.dcache.WriteReq_miss_latency::total 34774980 # number of WriteReq miss cycles 621system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 472500 # number of SwapReq miss cycles 622system.cpu0.dcache.SwapReq_miss_latency::total 472500 # number of SwapReq miss cycles 623system.cpu0.dcache.demand_miss_latency::cpu0.data 52068480 # number of demand (read+write) miss cycles 624system.cpu0.dcache.demand_miss_latency::total 52068480 # number of demand (read+write) miss cycles 625system.cpu0.dcache.overall_miss_latency::cpu0.data 52068480 # number of overall miss cycles 626system.cpu0.dcache.overall_miss_latency::total 52068480 # number of overall miss cycles 627system.cpu0.dcache.ReadReq_accesses::cpu0.data 76518 # number of ReadReq accesses(hits+misses) 628system.cpu0.dcache.ReadReq_accesses::total 76518 # number of ReadReq accesses(hits+misses) 629system.cpu0.dcache.WriteReq_accesses::cpu0.data 74155 # number of WriteReq accesses(hits+misses) 630system.cpu0.dcache.WriteReq_accesses::total 74155 # number of WriteReq accesses(hits+misses) 631system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) 632system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) 633system.cpu0.dcache.demand_accesses::cpu0.data 150673 # number of demand (read+write) accesses 634system.cpu0.dcache.demand_accesses::total 150673 # number of demand (read+write) accesses 635system.cpu0.dcache.overall_accesses::cpu0.data 150673 # number of overall (read+write) accesses 636system.cpu0.dcache.overall_accesses::total 150673 # number of overall (read+write) accesses 637system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.007279 # miss rate for ReadReq accesses 638system.cpu0.dcache.ReadReq_miss_rate::total 0.007279 # miss rate for ReadReq accesses 639system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007511 # miss rate for WriteReq accesses 640system.cpu0.dcache.WriteReq_miss_rate::total 0.007511 # miss rate for WriteReq accesses 641system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.619048 # miss rate for SwapReq accesses 642system.cpu0.dcache.SwapReq_miss_rate::total 0.619048 # miss rate for SwapReq accesses 643system.cpu0.dcache.demand_miss_rate::cpu0.data 0.007393 # miss rate for demand accesses 644system.cpu0.dcache.demand_miss_rate::total 0.007393 # miss rate for demand accesses 645system.cpu0.dcache.overall_miss_rate::cpu0.data 0.007393 # miss rate for overall accesses 646system.cpu0.dcache.overall_miss_rate::total 0.007393 # miss rate for overall accesses 647system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 31047.576302 # average ReadReq miss latency 648system.cpu0.dcache.ReadReq_avg_miss_latency::total 31047.576302 # average ReadReq miss latency 649system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 62432.639138 # average WriteReq miss latency 650system.cpu0.dcache.WriteReq_avg_miss_latency::total 62432.639138 # average WriteReq miss latency 651system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 18173.076923 # average SwapReq miss latency 652system.cpu0.dcache.SwapReq_avg_miss_latency::total 18173.076923 # average SwapReq miss latency 653system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 46740.107720 # average overall miss latency 654system.cpu0.dcache.demand_avg_miss_latency::total 46740.107720 # average overall miss latency 655system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 46740.107720 # average overall miss latency 656system.cpu0.dcache.overall_avg_miss_latency::total 46740.107720 # average overall miss latency 657system.cpu0.dcache.blocked_cycles::no_mshrs 891 # number of cycles access was blocked 658system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 659system.cpu0.dcache.blocked::no_mshrs 27 # number of cycles access was blocked 660system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 661system.cpu0.dcache.avg_blocked_cycles::no_mshrs 33 # average number of cycles each access was blocked 662system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 663system.cpu0.dcache.fast_writes 0 # number of fast writes performed 664system.cpu0.dcache.cache_copies 0 # number of cache copies performed 665system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks 666system.cpu0.dcache.writebacks::total 1 # number of writebacks 667system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 375 # number of ReadReq MSHR hits 668system.cpu0.dcache.ReadReq_mshr_hits::total 375 # number of ReadReq MSHR hits 669system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 379 # number of WriteReq MSHR hits 670system.cpu0.dcache.WriteReq_mshr_hits::total 379 # number of WriteReq MSHR hits 671system.cpu0.dcache.demand_mshr_hits::cpu0.data 754 # number of demand (read+write) MSHR hits 672system.cpu0.dcache.demand_mshr_hits::total 754 # number of demand (read+write) MSHR hits 673system.cpu0.dcache.overall_mshr_hits::cpu0.data 754 # number of overall MSHR hits 674system.cpu0.dcache.overall_mshr_hits::total 754 # number of overall MSHR hits 675system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 182 # number of ReadReq MSHR misses 676system.cpu0.dcache.ReadReq_mshr_misses::total 182 # number of ReadReq MSHR misses 677system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 178 # number of WriteReq MSHR misses 678system.cpu0.dcache.WriteReq_mshr_misses::total 178 # number of WriteReq MSHR misses 679system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 26 # number of SwapReq MSHR misses 680system.cpu0.dcache.SwapReq_mshr_misses::total 26 # number of SwapReq MSHR misses 681system.cpu0.dcache.demand_mshr_misses::cpu0.data 360 # number of demand (read+write) MSHR misses 682system.cpu0.dcache.demand_mshr_misses::total 360 # number of demand (read+write) MSHR misses 683system.cpu0.dcache.overall_mshr_misses::cpu0.data 360 # number of overall MSHR misses 684system.cpu0.dcache.overall_mshr_misses::total 360 # number of overall MSHR misses 685system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 6892000 # number of ReadReq MSHR miss cycles 686system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6892000 # number of ReadReq MSHR miss cycles 687system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 8487000 # number of WriteReq MSHR miss cycles 688system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8487000 # number of WriteReq MSHR miss cycles 689system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 446500 # number of SwapReq MSHR miss cycles 690system.cpu0.dcache.SwapReq_mshr_miss_latency::total 446500 # number of SwapReq MSHR miss cycles 691system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 15379000 # number of demand (read+write) MSHR miss cycles 692system.cpu0.dcache.demand_mshr_miss_latency::total 15379000 # number of demand (read+write) MSHR miss cycles 693system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 15379000 # number of overall MSHR miss cycles 694system.cpu0.dcache.overall_mshr_miss_latency::total 15379000 # number of overall MSHR miss cycles 695system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002379 # mshr miss rate for ReadReq accesses 696system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002379 # mshr miss rate for ReadReq accesses 697system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002400 # mshr miss rate for WriteReq accesses 698system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002400 # mshr miss rate for WriteReq accesses 699system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.619048 # mshr miss rate for SwapReq accesses 700system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.619048 # mshr miss rate for SwapReq accesses 701system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002389 # mshr miss rate for demand accesses 702system.cpu0.dcache.demand_mshr_miss_rate::total 0.002389 # mshr miss rate for demand accesses 703system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002389 # mshr miss rate for overall accesses 704system.cpu0.dcache.overall_mshr_miss_rate::total 0.002389 # mshr miss rate for overall accesses 705system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 37868.131868 # average ReadReq mshr miss latency 706system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 37868.131868 # average ReadReq mshr miss latency 707system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 47679.775281 # average WriteReq mshr miss latency 708system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 47679.775281 # average WriteReq mshr miss latency 709system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 17173.076923 # average SwapReq mshr miss latency 710system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 17173.076923 # average SwapReq mshr miss latency 711system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 42719.444444 # average overall mshr miss latency 712system.cpu0.dcache.demand_avg_mshr_miss_latency::total 42719.444444 # average overall mshr miss latency 713system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 42719.444444 # average overall mshr miss latency 714system.cpu0.dcache.overall_avg_mshr_miss_latency::total 42719.444444 # average overall mshr miss latency 715system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 716system.cpu0.icache.tags.replacements 315 # number of replacements 717system.cpu0.icache.tags.tagsinuse 241.200073 # Cycle average of tags in use 718system.cpu0.icache.tags.total_refs 5951 # Total number of references to valid blocks. 719system.cpu0.icache.tags.sampled_refs 607 # Sample count of references to valid blocks. 720system.cpu0.icache.tags.avg_refs 9.803954 # Average number of references to valid blocks. 721system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 722system.cpu0.icache.tags.occ_blocks::cpu0.inst 241.200073 # Average occupied blocks per requestor 723system.cpu0.icache.tags.occ_percent::cpu0.inst 0.471094 # Average percentage of cache occupancy 724system.cpu0.icache.tags.occ_percent::total 0.471094 # Average percentage of cache occupancy 725system.cpu0.icache.tags.occ_task_id_blocks::1024 292 # Occupied blocks per task id 726system.cpu0.icache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id 727system.cpu0.icache.tags.age_task_id_blocks_1024::1 173 # Occupied blocks per task id 728system.cpu0.icache.tags.age_task_id_blocks_1024::2 60 # Occupied blocks per task id 729system.cpu0.icache.tags.occ_task_id_percent::1024 0.570312 # Percentage of cache occupancy per task id 730system.cpu0.icache.tags.tag_accesses 7341 # Number of tag accesses 731system.cpu0.icache.tags.data_accesses 7341 # Number of data accesses 732system.cpu0.icache.ReadReq_hits::cpu0.inst 5951 # number of ReadReq hits 733system.cpu0.icache.ReadReq_hits::total 5951 # number of ReadReq hits 734system.cpu0.icache.demand_hits::cpu0.inst 5951 # number of demand (read+write) hits 735system.cpu0.icache.demand_hits::total 5951 # number of demand (read+write) hits 736system.cpu0.icache.overall_hits::cpu0.inst 5951 # number of overall hits 737system.cpu0.icache.overall_hits::total 5951 # number of overall hits 738system.cpu0.icache.ReadReq_misses::cpu0.inst 783 # number of ReadReq misses 739system.cpu0.icache.ReadReq_misses::total 783 # number of ReadReq misses 740system.cpu0.icache.demand_misses::cpu0.inst 783 # number of demand (read+write) misses 741system.cpu0.icache.demand_misses::total 783 # number of demand (read+write) misses 742system.cpu0.icache.overall_misses::cpu0.inst 783 # number of overall misses 743system.cpu0.icache.overall_misses::total 783 # number of overall misses 744system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 40367500 # number of ReadReq miss cycles 745system.cpu0.icache.ReadReq_miss_latency::total 40367500 # number of ReadReq miss cycles 746system.cpu0.icache.demand_miss_latency::cpu0.inst 40367500 # number of demand (read+write) miss cycles 747system.cpu0.icache.demand_miss_latency::total 40367500 # number of demand (read+write) miss cycles 748system.cpu0.icache.overall_miss_latency::cpu0.inst 40367500 # number of overall miss cycles 749system.cpu0.icache.overall_miss_latency::total 40367500 # number of overall miss cycles 750system.cpu0.icache.ReadReq_accesses::cpu0.inst 6734 # number of ReadReq accesses(hits+misses) 751system.cpu0.icache.ReadReq_accesses::total 6734 # number of ReadReq accesses(hits+misses) 752system.cpu0.icache.demand_accesses::cpu0.inst 6734 # number of demand (read+write) accesses 753system.cpu0.icache.demand_accesses::total 6734 # number of demand (read+write) accesses 754system.cpu0.icache.overall_accesses::cpu0.inst 6734 # number of overall (read+write) accesses 755system.cpu0.icache.overall_accesses::total 6734 # number of overall (read+write) accesses 756system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.116276 # miss rate for ReadReq accesses 757system.cpu0.icache.ReadReq_miss_rate::total 0.116276 # miss rate for ReadReq accesses 758system.cpu0.icache.demand_miss_rate::cpu0.inst 0.116276 # miss rate for demand accesses 759system.cpu0.icache.demand_miss_rate::total 0.116276 # miss rate for demand accesses 760system.cpu0.icache.overall_miss_rate::cpu0.inst 0.116276 # miss rate for overall accesses 761system.cpu0.icache.overall_miss_rate::total 0.116276 # miss rate for overall accesses 762system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 51554.916986 # average ReadReq miss latency 763system.cpu0.icache.ReadReq_avg_miss_latency::total 51554.916986 # average ReadReq miss latency 764system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 51554.916986 # average overall miss latency 765system.cpu0.icache.demand_avg_miss_latency::total 51554.916986 # average overall miss latency 766system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 51554.916986 # average overall miss latency 767system.cpu0.icache.overall_avg_miss_latency::total 51554.916986 # average overall miss latency 768system.cpu0.icache.blocked_cycles::no_mshrs 4 # number of cycles access was blocked 769system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 770system.cpu0.icache.blocked::no_mshrs 1 # number of cycles access was blocked 771system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 772system.cpu0.icache.avg_blocked_cycles::no_mshrs 4 # average number of cycles each access was blocked 773system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 774system.cpu0.icache.fast_writes 0 # number of fast writes performed 775system.cpu0.icache.cache_copies 0 # number of cache copies performed 776system.cpu0.icache.writebacks::writebacks 315 # number of writebacks 777system.cpu0.icache.writebacks::total 315 # number of writebacks 778system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 175 # number of ReadReq MSHR hits 779system.cpu0.icache.ReadReq_mshr_hits::total 175 # number of ReadReq MSHR hits 780system.cpu0.icache.demand_mshr_hits::cpu0.inst 175 # number of demand (read+write) MSHR hits 781system.cpu0.icache.demand_mshr_hits::total 175 # number of demand (read+write) MSHR hits 782system.cpu0.icache.overall_mshr_hits::cpu0.inst 175 # number of overall MSHR hits 783system.cpu0.icache.overall_mshr_hits::total 175 # number of overall MSHR hits 784system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 608 # number of ReadReq MSHR misses 785system.cpu0.icache.ReadReq_mshr_misses::total 608 # number of ReadReq MSHR misses 786system.cpu0.icache.demand_mshr_misses::cpu0.inst 608 # number of demand (read+write) MSHR misses 787system.cpu0.icache.demand_mshr_misses::total 608 # number of demand (read+write) MSHR misses 788system.cpu0.icache.overall_mshr_misses::cpu0.inst 608 # number of overall MSHR misses 789system.cpu0.icache.overall_mshr_misses::total 608 # number of overall MSHR misses 790system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 31309500 # number of ReadReq MSHR miss cycles 791system.cpu0.icache.ReadReq_mshr_miss_latency::total 31309500 # number of ReadReq MSHR miss cycles 792system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 31309500 # number of demand (read+write) MSHR miss cycles 793system.cpu0.icache.demand_mshr_miss_latency::total 31309500 # number of demand (read+write) MSHR miss cycles 794system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 31309500 # number of overall MSHR miss cycles 795system.cpu0.icache.overall_mshr_miss_latency::total 31309500 # number of overall MSHR miss cycles 796system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.090288 # mshr miss rate for ReadReq accesses 797system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.090288 # mshr miss rate for ReadReq accesses 798system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.090288 # mshr miss rate for demand accesses 799system.cpu0.icache.demand_mshr_miss_rate::total 0.090288 # mshr miss rate for demand accesses 800system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.090288 # mshr miss rate for overall accesses 801system.cpu0.icache.overall_mshr_miss_rate::total 0.090288 # mshr miss rate for overall accesses 802system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 51495.888158 # average ReadReq mshr miss latency 803system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 51495.888158 # average ReadReq mshr miss latency 804system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 51495.888158 # average overall mshr miss latency 805system.cpu0.icache.demand_avg_mshr_miss_latency::total 51495.888158 # average overall mshr miss latency 806system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 51495.888158 # average overall mshr miss latency 807system.cpu0.icache.overall_avg_mshr_miss_latency::total 51495.888158 # average overall mshr miss latency 808system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 809system.cpu1.branchPred.lookups 53782 # Number of BP lookups 810system.cpu1.branchPred.condPredicted 50347 # Number of conditional branches predicted 811system.cpu1.branchPred.condIncorrect 1277 # Number of conditional branches incorrect 812system.cpu1.branchPred.BTBLookups 46315 # Number of BTB lookups 813system.cpu1.branchPred.BTBHits 45397 # Number of BTB hits 814system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 815system.cpu1.branchPred.BTBHitPct 98.017921 # BTB Hit Percentage 816system.cpu1.branchPred.usedRAS 899 # Number of times the RAS was used to get a target. 817system.cpu1.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions. 818system.cpu1.numCycles 162898 # number of cpu cycles simulated 819system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 820system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 821system.cpu1.fetch.icacheStallCycles 29679 # Number of cycles fetch is stalled on an Icache miss 822system.cpu1.fetch.Insts 299544 # Number of instructions fetch has processed 823system.cpu1.fetch.Branches 53782 # Number of branches that fetch encountered 824system.cpu1.fetch.predictedBranches 46296 # Number of branches that fetch has predicted taken 825system.cpu1.fetch.Cycles 124703 # Number of cycles fetch has run and was not squashing or blocked 826system.cpu1.fetch.SquashCycles 2711 # Number of cycles fetch has spent squashing 827system.cpu1.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 828system.cpu1.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from 829system.cpu1.fetch.PendingTrapStallCycles 1084 # Number of stall cycles due to pending traps 830system.cpu1.fetch.IcacheWaitRetryStallCycles 11 # Number of stall cycles due to full MSHR 831system.cpu1.fetch.CacheLines 20165 # Number of cache lines fetched 832system.cpu1.fetch.IcacheSquashes 457 # Number of outstanding Icache misses that were squashed 833system.cpu1.fetch.rateDist::samples 156846 # Number of instructions fetched each cycle (Total) 834system.cpu1.fetch.rateDist::mean 1.909797 # Number of instructions fetched each cycle (Total) 835system.cpu1.fetch.rateDist::stdev 2.217375 # Number of instructions fetched each cycle (Total) 836system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 837system.cpu1.fetch.rateDist::0 53057 33.83% 33.83% # Number of instructions fetched each cycle (Total) 838system.cpu1.fetch.rateDist::1 52143 33.24% 67.07% # Number of instructions fetched each cycle (Total) 839system.cpu1.fetch.rateDist::2 5878 3.75% 70.82% # Number of instructions fetched each cycle (Total) 840system.cpu1.fetch.rateDist::3 3526 2.25% 73.07% # Number of instructions fetched each cycle (Total) 841system.cpu1.fetch.rateDist::4 939 0.60% 73.67% # Number of instructions fetched each cycle (Total) 842system.cpu1.fetch.rateDist::5 35272 22.49% 96.15% # Number of instructions fetched each cycle (Total) 843system.cpu1.fetch.rateDist::6 1247 0.80% 96.95% # Number of instructions fetched each cycle (Total) 844system.cpu1.fetch.rateDist::7 803 0.51% 97.46% # Number of instructions fetched each cycle (Total) 845system.cpu1.fetch.rateDist::8 3981 2.54% 100.00% # Number of instructions fetched each cycle (Total) 846system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 847system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 848system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 849system.cpu1.fetch.rateDist::total 156846 # Number of instructions fetched each cycle (Total) 850system.cpu1.fetch.branchRate 0.330158 # Number of branch fetches per cycle 851system.cpu1.fetch.rate 1.838844 # Number of inst fetches per cycle 852system.cpu1.decode.IdleCycles 17882 # Number of cycles decode is idle 853system.cpu1.decode.BlockedCycles 51023 # Number of cycles decode is blocked 854system.cpu1.decode.RunCycles 83554 # Number of cycles decode is running 855system.cpu1.decode.UnblockCycles 3022 # Number of cycles decode is unblocking 856system.cpu1.decode.SquashCycles 1355 # Number of cycles decode is squashing 857system.cpu1.decode.DecodedInsts 284108 # Number of instructions handled by decode 858system.cpu1.rename.SquashCycles 1355 # Number of cycles rename is squashing 859system.cpu1.rename.IdleCycles 18601 # Number of cycles rename is idle 860system.cpu1.rename.BlockCycles 22664 # Number of cycles rename is blocking 861system.cpu1.rename.serializeStallCycles 13899 # count of cycles rename stalled for serializing inst 862system.cpu1.rename.RunCycles 84840 # Number of cycles rename is running 863system.cpu1.rename.UnblockCycles 15477 # Number of cycles rename is unblocking 864system.cpu1.rename.RenamedInsts 280728 # Number of instructions processed by rename 865system.cpu1.rename.IQFullEvents 13732 # Number of times rename has blocked due to IQ full 866system.cpu1.rename.LQFullEvents 17 # Number of times rename has blocked due to LQ full 867system.cpu1.rename.FullRegisterEvents 6 # Number of times there has been no free registers 868system.cpu1.rename.RenamedOperands 198394 # Number of destination operands rename has renamed 869system.cpu1.rename.RenameLookups 541219 # Number of register rename lookups that rename has made 870system.cpu1.rename.int_rename_lookups 420944 # Number of integer rename lookups 871system.cpu1.rename.CommittedMaps 184552 # Number of HB maps that are committed 872system.cpu1.rename.UndoneMaps 13842 # Number of HB maps that are undone due to squashing 873system.cpu1.rename.serializingInsts 1192 # count of serializing insts renamed 874system.cpu1.rename.tempSerializingInsts 1257 # count of temporary serializing insts renamed 875system.cpu1.rename.skidInsts 20109 # count of insts added to the skid buffer 876system.cpu1.memDep0.insertedLoads 79403 # Number of loads inserted to the mem dependence unit. 877system.cpu1.memDep0.insertedStores 38032 # Number of stores inserted to the mem dependence unit. 878system.cpu1.memDep0.conflictingLoads 37516 # Number of conflicting loads. 879system.cpu1.memDep0.conflictingStores 32939 # Number of conflicting stores. 880system.cpu1.iq.iqInstsAdded 234221 # Number of instructions added to the IQ (excludes non-spec) 881system.cpu1.iq.iqNonSpecInstsAdded 5649 # Number of non-speculative instructions added to the IQ 882system.cpu1.iq.iqInstsIssued 235400 # Number of instructions issued 883system.cpu1.iq.iqSquashedInstsIssued 7 # Number of squashed instructions issued 884system.cpu1.iq.iqSquashedInstsExamined 12841 # Number of squashed instructions iterated over during squash; mainly for profiling 885system.cpu1.iq.iqSquashedOperandsExamined 10393 # Number of squashed operands that are examined and possibly removed from graph 886system.cpu1.iq.iqSquashedNonSpecRemoved 661 # Number of squashed non-spec instructions that were removed 887system.cpu1.iq.issued_per_cycle::samples 156846 # Number of insts issued each cycle 888system.cpu1.iq.issued_per_cycle::mean 1.500835 # Number of insts issued each cycle 889system.cpu1.iq.issued_per_cycle::stdev 1.378978 # Number of insts issued each cycle 890system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 891system.cpu1.iq.issued_per_cycle::0 56627 36.10% 36.10% # Number of insts issued each cycle 892system.cpu1.iq.issued_per_cycle::1 19405 12.37% 48.48% # Number of insts issued each cycle 893system.cpu1.iq.issued_per_cycle::2 37510 23.92% 72.39% # Number of insts issued each cycle 894system.cpu1.iq.issued_per_cycle::3 37026 23.61% 96.00% # Number of insts issued each cycle 895system.cpu1.iq.issued_per_cycle::4 3380 2.15% 98.15% # Number of insts issued each cycle 896system.cpu1.iq.issued_per_cycle::5 1607 1.02% 99.18% # Number of insts issued each cycle 897system.cpu1.iq.issued_per_cycle::6 891 0.57% 99.74% # Number of insts issued each cycle 898system.cpu1.iq.issued_per_cycle::7 204 0.13% 99.88% # Number of insts issued each cycle 899system.cpu1.iq.issued_per_cycle::8 196 0.12% 100.00% # Number of insts issued each cycle 900system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 901system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 902system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 903system.cpu1.iq.issued_per_cycle::total 156846 # Number of insts issued each cycle 904system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 905system.cpu1.iq.fu_full::IntAlu 79 24.38% 24.38% # attempts to use FU when none available 906system.cpu1.iq.fu_full::IntMult 0 0.00% 24.38% # attempts to use FU when none available 907system.cpu1.iq.fu_full::IntDiv 0 0.00% 24.38% # attempts to use FU when none available 908system.cpu1.iq.fu_full::FloatAdd 0 0.00% 24.38% # attempts to use FU when none available 909system.cpu1.iq.fu_full::FloatCmp 0 0.00% 24.38% # attempts to use FU when none available 910system.cpu1.iq.fu_full::FloatCvt 0 0.00% 24.38% # attempts to use FU when none available 911system.cpu1.iq.fu_full::FloatMult 0 0.00% 24.38% # attempts to use FU when none available 912system.cpu1.iq.fu_full::FloatDiv 0 0.00% 24.38% # attempts to use FU when none available 913system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 24.38% # attempts to use FU when none available 914system.cpu1.iq.fu_full::SimdAdd 0 0.00% 24.38% # attempts to use FU when none available 915system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 24.38% # attempts to use FU when none available 916system.cpu1.iq.fu_full::SimdAlu 0 0.00% 24.38% # attempts to use FU when none available 917system.cpu1.iq.fu_full::SimdCmp 0 0.00% 24.38% # attempts to use FU when none available 918system.cpu1.iq.fu_full::SimdCvt 0 0.00% 24.38% # attempts to use FU when none available 919system.cpu1.iq.fu_full::SimdMisc 0 0.00% 24.38% # attempts to use FU when none available 920system.cpu1.iq.fu_full::SimdMult 0 0.00% 24.38% # attempts to use FU when none available 921system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 24.38% # attempts to use FU when none available 922system.cpu1.iq.fu_full::SimdShift 0 0.00% 24.38% # attempts to use FU when none available 923system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 24.38% # attempts to use FU when none available 924system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 24.38% # attempts to use FU when none available 925system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 24.38% # attempts to use FU when none available 926system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 24.38% # attempts to use FU when none available 927system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 24.38% # attempts to use FU when none available 928system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 24.38% # attempts to use FU when none available 929system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 24.38% # attempts to use FU when none available 930system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 24.38% # attempts to use FU when none available 931system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 24.38% # attempts to use FU when none available 932system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 24.38% # attempts to use FU when none available 933system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 24.38% # attempts to use FU when none available 934system.cpu1.iq.fu_full::MemRead 36 11.11% 35.49% # attempts to use FU when none available 935system.cpu1.iq.fu_full::MemWrite 209 64.51% 100.00% # attempts to use FU when none available 936system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 937system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 938system.cpu1.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 939system.cpu1.iq.FU_type_0::IntAlu 114995 48.85% 48.85% # Type of FU issued 940system.cpu1.iq.FU_type_0::IntMult 0 0.00% 48.85% # Type of FU issued 941system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 48.85% # Type of FU issued 942system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 48.85% # Type of FU issued 943system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 48.85% # Type of FU issued 944system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 48.85% # Type of FU issued 945system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 48.85% # Type of FU issued 946system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 48.85% # Type of FU issued 947system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 48.85% # Type of FU issued 948system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 48.85% # Type of FU issued 949system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 48.85% # Type of FU issued 950system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 48.85% # Type of FU issued 951system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 48.85% # Type of FU issued 952system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 48.85% # Type of FU issued 953system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 48.85% # Type of FU issued 954system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 48.85% # Type of FU issued 955system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 48.85% # Type of FU issued 956system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 48.85% # Type of FU issued 957system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.85% # Type of FU issued 958system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 48.85% # Type of FU issued 959system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.85% # Type of FU issued 960system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.85% # Type of FU issued 961system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.85% # Type of FU issued 962system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.85% # Type of FU issued 963system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.85% # Type of FU issued 964system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.85% # Type of FU issued 965system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 48.85% # Type of FU issued 966system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.85% # Type of FU issued 967system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.85% # Type of FU issued 968system.cpu1.iq.FU_type_0::MemRead 82971 35.25% 84.10% # Type of FU issued 969system.cpu1.iq.FU_type_0::MemWrite 37434 15.90% 100.00% # Type of FU issued 970system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 971system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 972system.cpu1.iq.FU_type_0::total 235400 # Type of FU issued 973system.cpu1.iq.rate 1.445076 # Inst issue rate 974system.cpu1.iq.fu_busy_cnt 324 # FU busy when requested 975system.cpu1.iq.fu_busy_rate 0.001376 # FU busy rate (busy events/executed inst) 976system.cpu1.iq.int_inst_queue_reads 627977 # Number of integer instruction queue reads 977system.cpu1.iq.int_inst_queue_writes 252747 # Number of integer instruction queue writes 978system.cpu1.iq.int_inst_queue_wakeup_accesses 233879 # Number of integer instruction queue wakeup accesses 979system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads 980system.cpu1.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes 981system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses 982system.cpu1.iq.int_alu_accesses 235724 # Number of integer alu accesses 983system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses 984system.cpu1.iew.lsq.thread0.forwLoads 32768 # Number of loads that had data forwarded from stores 985system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 986system.cpu1.iew.lsq.thread0.squashedLoads 2551 # Number of loads squashed 987system.cpu1.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed 988system.cpu1.iew.lsq.thread0.memOrderViolation 36 # Number of memory ordering violations 989system.cpu1.iew.lsq.thread0.squashedStores 1483 # Number of stores squashed 990system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 991system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 992system.cpu1.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 993system.cpu1.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked 994system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle 995system.cpu1.iew.iewSquashCycles 1355 # Number of cycles IEW is squashing 996system.cpu1.iew.iewBlockCycles 6889 # Number of cycles IEW is blocking 997system.cpu1.iew.iewUnblockCycles 69 # Number of cycles IEW is unblocking 998system.cpu1.iew.iewDispatchedInsts 278263 # Number of instructions dispatched to IQ 999system.cpu1.iew.iewDispSquashedInsts 133 # Number of squashed instructions skipped by dispatch 1000system.cpu1.iew.iewDispLoadInsts 79403 # Number of dispatched load instructions 1001system.cpu1.iew.iewDispStoreInsts 38032 # Number of dispatched store instructions 1002system.cpu1.iew.iewDispNonSpecInsts 1130 # Number of dispatched non-speculative instructions 1003system.cpu1.iew.iewIQFullEvents 43 # Number of times the IQ has become full, causing a stall 1004system.cpu1.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 1005system.cpu1.iew.memOrderViolationEvents 36 # Number of memory order violations 1006system.cpu1.iew.predictedTakenIncorrect 442 # Number of branches that were predicted taken incorrectly 1007system.cpu1.iew.predictedNotTakenIncorrect 1069 # Number of branches that were predicted not taken incorrectly 1008system.cpu1.iew.branchMispredicts 1511 # Number of branch mispredicts detected at execute 1009system.cpu1.iew.iewExecutedInsts 234388 # Number of executed instructions 1010system.cpu1.iew.iewExecLoadInsts 78381 # Number of load instructions executed 1011system.cpu1.iew.iewExecSquashedInsts 1012 # Number of squashed instructions skipped in execute 1012system.cpu1.iew.exec_swp 0 # number of swp insts executed 1013system.cpu1.iew.exec_nop 38393 # number of nop insts executed 1014system.cpu1.iew.exec_refs 115730 # number of memory reference insts executed 1015system.cpu1.iew.exec_branches 47858 # Number of branches executed 1016system.cpu1.iew.exec_stores 37349 # Number of stores executed 1017system.cpu1.iew.exec_rate 1.438864 # Inst execution rate 1018system.cpu1.iew.wb_sent 234148 # cumulative count of insts sent to commit 1019system.cpu1.iew.wb_count 233879 # cumulative count of insts written-back 1020system.cpu1.iew.wb_producers 133368 # num instructions producing a value 1021system.cpu1.iew.wb_consumers 139978 # num instructions consuming a value 1022system.cpu1.iew.wb_rate 1.435739 # insts written-back per cycle 1023system.cpu1.iew.wb_fanout 0.952778 # average fanout of values written-back 1024system.cpu1.commit.commitSquashedInsts 13605 # The number of squashed insts skipped by commit 1025system.cpu1.commit.commitNonSpecStalls 4988 # The number of times commit has been forced to stall to communicate backwards 1026system.cpu1.commit.branchMispredicts 1277 # The number of times a branch was mispredicted 1027system.cpu1.commit.committed_per_cycle::samples 154309 # Number of insts commited each cycle 1028system.cpu1.commit.committed_per_cycle::mean 1.714761 # Number of insts commited each cycle 1029system.cpu1.commit.committed_per_cycle::stdev 2.081585 # Number of insts commited each cycle 1030system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 1031system.cpu1.commit.committed_per_cycle::0 61394 39.79% 39.79% # Number of insts commited each cycle 1032system.cpu1.commit.committed_per_cycle::1 44430 28.79% 68.58% # Number of insts commited each cycle 1033system.cpu1.commit.committed_per_cycle::2 5247 3.40% 71.98% # Number of insts commited each cycle 1034system.cpu1.commit.committed_per_cycle::3 5803 3.76% 75.74% # Number of insts commited each cycle 1035system.cpu1.commit.committed_per_cycle::4 1533 0.99% 76.73% # Number of insts commited each cycle 1036system.cpu1.commit.committed_per_cycle::5 32828 21.27% 98.01% # Number of insts commited each cycle 1037system.cpu1.commit.committed_per_cycle::6 824 0.53% 98.54% # Number of insts commited each cycle 1038system.cpu1.commit.committed_per_cycle::7 946 0.61% 99.15% # Number of insts commited each cycle 1039system.cpu1.commit.committed_per_cycle::8 1304 0.85% 100.00% # Number of insts commited each cycle 1040system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 1041system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 1042system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 1043system.cpu1.commit.committed_per_cycle::total 154309 # Number of insts commited each cycle 1044system.cpu1.commit.committedInsts 264603 # Number of instructions committed 1045system.cpu1.commit.committedOps 264603 # Number of ops (including micro ops) committed 1046system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed 1047system.cpu1.commit.refs 113401 # Number of memory references committed 1048system.cpu1.commit.loads 76852 # Number of loads committed 1049system.cpu1.commit.membars 4272 # Number of memory barriers committed 1050system.cpu1.commit.branches 46786 # Number of branches committed 1051system.cpu1.commit.fp_insts 0 # Number of committed floating point instructions. 1052system.cpu1.commit.int_insts 182306 # Number of committed integer instructions. 1053system.cpu1.commit.function_calls 322 # Number of function calls committed. 1054system.cpu1.commit.op_class_0::No_OpClass 37574 14.20% 14.20% # Class of committed instruction 1055system.cpu1.commit.op_class_0::IntAlu 109356 41.33% 55.53% # Class of committed instruction 1056system.cpu1.commit.op_class_0::IntMult 0 0.00% 55.53% # Class of committed instruction 1057system.cpu1.commit.op_class_0::IntDiv 0 0.00% 55.53% # Class of committed instruction 1058system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 55.53% # Class of committed instruction 1059system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 55.53% # Class of committed instruction 1060system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 55.53% # Class of committed instruction 1061system.cpu1.commit.op_class_0::FloatMult 0 0.00% 55.53% # Class of committed instruction 1062system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 55.53% # Class of committed instruction 1063system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 55.53% # Class of committed instruction 1064system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 55.53% # Class of committed instruction 1065system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 55.53% # Class of committed instruction 1066system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 55.53% # Class of committed instruction 1067system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 55.53% # Class of committed instruction 1068system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 55.53% # Class of committed instruction 1069system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 55.53% # Class of committed instruction 1070system.cpu1.commit.op_class_0::SimdMult 0 0.00% 55.53% # Class of committed instruction 1071system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 55.53% # Class of committed instruction 1072system.cpu1.commit.op_class_0::SimdShift 0 0.00% 55.53% # Class of committed instruction 1073system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 55.53% # Class of committed instruction 1074system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 55.53% # Class of committed instruction 1075system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 55.53% # Class of committed instruction 1076system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 55.53% # Class of committed instruction 1077system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 55.53% # Class of committed instruction 1078system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 55.53% # Class of committed instruction 1079system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 55.53% # Class of committed instruction 1080system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 55.53% # Class of committed instruction 1081system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 55.53% # Class of committed instruction 1082system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.53% # Class of committed instruction 1083system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.53% # Class of committed instruction 1084system.cpu1.commit.op_class_0::MemRead 81124 30.66% 86.19% # Class of committed instruction 1085system.cpu1.commit.op_class_0::MemWrite 36549 13.81% 100.00% # Class of committed instruction 1086system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 1087system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 1088system.cpu1.commit.op_class_0::total 264603 # Class of committed instruction 1089system.cpu1.commit.bw_lim_events 1304 # number cycles where commit BW limit reached 1090system.cpu1.rob.rob_reads 430627 # The number of ROB reads 1091system.cpu1.rob.rob_writes 558953 # The number of ROB writes 1092system.cpu1.timesIdled 228 # Number of times that the entire CPU went into an idle state and unscheduled itself 1093system.cpu1.idleCycles 6052 # Total number of cycles that the CPU has spent unscheduled due to idling 1094system.cpu1.quiesceCycles 45271 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1095system.cpu1.committedInsts 222757 # Number of Instructions Simulated 1096system.cpu1.committedOps 222757 # Number of Ops (including micro ops) Simulated 1097system.cpu1.cpi 0.731281 # CPI: Cycles Per Instruction 1098system.cpu1.cpi_total 0.731281 # CPI: Total CPI of All Threads 1099system.cpu1.ipc 1.367463 # IPC: Instructions Per Cycle 1100system.cpu1.ipc_total 1.367463 # IPC: Total IPC of All Threads 1101system.cpu1.int_regfile_reads 407061 # number of integer regfile reads 1102system.cpu1.int_regfile_writes 190501 # number of integer regfile writes 1103system.cpu1.fp_regfile_writes 64 # number of floating regfile writes 1104system.cpu1.misc_regfile_reads 117378 # number of misc regfile reads 1105system.cpu1.misc_regfile_writes 648 # number of misc regfile writes 1106system.cpu1.dcache.tags.replacements 0 # number of replacements 1107system.cpu1.dcache.tags.tagsinuse 25.769381 # Cycle average of tags in use 1108system.cpu1.dcache.tags.total_refs 42560 # Total number of references to valid blocks. 1109system.cpu1.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks. 1110system.cpu1.dcache.tags.avg_refs 1520 # Average number of references to valid blocks. 1111system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1112system.cpu1.dcache.tags.occ_blocks::cpu1.data 25.769381 # Average occupied blocks per requestor 1113system.cpu1.dcache.tags.occ_percent::cpu1.data 0.050331 # Average percentage of cache occupancy 1114system.cpu1.dcache.tags.occ_percent::total 0.050331 # Average percentage of cache occupancy 1115system.cpu1.dcache.tags.occ_task_id_blocks::1024 28 # Occupied blocks per task id 1116system.cpu1.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id 1117system.cpu1.dcache.tags.occ_task_id_percent::1024 0.054688 # Percentage of cache occupancy per task id 1118system.cpu1.dcache.tags.tag_accesses 328816 # Number of tag accesses 1119system.cpu1.dcache.tags.data_accesses 328816 # Number of data accesses 1120system.cpu1.dcache.ReadReq_hits::cpu1.data 45076 # number of ReadReq hits 1121system.cpu1.dcache.ReadReq_hits::total 45076 # number of ReadReq hits 1122system.cpu1.dcache.WriteReq_hits::cpu1.data 36319 # number of WriteReq hits 1123system.cpu1.dcache.WriteReq_hits::total 36319 # number of WriteReq hits 1124system.cpu1.dcache.SwapReq_hits::cpu1.data 14 # number of SwapReq hits 1125system.cpu1.dcache.SwapReq_hits::total 14 # number of SwapReq hits 1126system.cpu1.dcache.demand_hits::cpu1.data 81395 # number of demand (read+write) hits 1127system.cpu1.dcache.demand_hits::total 81395 # number of demand (read+write) hits 1128system.cpu1.dcache.overall_hits::cpu1.data 81395 # number of overall hits 1129system.cpu1.dcache.overall_hits::total 81395 # number of overall hits 1130system.cpu1.dcache.ReadReq_misses::cpu1.data 515 # number of ReadReq misses 1131system.cpu1.dcache.ReadReq_misses::total 515 # number of ReadReq misses 1132system.cpu1.dcache.WriteReq_misses::cpu1.data 160 # number of WriteReq misses 1133system.cpu1.dcache.WriteReq_misses::total 160 # number of WriteReq misses 1134system.cpu1.dcache.SwapReq_misses::cpu1.data 56 # number of SwapReq misses 1135system.cpu1.dcache.SwapReq_misses::total 56 # number of SwapReq misses 1136system.cpu1.dcache.demand_misses::cpu1.data 675 # number of demand (read+write) misses 1137system.cpu1.dcache.demand_misses::total 675 # number of demand (read+write) misses 1138system.cpu1.dcache.overall_misses::cpu1.data 675 # number of overall misses 1139system.cpu1.dcache.overall_misses::total 675 # number of overall misses 1140system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 10357000 # number of ReadReq miss cycles 1141system.cpu1.dcache.ReadReq_miss_latency::total 10357000 # number of ReadReq miss cycles 1142system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3384000 # number of WriteReq miss cycles 1143system.cpu1.dcache.WriteReq_miss_latency::total 3384000 # number of WriteReq miss cycles 1144system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 705000 # number of SwapReq miss cycles 1145system.cpu1.dcache.SwapReq_miss_latency::total 705000 # number of SwapReq miss cycles 1146system.cpu1.dcache.demand_miss_latency::cpu1.data 13741000 # number of demand (read+write) miss cycles 1147system.cpu1.dcache.demand_miss_latency::total 13741000 # number of demand (read+write) miss cycles 1148system.cpu1.dcache.overall_miss_latency::cpu1.data 13741000 # number of overall miss cycles 1149system.cpu1.dcache.overall_miss_latency::total 13741000 # number of overall miss cycles 1150system.cpu1.dcache.ReadReq_accesses::cpu1.data 45591 # number of ReadReq accesses(hits+misses) 1151system.cpu1.dcache.ReadReq_accesses::total 45591 # number of ReadReq accesses(hits+misses) 1152system.cpu1.dcache.WriteReq_accesses::cpu1.data 36479 # number of WriteReq accesses(hits+misses) 1153system.cpu1.dcache.WriteReq_accesses::total 36479 # number of WriteReq accesses(hits+misses) 1154system.cpu1.dcache.SwapReq_accesses::cpu1.data 70 # number of SwapReq accesses(hits+misses) 1155system.cpu1.dcache.SwapReq_accesses::total 70 # number of SwapReq accesses(hits+misses) 1156system.cpu1.dcache.demand_accesses::cpu1.data 82070 # number of demand (read+write) accesses 1157system.cpu1.dcache.demand_accesses::total 82070 # number of demand (read+write) accesses 1158system.cpu1.dcache.overall_accesses::cpu1.data 82070 # number of overall (read+write) accesses 1159system.cpu1.dcache.overall_accesses::total 82070 # number of overall (read+write) accesses 1160system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.011296 # miss rate for ReadReq accesses 1161system.cpu1.dcache.ReadReq_miss_rate::total 0.011296 # miss rate for ReadReq accesses 1162system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.004386 # miss rate for WriteReq accesses 1163system.cpu1.dcache.WriteReq_miss_rate::total 0.004386 # miss rate for WriteReq accesses 1164system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.800000 # miss rate for SwapReq accesses 1165system.cpu1.dcache.SwapReq_miss_rate::total 0.800000 # miss rate for SwapReq accesses 1166system.cpu1.dcache.demand_miss_rate::cpu1.data 0.008225 # miss rate for demand accesses 1167system.cpu1.dcache.demand_miss_rate::total 0.008225 # miss rate for demand accesses 1168system.cpu1.dcache.overall_miss_rate::cpu1.data 0.008225 # miss rate for overall accesses 1169system.cpu1.dcache.overall_miss_rate::total 0.008225 # miss rate for overall accesses 1170system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 20110.679612 # average ReadReq miss latency 1171system.cpu1.dcache.ReadReq_avg_miss_latency::total 20110.679612 # average ReadReq miss latency 1172system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21150 # average WriteReq miss latency 1173system.cpu1.dcache.WriteReq_avg_miss_latency::total 21150 # average WriteReq miss latency 1174system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 12589.285714 # average SwapReq miss latency 1175system.cpu1.dcache.SwapReq_avg_miss_latency::total 12589.285714 # average SwapReq miss latency 1176system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20357.037037 # average overall miss latency 1177system.cpu1.dcache.demand_avg_miss_latency::total 20357.037037 # average overall miss latency 1178system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20357.037037 # average overall miss latency 1179system.cpu1.dcache.overall_avg_miss_latency::total 20357.037037 # average overall miss latency 1180system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1181system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1182system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1183system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1184system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1185system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1186system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1187system.cpu1.dcache.cache_copies 0 # number of cache copies performed 1188system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 349 # number of ReadReq MSHR hits 1189system.cpu1.dcache.ReadReq_mshr_hits::total 349 # number of ReadReq MSHR hits 1190system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 53 # number of WriteReq MSHR hits 1191system.cpu1.dcache.WriteReq_mshr_hits::total 53 # number of WriteReq MSHR hits 1192system.cpu1.dcache.demand_mshr_hits::cpu1.data 402 # number of demand (read+write) MSHR hits 1193system.cpu1.dcache.demand_mshr_hits::total 402 # number of demand (read+write) MSHR hits 1194system.cpu1.dcache.overall_mshr_hits::cpu1.data 402 # number of overall MSHR hits 1195system.cpu1.dcache.overall_mshr_hits::total 402 # number of overall MSHR hits 1196system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 166 # number of ReadReq MSHR misses 1197system.cpu1.dcache.ReadReq_mshr_misses::total 166 # number of ReadReq MSHR misses 1198system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 107 # number of WriteReq MSHR misses 1199system.cpu1.dcache.WriteReq_mshr_misses::total 107 # number of WriteReq MSHR misses 1200system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 56 # number of SwapReq MSHR misses 1201system.cpu1.dcache.SwapReq_mshr_misses::total 56 # number of SwapReq MSHR misses 1202system.cpu1.dcache.demand_mshr_misses::cpu1.data 273 # number of demand (read+write) MSHR misses 1203system.cpu1.dcache.demand_mshr_misses::total 273 # number of demand (read+write) MSHR misses 1204system.cpu1.dcache.overall_mshr_misses::cpu1.data 273 # number of overall MSHR misses 1205system.cpu1.dcache.overall_mshr_misses::total 273 # number of overall MSHR misses 1206system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2153500 # number of ReadReq MSHR miss cycles 1207system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2153500 # number of ReadReq MSHR miss cycles 1208system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1760500 # number of WriteReq MSHR miss cycles 1209system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1760500 # number of WriteReq MSHR miss cycles 1210system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 649000 # number of SwapReq MSHR miss cycles 1211system.cpu1.dcache.SwapReq_mshr_miss_latency::total 649000 # number of SwapReq MSHR miss cycles 1212system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3914000 # number of demand (read+write) MSHR miss cycles 1213system.cpu1.dcache.demand_mshr_miss_latency::total 3914000 # number of demand (read+write) MSHR miss cycles 1214system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3914000 # number of overall MSHR miss cycles 1215system.cpu1.dcache.overall_mshr_miss_latency::total 3914000 # number of overall MSHR miss cycles 1216system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003641 # mshr miss rate for ReadReq accesses 1217system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003641 # mshr miss rate for ReadReq accesses 1218system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.002933 # mshr miss rate for WriteReq accesses 1219system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.002933 # mshr miss rate for WriteReq accesses 1220system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.800000 # mshr miss rate for SwapReq accesses 1221system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.800000 # mshr miss rate for SwapReq accesses 1222system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.003326 # mshr miss rate for demand accesses 1223system.cpu1.dcache.demand_mshr_miss_rate::total 0.003326 # mshr miss rate for demand accesses 1224system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.003326 # mshr miss rate for overall accesses 1225system.cpu1.dcache.overall_mshr_miss_rate::total 0.003326 # mshr miss rate for overall accesses 1226system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12972.891566 # average ReadReq mshr miss latency 1227system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12972.891566 # average ReadReq mshr miss latency 1228system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16453.271028 # average WriteReq mshr miss latency 1229system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16453.271028 # average WriteReq mshr miss latency 1230system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 11589.285714 # average SwapReq mshr miss latency 1231system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 11589.285714 # average SwapReq mshr miss latency 1232system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14336.996337 # average overall mshr miss latency 1233system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14336.996337 # average overall mshr miss latency 1234system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14336.996337 # average overall mshr miss latency 1235system.cpu1.dcache.overall_avg_mshr_miss_latency::total 14336.996337 # average overall mshr miss latency 1236system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1237system.cpu1.icache.tags.replacements 383 # number of replacements 1238system.cpu1.icache.tags.tagsinuse 84.449474 # Cycle average of tags in use 1239system.cpu1.icache.tags.total_refs 19585 # Total number of references to valid blocks. 1240system.cpu1.icache.tags.sampled_refs 496 # Sample count of references to valid blocks. 1241system.cpu1.icache.tags.avg_refs 39.485887 # Average number of references to valid blocks. 1242system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1243system.cpu1.icache.tags.occ_blocks::cpu1.inst 84.449474 # Average occupied blocks per requestor 1244system.cpu1.icache.tags.occ_percent::cpu1.inst 0.164940 # Average percentage of cache occupancy 1245system.cpu1.icache.tags.occ_percent::total 0.164940 # Average percentage of cache occupancy 1246system.cpu1.icache.tags.occ_task_id_blocks::1024 113 # Occupied blocks per task id 1247system.cpu1.icache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id 1248system.cpu1.icache.tags.age_task_id_blocks_1024::1 102 # Occupied blocks per task id 1249system.cpu1.icache.tags.occ_task_id_percent::1024 0.220703 # Percentage of cache occupancy per task id 1250system.cpu1.icache.tags.tag_accesses 20661 # Number of tag accesses 1251system.cpu1.icache.tags.data_accesses 20661 # Number of data accesses 1252system.cpu1.icache.ReadReq_hits::cpu1.inst 19585 # number of ReadReq hits 1253system.cpu1.icache.ReadReq_hits::total 19585 # number of ReadReq hits 1254system.cpu1.icache.demand_hits::cpu1.inst 19585 # number of demand (read+write) hits 1255system.cpu1.icache.demand_hits::total 19585 # number of demand (read+write) hits 1256system.cpu1.icache.overall_hits::cpu1.inst 19585 # number of overall hits 1257system.cpu1.icache.overall_hits::total 19585 # number of overall hits 1258system.cpu1.icache.ReadReq_misses::cpu1.inst 580 # number of ReadReq misses 1259system.cpu1.icache.ReadReq_misses::total 580 # number of ReadReq misses 1260system.cpu1.icache.demand_misses::cpu1.inst 580 # number of demand (read+write) misses 1261system.cpu1.icache.demand_misses::total 580 # number of demand (read+write) misses 1262system.cpu1.icache.overall_misses::cpu1.inst 580 # number of overall misses 1263system.cpu1.icache.overall_misses::total 580 # number of overall misses 1264system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 14033000 # number of ReadReq miss cycles 1265system.cpu1.icache.ReadReq_miss_latency::total 14033000 # number of ReadReq miss cycles 1266system.cpu1.icache.demand_miss_latency::cpu1.inst 14033000 # number of demand (read+write) miss cycles 1267system.cpu1.icache.demand_miss_latency::total 14033000 # number of demand (read+write) miss cycles 1268system.cpu1.icache.overall_miss_latency::cpu1.inst 14033000 # number of overall miss cycles 1269system.cpu1.icache.overall_miss_latency::total 14033000 # number of overall miss cycles 1270system.cpu1.icache.ReadReq_accesses::cpu1.inst 20165 # number of ReadReq accesses(hits+misses) 1271system.cpu1.icache.ReadReq_accesses::total 20165 # number of ReadReq accesses(hits+misses) 1272system.cpu1.icache.demand_accesses::cpu1.inst 20165 # number of demand (read+write) accesses 1273system.cpu1.icache.demand_accesses::total 20165 # number of demand (read+write) accesses 1274system.cpu1.icache.overall_accesses::cpu1.inst 20165 # number of overall (read+write) accesses 1275system.cpu1.icache.overall_accesses::total 20165 # number of overall (read+write) accesses 1276system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.028763 # miss rate for ReadReq accesses 1277system.cpu1.icache.ReadReq_miss_rate::total 0.028763 # miss rate for ReadReq accesses 1278system.cpu1.icache.demand_miss_rate::cpu1.inst 0.028763 # miss rate for demand accesses 1279system.cpu1.icache.demand_miss_rate::total 0.028763 # miss rate for demand accesses 1280system.cpu1.icache.overall_miss_rate::cpu1.inst 0.028763 # miss rate for overall accesses 1281system.cpu1.icache.overall_miss_rate::total 0.028763 # miss rate for overall accesses 1282system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 24194.827586 # average ReadReq miss latency 1283system.cpu1.icache.ReadReq_avg_miss_latency::total 24194.827586 # average ReadReq miss latency 1284system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 24194.827586 # average overall miss latency 1285system.cpu1.icache.demand_avg_miss_latency::total 24194.827586 # average overall miss latency 1286system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 24194.827586 # average overall miss latency 1287system.cpu1.icache.overall_avg_miss_latency::total 24194.827586 # average overall miss latency 1288system.cpu1.icache.blocked_cycles::no_mshrs 128 # number of cycles access was blocked 1289system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1290system.cpu1.icache.blocked::no_mshrs 2 # number of cycles access was blocked 1291system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1292system.cpu1.icache.avg_blocked_cycles::no_mshrs 64 # average number of cycles each access was blocked 1293system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1294system.cpu1.icache.fast_writes 0 # number of fast writes performed 1295system.cpu1.icache.cache_copies 0 # number of cache copies performed 1296system.cpu1.icache.writebacks::writebacks 383 # number of writebacks 1297system.cpu1.icache.writebacks::total 383 # number of writebacks 1298system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 84 # number of ReadReq MSHR hits 1299system.cpu1.icache.ReadReq_mshr_hits::total 84 # number of ReadReq MSHR hits 1300system.cpu1.icache.demand_mshr_hits::cpu1.inst 84 # number of demand (read+write) MSHR hits 1301system.cpu1.icache.demand_mshr_hits::total 84 # number of demand (read+write) MSHR hits 1302system.cpu1.icache.overall_mshr_hits::cpu1.inst 84 # number of overall MSHR hits 1303system.cpu1.icache.overall_mshr_hits::total 84 # number of overall MSHR hits 1304system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 496 # number of ReadReq MSHR misses 1305system.cpu1.icache.ReadReq_mshr_misses::total 496 # number of ReadReq MSHR misses 1306system.cpu1.icache.demand_mshr_misses::cpu1.inst 496 # number of demand (read+write) MSHR misses 1307system.cpu1.icache.demand_mshr_misses::total 496 # number of demand (read+write) MSHR misses 1308system.cpu1.icache.overall_mshr_misses::cpu1.inst 496 # number of overall MSHR misses 1309system.cpu1.icache.overall_mshr_misses::total 496 # number of overall MSHR misses 1310system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 11668000 # number of ReadReq MSHR miss cycles 1311system.cpu1.icache.ReadReq_mshr_miss_latency::total 11668000 # number of ReadReq MSHR miss cycles 1312system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 11668000 # number of demand (read+write) MSHR miss cycles 1313system.cpu1.icache.demand_mshr_miss_latency::total 11668000 # number of demand (read+write) MSHR miss cycles 1314system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 11668000 # number of overall MSHR miss cycles 1315system.cpu1.icache.overall_mshr_miss_latency::total 11668000 # number of overall MSHR miss cycles 1316system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024597 # mshr miss rate for ReadReq accesses 1317system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024597 # mshr miss rate for ReadReq accesses 1318system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024597 # mshr miss rate for demand accesses 1319system.cpu1.icache.demand_mshr_miss_rate::total 0.024597 # mshr miss rate for demand accesses 1320system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024597 # mshr miss rate for overall accesses 1321system.cpu1.icache.overall_mshr_miss_rate::total 0.024597 # mshr miss rate for overall accesses 1322system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 23524.193548 # average ReadReq mshr miss latency 1323system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 23524.193548 # average ReadReq mshr miss latency 1324system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 23524.193548 # average overall mshr miss latency 1325system.cpu1.icache.demand_avg_mshr_miss_latency::total 23524.193548 # average overall mshr miss latency 1326system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 23524.193548 # average overall mshr miss latency 1327system.cpu1.icache.overall_avg_mshr_miss_latency::total 23524.193548 # average overall mshr miss latency 1328system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1329system.cpu2.branchPred.lookups 46151 # Number of BP lookups 1330system.cpu2.branchPred.condPredicted 42669 # Number of conditional branches predicted 1331system.cpu2.branchPred.condIncorrect 1261 # Number of conditional branches incorrect 1332system.cpu2.branchPred.BTBLookups 38744 # Number of BTB lookups 1333system.cpu2.branchPred.BTBHits 37721 # Number of BTB hits 1334system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 1335system.cpu2.branchPred.BTBHitPct 97.359591 # BTB Hit Percentage 1336system.cpu2.branchPred.usedRAS 903 # Number of times the RAS was used to get a target. 1337system.cpu2.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions. 1338system.cpu2.numCycles 162526 # number of cpu cycles simulated 1339system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started 1340system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed 1341system.cpu2.fetch.icacheStallCycles 35053 # Number of cycles fetch is stalled on an Icache miss 1342system.cpu2.fetch.Insts 247865 # Number of instructions fetch has processed 1343system.cpu2.fetch.Branches 46151 # Number of branches that fetch encountered 1344system.cpu2.fetch.predictedBranches 38624 # Number of branches that fetch has predicted taken 1345system.cpu2.fetch.Cycles 123337 # Number of cycles fetch has run and was not squashing or blocked 1346system.cpu2.fetch.SquashCycles 2679 # Number of cycles fetch has spent squashing 1347system.cpu2.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 1348system.cpu2.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from 1349system.cpu2.fetch.PendingTrapStallCycles 1154 # Number of stall cycles due to pending traps 1350system.cpu2.fetch.CacheLines 26088 # Number of cache lines fetched 1351system.cpu2.fetch.IcacheSquashes 455 # Number of outstanding Icache misses that were squashed 1352system.cpu2.fetch.rateDist::samples 160896 # Number of instructions fetched each cycle (Total) 1353system.cpu2.fetch.rateDist::mean 1.540529 # Number of instructions fetched each cycle (Total) 1354system.cpu2.fetch.rateDist::stdev 2.092892 # Number of instructions fetched each cycle (Total) 1355system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 1356system.cpu2.fetch.rateDist::0 69454 43.17% 43.17% # Number of instructions fetched each cycle (Total) 1357system.cpu2.fetch.rateDist::1 47444 29.49% 72.65% # Number of instructions fetched each cycle (Total) 1358system.cpu2.fetch.rateDist::2 8853 5.50% 78.16% # Number of instructions fetched each cycle (Total) 1359system.cpu2.fetch.rateDist::3 3439 2.14% 80.29% # Number of instructions fetched each cycle (Total) 1360system.cpu2.fetch.rateDist::4 969 0.60% 80.90% # Number of instructions fetched each cycle (Total) 1361system.cpu2.fetch.rateDist::5 24720 15.36% 96.26% # Number of instructions fetched each cycle (Total) 1362system.cpu2.fetch.rateDist::6 1203 0.75% 97.01% # Number of instructions fetched each cycle (Total) 1363system.cpu2.fetch.rateDist::7 808 0.50% 97.51% # Number of instructions fetched each cycle (Total) 1364system.cpu2.fetch.rateDist::8 4006 2.49% 100.00% # Number of instructions fetched each cycle (Total) 1365system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 1366system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1367system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 1368system.cpu2.fetch.rateDist::total 160896 # Number of instructions fetched each cycle (Total) 1369system.cpu2.fetch.branchRate 0.283961 # Number of branch fetches per cycle 1370system.cpu2.fetch.rate 1.525079 # Number of inst fetches per cycle 1371system.cpu2.decode.IdleCycles 17877 # Number of cycles decode is idle 1372system.cpu2.decode.BlockedCycles 74268 # Number of cycles decode is blocked 1373system.cpu2.decode.RunCycles 63015 # Number of cycles decode is running 1374system.cpu2.decode.UnblockCycles 4387 # Number of cycles decode is unblocking 1375system.cpu2.decode.SquashCycles 1339 # Number of cycles decode is squashing 1376system.cpu2.decode.DecodedInsts 232406 # Number of instructions handled by decode 1377system.cpu2.rename.SquashCycles 1339 # Number of cycles rename is squashing 1378system.cpu2.rename.IdleCycles 18566 # Number of cycles rename is idle 1379system.cpu2.rename.BlockCycles 36272 # Number of cycles rename is blocking 1380system.cpu2.rename.serializeStallCycles 13923 # count of cycles rename stalled for serializing inst 1381system.cpu2.rename.RunCycles 64728 # Number of cycles rename is running 1382system.cpu2.rename.UnblockCycles 26058 # Number of cycles rename is unblocking 1383system.cpu2.rename.RenamedInsts 229231 # Number of instructions processed by rename 1384system.cpu2.rename.IQFullEvents 23352 # Number of times rename has blocked due to IQ full 1385system.cpu2.rename.LQFullEvents 13 # Number of times rename has blocked due to LQ full 1386system.cpu2.rename.FullRegisterEvents 3 # Number of times there has been no free registers 1387system.cpu2.rename.RenamedOperands 159189 # Number of destination operands rename has renamed 1388system.cpu2.rename.RenameLookups 426806 # Number of register rename lookups that rename has made 1389system.cpu2.rename.int_rename_lookups 335096 # Number of integer rename lookups 1390system.cpu2.rename.CommittedMaps 145681 # Number of HB maps that are committed 1391system.cpu2.rename.UndoneMaps 13508 # Number of HB maps that are undone due to squashing 1392system.cpu2.rename.serializingInsts 1198 # count of serializing insts renamed 1393system.cpu2.rename.tempSerializingInsts 1266 # count of temporary serializing insts renamed 1394system.cpu2.rename.skidInsts 30557 # count of insts added to the skid buffer 1395system.cpu2.memDep0.insertedLoads 61312 # Number of loads inserted to the mem dependence unit. 1396system.cpu2.memDep0.insertedStores 27565 # Number of stores inserted to the mem dependence unit. 1397system.cpu2.memDep0.conflictingLoads 29913 # Number of conflicting loads. 1398system.cpu2.memDep0.conflictingStores 22477 # Number of conflicting stores. 1399system.cpu2.iq.iqInstsAdded 187400 # Number of instructions added to the IQ (excludes non-spec) 1400system.cpu2.iq.iqNonSpecInstsAdded 8554 # Number of non-speculative instructions added to the IQ 1401system.cpu2.iq.iqInstsIssued 191519 # Number of instructions issued 1402system.cpu2.iq.iqSquashedInstsIssued 13 # Number of squashed instructions issued 1403system.cpu2.iq.iqSquashedInstsExamined 12551 # Number of squashed instructions iterated over during squash; mainly for profiling 1404system.cpu2.iq.iqSquashedOperandsExamined 10065 # Number of squashed operands that are examined and possibly removed from graph 1405system.cpu2.iq.iqSquashedNonSpecRemoved 731 # Number of squashed non-spec instructions that were removed 1406system.cpu2.iq.issued_per_cycle::samples 160896 # Number of insts issued each cycle 1407system.cpu2.iq.issued_per_cycle::mean 1.190328 # Number of insts issued each cycle 1408system.cpu2.iq.issued_per_cycle::stdev 1.355636 # Number of insts issued each cycle 1409system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 1410system.cpu2.iq.issued_per_cycle::0 73129 45.45% 45.45% # Number of insts issued each cycle 1411system.cpu2.iq.issued_per_cycle::1 27885 17.33% 62.78% # Number of insts issued each cycle 1412system.cpu2.iq.issued_per_cycle::2 27023 16.80% 79.58% # Number of insts issued each cycle 1413system.cpu2.iq.issued_per_cycle::3 26608 16.54% 96.11% # Number of insts issued each cycle 1414system.cpu2.iq.issued_per_cycle::4 3367 2.09% 98.21% # Number of insts issued each cycle 1415system.cpu2.iq.issued_per_cycle::5 1611 1.00% 99.21% # Number of insts issued each cycle 1416system.cpu2.iq.issued_per_cycle::6 866 0.54% 99.75% # Number of insts issued each cycle 1417system.cpu2.iq.issued_per_cycle::7 211 0.13% 99.88% # Number of insts issued each cycle 1418system.cpu2.iq.issued_per_cycle::8 196 0.12% 100.00% # Number of insts issued each cycle 1419system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1420system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1421system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 1422system.cpu2.iq.issued_per_cycle::total 160896 # Number of insts issued each cycle 1423system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 1424system.cpu2.iq.fu_full::IntAlu 80 24.02% 24.02% # attempts to use FU when none available 1425system.cpu2.iq.fu_full::IntMult 0 0.00% 24.02% # attempts to use FU when none available 1426system.cpu2.iq.fu_full::IntDiv 0 0.00% 24.02% # attempts to use FU when none available 1427system.cpu2.iq.fu_full::FloatAdd 0 0.00% 24.02% # attempts to use FU when none available 1428system.cpu2.iq.fu_full::FloatCmp 0 0.00% 24.02% # attempts to use FU when none available 1429system.cpu2.iq.fu_full::FloatCvt 0 0.00% 24.02% # attempts to use FU when none available 1430system.cpu2.iq.fu_full::FloatMult 0 0.00% 24.02% # attempts to use FU when none available 1431system.cpu2.iq.fu_full::FloatDiv 0 0.00% 24.02% # attempts to use FU when none available 1432system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 24.02% # attempts to use FU when none available 1433system.cpu2.iq.fu_full::SimdAdd 0 0.00% 24.02% # attempts to use FU when none available 1434system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 24.02% # attempts to use FU when none available 1435system.cpu2.iq.fu_full::SimdAlu 0 0.00% 24.02% # attempts to use FU when none available 1436system.cpu2.iq.fu_full::SimdCmp 0 0.00% 24.02% # attempts to use FU when none available 1437system.cpu2.iq.fu_full::SimdCvt 0 0.00% 24.02% # attempts to use FU when none available 1438system.cpu2.iq.fu_full::SimdMisc 0 0.00% 24.02% # attempts to use FU when none available 1439system.cpu2.iq.fu_full::SimdMult 0 0.00% 24.02% # attempts to use FU when none available 1440system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 24.02% # attempts to use FU when none available 1441system.cpu2.iq.fu_full::SimdShift 0 0.00% 24.02% # attempts to use FU when none available 1442system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 24.02% # attempts to use FU when none available 1443system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 24.02% # attempts to use FU when none available 1444system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 24.02% # attempts to use FU when none available 1445system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 24.02% # attempts to use FU when none available 1446system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 24.02% # attempts to use FU when none available 1447system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 24.02% # attempts to use FU when none available 1448system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 24.02% # attempts to use FU when none available 1449system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 24.02% # attempts to use FU when none available 1450system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 24.02% # attempts to use FU when none available 1451system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 24.02% # attempts to use FU when none available 1452system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 24.02% # attempts to use FU when none available 1453system.cpu2.iq.fu_full::MemRead 44 13.21% 37.24% # attempts to use FU when none available 1454system.cpu2.iq.fu_full::MemWrite 209 62.76% 100.00% # attempts to use FU when none available 1455system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 1456system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 1457system.cpu2.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 1458system.cpu2.iq.FU_type_0::IntAlu 96792 50.54% 50.54% # Type of FU issued 1459system.cpu2.iq.FU_type_0::IntMult 0 0.00% 50.54% # Type of FU issued 1460system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 50.54% # Type of FU issued 1461system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 50.54% # Type of FU issued 1462system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 50.54% # Type of FU issued 1463system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 50.54% # Type of FU issued 1464system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 50.54% # Type of FU issued 1465system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 50.54% # Type of FU issued 1466system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 50.54% # Type of FU issued 1467system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 50.54% # Type of FU issued 1468system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 50.54% # Type of FU issued 1469system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 50.54% # Type of FU issued 1470system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 50.54% # Type of FU issued 1471system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 50.54% # Type of FU issued 1472system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 50.54% # Type of FU issued 1473system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 50.54% # Type of FU issued 1474system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 50.54% # Type of FU issued 1475system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 50.54% # Type of FU issued 1476system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 50.54% # Type of FU issued 1477system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 50.54% # Type of FU issued 1478system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 50.54% # Type of FU issued 1479system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 50.54% # Type of FU issued 1480system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 50.54% # Type of FU issued 1481system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 50.54% # Type of FU issued 1482system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 50.54% # Type of FU issued 1483system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 50.54% # Type of FU issued 1484system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 50.54% # Type of FU issued 1485system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 50.54% # Type of FU issued 1486system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 50.54% # Type of FU issued 1487system.cpu2.iq.FU_type_0::MemRead 67722 35.36% 85.90% # Type of FU issued 1488system.cpu2.iq.FU_type_0::MemWrite 27005 14.10% 100.00% # Type of FU issued 1489system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 1490system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 1491system.cpu2.iq.FU_type_0::total 191519 # Type of FU issued 1492system.cpu2.iq.rate 1.178390 # Inst issue rate 1493system.cpu2.iq.fu_busy_cnt 333 # FU busy when requested 1494system.cpu2.iq.fu_busy_rate 0.001739 # FU busy rate (busy events/executed inst) 1495system.cpu2.iq.int_inst_queue_reads 544280 # Number of integer instruction queue reads 1496system.cpu2.iq.int_inst_queue_writes 208542 # Number of integer instruction queue writes 1497system.cpu2.iq.int_inst_queue_wakeup_accesses 190032 # Number of integer instruction queue wakeup accesses 1498system.cpu2.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads 1499system.cpu2.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes 1500system.cpu2.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses 1501system.cpu2.iq.int_alu_accesses 191852 # Number of integer alu accesses 1502system.cpu2.iq.fp_alu_accesses 0 # Number of floating point alu accesses 1503system.cpu2.iew.lsq.thread0.forwLoads 22329 # Number of loads that had data forwarded from stores 1504system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 1505system.cpu2.iew.lsq.thread0.squashedLoads 2475 # Number of loads squashed 1506system.cpu2.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed 1507system.cpu2.iew.lsq.thread0.memOrderViolation 37 # Number of memory ordering violations 1508system.cpu2.iew.lsq.thread0.squashedStores 1441 # Number of stores squashed 1509system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 1510system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 1511system.cpu2.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 1512system.cpu2.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked 1513system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle 1514system.cpu2.iew.iewSquashCycles 1339 # Number of cycles IEW is squashing 1515system.cpu2.iew.iewBlockCycles 9482 # Number of cycles IEW is blocking 1516system.cpu2.iew.iewUnblockCycles 66 # Number of cycles IEW is unblocking 1517system.cpu2.iew.iewDispatchedInsts 226726 # Number of instructions dispatched to IQ 1518system.cpu2.iew.iewDispSquashedInsts 191 # Number of squashed instructions skipped by dispatch 1519system.cpu2.iew.iewDispLoadInsts 61312 # Number of dispatched load instructions 1520system.cpu2.iew.iewDispStoreInsts 27565 # Number of dispatched store instructions 1521system.cpu2.iew.iewDispNonSpecInsts 1142 # Number of dispatched non-speculative instructions 1522system.cpu2.iew.iewIQFullEvents 36 # Number of times the IQ has become full, causing a stall 1523system.cpu2.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 1524system.cpu2.iew.memOrderViolationEvents 37 # Number of memory order violations 1525system.cpu2.iew.predictedTakenIncorrect 430 # Number of branches that were predicted taken incorrectly 1526system.cpu2.iew.predictedNotTakenIncorrect 1052 # Number of branches that were predicted not taken incorrectly 1527system.cpu2.iew.branchMispredicts 1482 # Number of branch mispredicts detected at execute 1528system.cpu2.iew.iewExecutedInsts 190532 # Number of executed instructions 1529system.cpu2.iew.iewExecLoadInsts 60316 # Number of load instructions executed 1530system.cpu2.iew.iewExecSquashedInsts 987 # Number of squashed instructions skipped in execute 1531system.cpu2.iew.exec_swp 0 # number of swp insts executed 1532system.cpu2.iew.exec_nop 30772 # number of nop insts executed 1533system.cpu2.iew.exec_refs 87235 # number of memory reference insts executed 1534system.cpu2.iew.exec_branches 40210 # Number of branches executed 1535system.cpu2.iew.exec_stores 26919 # Number of stores executed 1536system.cpu2.iew.exec_rate 1.172317 # Inst execution rate 1537system.cpu2.iew.wb_sent 190296 # cumulative count of insts sent to commit 1538system.cpu2.iew.wb_count 190032 # cumulative count of insts written-back 1539system.cpu2.iew.wb_producers 104798 # num instructions producing a value 1540system.cpu2.iew.wb_consumers 111375 # num instructions consuming a value 1541system.cpu2.iew.wb_rate 1.169241 # insts written-back per cycle 1542system.cpu2.iew.wb_fanout 0.940947 # average fanout of values written-back 1543system.cpu2.commit.commitSquashedInsts 13298 # The number of squashed insts skipped by commit 1544system.cpu2.commit.commitNonSpecStalls 7823 # The number of times commit has been forced to stall to communicate backwards 1545system.cpu2.commit.branchMispredicts 1261 # The number of times a branch was mispredicted 1546system.cpu2.commit.committed_per_cycle::samples 158397 # Number of insts commited each cycle 1547system.cpu2.commit.committed_per_cycle::mean 1.347140 # Number of insts commited each cycle 1548system.cpu2.commit.committed_per_cycle::stdev 1.933730 # Number of insts commited each cycle 1549system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 1550system.cpu2.commit.committed_per_cycle::0 80708 50.95% 50.95% # Number of insts commited each cycle 1551system.cpu2.commit.committed_per_cycle::1 36780 23.22% 74.17% # Number of insts commited each cycle 1552system.cpu2.commit.committed_per_cycle::2 5258 3.32% 77.49% # Number of insts commited each cycle 1553system.cpu2.commit.committed_per_cycle::3 8633 5.45% 82.94% # Number of insts commited each cycle 1554system.cpu2.commit.committed_per_cycle::4 1531 0.97% 83.91% # Number of insts commited each cycle 1555system.cpu2.commit.committed_per_cycle::5 22393 14.14% 98.05% # Number of insts commited each cycle 1556system.cpu2.commit.committed_per_cycle::6 849 0.54% 98.58% # Number of insts commited each cycle 1557system.cpu2.commit.committed_per_cycle::7 955 0.60% 99.19% # Number of insts commited each cycle 1558system.cpu2.commit.committed_per_cycle::8 1290 0.81% 100.00% # Number of insts commited each cycle 1559system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 1560system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 1561system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 1562system.cpu2.commit.committed_per_cycle::total 158397 # Number of insts commited each cycle 1563system.cpu2.commit.committedInsts 213383 # Number of instructions committed 1564system.cpu2.commit.committedOps 213383 # Number of ops (including micro ops) committed 1565system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed 1566system.cpu2.commit.refs 84961 # Number of memory references committed 1567system.cpu2.commit.loads 58837 # Number of loads committed 1568system.cpu2.commit.membars 7109 # Number of memory barriers committed 1569system.cpu2.commit.branches 39190 # Number of branches committed 1570system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions. 1571system.cpu2.commit.int_insts 146276 # Number of committed integer instructions. 1572system.cpu2.commit.function_calls 322 # Number of function calls committed. 1573system.cpu2.commit.op_class_0::No_OpClass 29980 14.05% 14.05% # Class of committed instruction 1574system.cpu2.commit.op_class_0::IntAlu 91333 42.80% 56.85% # Class of committed instruction 1575system.cpu2.commit.op_class_0::IntMult 0 0.00% 56.85% # Class of committed instruction 1576system.cpu2.commit.op_class_0::IntDiv 0 0.00% 56.85% # Class of committed instruction 1577system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 56.85% # Class of committed instruction 1578system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 56.85% # Class of committed instruction 1579system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 56.85% # Class of committed instruction 1580system.cpu2.commit.op_class_0::FloatMult 0 0.00% 56.85% # Class of committed instruction 1581system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 56.85% # Class of committed instruction 1582system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 56.85% # Class of committed instruction 1583system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 56.85% # Class of committed instruction 1584system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 56.85% # Class of committed instruction 1585system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 56.85% # Class of committed instruction 1586system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 56.85% # Class of committed instruction 1587system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 56.85% # Class of committed instruction 1588system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 56.85% # Class of committed instruction 1589system.cpu2.commit.op_class_0::SimdMult 0 0.00% 56.85% # Class of committed instruction 1590system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 56.85% # Class of committed instruction 1591system.cpu2.commit.op_class_0::SimdShift 0 0.00% 56.85% # Class of committed instruction 1592system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 56.85% # Class of committed instruction 1593system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 56.85% # Class of committed instruction 1594system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 56.85% # Class of committed instruction 1595system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 56.85% # Class of committed instruction 1596system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 56.85% # Class of committed instruction 1597system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 56.85% # Class of committed instruction 1598system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 56.85% # Class of committed instruction 1599system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 56.85% # Class of committed instruction 1600system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 56.85% # Class of committed instruction 1601system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 56.85% # Class of committed instruction 1602system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 56.85% # Class of committed instruction 1603system.cpu2.commit.op_class_0::MemRead 65946 30.90% 87.76% # Class of committed instruction 1604system.cpu2.commit.op_class_0::MemWrite 26124 12.24% 100.00% # Class of committed instruction 1605system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 1606system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 1607system.cpu2.commit.op_class_0::total 213383 # Class of committed instruction 1608system.cpu2.commit.bw_lim_events 1290 # number cycles where commit BW limit reached 1609system.cpu2.rob.rob_reads 383202 # The number of ROB reads 1610system.cpu2.rob.rob_writes 455861 # The number of ROB writes 1611system.cpu2.timesIdled 213 # Number of times that the entire CPU went into an idle state and unscheduled itself 1612system.cpu2.idleCycles 1630 # Total number of cycles that the CPU has spent unscheduled due to idling 1613system.cpu2.quiesceCycles 45643 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1614system.cpu2.committedInsts 176294 # Number of Instructions Simulated 1615system.cpu2.committedOps 176294 # Number of Ops (including micro ops) Simulated 1616system.cpu2.cpi 0.921903 # CPI: Cycles Per Instruction 1617system.cpu2.cpi_total 0.921903 # CPI: Total CPI of All Threads 1618system.cpu2.ipc 1.084713 # IPC: Instructions Per Cycle 1619system.cpu2.ipc_total 1.084713 # IPC: Total IPC of All Threads 1620system.cpu2.int_regfile_reads 321409 # number of integer regfile reads 1621system.cpu2.int_regfile_writes 151400 # number of integer regfile writes 1622system.cpu2.fp_regfile_writes 64 # number of floating regfile writes 1623system.cpu2.misc_regfile_reads 88848 # number of misc regfile reads 1624system.cpu2.misc_regfile_writes 648 # number of misc regfile writes 1625system.cpu2.dcache.tags.replacements 0 # number of replacements 1626system.cpu2.dcache.tags.tagsinuse 23.120660 # Cycle average of tags in use 1627system.cpu2.dcache.tags.total_refs 32242 # Total number of references to valid blocks. 1628system.cpu2.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. 1629system.cpu2.dcache.tags.avg_refs 1111.793103 # Average number of references to valid blocks. 1630system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1631system.cpu2.dcache.tags.occ_blocks::cpu2.data 23.120660 # Average occupied blocks per requestor 1632system.cpu2.dcache.tags.occ_percent::cpu2.data 0.045158 # Average percentage of cache occupancy 1633system.cpu2.dcache.tags.occ_percent::total 0.045158 # Average percentage of cache occupancy 1634system.cpu2.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id 1635system.cpu2.dcache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id 1636system.cpu2.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id 1637system.cpu2.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id 1638system.cpu2.dcache.tags.tag_accesses 256599 # Number of tag accesses 1639system.cpu2.dcache.tags.data_accesses 256599 # Number of data accesses 1640system.cpu2.dcache.ReadReq_hits::cpu2.data 37491 # number of ReadReq hits 1641system.cpu2.dcache.ReadReq_hits::total 37491 # number of ReadReq hits 1642system.cpu2.dcache.WriteReq_hits::cpu2.data 25903 # number of WriteReq hits 1643system.cpu2.dcache.WriteReq_hits::total 25903 # number of WriteReq hits 1644system.cpu2.dcache.SwapReq_hits::cpu2.data 19 # number of SwapReq hits 1645system.cpu2.dcache.SwapReq_hits::total 19 # number of SwapReq hits 1646system.cpu2.dcache.demand_hits::cpu2.data 63394 # number of demand (read+write) hits 1647system.cpu2.dcache.demand_hits::total 63394 # number of demand (read+write) hits 1648system.cpu2.dcache.overall_hits::cpu2.data 63394 # number of overall hits 1649system.cpu2.dcache.overall_hits::total 63394 # number of overall hits 1650system.cpu2.dcache.ReadReq_misses::cpu2.data 473 # number of ReadReq misses 1651system.cpu2.dcache.ReadReq_misses::total 473 # number of ReadReq misses 1652system.cpu2.dcache.WriteReq_misses::cpu2.data 153 # number of WriteReq misses 1653system.cpu2.dcache.WriteReq_misses::total 153 # number of WriteReq misses 1654system.cpu2.dcache.SwapReq_misses::cpu2.data 49 # number of SwapReq misses 1655system.cpu2.dcache.SwapReq_misses::total 49 # number of SwapReq misses 1656system.cpu2.dcache.demand_misses::cpu2.data 626 # number of demand (read+write) misses 1657system.cpu2.dcache.demand_misses::total 626 # number of demand (read+write) misses 1658system.cpu2.dcache.overall_misses::cpu2.data 626 # number of overall misses 1659system.cpu2.dcache.overall_misses::total 626 # number of overall misses 1660system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 7957500 # number of ReadReq miss cycles 1661system.cpu2.dcache.ReadReq_miss_latency::total 7957500 # number of ReadReq miss cycles 1662system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 3701500 # number of WriteReq miss cycles 1663system.cpu2.dcache.WriteReq_miss_latency::total 3701500 # number of WriteReq miss cycles 1664system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 605000 # number of SwapReq miss cycles 1665system.cpu2.dcache.SwapReq_miss_latency::total 605000 # number of SwapReq miss cycles 1666system.cpu2.dcache.demand_miss_latency::cpu2.data 11659000 # number of demand (read+write) miss cycles 1667system.cpu2.dcache.demand_miss_latency::total 11659000 # number of demand (read+write) miss cycles 1668system.cpu2.dcache.overall_miss_latency::cpu2.data 11659000 # number of overall miss cycles 1669system.cpu2.dcache.overall_miss_latency::total 11659000 # number of overall miss cycles 1670system.cpu2.dcache.ReadReq_accesses::cpu2.data 37964 # number of ReadReq accesses(hits+misses) 1671system.cpu2.dcache.ReadReq_accesses::total 37964 # number of ReadReq accesses(hits+misses) 1672system.cpu2.dcache.WriteReq_accesses::cpu2.data 26056 # number of WriteReq accesses(hits+misses) 1673system.cpu2.dcache.WriteReq_accesses::total 26056 # number of WriteReq accesses(hits+misses) 1674system.cpu2.dcache.SwapReq_accesses::cpu2.data 68 # number of SwapReq accesses(hits+misses) 1675system.cpu2.dcache.SwapReq_accesses::total 68 # number of SwapReq accesses(hits+misses) 1676system.cpu2.dcache.demand_accesses::cpu2.data 64020 # number of demand (read+write) accesses 1677system.cpu2.dcache.demand_accesses::total 64020 # number of demand (read+write) accesses 1678system.cpu2.dcache.overall_accesses::cpu2.data 64020 # number of overall (read+write) accesses 1679system.cpu2.dcache.overall_accesses::total 64020 # number of overall (read+write) accesses 1680system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.012459 # miss rate for ReadReq accesses 1681system.cpu2.dcache.ReadReq_miss_rate::total 0.012459 # miss rate for ReadReq accesses 1682system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.005872 # miss rate for WriteReq accesses 1683system.cpu2.dcache.WriteReq_miss_rate::total 0.005872 # miss rate for WriteReq accesses 1684system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.720588 # miss rate for SwapReq accesses 1685system.cpu2.dcache.SwapReq_miss_rate::total 0.720588 # miss rate for SwapReq accesses 1686system.cpu2.dcache.demand_miss_rate::cpu2.data 0.009778 # miss rate for demand accesses 1687system.cpu2.dcache.demand_miss_rate::total 0.009778 # miss rate for demand accesses 1688system.cpu2.dcache.overall_miss_rate::cpu2.data 0.009778 # miss rate for overall accesses 1689system.cpu2.dcache.overall_miss_rate::total 0.009778 # miss rate for overall accesses 1690system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 16823.467230 # average ReadReq miss latency 1691system.cpu2.dcache.ReadReq_avg_miss_latency::total 16823.467230 # average ReadReq miss latency 1692system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 24192.810458 # average WriteReq miss latency 1693system.cpu2.dcache.WriteReq_avg_miss_latency::total 24192.810458 # average WriteReq miss latency 1694system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 12346.938776 # average SwapReq miss latency 1695system.cpu2.dcache.SwapReq_avg_miss_latency::total 12346.938776 # average SwapReq miss latency 1696system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 18624.600639 # average overall miss latency 1697system.cpu2.dcache.demand_avg_miss_latency::total 18624.600639 # average overall miss latency 1698system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 18624.600639 # average overall miss latency 1699system.cpu2.dcache.overall_avg_miss_latency::total 18624.600639 # average overall miss latency 1700system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1701system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1702system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1703system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked 1704system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1705system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1706system.cpu2.dcache.fast_writes 0 # number of fast writes performed 1707system.cpu2.dcache.cache_copies 0 # number of cache copies performed 1708system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 311 # number of ReadReq MSHR hits 1709system.cpu2.dcache.ReadReq_mshr_hits::total 311 # number of ReadReq MSHR hits 1710system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 50 # number of WriteReq MSHR hits 1711system.cpu2.dcache.WriteReq_mshr_hits::total 50 # number of WriteReq MSHR hits 1712system.cpu2.dcache.demand_mshr_hits::cpu2.data 361 # number of demand (read+write) MSHR hits 1713system.cpu2.dcache.demand_mshr_hits::total 361 # number of demand (read+write) MSHR hits 1714system.cpu2.dcache.overall_mshr_hits::cpu2.data 361 # number of overall MSHR hits 1715system.cpu2.dcache.overall_mshr_hits::total 361 # number of overall MSHR hits 1716system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 162 # number of ReadReq MSHR misses 1717system.cpu2.dcache.ReadReq_mshr_misses::total 162 # number of ReadReq MSHR misses 1718system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 103 # number of WriteReq MSHR misses 1719system.cpu2.dcache.WriteReq_mshr_misses::total 103 # number of WriteReq MSHR misses 1720system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 49 # number of SwapReq MSHR misses 1721system.cpu2.dcache.SwapReq_mshr_misses::total 49 # number of SwapReq MSHR misses 1722system.cpu2.dcache.demand_mshr_misses::cpu2.data 265 # number of demand (read+write) MSHR misses 1723system.cpu2.dcache.demand_mshr_misses::total 265 # number of demand (read+write) MSHR misses 1724system.cpu2.dcache.overall_mshr_misses::cpu2.data 265 # number of overall MSHR misses 1725system.cpu2.dcache.overall_mshr_misses::total 265 # number of overall MSHR misses 1726system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1647500 # number of ReadReq MSHR miss cycles 1727system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1647500 # number of ReadReq MSHR miss cycles 1728system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1967500 # number of WriteReq MSHR miss cycles 1729system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1967500 # number of WriteReq MSHR miss cycles 1730system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 556000 # number of SwapReq MSHR miss cycles 1731system.cpu2.dcache.SwapReq_mshr_miss_latency::total 556000 # number of SwapReq MSHR miss cycles 1732system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3615000 # number of demand (read+write) MSHR miss cycles 1733system.cpu2.dcache.demand_mshr_miss_latency::total 3615000 # number of demand (read+write) MSHR miss cycles 1734system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3615000 # number of overall MSHR miss cycles 1735system.cpu2.dcache.overall_mshr_miss_latency::total 3615000 # number of overall MSHR miss cycles 1736system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.004267 # mshr miss rate for ReadReq accesses 1737system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.004267 # mshr miss rate for ReadReq accesses 1738system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.003953 # mshr miss rate for WriteReq accesses 1739system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.003953 # mshr miss rate for WriteReq accesses 1740system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.720588 # mshr miss rate for SwapReq accesses 1741system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.720588 # mshr miss rate for SwapReq accesses 1742system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.004139 # mshr miss rate for demand accesses 1743system.cpu2.dcache.demand_mshr_miss_rate::total 0.004139 # mshr miss rate for demand accesses 1744system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.004139 # mshr miss rate for overall accesses 1745system.cpu2.dcache.overall_mshr_miss_rate::total 0.004139 # mshr miss rate for overall accesses 1746system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 10169.753086 # average ReadReq mshr miss latency 1747system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 10169.753086 # average ReadReq mshr miss latency 1748system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 19101.941748 # average WriteReq mshr miss latency 1749system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 19101.941748 # average WriteReq mshr miss latency 1750system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 11346.938776 # average SwapReq mshr miss latency 1751system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 11346.938776 # average SwapReq mshr miss latency 1752system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 13641.509434 # average overall mshr miss latency 1753system.cpu2.dcache.demand_avg_mshr_miss_latency::total 13641.509434 # average overall mshr miss latency 1754system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 13641.509434 # average overall mshr miss latency 1755system.cpu2.dcache.overall_avg_mshr_miss_latency::total 13641.509434 # average overall mshr miss latency 1756system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1757system.cpu2.icache.tags.replacements 386 # number of replacements 1758system.cpu2.icache.tags.tagsinuse 77.580266 # Cycle average of tags in use 1759system.cpu2.icache.tags.total_refs 25515 # Total number of references to valid blocks. 1760system.cpu2.icache.tags.sampled_refs 500 # Sample count of references to valid blocks. 1761system.cpu2.icache.tags.avg_refs 51.030000 # Average number of references to valid blocks. 1762system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1763system.cpu2.icache.tags.occ_blocks::cpu2.inst 77.580266 # Average occupied blocks per requestor 1764system.cpu2.icache.tags.occ_percent::cpu2.inst 0.151524 # Average percentage of cache occupancy 1765system.cpu2.icache.tags.occ_percent::total 0.151524 # Average percentage of cache occupancy 1766system.cpu2.icache.tags.occ_task_id_blocks::1024 114 # Occupied blocks per task id 1767system.cpu2.icache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id 1768system.cpu2.icache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id 1769system.cpu2.icache.tags.occ_task_id_percent::1024 0.222656 # Percentage of cache occupancy per task id 1770system.cpu2.icache.tags.tag_accesses 26588 # Number of tag accesses 1771system.cpu2.icache.tags.data_accesses 26588 # Number of data accesses 1772system.cpu2.icache.ReadReq_hits::cpu2.inst 25515 # number of ReadReq hits 1773system.cpu2.icache.ReadReq_hits::total 25515 # number of ReadReq hits 1774system.cpu2.icache.demand_hits::cpu2.inst 25515 # number of demand (read+write) hits 1775system.cpu2.icache.demand_hits::total 25515 # number of demand (read+write) hits 1776system.cpu2.icache.overall_hits::cpu2.inst 25515 # number of overall hits 1777system.cpu2.icache.overall_hits::total 25515 # number of overall hits 1778system.cpu2.icache.ReadReq_misses::cpu2.inst 573 # number of ReadReq misses 1779system.cpu2.icache.ReadReq_misses::total 573 # number of ReadReq misses 1780system.cpu2.icache.demand_misses::cpu2.inst 573 # number of demand (read+write) misses 1781system.cpu2.icache.demand_misses::total 573 # number of demand (read+write) misses 1782system.cpu2.icache.overall_misses::cpu2.inst 573 # number of overall misses 1783system.cpu2.icache.overall_misses::total 573 # number of overall misses 1784system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 7955500 # number of ReadReq miss cycles 1785system.cpu2.icache.ReadReq_miss_latency::total 7955500 # number of ReadReq miss cycles 1786system.cpu2.icache.demand_miss_latency::cpu2.inst 7955500 # number of demand (read+write) miss cycles 1787system.cpu2.icache.demand_miss_latency::total 7955500 # number of demand (read+write) miss cycles 1788system.cpu2.icache.overall_miss_latency::cpu2.inst 7955500 # number of overall miss cycles 1789system.cpu2.icache.overall_miss_latency::total 7955500 # number of overall miss cycles 1790system.cpu2.icache.ReadReq_accesses::cpu2.inst 26088 # number of ReadReq accesses(hits+misses) 1791system.cpu2.icache.ReadReq_accesses::total 26088 # number of ReadReq accesses(hits+misses) 1792system.cpu2.icache.demand_accesses::cpu2.inst 26088 # number of demand (read+write) accesses 1793system.cpu2.icache.demand_accesses::total 26088 # number of demand (read+write) accesses 1794system.cpu2.icache.overall_accesses::cpu2.inst 26088 # number of overall (read+write) accesses 1795system.cpu2.icache.overall_accesses::total 26088 # number of overall (read+write) accesses 1796system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.021964 # miss rate for ReadReq accesses 1797system.cpu2.icache.ReadReq_miss_rate::total 0.021964 # miss rate for ReadReq accesses 1798system.cpu2.icache.demand_miss_rate::cpu2.inst 0.021964 # miss rate for demand accesses 1799system.cpu2.icache.demand_miss_rate::total 0.021964 # miss rate for demand accesses 1800system.cpu2.icache.overall_miss_rate::cpu2.inst 0.021964 # miss rate for overall accesses 1801system.cpu2.icache.overall_miss_rate::total 0.021964 # miss rate for overall accesses 1802system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 13883.944154 # average ReadReq miss latency 1803system.cpu2.icache.ReadReq_avg_miss_latency::total 13883.944154 # average ReadReq miss latency 1804system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 13883.944154 # average overall miss latency 1805system.cpu2.icache.demand_avg_miss_latency::total 13883.944154 # average overall miss latency 1806system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 13883.944154 # average overall miss latency 1807system.cpu2.icache.overall_avg_miss_latency::total 13883.944154 # average overall miss latency 1808system.cpu2.icache.blocked_cycles::no_mshrs 5 # number of cycles access was blocked 1809system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1810system.cpu2.icache.blocked::no_mshrs 1 # number of cycles access was blocked 1811system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked 1812system.cpu2.icache.avg_blocked_cycles::no_mshrs 5 # average number of cycles each access was blocked 1813system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1814system.cpu2.icache.fast_writes 0 # number of fast writes performed 1815system.cpu2.icache.cache_copies 0 # number of cache copies performed 1816system.cpu2.icache.writebacks::writebacks 386 # number of writebacks 1817system.cpu2.icache.writebacks::total 386 # number of writebacks 1818system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 73 # number of ReadReq MSHR hits 1819system.cpu2.icache.ReadReq_mshr_hits::total 73 # number of ReadReq MSHR hits 1820system.cpu2.icache.demand_mshr_hits::cpu2.inst 73 # number of demand (read+write) MSHR hits 1821system.cpu2.icache.demand_mshr_hits::total 73 # number of demand (read+write) MSHR hits 1822system.cpu2.icache.overall_mshr_hits::cpu2.inst 73 # number of overall MSHR hits 1823system.cpu2.icache.overall_mshr_hits::total 73 # number of overall MSHR hits 1824system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 500 # number of ReadReq MSHR misses 1825system.cpu2.icache.ReadReq_mshr_misses::total 500 # number of ReadReq MSHR misses 1826system.cpu2.icache.demand_mshr_misses::cpu2.inst 500 # number of demand (read+write) MSHR misses 1827system.cpu2.icache.demand_mshr_misses::total 500 # number of demand (read+write) MSHR misses 1828system.cpu2.icache.overall_mshr_misses::cpu2.inst 500 # number of overall MSHR misses 1829system.cpu2.icache.overall_mshr_misses::total 500 # number of overall MSHR misses 1830system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 6895000 # number of ReadReq MSHR miss cycles 1831system.cpu2.icache.ReadReq_mshr_miss_latency::total 6895000 # number of ReadReq MSHR miss cycles 1832system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 6895000 # number of demand (read+write) MSHR miss cycles 1833system.cpu2.icache.demand_mshr_miss_latency::total 6895000 # number of demand (read+write) MSHR miss cycles 1834system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 6895000 # number of overall MSHR miss cycles 1835system.cpu2.icache.overall_mshr_miss_latency::total 6895000 # number of overall MSHR miss cycles 1836system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.019166 # mshr miss rate for ReadReq accesses 1837system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.019166 # mshr miss rate for ReadReq accesses 1838system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.019166 # mshr miss rate for demand accesses 1839system.cpu2.icache.demand_mshr_miss_rate::total 0.019166 # mshr miss rate for demand accesses 1840system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.019166 # mshr miss rate for overall accesses 1841system.cpu2.icache.overall_mshr_miss_rate::total 0.019166 # mshr miss rate for overall accesses 1842system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 13790 # average ReadReq mshr miss latency 1843system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 13790 # average ReadReq mshr miss latency 1844system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 13790 # average overall mshr miss latency 1845system.cpu2.icache.demand_avg_mshr_miss_latency::total 13790 # average overall mshr miss latency 1846system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 13790 # average overall mshr miss latency 1847system.cpu2.icache.overall_avg_mshr_miss_latency::total 13790 # average overall mshr miss latency 1848system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1849system.cpu3.branchPred.lookups 52678 # Number of BP lookups 1850system.cpu3.branchPred.condPredicted 49211 # Number of conditional branches predicted 1851system.cpu3.branchPred.condIncorrect 1284 # Number of conditional branches incorrect 1852system.cpu3.branchPred.BTBLookups 45275 # Number of BTB lookups 1853system.cpu3.branchPred.BTBHits 44303 # Number of BTB hits 1854system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 1855system.cpu3.branchPred.BTBHitPct 97.853120 # BTB Hit Percentage 1856system.cpu3.branchPred.usedRAS 906 # Number of times the RAS was used to get a target. 1857system.cpu3.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions. 1858system.cpu3.numCycles 162161 # number of cpu cycles simulated 1859system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started 1860system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed 1861system.cpu3.fetch.icacheStallCycles 30846 # Number of cycles fetch is stalled on an Icache miss 1862system.cpu3.fetch.Insts 291154 # Number of instructions fetch has processed 1863system.cpu3.fetch.Branches 52678 # Number of branches that fetch encountered 1864system.cpu3.fetch.predictedBranches 45209 # Number of branches that fetch has predicted taken 1865system.cpu3.fetch.Cycles 126827 # Number of cycles fetch has run and was not squashing or blocked 1866system.cpu3.fetch.SquashCycles 2723 # Number of cycles fetch has spent squashing 1867system.cpu3.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 1868system.cpu3.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from 1869system.cpu3.fetch.PendingTrapStallCycles 1166 # Number of stall cycles due to pending traps 1870system.cpu3.fetch.CacheLines 21882 # Number of cache lines fetched 1871system.cpu3.fetch.IcacheSquashes 451 # Number of outstanding Icache misses that were squashed 1872system.cpu3.fetch.rateDist::samples 160213 # Number of instructions fetched each cycle (Total) 1873system.cpu3.fetch.rateDist::mean 1.817293 # Number of instructions fetched each cycle (Total) 1874system.cpu3.fetch.rateDist::stdev 2.188011 # Number of instructions fetched each cycle (Total) 1875system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 1876system.cpu3.fetch.rateDist::0 57700 36.01% 36.01% # Number of instructions fetched each cycle (Total) 1877system.cpu3.fetch.rateDist::1 51927 32.41% 68.43% # Number of instructions fetched each cycle (Total) 1878system.cpu3.fetch.rateDist::2 6814 4.25% 72.68% # Number of instructions fetched each cycle (Total) 1879system.cpu3.fetch.rateDist::3 3535 2.21% 74.89% # Number of instructions fetched each cycle (Total) 1880system.cpu3.fetch.rateDist::4 932 0.58% 75.47% # Number of instructions fetched each cycle (Total) 1881system.cpu3.fetch.rateDist::5 33301 20.79% 96.25% # Number of instructions fetched each cycle (Total) 1882system.cpu3.fetch.rateDist::6 1242 0.78% 97.03% # Number of instructions fetched each cycle (Total) 1883system.cpu3.fetch.rateDist::7 787 0.49% 97.52% # Number of instructions fetched each cycle (Total) 1884system.cpu3.fetch.rateDist::8 3975 2.48% 100.00% # Number of instructions fetched each cycle (Total) 1885system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 1886system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1887system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 1888system.cpu3.fetch.rateDist::total 160213 # Number of instructions fetched each cycle (Total) 1889system.cpu3.fetch.branchRate 0.324850 # Number of branch fetches per cycle 1890system.cpu3.fetch.rate 1.795463 # Number of inst fetches per cycle 1891system.cpu3.decode.IdleCycles 17433 # Number of cycles decode is idle 1892system.cpu3.decode.BlockedCycles 58368 # Number of cycles decode is blocked 1893system.cpu3.decode.RunCycles 79576 # Number of cycles decode is running 1894system.cpu3.decode.UnblockCycles 3465 # Number of cycles decode is unblocking 1895system.cpu3.decode.SquashCycles 1361 # Number of cycles decode is squashing 1896system.cpu3.decode.DecodedInsts 275763 # Number of instructions handled by decode 1897system.cpu3.rename.SquashCycles 1361 # Number of cycles rename is squashing 1898system.cpu3.rename.IdleCycles 18155 # Number of cycles rename is idle 1899system.cpu3.rename.BlockCycles 26788 # Number of cycles rename is blocking 1900system.cpu3.rename.serializeStallCycles 14101 # count of cycles rename stalled for serializing inst 1901system.cpu3.rename.RunCycles 81078 # Number of cycles rename is running 1902system.cpu3.rename.UnblockCycles 18720 # Number of cycles rename is unblocking 1903system.cpu3.rename.RenamedInsts 272367 # Number of instructions processed by rename 1904system.cpu3.rename.IQFullEvents 16743 # Number of times rename has blocked due to IQ full 1905system.cpu3.rename.LQFullEvents 17 # Number of times rename has blocked due to LQ full 1906system.cpu3.rename.FullRegisterEvents 3 # Number of times there has been no free registers 1907system.cpu3.rename.RenamedOperands 191251 # Number of destination operands rename has renamed 1908system.cpu3.rename.RenameLookups 520897 # Number of register rename lookups that rename has made 1909system.cpu3.rename.int_rename_lookups 405695 # Number of integer rename lookups 1910system.cpu3.rename.CommittedMaps 177247 # Number of HB maps that are committed 1911system.cpu3.rename.UndoneMaps 14004 # Number of HB maps that are undone due to squashing 1912system.cpu3.rename.serializingInsts 1196 # count of serializing insts renamed 1913system.cpu3.rename.tempSerializingInsts 1267 # count of temporary serializing insts renamed 1914system.cpu3.rename.skidInsts 23402 # count of insts added to the skid buffer 1915system.cpu3.memDep0.insertedLoads 76309 # Number of loads inserted to the mem dependence unit. 1916system.cpu3.memDep0.insertedStores 36069 # Number of stores inserted to the mem dependence unit. 1917system.cpu3.memDep0.conflictingLoads 36463 # Number of conflicting loads. 1918system.cpu3.memDep0.conflictingStores 30962 # Number of conflicting stores. 1919system.cpu3.iq.iqInstsAdded 226032 # Number of instructions added to the IQ (excludes non-spec) 1920system.cpu3.iq.iqNonSpecInstsAdded 6585 # Number of non-speculative instructions added to the IQ 1921system.cpu3.iq.iqInstsIssued 227862 # Number of instructions issued 1922system.cpu3.iq.iqSquashedInstsIssued 13 # Number of squashed instructions issued 1923system.cpu3.iq.iqSquashedInstsExamined 13164 # Number of squashed instructions iterated over during squash; mainly for profiling 1924system.cpu3.iq.iqSquashedOperandsExamined 10986 # Number of squashed operands that are examined and possibly removed from graph 1925system.cpu3.iq.iqSquashedNonSpecRemoved 709 # Number of squashed non-spec instructions that were removed 1926system.cpu3.iq.issued_per_cycle::samples 160213 # Number of insts issued each cycle 1927system.cpu3.iq.issued_per_cycle::mean 1.422244 # Number of insts issued each cycle 1928system.cpu3.iq.issued_per_cycle::stdev 1.377526 # Number of insts issued each cycle 1929system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 1930system.cpu3.iq.issued_per_cycle::0 61467 38.37% 38.37% # Number of insts issued each cycle 1931system.cpu3.iq.issued_per_cycle::1 22016 13.74% 52.11% # Number of insts issued each cycle 1932system.cpu3.iq.issued_per_cycle::2 35438 22.12% 74.23% # Number of insts issued each cycle 1933system.cpu3.iq.issued_per_cycle::3 35000 21.85% 96.07% # Number of insts issued each cycle 1934system.cpu3.iq.issued_per_cycle::4 3395 2.12% 98.19% # Number of insts issued each cycle 1935system.cpu3.iq.issued_per_cycle::5 1603 1.00% 99.19% # Number of insts issued each cycle 1936system.cpu3.iq.issued_per_cycle::6 883 0.55% 99.74% # Number of insts issued each cycle 1937system.cpu3.iq.issued_per_cycle::7 211 0.13% 99.88% # Number of insts issued each cycle 1938system.cpu3.iq.issued_per_cycle::8 200 0.12% 100.00% # Number of insts issued each cycle 1939system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1940system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1941system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 1942system.cpu3.iq.issued_per_cycle::total 160213 # Number of insts issued each cycle 1943system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 1944system.cpu3.iq.fu_full::IntAlu 82 24.12% 24.12% # attempts to use FU when none available 1945system.cpu3.iq.fu_full::IntMult 0 0.00% 24.12% # attempts to use FU when none available 1946system.cpu3.iq.fu_full::IntDiv 0 0.00% 24.12% # attempts to use FU when none available 1947system.cpu3.iq.fu_full::FloatAdd 0 0.00% 24.12% # attempts to use FU when none available 1948system.cpu3.iq.fu_full::FloatCmp 0 0.00% 24.12% # attempts to use FU when none available 1949system.cpu3.iq.fu_full::FloatCvt 0 0.00% 24.12% # attempts to use FU when none available 1950system.cpu3.iq.fu_full::FloatMult 0 0.00% 24.12% # attempts to use FU when none available 1951system.cpu3.iq.fu_full::FloatDiv 0 0.00% 24.12% # attempts to use FU when none available 1952system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 24.12% # attempts to use FU when none available 1953system.cpu3.iq.fu_full::SimdAdd 0 0.00% 24.12% # attempts to use FU when none available 1954system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 24.12% # attempts to use FU when none available 1955system.cpu3.iq.fu_full::SimdAlu 0 0.00% 24.12% # attempts to use FU when none available 1956system.cpu3.iq.fu_full::SimdCmp 0 0.00% 24.12% # attempts to use FU when none available 1957system.cpu3.iq.fu_full::SimdCvt 0 0.00% 24.12% # attempts to use FU when none available 1958system.cpu3.iq.fu_full::SimdMisc 0 0.00% 24.12% # attempts to use FU when none available 1959system.cpu3.iq.fu_full::SimdMult 0 0.00% 24.12% # attempts to use FU when none available 1960system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 24.12% # attempts to use FU when none available 1961system.cpu3.iq.fu_full::SimdShift 0 0.00% 24.12% # attempts to use FU when none available 1962system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 24.12% # attempts to use FU when none available 1963system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 24.12% # attempts to use FU when none available 1964system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 24.12% # attempts to use FU when none available 1965system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 24.12% # attempts to use FU when none available 1966system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 24.12% # attempts to use FU when none available 1967system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 24.12% # attempts to use FU when none available 1968system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 24.12% # attempts to use FU when none available 1969system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 24.12% # attempts to use FU when none available 1970system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 24.12% # attempts to use FU when none available 1971system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 24.12% # attempts to use FU when none available 1972system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 24.12% # attempts to use FU when none available 1973system.cpu3.iq.fu_full::MemRead 49 14.41% 38.53% # attempts to use FU when none available 1974system.cpu3.iq.fu_full::MemWrite 209 61.47% 100.00% # attempts to use FU when none available 1975system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 1976system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 1977system.cpu3.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 1978system.cpu3.iq.FU_type_0::IntAlu 111773 49.05% 49.05% # Type of FU issued 1979system.cpu3.iq.FU_type_0::IntMult 0 0.00% 49.05% # Type of FU issued 1980system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 49.05% # Type of FU issued 1981system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 49.05% # Type of FU issued 1982system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 49.05% # Type of FU issued 1983system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 49.05% # Type of FU issued 1984system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 49.05% # Type of FU issued 1985system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 49.05% # Type of FU issued 1986system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 49.05% # Type of FU issued 1987system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 49.05% # Type of FU issued 1988system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 49.05% # Type of FU issued 1989system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 49.05% # Type of FU issued 1990system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 49.05% # Type of FU issued 1991system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 49.05% # Type of FU issued 1992system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 49.05% # Type of FU issued 1993system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 49.05% # Type of FU issued 1994system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 49.05% # Type of FU issued 1995system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 49.05% # Type of FU issued 1996system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.05% # Type of FU issued 1997system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 49.05% # Type of FU issued 1998system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.05% # Type of FU issued 1999system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.05% # Type of FU issued 2000system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.05% # Type of FU issued 2001system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.05% # Type of FU issued 2002system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.05% # Type of FU issued 2003system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.05% # Type of FU issued 2004system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 49.05% # Type of FU issued 2005system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.05% # Type of FU issued 2006system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.05% # Type of FU issued 2007system.cpu3.iq.FU_type_0::MemRead 80677 35.41% 84.46% # Type of FU issued 2008system.cpu3.iq.FU_type_0::MemWrite 35412 15.54% 100.00% # Type of FU issued 2009system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 2010system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 2011system.cpu3.iq.FU_type_0::total 227862 # Type of FU issued 2012system.cpu3.iq.rate 1.405159 # Inst issue rate 2013system.cpu3.iq.fu_busy_cnt 340 # FU busy when requested 2014system.cpu3.iq.fu_busy_rate 0.001492 # FU busy rate (busy events/executed inst) 2015system.cpu3.iq.int_inst_queue_reads 616290 # Number of integer instruction queue reads 2016system.cpu3.iq.int_inst_queue_writes 245818 # Number of integer instruction queue writes 2017system.cpu3.iq.int_inst_queue_wakeup_accesses 226322 # Number of integer instruction queue wakeup accesses 2018system.cpu3.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads 2019system.cpu3.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes 2020system.cpu3.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses 2021system.cpu3.iq.int_alu_accesses 228202 # Number of integer alu accesses 2022system.cpu3.iq.fp_alu_accesses 0 # Number of floating point alu accesses 2023system.cpu3.iew.lsq.thread0.forwLoads 30727 # Number of loads that had data forwarded from stores 2024system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 2025system.cpu3.iew.lsq.thread0.squashedLoads 2667 # Number of loads squashed 2026system.cpu3.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed 2027system.cpu3.iew.lsq.thread0.memOrderViolation 37 # Number of memory ordering violations 2028system.cpu3.iew.lsq.thread0.squashedStores 1566 # Number of stores squashed 2029system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 2030system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 2031system.cpu3.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 2032system.cpu3.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked 2033system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle 2034system.cpu3.iew.iewSquashCycles 1361 # Number of cycles IEW is squashing 2035system.cpu3.iew.iewBlockCycles 7576 # Number of cycles IEW is blocking 2036system.cpu3.iew.iewUnblockCycles 66 # Number of cycles IEW is unblocking 2037system.cpu3.iew.iewDispatchedInsts 269910 # Number of instructions dispatched to IQ 2038system.cpu3.iew.iewDispSquashedInsts 166 # Number of squashed instructions skipped by dispatch 2039system.cpu3.iew.iewDispLoadInsts 76309 # Number of dispatched load instructions 2040system.cpu3.iew.iewDispStoreInsts 36069 # Number of dispatched store instructions 2041system.cpu3.iew.iewDispNonSpecInsts 1148 # Number of dispatched non-speculative instructions 2042system.cpu3.iew.iewIQFullEvents 41 # Number of times the IQ has become full, causing a stall 2043system.cpu3.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 2044system.cpu3.iew.memOrderViolationEvents 37 # Number of memory order violations 2045system.cpu3.iew.predictedTakenIncorrect 452 # Number of branches that were predicted taken incorrectly 2046system.cpu3.iew.predictedNotTakenIncorrect 1067 # Number of branches that were predicted not taken incorrectly 2047system.cpu3.iew.branchMispredicts 1519 # Number of branch mispredicts detected at execute 2048system.cpu3.iew.iewExecutedInsts 226838 # Number of executed instructions 2049system.cpu3.iew.iewExecLoadInsts 75201 # Number of load instructions executed 2050system.cpu3.iew.iewExecSquashedInsts 1024 # Number of squashed instructions skipped in execute 2051system.cpu3.iew.exec_swp 0 # number of swp insts executed 2052system.cpu3.iew.exec_nop 37293 # number of nop insts executed 2053system.cpu3.iew.exec_refs 110524 # number of memory reference insts executed 2054system.cpu3.iew.exec_branches 46686 # Number of branches executed 2055system.cpu3.iew.exec_stores 35323 # Number of stores executed 2056system.cpu3.iew.exec_rate 1.398844 # Inst execution rate 2057system.cpu3.iew.wb_sent 226605 # cumulative count of insts sent to commit 2058system.cpu3.iew.wb_count 226322 # cumulative count of insts written-back 2059system.cpu3.iew.wb_producers 128132 # num instructions producing a value 2060system.cpu3.iew.wb_consumers 134738 # num instructions consuming a value 2061system.cpu3.iew.wb_rate 1.395662 # insts written-back per cycle 2062system.cpu3.iew.wb_fanout 0.950972 # average fanout of values written-back 2063system.cpu3.commit.commitSquashedInsts 13998 # The number of squashed insts skipped by commit 2064system.cpu3.commit.commitNonSpecStalls 5876 # The number of times commit has been forced to stall to communicate backwards 2065system.cpu3.commit.branchMispredicts 1284 # The number of times a branch was mispredicted 2066system.cpu3.commit.committed_per_cycle::samples 157615 # Number of insts commited each cycle 2067system.cpu3.commit.committed_per_cycle::mean 1.623367 # Number of insts commited each cycle 2068system.cpu3.commit.committed_per_cycle::stdev 2.050526 # Number of insts commited each cycle 2069system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 2070system.cpu3.commit.committed_per_cycle::0 67043 42.54% 42.54% # Number of insts commited each cycle 2071system.cpu3.commit.committed_per_cycle::1 43238 27.43% 69.97% # Number of insts commited each cycle 2072system.cpu3.commit.committed_per_cycle::2 5262 3.34% 73.31% # Number of insts commited each cycle 2073system.cpu3.commit.committed_per_cycle::3 6673 4.23% 77.54% # Number of insts commited each cycle 2074system.cpu3.commit.committed_per_cycle::4 1534 0.97% 78.51% # Number of insts commited each cycle 2075system.cpu3.commit.committed_per_cycle::5 30788 19.53% 98.05% # Number of insts commited each cycle 2076system.cpu3.commit.committed_per_cycle::6 827 0.52% 98.57% # Number of insts commited each cycle 2077system.cpu3.commit.committed_per_cycle::7 952 0.60% 99.18% # Number of insts commited each cycle 2078system.cpu3.commit.committed_per_cycle::8 1298 0.82% 100.00% # Number of insts commited each cycle 2079system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 2080system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 2081system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 2082system.cpu3.commit.committed_per_cycle::total 157615 # Number of insts commited each cycle 2083system.cpu3.commit.committedInsts 255867 # Number of instructions committed 2084system.cpu3.commit.committedOps 255867 # Number of ops (including micro ops) committed 2085system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed 2086system.cpu3.commit.refs 108145 # Number of memory references committed 2087system.cpu3.commit.loads 73642 # Number of loads committed 2088system.cpu3.commit.membars 5159 # Number of memory barriers committed 2089system.cpu3.commit.branches 45627 # Number of branches committed 2090system.cpu3.commit.fp_insts 0 # Number of committed floating point instructions. 2091system.cpu3.commit.int_insts 175889 # Number of committed integer instructions. 2092system.cpu3.commit.function_calls 322 # Number of function calls committed. 2093system.cpu3.commit.op_class_0::No_OpClass 36414 14.23% 14.23% # Class of committed instruction 2094system.cpu3.commit.op_class_0::IntAlu 106149 41.49% 55.72% # Class of committed instruction 2095system.cpu3.commit.op_class_0::IntMult 0 0.00% 55.72% # Class of committed instruction 2096system.cpu3.commit.op_class_0::IntDiv 0 0.00% 55.72% # Class of committed instruction 2097system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 55.72% # Class of committed instruction 2098system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 55.72% # Class of committed instruction 2099system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 55.72% # Class of committed instruction 2100system.cpu3.commit.op_class_0::FloatMult 0 0.00% 55.72% # Class of committed instruction 2101system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 55.72% # Class of committed instruction 2102system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 55.72% # Class of committed instruction 2103system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 55.72% # Class of committed instruction 2104system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 55.72% # Class of committed instruction 2105system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 55.72% # Class of committed instruction 2106system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 55.72% # Class of committed instruction 2107system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 55.72% # Class of committed instruction 2108system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 55.72% # Class of committed instruction 2109system.cpu3.commit.op_class_0::SimdMult 0 0.00% 55.72% # Class of committed instruction 2110system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 55.72% # Class of committed instruction 2111system.cpu3.commit.op_class_0::SimdShift 0 0.00% 55.72% # Class of committed instruction 2112system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 55.72% # Class of committed instruction 2113system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 55.72% # Class of committed instruction 2114system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 55.72% # Class of committed instruction 2115system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 55.72% # Class of committed instruction 2116system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 55.72% # Class of committed instruction 2117system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 55.72% # Class of committed instruction 2118system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 55.72% # Class of committed instruction 2119system.cpu3.commit.op_class_0::SimdFloatMisc 0 0.00% 55.72% # Class of committed instruction 2120system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 55.72% # Class of committed instruction 2121system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.72% # Class of committed instruction 2122system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.72% # Class of committed instruction 2123system.cpu3.commit.op_class_0::MemRead 78801 30.80% 86.52% # Class of committed instruction 2124system.cpu3.commit.op_class_0::MemWrite 34503 13.48% 100.00% # Class of committed instruction 2125system.cpu3.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 2126system.cpu3.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 2127system.cpu3.commit.op_class_0::total 255867 # Class of committed instruction 2128system.cpu3.commit.bw_lim_events 1298 # number cycles where commit BW limit reached 2129system.cpu3.rob.rob_reads 425596 # The number of ROB reads 2130system.cpu3.rob.rob_writes 542328 # The number of ROB writes 2131system.cpu3.timesIdled 209 # Number of times that the entire CPU went into an idle state and unscheduled itself 2132system.cpu3.idleCycles 1948 # Total number of cycles that the CPU has spent unscheduled due to idling 2133system.cpu3.quiesceCycles 46007 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 2134system.cpu3.committedInsts 214294 # Number of Instructions Simulated 2135system.cpu3.committedOps 214294 # Number of Ops (including micro ops) Simulated 2136system.cpu3.cpi 0.756722 # CPI: Cycles Per Instruction 2137system.cpu3.cpi_total 0.756722 # CPI: Total CPI of All Threads 2138system.cpu3.ipc 1.321489 # IPC: Instructions Per Cycle 2139system.cpu3.ipc_total 1.321489 # IPC: Total IPC of All Threads 2140system.cpu3.int_regfile_reads 391365 # number of integer regfile reads 2141system.cpu3.int_regfile_writes 183208 # number of integer regfile writes 2142system.cpu3.fp_regfile_writes 64 # number of floating regfile writes 2143system.cpu3.misc_regfile_reads 112150 # number of misc regfile reads 2144system.cpu3.misc_regfile_writes 648 # number of misc regfile writes 2145system.cpu3.dcache.tags.replacements 0 # number of replacements 2146system.cpu3.dcache.tags.tagsinuse 24.277315 # Cycle average of tags in use 2147system.cpu3.dcache.tags.total_refs 40522 # Total number of references to valid blocks. 2148system.cpu3.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks. 2149system.cpu3.dcache.tags.avg_refs 1447.214286 # Average number of references to valid blocks. 2150system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 2151system.cpu3.dcache.tags.occ_blocks::cpu3.data 24.277315 # Average occupied blocks per requestor 2152system.cpu3.dcache.tags.occ_percent::cpu3.data 0.047417 # Average percentage of cache occupancy 2153system.cpu3.dcache.tags.occ_percent::total 0.047417 # Average percentage of cache occupancy 2154system.cpu3.dcache.tags.occ_task_id_blocks::1024 28 # Occupied blocks per task id 2155system.cpu3.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id 2156system.cpu3.dcache.tags.occ_task_id_percent::1024 0.054688 # Percentage of cache occupancy per task id 2157system.cpu3.dcache.tags.tag_accesses 316074 # Number of tag accesses 2158system.cpu3.dcache.tags.data_accesses 316074 # Number of data accesses 2159system.cpu3.dcache.ReadReq_hits::cpu3.data 43937 # number of ReadReq hits 2160system.cpu3.dcache.ReadReq_hits::total 43937 # number of ReadReq hits 2161system.cpu3.dcache.WriteReq_hits::cpu3.data 34273 # number of WriteReq hits 2162system.cpu3.dcache.WriteReq_hits::total 34273 # number of WriteReq hits 2163system.cpu3.dcache.SwapReq_hits::cpu3.data 14 # number of SwapReq hits 2164system.cpu3.dcache.SwapReq_hits::total 14 # number of SwapReq hits 2165system.cpu3.dcache.demand_hits::cpu3.data 78210 # number of demand (read+write) hits 2166system.cpu3.dcache.demand_hits::total 78210 # number of demand (read+write) hits 2167system.cpu3.dcache.overall_hits::cpu3.data 78210 # number of overall hits 2168system.cpu3.dcache.overall_hits::total 78210 # number of overall hits 2169system.cpu3.dcache.ReadReq_misses::cpu3.data 514 # number of ReadReq misses 2170system.cpu3.dcache.ReadReq_misses::total 514 # number of ReadReq misses 2171system.cpu3.dcache.WriteReq_misses::cpu3.data 159 # number of WriteReq misses 2172system.cpu3.dcache.WriteReq_misses::total 159 # number of WriteReq misses 2173system.cpu3.dcache.SwapReq_misses::cpu3.data 57 # number of SwapReq misses 2174system.cpu3.dcache.SwapReq_misses::total 57 # number of SwapReq misses 2175system.cpu3.dcache.demand_misses::cpu3.data 673 # number of demand (read+write) misses 2176system.cpu3.dcache.demand_misses::total 673 # number of demand (read+write) misses 2177system.cpu3.dcache.overall_misses::cpu3.data 673 # number of overall misses 2178system.cpu3.dcache.overall_misses::total 673 # number of overall misses 2179system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 9349000 # number of ReadReq miss cycles 2180system.cpu3.dcache.ReadReq_miss_latency::total 9349000 # number of ReadReq miss cycles 2181system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 3790500 # number of WriteReq miss cycles 2182system.cpu3.dcache.WriteReq_miss_latency::total 3790500 # number of WriteReq miss cycles 2183system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 680500 # number of SwapReq miss cycles 2184system.cpu3.dcache.SwapReq_miss_latency::total 680500 # number of SwapReq miss cycles 2185system.cpu3.dcache.demand_miss_latency::cpu3.data 13139500 # number of demand (read+write) miss cycles 2186system.cpu3.dcache.demand_miss_latency::total 13139500 # number of demand (read+write) miss cycles 2187system.cpu3.dcache.overall_miss_latency::cpu3.data 13139500 # number of overall miss cycles 2188system.cpu3.dcache.overall_miss_latency::total 13139500 # number of overall miss cycles 2189system.cpu3.dcache.ReadReq_accesses::cpu3.data 44451 # number of ReadReq accesses(hits+misses) 2190system.cpu3.dcache.ReadReq_accesses::total 44451 # number of ReadReq accesses(hits+misses) 2191system.cpu3.dcache.WriteReq_accesses::cpu3.data 34432 # number of WriteReq accesses(hits+misses) 2192system.cpu3.dcache.WriteReq_accesses::total 34432 # number of WriteReq accesses(hits+misses) 2193system.cpu3.dcache.SwapReq_accesses::cpu3.data 71 # number of SwapReq accesses(hits+misses) 2194system.cpu3.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses) 2195system.cpu3.dcache.demand_accesses::cpu3.data 78883 # number of demand (read+write) accesses 2196system.cpu3.dcache.demand_accesses::total 78883 # number of demand (read+write) accesses 2197system.cpu3.dcache.overall_accesses::cpu3.data 78883 # number of overall (read+write) accesses 2198system.cpu3.dcache.overall_accesses::total 78883 # number of overall (read+write) accesses 2199system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.011563 # miss rate for ReadReq accesses 2200system.cpu3.dcache.ReadReq_miss_rate::total 0.011563 # miss rate for ReadReq accesses 2201system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.004618 # miss rate for WriteReq accesses 2202system.cpu3.dcache.WriteReq_miss_rate::total 0.004618 # miss rate for WriteReq accesses 2203system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.802817 # miss rate for SwapReq accesses 2204system.cpu3.dcache.SwapReq_miss_rate::total 0.802817 # miss rate for SwapReq accesses 2205system.cpu3.dcache.demand_miss_rate::cpu3.data 0.008532 # miss rate for demand accesses 2206system.cpu3.dcache.demand_miss_rate::total 0.008532 # miss rate for demand accesses 2207system.cpu3.dcache.overall_miss_rate::cpu3.data 0.008532 # miss rate for overall accesses 2208system.cpu3.dcache.overall_miss_rate::total 0.008532 # miss rate for overall accesses 2209system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 18188.715953 # average ReadReq miss latency 2210system.cpu3.dcache.ReadReq_avg_miss_latency::total 18188.715953 # average ReadReq miss latency 2211system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 23839.622642 # average WriteReq miss latency 2212system.cpu3.dcache.WriteReq_avg_miss_latency::total 23839.622642 # average WriteReq miss latency 2213system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 11938.596491 # average SwapReq miss latency 2214system.cpu3.dcache.SwapReq_avg_miss_latency::total 11938.596491 # average SwapReq miss latency 2215system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 19523.774146 # average overall miss latency 2216system.cpu3.dcache.demand_avg_miss_latency::total 19523.774146 # average overall miss latency 2217system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 19523.774146 # average overall miss latency 2218system.cpu3.dcache.overall_avg_miss_latency::total 19523.774146 # average overall miss latency 2219system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2220system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2221system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 2222system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked 2223system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2224system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2225system.cpu3.dcache.fast_writes 0 # number of fast writes performed 2226system.cpu3.dcache.cache_copies 0 # number of cache copies performed 2227system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 347 # number of ReadReq MSHR hits 2228system.cpu3.dcache.ReadReq_mshr_hits::total 347 # number of ReadReq MSHR hits 2229system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 52 # number of WriteReq MSHR hits 2230system.cpu3.dcache.WriteReq_mshr_hits::total 52 # number of WriteReq MSHR hits 2231system.cpu3.dcache.demand_mshr_hits::cpu3.data 399 # number of demand (read+write) MSHR hits 2232system.cpu3.dcache.demand_mshr_hits::total 399 # number of demand (read+write) MSHR hits 2233system.cpu3.dcache.overall_mshr_hits::cpu3.data 399 # number of overall MSHR hits 2234system.cpu3.dcache.overall_mshr_hits::total 399 # number of overall MSHR hits 2235system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 167 # number of ReadReq MSHR misses 2236system.cpu3.dcache.ReadReq_mshr_misses::total 167 # number of ReadReq MSHR misses 2237system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 107 # number of WriteReq MSHR misses 2238system.cpu3.dcache.WriteReq_mshr_misses::total 107 # number of WriteReq MSHR misses 2239system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 57 # number of SwapReq MSHR misses 2240system.cpu3.dcache.SwapReq_mshr_misses::total 57 # number of SwapReq MSHR misses 2241system.cpu3.dcache.demand_mshr_misses::cpu3.data 274 # number of demand (read+write) MSHR misses 2242system.cpu3.dcache.demand_mshr_misses::total 274 # number of demand (read+write) MSHR misses 2243system.cpu3.dcache.overall_mshr_misses::cpu3.data 274 # number of overall MSHR misses 2244system.cpu3.dcache.overall_mshr_misses::total 274 # number of overall MSHR misses 2245system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1719000 # number of ReadReq MSHR miss cycles 2246system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1719000 # number of ReadReq MSHR miss cycles 2247system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 2129500 # number of WriteReq MSHR miss cycles 2248system.cpu3.dcache.WriteReq_mshr_miss_latency::total 2129500 # number of WriteReq MSHR miss cycles 2249system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 623500 # number of SwapReq MSHR miss cycles 2250system.cpu3.dcache.SwapReq_mshr_miss_latency::total 623500 # number of SwapReq MSHR miss cycles 2251system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 3848500 # number of demand (read+write) MSHR miss cycles 2252system.cpu3.dcache.demand_mshr_miss_latency::total 3848500 # number of demand (read+write) MSHR miss cycles 2253system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 3848500 # number of overall MSHR miss cycles 2254system.cpu3.dcache.overall_mshr_miss_latency::total 3848500 # number of overall MSHR miss cycles 2255system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003757 # mshr miss rate for ReadReq accesses 2256system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003757 # mshr miss rate for ReadReq accesses 2257system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.003108 # mshr miss rate for WriteReq accesses 2258system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.003108 # mshr miss rate for WriteReq accesses 2259system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.802817 # mshr miss rate for SwapReq accesses 2260system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.802817 # mshr miss rate for SwapReq accesses 2261system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.003473 # mshr miss rate for demand accesses 2262system.cpu3.dcache.demand_mshr_miss_rate::total 0.003473 # mshr miss rate for demand accesses 2263system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.003473 # mshr miss rate for overall accesses 2264system.cpu3.dcache.overall_mshr_miss_rate::total 0.003473 # mshr miss rate for overall accesses 2265system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 10293.413174 # average ReadReq mshr miss latency 2266system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 10293.413174 # average ReadReq mshr miss latency 2267system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 19901.869159 # average WriteReq mshr miss latency 2268system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 19901.869159 # average WriteReq mshr miss latency 2269system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 10938.596491 # average SwapReq mshr miss latency 2270system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 10938.596491 # average SwapReq mshr miss latency 2271system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 14045.620438 # average overall mshr miss latency 2272system.cpu3.dcache.demand_avg_mshr_miss_latency::total 14045.620438 # average overall mshr miss latency 2273system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 14045.620438 # average overall mshr miss latency 2274system.cpu3.dcache.overall_avg_mshr_miss_latency::total 14045.620438 # average overall mshr miss latency 2275system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 2276system.cpu3.icache.tags.replacements 384 # number of replacements 2277system.cpu3.icache.tags.tagsinuse 81.046367 # Cycle average of tags in use 2278system.cpu3.icache.tags.total_refs 21310 # Total number of references to valid blocks. 2279system.cpu3.icache.tags.sampled_refs 498 # Sample count of references to valid blocks. 2280system.cpu3.icache.tags.avg_refs 42.791165 # Average number of references to valid blocks. 2281system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 2282system.cpu3.icache.tags.occ_blocks::cpu3.inst 81.046367 # Average occupied blocks per requestor 2283system.cpu3.icache.tags.occ_percent::cpu3.inst 0.158294 # Average percentage of cache occupancy 2284system.cpu3.icache.tags.occ_percent::total 0.158294 # Average percentage of cache occupancy 2285system.cpu3.icache.tags.occ_task_id_blocks::1024 114 # Occupied blocks per task id 2286system.cpu3.icache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id 2287system.cpu3.icache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id 2288system.cpu3.icache.tags.occ_task_id_percent::1024 0.222656 # Percentage of cache occupancy per task id 2289system.cpu3.icache.tags.tag_accesses 22380 # Number of tag accesses 2290system.cpu3.icache.tags.data_accesses 22380 # Number of data accesses 2291system.cpu3.icache.ReadReq_hits::cpu3.inst 21310 # number of ReadReq hits 2292system.cpu3.icache.ReadReq_hits::total 21310 # number of ReadReq hits 2293system.cpu3.icache.demand_hits::cpu3.inst 21310 # number of demand (read+write) hits 2294system.cpu3.icache.demand_hits::total 21310 # number of demand (read+write) hits 2295system.cpu3.icache.overall_hits::cpu3.inst 21310 # number of overall hits 2296system.cpu3.icache.overall_hits::total 21310 # number of overall hits 2297system.cpu3.icache.ReadReq_misses::cpu3.inst 572 # number of ReadReq misses 2298system.cpu3.icache.ReadReq_misses::total 572 # number of ReadReq misses 2299system.cpu3.icache.demand_misses::cpu3.inst 572 # number of demand (read+write) misses 2300system.cpu3.icache.demand_misses::total 572 # number of demand (read+write) misses 2301system.cpu3.icache.overall_misses::cpu3.inst 572 # number of overall misses 2302system.cpu3.icache.overall_misses::total 572 # number of overall misses 2303system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 8104500 # number of ReadReq miss cycles 2304system.cpu3.icache.ReadReq_miss_latency::total 8104500 # number of ReadReq miss cycles 2305system.cpu3.icache.demand_miss_latency::cpu3.inst 8104500 # number of demand (read+write) miss cycles 2306system.cpu3.icache.demand_miss_latency::total 8104500 # number of demand (read+write) miss cycles 2307system.cpu3.icache.overall_miss_latency::cpu3.inst 8104500 # number of overall miss cycles 2308system.cpu3.icache.overall_miss_latency::total 8104500 # number of overall miss cycles 2309system.cpu3.icache.ReadReq_accesses::cpu3.inst 21882 # number of ReadReq accesses(hits+misses) 2310system.cpu3.icache.ReadReq_accesses::total 21882 # number of ReadReq accesses(hits+misses) 2311system.cpu3.icache.demand_accesses::cpu3.inst 21882 # number of demand (read+write) accesses 2312system.cpu3.icache.demand_accesses::total 21882 # number of demand (read+write) accesses 2313system.cpu3.icache.overall_accesses::cpu3.inst 21882 # number of overall (read+write) accesses 2314system.cpu3.icache.overall_accesses::total 21882 # number of overall (read+write) accesses 2315system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.026140 # miss rate for ReadReq accesses 2316system.cpu3.icache.ReadReq_miss_rate::total 0.026140 # miss rate for ReadReq accesses 2317system.cpu3.icache.demand_miss_rate::cpu3.inst 0.026140 # miss rate for demand accesses 2318system.cpu3.icache.demand_miss_rate::total 0.026140 # miss rate for demand accesses 2319system.cpu3.icache.overall_miss_rate::cpu3.inst 0.026140 # miss rate for overall accesses 2320system.cpu3.icache.overall_miss_rate::total 0.026140 # miss rate for overall accesses 2321system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 14168.706294 # average ReadReq miss latency 2322system.cpu3.icache.ReadReq_avg_miss_latency::total 14168.706294 # average ReadReq miss latency 2323system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 14168.706294 # average overall miss latency 2324system.cpu3.icache.demand_avg_miss_latency::total 14168.706294 # average overall miss latency 2325system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 14168.706294 # average overall miss latency 2326system.cpu3.icache.overall_avg_miss_latency::total 14168.706294 # average overall miss latency 2327system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2328system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2329system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked 2330system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked 2331system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2332system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2333system.cpu3.icache.fast_writes 0 # number of fast writes performed 2334system.cpu3.icache.cache_copies 0 # number of cache copies performed 2335system.cpu3.icache.writebacks::writebacks 384 # number of writebacks 2336system.cpu3.icache.writebacks::total 384 # number of writebacks 2337system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 74 # number of ReadReq MSHR hits 2338system.cpu3.icache.ReadReq_mshr_hits::total 74 # number of ReadReq MSHR hits 2339system.cpu3.icache.demand_mshr_hits::cpu3.inst 74 # number of demand (read+write) MSHR hits 2340system.cpu3.icache.demand_mshr_hits::total 74 # number of demand (read+write) MSHR hits 2341system.cpu3.icache.overall_mshr_hits::cpu3.inst 74 # number of overall MSHR hits 2342system.cpu3.icache.overall_mshr_hits::total 74 # number of overall MSHR hits 2343system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 498 # number of ReadReq MSHR misses 2344system.cpu3.icache.ReadReq_mshr_misses::total 498 # number of ReadReq MSHR misses 2345system.cpu3.icache.demand_mshr_misses::cpu3.inst 498 # number of demand (read+write) MSHR misses 2346system.cpu3.icache.demand_mshr_misses::total 498 # number of demand (read+write) MSHR misses 2347system.cpu3.icache.overall_mshr_misses::cpu3.inst 498 # number of overall MSHR misses 2348system.cpu3.icache.overall_mshr_misses::total 498 # number of overall MSHR misses 2349system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 6912000 # number of ReadReq MSHR miss cycles 2350system.cpu3.icache.ReadReq_mshr_miss_latency::total 6912000 # number of ReadReq MSHR miss cycles 2351system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 6912000 # number of demand (read+write) MSHR miss cycles 2352system.cpu3.icache.demand_mshr_miss_latency::total 6912000 # number of demand (read+write) MSHR miss cycles 2353system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 6912000 # number of overall MSHR miss cycles 2354system.cpu3.icache.overall_mshr_miss_latency::total 6912000 # number of overall MSHR miss cycles 2355system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.022758 # mshr miss rate for ReadReq accesses 2356system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.022758 # mshr miss rate for ReadReq accesses 2357system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.022758 # mshr miss rate for demand accesses 2358system.cpu3.icache.demand_mshr_miss_rate::total 0.022758 # mshr miss rate for demand accesses 2359system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.022758 # mshr miss rate for overall accesses 2360system.cpu3.icache.overall_mshr_miss_rate::total 0.022758 # mshr miss rate for overall accesses 2361system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 13879.518072 # average ReadReq mshr miss latency 2362system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 13879.518072 # average ReadReq mshr miss latency 2363system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 13879.518072 # average overall mshr miss latency 2364system.cpu3.icache.demand_avg_mshr_miss_latency::total 13879.518072 # average overall mshr miss latency 2365system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 13879.518072 # average overall mshr miss latency 2366system.cpu3.icache.overall_avg_mshr_miss_latency::total 13879.518072 # average overall mshr miss latency 2367system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate 2368system.l2c.tags.replacements 0 # number of replacements 2369system.l2c.tags.tagsinuse 419.218954 # Cycle average of tags in use 2370system.l2c.tags.total_refs 2347 # Total number of references to valid blocks. 2371system.l2c.tags.sampled_refs 532 # Sample count of references to valid blocks. 2372system.l2c.tags.avg_refs 4.411654 # Average number of references to valid blocks. 2373system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 2374system.l2c.tags.occ_blocks::writebacks 0.788461 # Average occupied blocks per requestor 2375system.l2c.tags.occ_blocks::cpu0.inst 288.048945 # Average occupied blocks per requestor 2376system.l2c.tags.occ_blocks::cpu0.data 58.083381 # Average occupied blocks per requestor 2377system.l2c.tags.occ_blocks::cpu1.inst 60.484959 # Average occupied blocks per requestor 2378system.l2c.tags.occ_blocks::cpu1.data 5.324168 # Average occupied blocks per requestor 2379system.l2c.tags.occ_blocks::cpu2.inst 2.350458 # Average occupied blocks per requestor 2380system.l2c.tags.occ_blocks::cpu2.data 0.677584 # Average occupied blocks per requestor 2381system.l2c.tags.occ_blocks::cpu3.inst 2.742702 # Average occupied blocks per requestor 2382system.l2c.tags.occ_blocks::cpu3.data 0.718294 # Average occupied blocks per requestor 2383system.l2c.tags.occ_percent::writebacks 0.000012 # Average percentage of cache occupancy 2384system.l2c.tags.occ_percent::cpu0.inst 0.004395 # Average percentage of cache occupancy 2385system.l2c.tags.occ_percent::cpu0.data 0.000886 # Average percentage of cache occupancy 2386system.l2c.tags.occ_percent::cpu1.inst 0.000923 # Average percentage of cache occupancy 2387system.l2c.tags.occ_percent::cpu1.data 0.000081 # Average percentage of cache occupancy 2388system.l2c.tags.occ_percent::cpu2.inst 0.000036 # Average percentage of cache occupancy 2389system.l2c.tags.occ_percent::cpu2.data 0.000010 # Average percentage of cache occupancy 2390system.l2c.tags.occ_percent::cpu3.inst 0.000042 # Average percentage of cache occupancy 2391system.l2c.tags.occ_percent::cpu3.data 0.000011 # Average percentage of cache occupancy 2392system.l2c.tags.occ_percent::total 0.006397 # Average percentage of cache occupancy 2393system.l2c.tags.occ_task_id_blocks::1024 532 # Occupied blocks per task id 2394system.l2c.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id 2395system.l2c.tags.age_task_id_blocks_1024::1 340 # Occupied blocks per task id 2396system.l2c.tags.age_task_id_blocks_1024::2 141 # Occupied blocks per task id 2397system.l2c.tags.occ_task_id_percent::1024 0.008118 # Percentage of cache occupancy per task id 2398system.l2c.tags.tag_accesses 25618 # Number of tag accesses 2399system.l2c.tags.data_accesses 25618 # Number of data accesses 2400system.l2c.WritebackDirty_hits::writebacks 1 # number of WritebackDirty hits 2401system.l2c.WritebackDirty_hits::total 1 # number of WritebackDirty hits 2402system.l2c.WritebackClean_hits::writebacks 676 # number of WritebackClean hits 2403system.l2c.WritebackClean_hits::total 676 # number of WritebackClean hits 2404system.l2c.UpgradeReq_hits::cpu0.data 3 # number of UpgradeReq hits 2405system.l2c.UpgradeReq_hits::total 3 # number of UpgradeReq hits 2406system.l2c.ReadCleanReq_hits::cpu0.inst 246 # number of ReadCleanReq hits 2407system.l2c.ReadCleanReq_hits::cpu1.inst 412 # number of ReadCleanReq hits 2408system.l2c.ReadCleanReq_hits::cpu2.inst 491 # number of ReadCleanReq hits 2409system.l2c.ReadCleanReq_hits::cpu3.inst 489 # number of ReadCleanReq hits 2410system.l2c.ReadCleanReq_hits::total 1638 # number of ReadCleanReq hits 2411system.l2c.ReadSharedReq_hits::cpu0.data 5 # number of ReadSharedReq hits 2412system.l2c.ReadSharedReq_hits::cpu1.data 5 # number of ReadSharedReq hits 2413system.l2c.ReadSharedReq_hits::cpu2.data 11 # number of ReadSharedReq hits 2414system.l2c.ReadSharedReq_hits::cpu3.data 11 # number of ReadSharedReq hits 2415system.l2c.ReadSharedReq_hits::total 32 # number of ReadSharedReq hits 2416system.l2c.demand_hits::cpu0.inst 246 # number of demand (read+write) hits 2417system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits 2418system.l2c.demand_hits::cpu1.inst 412 # number of demand (read+write) hits 2419system.l2c.demand_hits::cpu1.data 5 # number of demand (read+write) hits 2420system.l2c.demand_hits::cpu2.inst 491 # number of demand (read+write) hits 2421system.l2c.demand_hits::cpu2.data 11 # number of demand (read+write) hits 2422system.l2c.demand_hits::cpu3.inst 489 # number of demand (read+write) hits 2423system.l2c.demand_hits::cpu3.data 11 # number of demand (read+write) hits 2424system.l2c.demand_hits::total 1670 # number of demand (read+write) hits 2425system.l2c.overall_hits::cpu0.inst 246 # number of overall hits 2426system.l2c.overall_hits::cpu0.data 5 # number of overall hits 2427system.l2c.overall_hits::cpu1.inst 412 # number of overall hits 2428system.l2c.overall_hits::cpu1.data 5 # number of overall hits 2429system.l2c.overall_hits::cpu2.inst 491 # number of overall hits 2430system.l2c.overall_hits::cpu2.data 11 # number of overall hits 2431system.l2c.overall_hits::cpu3.inst 489 # number of overall hits 2432system.l2c.overall_hits::cpu3.data 11 # number of overall hits 2433system.l2c.overall_hits::total 1670 # number of overall hits 2434system.l2c.UpgradeReq_misses::cpu0.data 27 # number of UpgradeReq misses 2435system.l2c.UpgradeReq_misses::cpu1.data 20 # number of UpgradeReq misses 2436system.l2c.UpgradeReq_misses::cpu2.data 21 # number of UpgradeReq misses 2437system.l2c.UpgradeReq_misses::cpu3.data 21 # number of UpgradeReq misses 2438system.l2c.UpgradeReq_misses::total 89 # number of UpgradeReq misses 2439system.l2c.ReadExReq_misses::cpu0.data 94 # number of ReadExReq misses 2440system.l2c.ReadExReq_misses::cpu1.data 13 # number of ReadExReq misses 2441system.l2c.ReadExReq_misses::cpu2.data 12 # number of ReadExReq misses 2442system.l2c.ReadExReq_misses::cpu3.data 12 # number of ReadExReq misses 2443system.l2c.ReadExReq_misses::total 131 # number of ReadExReq misses 2444system.l2c.ReadCleanReq_misses::cpu0.inst 362 # number of ReadCleanReq misses 2445system.l2c.ReadCleanReq_misses::cpu1.inst 84 # number of ReadCleanReq misses 2446system.l2c.ReadCleanReq_misses::cpu2.inst 9 # number of ReadCleanReq misses 2447system.l2c.ReadCleanReq_misses::cpu3.inst 9 # number of ReadCleanReq misses 2448system.l2c.ReadCleanReq_misses::total 464 # number of ReadCleanReq misses 2449system.l2c.ReadSharedReq_misses::cpu0.data 75 # number of ReadSharedReq misses 2450system.l2c.ReadSharedReq_misses::cpu1.data 7 # number of ReadSharedReq misses 2451system.l2c.ReadSharedReq_misses::cpu2.data 1 # number of ReadSharedReq misses 2452system.l2c.ReadSharedReq_misses::cpu3.data 1 # number of ReadSharedReq misses 2453system.l2c.ReadSharedReq_misses::total 84 # number of ReadSharedReq misses 2454system.l2c.demand_misses::cpu0.inst 362 # number of demand (read+write) misses 2455system.l2c.demand_misses::cpu0.data 169 # number of demand (read+write) misses 2456system.l2c.demand_misses::cpu1.inst 84 # number of demand (read+write) misses 2457system.l2c.demand_misses::cpu1.data 20 # number of demand (read+write) misses 2458system.l2c.demand_misses::cpu2.inst 9 # number of demand (read+write) misses 2459system.l2c.demand_misses::cpu2.data 13 # number of demand (read+write) misses 2460system.l2c.demand_misses::cpu3.inst 9 # number of demand (read+write) misses 2461system.l2c.demand_misses::cpu3.data 13 # number of demand (read+write) misses 2462system.l2c.demand_misses::total 679 # number of demand (read+write) misses 2463system.l2c.overall_misses::cpu0.inst 362 # number of overall misses 2464system.l2c.overall_misses::cpu0.data 169 # number of overall misses 2465system.l2c.overall_misses::cpu1.inst 84 # number of overall misses 2466system.l2c.overall_misses::cpu1.data 20 # number of overall misses 2467system.l2c.overall_misses::cpu2.inst 9 # number of overall misses 2468system.l2c.overall_misses::cpu2.data 13 # number of overall misses 2469system.l2c.overall_misses::cpu3.inst 9 # number of overall misses 2470system.l2c.overall_misses::cpu3.data 13 # number of overall misses 2471system.l2c.overall_misses::total 679 # number of overall misses 2472system.l2c.ReadExReq_miss_latency::cpu0.data 7611000 # number of ReadExReq miss cycles 2473system.l2c.ReadExReq_miss_latency::cpu1.data 1059000 # number of ReadExReq miss cycles 2474system.l2c.ReadExReq_miss_latency::cpu2.data 1210500 # number of ReadExReq miss cycles 2475system.l2c.ReadExReq_miss_latency::cpu3.data 1399000 # number of ReadExReq miss cycles 2476system.l2c.ReadExReq_miss_latency::total 11279500 # number of ReadExReq miss cycles 2477system.l2c.ReadCleanReq_miss_latency::cpu0.inst 27676500 # number of ReadCleanReq miss cycles 2478system.l2c.ReadCleanReq_miss_latency::cpu1.inst 6293000 # number of ReadCleanReq miss cycles 2479system.l2c.ReadCleanReq_miss_latency::cpu2.inst 614000 # number of ReadCleanReq miss cycles 2480system.l2c.ReadCleanReq_miss_latency::cpu3.inst 660000 # number of ReadCleanReq miss cycles 2481system.l2c.ReadCleanReq_miss_latency::total 35243500 # number of ReadCleanReq miss cycles 2482system.l2c.ReadSharedReq_miss_latency::cpu0.data 5981500 # number of ReadSharedReq miss cycles 2483system.l2c.ReadSharedReq_miss_latency::cpu1.data 540000 # number of ReadSharedReq miss cycles 2484system.l2c.ReadSharedReq_miss_latency::cpu2.data 82500 # number of ReadSharedReq miss cycles 2485system.l2c.ReadSharedReq_miss_latency::cpu3.data 96500 # number of ReadSharedReq miss cycles 2486system.l2c.ReadSharedReq_miss_latency::total 6700500 # number of ReadSharedReq miss cycles 2487system.l2c.demand_miss_latency::cpu0.inst 27676500 # number of demand (read+write) miss cycles 2488system.l2c.demand_miss_latency::cpu0.data 13592500 # number of demand (read+write) miss cycles 2489system.l2c.demand_miss_latency::cpu1.inst 6293000 # number of demand (read+write) miss cycles 2490system.l2c.demand_miss_latency::cpu1.data 1599000 # number of demand (read+write) miss cycles 2491system.l2c.demand_miss_latency::cpu2.inst 614000 # number of demand (read+write) miss cycles 2492system.l2c.demand_miss_latency::cpu2.data 1293000 # number of demand (read+write) miss cycles 2493system.l2c.demand_miss_latency::cpu3.inst 660000 # number of demand (read+write) miss cycles 2494system.l2c.demand_miss_latency::cpu3.data 1495500 # number of demand (read+write) miss cycles 2495system.l2c.demand_miss_latency::total 53223500 # number of demand (read+write) miss cycles 2496system.l2c.overall_miss_latency::cpu0.inst 27676500 # number of overall miss cycles 2497system.l2c.overall_miss_latency::cpu0.data 13592500 # number of overall miss cycles 2498system.l2c.overall_miss_latency::cpu1.inst 6293000 # number of overall miss cycles 2499system.l2c.overall_miss_latency::cpu1.data 1599000 # number of overall miss cycles 2500system.l2c.overall_miss_latency::cpu2.inst 614000 # number of overall miss cycles 2501system.l2c.overall_miss_latency::cpu2.data 1293000 # number of overall miss cycles 2502system.l2c.overall_miss_latency::cpu3.inst 660000 # number of overall miss cycles 2503system.l2c.overall_miss_latency::cpu3.data 1495500 # number of overall miss cycles 2504system.l2c.overall_miss_latency::total 53223500 # number of overall miss cycles 2505system.l2c.WritebackDirty_accesses::writebacks 1 # number of WritebackDirty accesses(hits+misses) 2506system.l2c.WritebackDirty_accesses::total 1 # number of WritebackDirty accesses(hits+misses) 2507system.l2c.WritebackClean_accesses::writebacks 676 # number of WritebackClean accesses(hits+misses) 2508system.l2c.WritebackClean_accesses::total 676 # number of WritebackClean accesses(hits+misses) 2509system.l2c.UpgradeReq_accesses::cpu0.data 30 # number of UpgradeReq accesses(hits+misses) 2510system.l2c.UpgradeReq_accesses::cpu1.data 20 # number of UpgradeReq accesses(hits+misses) 2511system.l2c.UpgradeReq_accesses::cpu2.data 21 # number of UpgradeReq accesses(hits+misses) 2512system.l2c.UpgradeReq_accesses::cpu3.data 21 # number of UpgradeReq accesses(hits+misses) 2513system.l2c.UpgradeReq_accesses::total 92 # number of UpgradeReq accesses(hits+misses) 2514system.l2c.ReadExReq_accesses::cpu0.data 94 # number of ReadExReq accesses(hits+misses) 2515system.l2c.ReadExReq_accesses::cpu1.data 13 # number of ReadExReq accesses(hits+misses) 2516system.l2c.ReadExReq_accesses::cpu2.data 12 # number of ReadExReq accesses(hits+misses) 2517system.l2c.ReadExReq_accesses::cpu3.data 12 # number of ReadExReq accesses(hits+misses) 2518system.l2c.ReadExReq_accesses::total 131 # number of ReadExReq accesses(hits+misses) 2519system.l2c.ReadCleanReq_accesses::cpu0.inst 608 # number of ReadCleanReq accesses(hits+misses) 2520system.l2c.ReadCleanReq_accesses::cpu1.inst 496 # number of ReadCleanReq accesses(hits+misses) 2521system.l2c.ReadCleanReq_accesses::cpu2.inst 500 # number of ReadCleanReq accesses(hits+misses) 2522system.l2c.ReadCleanReq_accesses::cpu3.inst 498 # number of ReadCleanReq accesses(hits+misses) 2523system.l2c.ReadCleanReq_accesses::total 2102 # number of ReadCleanReq accesses(hits+misses) 2524system.l2c.ReadSharedReq_accesses::cpu0.data 80 # number of ReadSharedReq accesses(hits+misses) 2525system.l2c.ReadSharedReq_accesses::cpu1.data 12 # number of ReadSharedReq accesses(hits+misses) 2526system.l2c.ReadSharedReq_accesses::cpu2.data 12 # number of ReadSharedReq accesses(hits+misses) 2527system.l2c.ReadSharedReq_accesses::cpu3.data 12 # number of ReadSharedReq accesses(hits+misses) 2528system.l2c.ReadSharedReq_accesses::total 116 # number of ReadSharedReq accesses(hits+misses) 2529system.l2c.demand_accesses::cpu0.inst 608 # number of demand (read+write) accesses 2530system.l2c.demand_accesses::cpu0.data 174 # number of demand (read+write) accesses 2531system.l2c.demand_accesses::cpu1.inst 496 # number of demand (read+write) accesses 2532system.l2c.demand_accesses::cpu1.data 25 # number of demand (read+write) accesses 2533system.l2c.demand_accesses::cpu2.inst 500 # number of demand (read+write) accesses 2534system.l2c.demand_accesses::cpu2.data 24 # number of demand (read+write) accesses 2535system.l2c.demand_accesses::cpu3.inst 498 # number of demand (read+write) accesses 2536system.l2c.demand_accesses::cpu3.data 24 # number of demand (read+write) accesses 2537system.l2c.demand_accesses::total 2349 # number of demand (read+write) accesses 2538system.l2c.overall_accesses::cpu0.inst 608 # number of overall (read+write) accesses 2539system.l2c.overall_accesses::cpu0.data 174 # number of overall (read+write) accesses 2540system.l2c.overall_accesses::cpu1.inst 496 # number of overall (read+write) accesses 2541system.l2c.overall_accesses::cpu1.data 25 # number of overall (read+write) accesses 2542system.l2c.overall_accesses::cpu2.inst 500 # number of overall (read+write) accesses 2543system.l2c.overall_accesses::cpu2.data 24 # number of overall (read+write) accesses 2544system.l2c.overall_accesses::cpu3.inst 498 # number of overall (read+write) accesses 2545system.l2c.overall_accesses::cpu3.data 24 # number of overall (read+write) accesses 2546system.l2c.overall_accesses::total 2349 # number of overall (read+write) accesses 2547system.l2c.UpgradeReq_miss_rate::cpu0.data 0.900000 # miss rate for UpgradeReq accesses 2548system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses 2549system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses 2550system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses 2551system.l2c.UpgradeReq_miss_rate::total 0.967391 # miss rate for UpgradeReq accesses 2552system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses 2553system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses 2554system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses 2555system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses 2556system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 2557system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.595395 # miss rate for ReadCleanReq accesses 2558system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.169355 # miss rate for ReadCleanReq accesses 2559system.l2c.ReadCleanReq_miss_rate::cpu2.inst 0.018000 # miss rate for ReadCleanReq accesses 2560system.l2c.ReadCleanReq_miss_rate::cpu3.inst 0.018072 # miss rate for ReadCleanReq accesses 2561system.l2c.ReadCleanReq_miss_rate::total 0.220742 # miss rate for ReadCleanReq accesses 2562system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.937500 # miss rate for ReadSharedReq accesses 2563system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.583333 # miss rate for ReadSharedReq accesses 2564system.l2c.ReadSharedReq_miss_rate::cpu2.data 0.083333 # miss rate for ReadSharedReq accesses 2565system.l2c.ReadSharedReq_miss_rate::cpu3.data 0.083333 # miss rate for ReadSharedReq accesses 2566system.l2c.ReadSharedReq_miss_rate::total 0.724138 # miss rate for ReadSharedReq accesses 2567system.l2c.demand_miss_rate::cpu0.inst 0.595395 # miss rate for demand accesses 2568system.l2c.demand_miss_rate::cpu0.data 0.971264 # miss rate for demand accesses 2569system.l2c.demand_miss_rate::cpu1.inst 0.169355 # miss rate for demand accesses 2570system.l2c.demand_miss_rate::cpu1.data 0.800000 # miss rate for demand accesses 2571system.l2c.demand_miss_rate::cpu2.inst 0.018000 # miss rate for demand accesses 2572system.l2c.demand_miss_rate::cpu2.data 0.541667 # miss rate for demand accesses 2573system.l2c.demand_miss_rate::cpu3.inst 0.018072 # miss rate for demand accesses 2574system.l2c.demand_miss_rate::cpu3.data 0.541667 # miss rate for demand accesses 2575system.l2c.demand_miss_rate::total 0.289059 # miss rate for demand accesses 2576system.l2c.overall_miss_rate::cpu0.inst 0.595395 # miss rate for overall accesses 2577system.l2c.overall_miss_rate::cpu0.data 0.971264 # miss rate for overall accesses 2578system.l2c.overall_miss_rate::cpu1.inst 0.169355 # miss rate for overall accesses 2579system.l2c.overall_miss_rate::cpu1.data 0.800000 # miss rate for overall accesses 2580system.l2c.overall_miss_rate::cpu2.inst 0.018000 # miss rate for overall accesses 2581system.l2c.overall_miss_rate::cpu2.data 0.541667 # miss rate for overall accesses 2582system.l2c.overall_miss_rate::cpu3.inst 0.018072 # miss rate for overall accesses 2583system.l2c.overall_miss_rate::cpu3.data 0.541667 # miss rate for overall accesses 2584system.l2c.overall_miss_rate::total 0.289059 # miss rate for overall accesses 2585system.l2c.ReadExReq_avg_miss_latency::cpu0.data 80968.085106 # average ReadExReq miss latency 2586system.l2c.ReadExReq_avg_miss_latency::cpu1.data 81461.538462 # average ReadExReq miss latency 2587system.l2c.ReadExReq_avg_miss_latency::cpu2.data 100875 # average ReadExReq miss latency 2588system.l2c.ReadExReq_avg_miss_latency::cpu3.data 116583.333333 # average ReadExReq miss latency 2589system.l2c.ReadExReq_avg_miss_latency::total 86103.053435 # average ReadExReq miss latency 2590system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 76454.419890 # average ReadCleanReq miss latency 2591system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 74916.666667 # average ReadCleanReq miss latency 2592system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 68222.222222 # average ReadCleanReq miss latency 2593system.l2c.ReadCleanReq_avg_miss_latency::cpu3.inst 73333.333333 # average ReadCleanReq miss latency 2594system.l2c.ReadCleanReq_avg_miss_latency::total 75955.818966 # average ReadCleanReq miss latency 2595system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 79753.333333 # average ReadSharedReq miss latency 2596system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 77142.857143 # average ReadSharedReq miss latency 2597system.l2c.ReadSharedReq_avg_miss_latency::cpu2.data 82500 # average ReadSharedReq miss latency 2598system.l2c.ReadSharedReq_avg_miss_latency::cpu3.data 96500 # average ReadSharedReq miss latency 2599system.l2c.ReadSharedReq_avg_miss_latency::total 79767.857143 # average ReadSharedReq miss latency 2600system.l2c.demand_avg_miss_latency::cpu0.inst 76454.419890 # average overall miss latency 2601system.l2c.demand_avg_miss_latency::cpu0.data 80428.994083 # average overall miss latency 2602system.l2c.demand_avg_miss_latency::cpu1.inst 74916.666667 # average overall miss latency 2603system.l2c.demand_avg_miss_latency::cpu1.data 79950 # average overall miss latency 2604system.l2c.demand_avg_miss_latency::cpu2.inst 68222.222222 # average overall miss latency 2605system.l2c.demand_avg_miss_latency::cpu2.data 99461.538462 # average overall miss latency 2606system.l2c.demand_avg_miss_latency::cpu3.inst 73333.333333 # average overall miss latency 2607system.l2c.demand_avg_miss_latency::cpu3.data 115038.461538 # average overall miss latency 2608system.l2c.demand_avg_miss_latency::total 78385.125184 # average overall miss latency 2609system.l2c.overall_avg_miss_latency::cpu0.inst 76454.419890 # average overall miss latency 2610system.l2c.overall_avg_miss_latency::cpu0.data 80428.994083 # average overall miss latency 2611system.l2c.overall_avg_miss_latency::cpu1.inst 74916.666667 # average overall miss latency 2612system.l2c.overall_avg_miss_latency::cpu1.data 79950 # average overall miss latency 2613system.l2c.overall_avg_miss_latency::cpu2.inst 68222.222222 # average overall miss latency 2614system.l2c.overall_avg_miss_latency::cpu2.data 99461.538462 # average overall miss latency 2615system.l2c.overall_avg_miss_latency::cpu3.inst 73333.333333 # average overall miss latency 2616system.l2c.overall_avg_miss_latency::cpu3.data 115038.461538 # average overall miss latency 2617system.l2c.overall_avg_miss_latency::total 78385.125184 # average overall miss latency 2618system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2619system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 2620system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 2621system.l2c.blocked::no_targets 0 # number of cycles access was blocked 2622system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2623system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2624system.l2c.fast_writes 0 # number of fast writes performed 2625system.l2c.cache_copies 0 # number of cache copies performed 2626system.l2c.ReadCleanReq_mshr_hits::cpu0.inst 1 # number of ReadCleanReq MSHR hits 2627system.l2c.ReadCleanReq_mshr_hits::cpu1.inst 4 # number of ReadCleanReq MSHR hits 2628system.l2c.ReadCleanReq_mshr_hits::cpu2.inst 6 # number of ReadCleanReq MSHR hits 2629system.l2c.ReadCleanReq_mshr_hits::cpu3.inst 2 # number of ReadCleanReq MSHR hits 2630system.l2c.ReadCleanReq_mshr_hits::total 13 # number of ReadCleanReq MSHR hits 2631system.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits 2632system.l2c.demand_mshr_hits::cpu1.inst 4 # number of demand (read+write) MSHR hits 2633system.l2c.demand_mshr_hits::cpu2.inst 6 # number of demand (read+write) MSHR hits 2634system.l2c.demand_mshr_hits::cpu3.inst 2 # number of demand (read+write) MSHR hits 2635system.l2c.demand_mshr_hits::total 13 # number of demand (read+write) MSHR hits 2636system.l2c.overall_mshr_hits::cpu0.inst 1 # number of overall MSHR hits 2637system.l2c.overall_mshr_hits::cpu1.inst 4 # number of overall MSHR hits 2638system.l2c.overall_mshr_hits::cpu2.inst 6 # number of overall MSHR hits 2639system.l2c.overall_mshr_hits::cpu3.inst 2 # number of overall MSHR hits 2640system.l2c.overall_mshr_hits::total 13 # number of overall MSHR hits 2641system.l2c.UpgradeReq_mshr_misses::cpu0.data 27 # number of UpgradeReq MSHR misses 2642system.l2c.UpgradeReq_mshr_misses::cpu1.data 20 # number of UpgradeReq MSHR misses 2643system.l2c.UpgradeReq_mshr_misses::cpu2.data 21 # number of UpgradeReq MSHR misses 2644system.l2c.UpgradeReq_mshr_misses::cpu3.data 21 # number of UpgradeReq MSHR misses 2645system.l2c.UpgradeReq_mshr_misses::total 89 # number of UpgradeReq MSHR misses 2646system.l2c.ReadExReq_mshr_misses::cpu0.data 94 # number of ReadExReq MSHR misses 2647system.l2c.ReadExReq_mshr_misses::cpu1.data 13 # number of ReadExReq MSHR misses 2648system.l2c.ReadExReq_mshr_misses::cpu2.data 12 # number of ReadExReq MSHR misses 2649system.l2c.ReadExReq_mshr_misses::cpu3.data 12 # number of ReadExReq MSHR misses 2650system.l2c.ReadExReq_mshr_misses::total 131 # number of ReadExReq MSHR misses 2651system.l2c.ReadCleanReq_mshr_misses::cpu0.inst 361 # number of ReadCleanReq MSHR misses 2652system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 80 # number of ReadCleanReq MSHR misses 2653system.l2c.ReadCleanReq_mshr_misses::cpu2.inst 3 # number of ReadCleanReq MSHR misses 2654system.l2c.ReadCleanReq_mshr_misses::cpu3.inst 7 # number of ReadCleanReq MSHR misses 2655system.l2c.ReadCleanReq_mshr_misses::total 451 # number of ReadCleanReq MSHR misses 2656system.l2c.ReadSharedReq_mshr_misses::cpu0.data 75 # number of ReadSharedReq MSHR misses 2657system.l2c.ReadSharedReq_mshr_misses::cpu1.data 7 # number of ReadSharedReq MSHR misses 2658system.l2c.ReadSharedReq_mshr_misses::cpu2.data 1 # number of ReadSharedReq MSHR misses 2659system.l2c.ReadSharedReq_mshr_misses::cpu3.data 1 # number of ReadSharedReq MSHR misses 2660system.l2c.ReadSharedReq_mshr_misses::total 84 # number of ReadSharedReq MSHR misses 2661system.l2c.demand_mshr_misses::cpu0.inst 361 # number of demand (read+write) MSHR misses 2662system.l2c.demand_mshr_misses::cpu0.data 169 # number of demand (read+write) MSHR misses 2663system.l2c.demand_mshr_misses::cpu1.inst 80 # number of demand (read+write) MSHR misses 2664system.l2c.demand_mshr_misses::cpu1.data 20 # number of demand (read+write) MSHR misses 2665system.l2c.demand_mshr_misses::cpu2.inst 3 # number of demand (read+write) MSHR misses 2666system.l2c.demand_mshr_misses::cpu2.data 13 # number of demand (read+write) MSHR misses 2667system.l2c.demand_mshr_misses::cpu3.inst 7 # number of demand (read+write) MSHR misses 2668system.l2c.demand_mshr_misses::cpu3.data 13 # number of demand (read+write) MSHR misses 2669system.l2c.demand_mshr_misses::total 666 # number of demand (read+write) MSHR misses 2670system.l2c.overall_mshr_misses::cpu0.inst 361 # number of overall MSHR misses 2671system.l2c.overall_mshr_misses::cpu0.data 169 # number of overall MSHR misses 2672system.l2c.overall_mshr_misses::cpu1.inst 80 # number of overall MSHR misses 2673system.l2c.overall_mshr_misses::cpu1.data 20 # number of overall MSHR misses 2674system.l2c.overall_mshr_misses::cpu2.inst 3 # number of overall MSHR misses 2675system.l2c.overall_mshr_misses::cpu2.data 13 # number of overall MSHR misses 2676system.l2c.overall_mshr_misses::cpu3.inst 7 # number of overall MSHR misses 2677system.l2c.overall_mshr_misses::cpu3.data 13 # number of overall MSHR misses 2678system.l2c.overall_mshr_misses::total 666 # number of overall MSHR misses 2679system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 587000 # number of UpgradeReq MSHR miss cycles 2680system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 437000 # number of UpgradeReq MSHR miss cycles 2681system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 459996 # number of UpgradeReq MSHR miss cycles 2682system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 457500 # number of UpgradeReq MSHR miss cycles 2683system.l2c.UpgradeReq_mshr_miss_latency::total 1941496 # number of UpgradeReq MSHR miss cycles 2684system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 6671000 # number of ReadExReq MSHR miss cycles 2685system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 929000 # number of ReadExReq MSHR miss cycles 2686system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 1090500 # number of ReadExReq MSHR miss cycles 2687system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 1279000 # number of ReadExReq MSHR miss cycles 2688system.l2c.ReadExReq_mshr_miss_latency::total 9969500 # number of ReadExReq MSHR miss cycles 2689system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst 23889000 # number of ReadCleanReq MSHR miss cycles 2690system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 5285500 # number of ReadCleanReq MSHR miss cycles 2691system.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst 219000 # number of ReadCleanReq MSHR miss cycles 2692system.l2c.ReadCleanReq_mshr_miss_latency::cpu3.inst 495500 # number of ReadCleanReq MSHR miss cycles 2693system.l2c.ReadCleanReq_mshr_miss_latency::total 29889000 # number of ReadCleanReq MSHR miss cycles 2694system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 5231500 # number of ReadSharedReq MSHR miss cycles 2695system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 470000 # number of ReadSharedReq MSHR miss cycles 2696system.l2c.ReadSharedReq_mshr_miss_latency::cpu2.data 72500 # number of ReadSharedReq MSHR miss cycles 2697system.l2c.ReadSharedReq_mshr_miss_latency::cpu3.data 86500 # number of ReadSharedReq MSHR miss cycles 2698system.l2c.ReadSharedReq_mshr_miss_latency::total 5860500 # number of ReadSharedReq MSHR miss cycles 2699system.l2c.demand_mshr_miss_latency::cpu0.inst 23889000 # number of demand (read+write) MSHR miss cycles 2700system.l2c.demand_mshr_miss_latency::cpu0.data 11902500 # number of demand (read+write) MSHR miss cycles 2701system.l2c.demand_mshr_miss_latency::cpu1.inst 5285500 # number of demand (read+write) MSHR miss cycles 2702system.l2c.demand_mshr_miss_latency::cpu1.data 1399000 # number of demand (read+write) MSHR miss cycles 2703system.l2c.demand_mshr_miss_latency::cpu2.inst 219000 # number of demand (read+write) MSHR miss cycles 2704system.l2c.demand_mshr_miss_latency::cpu2.data 1163000 # number of demand (read+write) MSHR miss cycles 2705system.l2c.demand_mshr_miss_latency::cpu3.inst 495500 # number of demand (read+write) MSHR miss cycles 2706system.l2c.demand_mshr_miss_latency::cpu3.data 1365500 # number of demand (read+write) MSHR miss cycles 2707system.l2c.demand_mshr_miss_latency::total 45719000 # number of demand (read+write) MSHR miss cycles 2708system.l2c.overall_mshr_miss_latency::cpu0.inst 23889000 # number of overall MSHR miss cycles 2709system.l2c.overall_mshr_miss_latency::cpu0.data 11902500 # number of overall MSHR miss cycles 2710system.l2c.overall_mshr_miss_latency::cpu1.inst 5285500 # number of overall MSHR miss cycles 2711system.l2c.overall_mshr_miss_latency::cpu1.data 1399000 # number of overall MSHR miss cycles 2712system.l2c.overall_mshr_miss_latency::cpu2.inst 219000 # number of overall MSHR miss cycles 2713system.l2c.overall_mshr_miss_latency::cpu2.data 1163000 # number of overall MSHR miss cycles 2714system.l2c.overall_mshr_miss_latency::cpu3.inst 495500 # number of overall MSHR miss cycles 2715system.l2c.overall_mshr_miss_latency::cpu3.data 1365500 # number of overall MSHR miss cycles 2716system.l2c.overall_mshr_miss_latency::total 45719000 # number of overall MSHR miss cycles 2717system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.900000 # mshr miss rate for UpgradeReq accesses 2718system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses 2719system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for UpgradeReq accesses 2720system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for UpgradeReq accesses 2721system.l2c.UpgradeReq_mshr_miss_rate::total 0.967391 # mshr miss rate for UpgradeReq accesses 2722system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses 2723system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses 2724system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses 2725system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for ReadExReq accesses 2726system.l2c.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 2727system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.593750 # mshr miss rate for ReadCleanReq accesses 2728system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.161290 # mshr miss rate for ReadCleanReq accesses 2729system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.006000 # mshr miss rate for ReadCleanReq accesses 2730system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst 0.014056 # mshr miss rate for ReadCleanReq accesses 2731system.l2c.ReadCleanReq_mshr_miss_rate::total 0.214558 # mshr miss rate for ReadCleanReq accesses 2732system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.937500 # mshr miss rate for ReadSharedReq accesses 2733system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.583333 # mshr miss rate for ReadSharedReq accesses 2734system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data 0.083333 # mshr miss rate for ReadSharedReq accesses 2735system.l2c.ReadSharedReq_mshr_miss_rate::cpu3.data 0.083333 # mshr miss rate for ReadSharedReq accesses 2736system.l2c.ReadSharedReq_mshr_miss_rate::total 0.724138 # mshr miss rate for ReadSharedReq accesses 2737system.l2c.demand_mshr_miss_rate::cpu0.inst 0.593750 # mshr miss rate for demand accesses 2738system.l2c.demand_mshr_miss_rate::cpu0.data 0.971264 # mshr miss rate for demand accesses 2739system.l2c.demand_mshr_miss_rate::cpu1.inst 0.161290 # mshr miss rate for demand accesses 2740system.l2c.demand_mshr_miss_rate::cpu1.data 0.800000 # mshr miss rate for demand accesses 2741system.l2c.demand_mshr_miss_rate::cpu2.inst 0.006000 # mshr miss rate for demand accesses 2742system.l2c.demand_mshr_miss_rate::cpu2.data 0.541667 # mshr miss rate for demand accesses 2743system.l2c.demand_mshr_miss_rate::cpu3.inst 0.014056 # mshr miss rate for demand accesses 2744system.l2c.demand_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for demand accesses 2745system.l2c.demand_mshr_miss_rate::total 0.283525 # mshr miss rate for demand accesses 2746system.l2c.overall_mshr_miss_rate::cpu0.inst 0.593750 # mshr miss rate for overall accesses 2747system.l2c.overall_mshr_miss_rate::cpu0.data 0.971264 # mshr miss rate for overall accesses 2748system.l2c.overall_mshr_miss_rate::cpu1.inst 0.161290 # mshr miss rate for overall accesses 2749system.l2c.overall_mshr_miss_rate::cpu1.data 0.800000 # mshr miss rate for overall accesses 2750system.l2c.overall_mshr_miss_rate::cpu2.inst 0.006000 # mshr miss rate for overall accesses 2751system.l2c.overall_mshr_miss_rate::cpu2.data 0.541667 # mshr miss rate for overall accesses 2752system.l2c.overall_mshr_miss_rate::cpu3.inst 0.014056 # mshr miss rate for overall accesses 2753system.l2c.overall_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for overall accesses 2754system.l2c.overall_mshr_miss_rate::total 0.283525 # mshr miss rate for overall accesses 2755system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 21740.740741 # average UpgradeReq mshr miss latency 2756system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 21850 # average UpgradeReq mshr miss latency 2757system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 21904.571429 # average UpgradeReq mshr miss latency 2758system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 21785.714286 # average UpgradeReq mshr miss latency 2759system.l2c.UpgradeReq_avg_mshr_miss_latency::total 21814.561798 # average UpgradeReq mshr miss latency 2760system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 70968.085106 # average ReadExReq mshr miss latency 2761system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 71461.538462 # average ReadExReq mshr miss latency 2762system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 90875 # average ReadExReq mshr miss latency 2763system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 106583.333333 # average ReadExReq mshr miss latency 2764system.l2c.ReadExReq_avg_mshr_miss_latency::total 76103.053435 # average ReadExReq mshr miss latency 2765system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 66174.515235 # average ReadCleanReq mshr miss latency 2766system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 66068.750000 # average ReadCleanReq mshr miss latency 2767system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 73000 # average ReadCleanReq mshr miss latency 2768system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 70785.714286 # average ReadCleanReq mshr miss latency 2769system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 66272.727273 # average ReadCleanReq mshr miss latency 2770system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 69753.333333 # average ReadSharedReq mshr miss latency 2771system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 67142.857143 # average ReadSharedReq mshr miss latency 2772system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 72500 # average ReadSharedReq mshr miss latency 2773system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 86500 # average ReadSharedReq mshr miss latency 2774system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 69767.857143 # average ReadSharedReq mshr miss latency 2775system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 66174.515235 # average overall mshr miss latency 2776system.l2c.demand_avg_mshr_miss_latency::cpu0.data 70428.994083 # average overall mshr miss latency 2777system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 66068.750000 # average overall mshr miss latency 2778system.l2c.demand_avg_mshr_miss_latency::cpu1.data 69950 # average overall mshr miss latency 2779system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 73000 # average overall mshr miss latency 2780system.l2c.demand_avg_mshr_miss_latency::cpu2.data 89461.538462 # average overall mshr miss latency 2781system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 70785.714286 # average overall mshr miss latency 2782system.l2c.demand_avg_mshr_miss_latency::cpu3.data 105038.461538 # average overall mshr miss latency 2783system.l2c.demand_avg_mshr_miss_latency::total 68647.147147 # average overall mshr miss latency 2784system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 66174.515235 # average overall mshr miss latency 2785system.l2c.overall_avg_mshr_miss_latency::cpu0.data 70428.994083 # average overall mshr miss latency 2786system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 66068.750000 # average overall mshr miss latency 2787system.l2c.overall_avg_mshr_miss_latency::cpu1.data 69950 # average overall mshr miss latency 2788system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 73000 # average overall mshr miss latency 2789system.l2c.overall_avg_mshr_miss_latency::cpu2.data 89461.538462 # average overall mshr miss latency 2790system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 70785.714286 # average overall mshr miss latency 2791system.l2c.overall_avg_mshr_miss_latency::cpu3.data 105038.461538 # average overall mshr miss latency 2792system.l2c.overall_avg_mshr_miss_latency::total 68647.147147 # average overall mshr miss latency 2793system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 2794system.membus.trans_dist::ReadResp 534 # Transaction distribution 2795system.membus.trans_dist::UpgradeReq 290 # Transaction distribution 2796system.membus.trans_dist::UpgradeResp 89 # Transaction distribution 2797system.membus.trans_dist::ReadExReq 162 # Transaction distribution 2798system.membus.trans_dist::ReadExResp 131 # Transaction distribution 2799system.membus.trans_dist::ReadSharedReq 535 # Transaction distribution 2800system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1741 # Packet count per connected master and slave (bytes) 2801system.membus.pkt_count::total 1741 # Packet count per connected master and slave (bytes) 2802system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 42560 # Cumulative packet size per connected master and slave (bytes) 2803system.membus.pkt_size::total 42560 # Cumulative packet size per connected master and slave (bytes) 2804system.membus.snoops 232 # Total snoops (count) 2805system.membus.snoop_fanout::samples 987 # Request fanout histogram 2806system.membus.snoop_fanout::mean 0 # Request fanout histogram 2807system.membus.snoop_fanout::stdev 0 # Request fanout histogram 2808system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2809system.membus.snoop_fanout::0 987 100.00% 100.00% # Request fanout histogram 2810system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 2811system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2812system.membus.snoop_fanout::min_value 0 # Request fanout histogram 2813system.membus.snoop_fanout::max_value 0 # Request fanout histogram 2814system.membus.snoop_fanout::total 987 # Request fanout histogram 2815system.membus.reqLayer0.occupancy 936504 # Layer occupancy (ticks) 2816system.membus.reqLayer0.utilization 0.9 # Layer utilization (%) 2817system.membus.respLayer1.occupancy 3712661 # Layer occupancy (ticks) 2818system.membus.respLayer1.utilization 3.4 # Layer utilization (%) 2819system.toL2Bus.snoop_filter.tot_requests 4933 # Total number of requests made to the snoop filter. 2820system.toL2Bus.snoop_filter.hit_single_requests 1339 # Number of requests hitting in the snoop filter with a single holder of the requested data. 2821system.toL2Bus.snoop_filter.hit_multi_requests 2364 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 2822system.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 2823system.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 2824system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 2825system.toL2Bus.trans_dist::ReadResp 2778 # Transaction distribution 2826system.toL2Bus.trans_dist::WritebackDirty 1 # Transaction distribution 2827system.toL2Bus.trans_dist::WritebackClean 676 # Transaction distribution 2828system.toL2Bus.trans_dist::CleanEvict 1 # Transaction distribution 2829system.toL2Bus.trans_dist::UpgradeReq 293 # Transaction distribution 2830system.toL2Bus.trans_dist::UpgradeResp 293 # Transaction distribution 2831system.toL2Bus.trans_dist::ReadExReq 391 # Transaction distribution 2832system.toL2Bus.trans_dist::ReadExResp 391 # Transaction distribution 2833system.toL2Bus.trans_dist::ReadCleanReq 2102 # Transaction distribution 2834system.toL2Bus.trans_dist::ReadSharedReq 677 # Transaction distribution 2835system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1448 # Packet count per connected master and slave (bytes) 2836system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 592 # Packet count per connected master and slave (bytes) 2837system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1140 # Packet count per connected master and slave (bytes) 2838system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 374 # Packet count per connected master and slave (bytes) 2839system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 1151 # Packet count per connected master and slave (bytes) 2840system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 360 # Packet count per connected master and slave (bytes) 2841system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 1140 # Packet count per connected master and slave (bytes) 2842system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 376 # Packet count per connected master and slave (bytes) 2843system.toL2Bus.pkt_count::total 6581 # Packet count per connected master and slave (bytes) 2844system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 53760 # Cumulative packet size per connected master and slave (bytes) 2845system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 11200 # Cumulative packet size per connected master and slave (bytes) 2846system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 41216 # Cumulative packet size per connected master and slave (bytes) 2847system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes) 2848system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 41664 # Cumulative packet size per connected master and slave (bytes) 2849system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 1536 # Cumulative packet size per connected master and slave (bytes) 2850system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 41088 # Cumulative packet size per connected master and slave (bytes) 2851system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 1536 # Cumulative packet size per connected master and slave (bytes) 2852system.toL2Bus.pkt_size::total 193600 # Cumulative packet size per connected master and slave (bytes) 2853system.toL2Bus.snoops 1022 # Total snoops (count) 2854system.toL2Bus.snoop_fanout::samples 3463 # Request fanout histogram 2855system.toL2Bus.snoop_fanout::mean 1.289633 # Request fanout histogram 2856system.toL2Bus.snoop_fanout::stdev 1.182691 # Request fanout histogram 2857system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2858system.toL2Bus.snoop_fanout::0 1230 35.52% 35.52% # Request fanout histogram 2859system.toL2Bus.snoop_fanout::1 835 24.11% 59.63% # Request fanout histogram 2860system.toL2Bus.snoop_fanout::2 563 16.26% 75.89% # Request fanout histogram 2861system.toL2Bus.snoop_fanout::3 835 24.11% 100.00% # Request fanout histogram 2862system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram 2863system.toL2Bus.snoop_fanout::5 0 0.00% 100.00% # Request fanout histogram 2864system.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram 2865system.toL2Bus.snoop_fanout::7 0 0.00% 100.00% # Request fanout histogram 2866system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram 2867system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2868system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 2869system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram 2870system.toL2Bus.snoop_fanout::total 3463 # Request fanout histogram 2871system.toL2Bus.reqLayer0.occupancy 3953462 # Layer occupancy (ticks) 2872system.toL2Bus.reqLayer0.utilization 3.7 # Layer utilization (%) 2873system.toL2Bus.respLayer0.occupancy 911498 # Layer occupancy (ticks) 2874system.toL2Bus.respLayer0.utilization 0.8 # Layer utilization (%) 2875system.toL2Bus.respLayer1.occupancy 505495 # Layer occupancy (ticks) 2876system.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) 2877system.toL2Bus.respLayer2.occupancy 746495 # Layer occupancy (ticks) 2878system.toL2Bus.respLayer2.utilization 0.7 # Layer utilization (%) 2879system.toL2Bus.respLayer3.occupancy 439455 # Layer occupancy (ticks) 2880system.toL2Bus.respLayer3.utilization 0.4 # Layer utilization (%) 2881system.toL2Bus.respLayer4.occupancy 752991 # Layer occupancy (ticks) 2882system.toL2Bus.respLayer4.utilization 0.7 # Layer utilization (%) 2883system.toL2Bus.respLayer5.occupancy 419474 # Layer occupancy (ticks) 2884system.toL2Bus.respLayer5.utilization 0.4 # Layer utilization (%) 2885system.toL2Bus.respLayer6.occupancy 747998 # Layer occupancy (ticks) 2886system.toL2Bus.respLayer6.utilization 0.7 # Layer utilization (%) 2887system.toL2Bus.respLayer7.occupancy 434475 # Layer occupancy (ticks) 2888system.toL2Bus.respLayer7.utilization 0.4 # Layer utilization (%) 2889 2890---------- End Simulation Statistics ---------- 2891