stats.txt revision 10892:bd37e25fb3b7
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000108 # Number of seconds simulated 4sim_ticks 107900000 # Number of ticks simulated 5final_tick 107900000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 161691 # Simulator instruction rate (inst/s) 8host_op_rate 161690 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 17527940 # Simulator tick rate (ticks/s) 10host_mem_usage 308804 # Number of bytes of host memory used 11host_seconds 6.16 # Real time elapsed on the host 12sim_insts 995346 # Number of instructions simulated 13sim_ops 995346 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu0.inst 23168 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.data 10816 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu1.inst 5440 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu1.data 1280 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu2.data 832 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu3.inst 576 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu3.data 832 # Number of bytes read from this memory 23system.physmem.bytes_read::total 42944 # Number of bytes read from this memory 24system.physmem.bytes_inst_read::cpu0.inst 23168 # Number of instructions bytes read from this memory 25system.physmem.bytes_inst_read::cpu1.inst 5440 # Number of instructions bytes read from this memory 26system.physmem.bytes_inst_read::cpu3.inst 576 # Number of instructions bytes read from this memory 27system.physmem.bytes_inst_read::total 29184 # Number of instructions bytes read from this memory 28system.physmem.num_reads::cpu0.inst 362 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu0.data 169 # Number of read requests responded to by this memory 30system.physmem.num_reads::cpu1.inst 85 # Number of read requests responded to by this memory 31system.physmem.num_reads::cpu1.data 20 # Number of read requests responded to by this memory 32system.physmem.num_reads::cpu2.data 13 # Number of read requests responded to by this memory 33system.physmem.num_reads::cpu3.inst 9 # Number of read requests responded to by this memory 34system.physmem.num_reads::cpu3.data 13 # Number of read requests responded to by this memory 35system.physmem.num_reads::total 671 # Number of read requests responded to by this memory 36system.physmem.bw_read::cpu0.inst 214717331 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::cpu0.data 100240964 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu1.inst 50417053 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::cpu1.data 11862836 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::cpu2.data 7710843 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::cpu3.inst 5338276 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_read::cpu3.data 7710843 # Total read bandwidth from this memory (bytes/s) 43system.physmem.bw_read::total 397998146 # Total read bandwidth from this memory (bytes/s) 44system.physmem.bw_inst_read::cpu0.inst 214717331 # Instruction read bandwidth from this memory (bytes/s) 45system.physmem.bw_inst_read::cpu1.inst 50417053 # Instruction read bandwidth from this memory (bytes/s) 46system.physmem.bw_inst_read::cpu3.inst 5338276 # Instruction read bandwidth from this memory (bytes/s) 47system.physmem.bw_inst_read::total 270472660 # Instruction read bandwidth from this memory (bytes/s) 48system.physmem.bw_total::cpu0.inst 214717331 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu0.data 100240964 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu1.inst 50417053 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::cpu1.data 11862836 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::cpu2.data 7710843 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.bw_total::cpu3.inst 5338276 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.bw_total::cpu3.data 7710843 # Total bandwidth to/from this memory (bytes/s) 55system.physmem.bw_total::total 397998146 # Total bandwidth to/from this memory (bytes/s) 56system.physmem.readReqs 672 # Number of read requests accepted 57system.physmem.writeReqs 0 # Number of write requests accepted 58system.physmem.readBursts 672 # Number of DRAM read bursts, including those serviced by the write queue 59system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 60system.physmem.bytesReadDRAM 43008 # Total number of bytes read from DRAM 61system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 62system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 63system.physmem.bytesReadSys 43008 # Total read bytes from the system interface side 64system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 65system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 66system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 67system.physmem.neitherReadNorWriteReqs 75 # Number of requests that are neither read nor write 68system.physmem.perBankRdBursts::0 114 # Per bank write bursts 69system.physmem.perBankRdBursts::1 42 # Per bank write bursts 70system.physmem.perBankRdBursts::2 30 # Per bank write bursts 71system.physmem.perBankRdBursts::3 60 # Per bank write bursts 72system.physmem.perBankRdBursts::4 66 # Per bank write bursts 73system.physmem.perBankRdBursts::5 28 # Per bank write bursts 74system.physmem.perBankRdBursts::6 18 # Per bank write bursts 75system.physmem.perBankRdBursts::7 24 # Per bank write bursts 76system.physmem.perBankRdBursts::8 7 # Per bank write bursts 77system.physmem.perBankRdBursts::9 29 # Per bank write bursts 78system.physmem.perBankRdBursts::10 23 # Per bank write bursts 79system.physmem.perBankRdBursts::11 14 # Per bank write bursts 80system.physmem.perBankRdBursts::12 65 # Per bank write bursts 81system.physmem.perBankRdBursts::13 38 # Per bank write bursts 82system.physmem.perBankRdBursts::14 17 # Per bank write bursts 83system.physmem.perBankRdBursts::15 97 # Per bank write bursts 84system.physmem.perBankWrBursts::0 0 # Per bank write bursts 85system.physmem.perBankWrBursts::1 0 # Per bank write bursts 86system.physmem.perBankWrBursts::2 0 # Per bank write bursts 87system.physmem.perBankWrBursts::3 0 # Per bank write bursts 88system.physmem.perBankWrBursts::4 0 # Per bank write bursts 89system.physmem.perBankWrBursts::5 0 # Per bank write bursts 90system.physmem.perBankWrBursts::6 0 # Per bank write bursts 91system.physmem.perBankWrBursts::7 0 # Per bank write bursts 92system.physmem.perBankWrBursts::8 0 # Per bank write bursts 93system.physmem.perBankWrBursts::9 0 # Per bank write bursts 94system.physmem.perBankWrBursts::10 0 # Per bank write bursts 95system.physmem.perBankWrBursts::11 0 # Per bank write bursts 96system.physmem.perBankWrBursts::12 0 # Per bank write bursts 97system.physmem.perBankWrBursts::13 0 # Per bank write bursts 98system.physmem.perBankWrBursts::14 0 # Per bank write bursts 99system.physmem.perBankWrBursts::15 0 # Per bank write bursts 100system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 101system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 102system.physmem.totGap 107872000 # Total gap between requests 103system.physmem.readPktSize::0 0 # Read request sizes (log2) 104system.physmem.readPktSize::1 0 # Read request sizes (log2) 105system.physmem.readPktSize::2 0 # Read request sizes (log2) 106system.physmem.readPktSize::3 0 # Read request sizes (log2) 107system.physmem.readPktSize::4 0 # Read request sizes (log2) 108system.physmem.readPktSize::5 0 # Read request sizes (log2) 109system.physmem.readPktSize::6 672 # Read request sizes (log2) 110system.physmem.writePktSize::0 0 # Write request sizes (log2) 111system.physmem.writePktSize::1 0 # Write request sizes (log2) 112system.physmem.writePktSize::2 0 # Write request sizes (log2) 113system.physmem.writePktSize::3 0 # Write request sizes (log2) 114system.physmem.writePktSize::4 0 # Write request sizes (log2) 115system.physmem.writePktSize::5 0 # Write request sizes (log2) 116system.physmem.writePktSize::6 0 # Write request sizes (log2) 117system.physmem.rdQLenPdf::0 402 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::1 188 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::2 59 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::3 18 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 149system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 213system.physmem.bytesPerActivate::samples 149 # Bytes accessed per row activation 214system.physmem.bytesPerActivate::mean 269.744966 # Bytes accessed per row activation 215system.physmem.bytesPerActivate::gmean 188.953250 # Bytes accessed per row activation 216system.physmem.bytesPerActivate::stdev 233.682770 # Bytes accessed per row activation 217system.physmem.bytesPerActivate::0-127 43 28.86% 28.86% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::128-255 40 26.85% 55.70% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::256-383 25 16.78% 72.48% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::384-511 17 11.41% 83.89% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::512-639 8 5.37% 89.26% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::640-767 7 4.70% 93.96% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::768-895 4 2.68% 96.64% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::896-1023 2 1.34% 97.99% # Bytes accessed per row activation 225system.physmem.bytesPerActivate::1024-1151 3 2.01% 100.00% # Bytes accessed per row activation 226system.physmem.bytesPerActivate::total 149 # Bytes accessed per row activation 227system.physmem.totQLat 7242000 # Total ticks spent queuing 228system.physmem.totMemAccLat 19842000 # Total ticks spent from burst creation until serviced by the DRAM 229system.physmem.totBusLat 3360000 # Total ticks spent in databus transfers 230system.physmem.avgQLat 10776.79 # Average queueing delay per DRAM burst 231system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 232system.physmem.avgMemAccLat 29526.79 # Average memory access latency per DRAM burst 233system.physmem.avgRdBW 398.59 # Average DRAM read bandwidth in MiByte/s 234system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 235system.physmem.avgRdBWSys 398.59 # Average system read bandwidth in MiByte/s 236system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 237system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 238system.physmem.busUtil 3.11 # Data bus utilization in percentage 239system.physmem.busUtilRead 3.11 # Data bus utilization in percentage for reads 240system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 241system.physmem.avgRdQLen 1.38 # Average read queue length when enqueuing 242system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 243system.physmem.readRowHits 512 # Number of row buffer hits during reads 244system.physmem.writeRowHits 0 # Number of row buffer hits during writes 245system.physmem.readRowHitRate 76.19 # Row buffer hit rate for reads 246system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 247system.physmem.avgGap 160523.81 # Average gap between requests 248system.physmem.pageHitRate 76.19 # Row buffer hit rate, read and write combined 249system.physmem_0.actEnergy 710640 # Energy for activate commands per rank (pJ) 250system.physmem_0.preEnergy 387750 # Energy for precharge commands per rank (pJ) 251system.physmem_0.readEnergy 2776800 # Energy for read commands per rank (pJ) 252system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 253system.physmem_0.refreshEnergy 6611280 # Energy for refresh commands per rank (pJ) 254system.physmem_0.actBackEnergy 34825860 # Energy for active background per rank (pJ) 255system.physmem_0.preBackEnergy 30339750 # Energy for precharge background per rank (pJ) 256system.physmem_0.totalEnergy 75652080 # Total energy per rank (pJ) 257system.physmem_0.averagePower 745.478401 # Core power per rank (mW) 258system.physmem_0.memoryStateTime::IDLE 52910500 # Time in different power states 259system.physmem_0.memoryStateTime::REF 3380000 # Time in different power states 260system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 261system.physmem_0.memoryStateTime::ACT 47852500 # Time in different power states 262system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 263system.physmem_1.actEnergy 385560 # Energy for activate commands per rank (pJ) 264system.physmem_1.preEnergy 210375 # Energy for precharge commands per rank (pJ) 265system.physmem_1.readEnergy 2067000 # Energy for read commands per rank (pJ) 266system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 267system.physmem_1.refreshEnergy 6611280 # Energy for refresh commands per rank (pJ) 268system.physmem_1.actBackEnergy 31297275 # Energy for active background per rank (pJ) 269system.physmem_1.preBackEnergy 33426750 # Energy for precharge background per rank (pJ) 270system.physmem_1.totalEnergy 73998240 # Total energy per rank (pJ) 271system.physmem_1.averagePower 729.280213 # Core power per rank (mW) 272system.physmem_1.memoryStateTime::IDLE 59054500 # Time in different power states 273system.physmem_1.memoryStateTime::REF 3380000 # Time in different power states 274system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 275system.physmem_1.memoryStateTime::ACT 42666000 # Time in different power states 276system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 277system.cpu0.branchPred.lookups 81516 # Number of BP lookups 278system.cpu0.branchPred.condPredicted 78639 # Number of conditional branches predicted 279system.cpu0.branchPred.condIncorrect 1206 # Number of conditional branches incorrect 280system.cpu0.branchPred.BTBLookups 78220 # Number of BTB lookups 281system.cpu0.branchPred.BTBHits 75547 # Number of BTB hits 282system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 283system.cpu0.branchPred.BTBHitPct 96.582715 # BTB Hit Percentage 284system.cpu0.branchPred.usedRAS 751 # Number of times the RAS was used to get a target. 285system.cpu0.branchPred.RASInCorrect 128 # Number of incorrect RAS predictions. 286system.cpu_clk_domain.clock 500 # Clock period in ticks 287system.cpu0.workload.num_syscalls 89 # Number of system calls 288system.cpu0.numCycles 215801 # number of cpu cycles simulated 289system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 290system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 291system.cpu0.fetch.icacheStallCycles 19984 # Number of cycles fetch is stalled on an Icache miss 292system.cpu0.fetch.Insts 481810 # Number of instructions fetch has processed 293system.cpu0.fetch.Branches 81516 # Number of branches that fetch encountered 294system.cpu0.fetch.predictedBranches 76298 # Number of branches that fetch has predicted taken 295system.cpu0.fetch.Cycles 165347 # Number of cycles fetch has run and was not squashing or blocked 296system.cpu0.fetch.SquashCycles 2711 # Number of cycles fetch has spent squashing 297system.cpu0.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 298system.cpu0.fetch.PendingTrapStallCycles 2206 # Number of stall cycles due to pending traps 299system.cpu0.fetch.CacheLines 7238 # Number of cache lines fetched 300system.cpu0.fetch.IcacheSquashes 649 # Number of outstanding Icache misses that were squashed 301system.cpu0.fetch.rateDist::samples 188895 # Number of instructions fetched each cycle (Total) 302system.cpu0.fetch.rateDist::mean 2.550676 # Number of instructions fetched each cycle (Total) 303system.cpu0.fetch.rateDist::stdev 2.226315 # Number of instructions fetched each cycle (Total) 304system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 305system.cpu0.fetch.rateDist::0 31263 16.55% 16.55% # Number of instructions fetched each cycle (Total) 306system.cpu0.fetch.rateDist::1 77878 41.23% 57.78% # Number of instructions fetched each cycle (Total) 307system.cpu0.fetch.rateDist::2 817 0.43% 58.21% # Number of instructions fetched each cycle (Total) 308system.cpu0.fetch.rateDist::3 1146 0.61% 58.82% # Number of instructions fetched each cycle (Total) 309system.cpu0.fetch.rateDist::4 622 0.33% 59.15% # Number of instructions fetched each cycle (Total) 310system.cpu0.fetch.rateDist::5 73043 38.67% 97.82% # Number of instructions fetched each cycle (Total) 311system.cpu0.fetch.rateDist::6 702 0.37% 98.19% # Number of instructions fetched each cycle (Total) 312system.cpu0.fetch.rateDist::7 447 0.24% 98.42% # Number of instructions fetched each cycle (Total) 313system.cpu0.fetch.rateDist::8 2977 1.58% 100.00% # Number of instructions fetched each cycle (Total) 314system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 315system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 316system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 317system.cpu0.fetch.rateDist::total 188895 # Number of instructions fetched each cycle (Total) 318system.cpu0.fetch.branchRate 0.377737 # Number of branch fetches per cycle 319system.cpu0.fetch.rate 2.232659 # Number of inst fetches per cycle 320system.cpu0.decode.IdleCycles 15795 # Number of cycles decode is idle 321system.cpu0.decode.BlockedCycles 18848 # Number of cycles decode is blocked 322system.cpu0.decode.RunCycles 152228 # Number of cycles decode is running 323system.cpu0.decode.UnblockCycles 669 # Number of cycles decode is unblocking 324system.cpu0.decode.SquashCycles 1355 # Number of cycles decode is squashing 325system.cpu0.decode.DecodedInsts 470263 # Number of instructions handled by decode 326system.cpu0.rename.SquashCycles 1355 # Number of cycles rename is squashing 327system.cpu0.rename.IdleCycles 16424 # Number of cycles rename is idle 328system.cpu0.rename.BlockCycles 2157 # Number of cycles rename is blocking 329system.cpu0.rename.serializeStallCycles 15249 # count of cycles rename stalled for serializing inst 330system.cpu0.rename.RunCycles 152226 # Number of cycles rename is running 331system.cpu0.rename.UnblockCycles 1484 # Number of cycles rename is unblocking 332system.cpu0.rename.RenamedInsts 466822 # Number of instructions processed by rename 333system.cpu0.rename.IQFullEvents 20 # Number of times rename has blocked due to IQ full 334system.cpu0.rename.LQFullEvents 9 # Number of times rename has blocked due to LQ full 335system.cpu0.rename.SQFullEvents 991 # Number of times rename has blocked due to SQ full 336system.cpu0.rename.RenamedOperands 319803 # Number of destination operands rename has renamed 337system.cpu0.rename.RenameLookups 930944 # Number of register rename lookups that rename has made 338system.cpu0.rename.int_rename_lookups 703631 # Number of integer rename lookups 339system.cpu0.rename.CommittedMaps 305659 # Number of HB maps that are committed 340system.cpu0.rename.UndoneMaps 14144 # Number of HB maps that are undone due to squashing 341system.cpu0.rename.serializingInsts 901 # count of serializing insts renamed 342system.cpu0.rename.tempSerializingInsts 908 # count of temporary serializing insts renamed 343system.cpu0.rename.skidInsts 4515 # count of insts added to the skid buffer 344system.cpu0.memDep0.insertedLoads 148895 # Number of loads inserted to the mem dependence unit. 345system.cpu0.memDep0.insertedStores 75333 # Number of stores inserted to the mem dependence unit. 346system.cpu0.memDep0.conflictingLoads 72583 # Number of conflicting loads. 347system.cpu0.memDep0.conflictingStores 72320 # Number of conflicting stores. 348system.cpu0.iq.iqInstsAdded 390748 # Number of instructions added to the IQ (excludes non-spec) 349system.cpu0.iq.iqNonSpecInstsAdded 967 # Number of non-speculative instructions added to the IQ 350system.cpu0.iq.iqInstsIssued 387435 # Number of instructions issued 351system.cpu0.iq.iqSquashedInstsIssued 23 # Number of squashed instructions issued 352system.cpu0.iq.iqSquashedInstsExamined 13210 # Number of squashed instructions iterated over during squash; mainly for profiling 353system.cpu0.iq.iqSquashedOperandsExamined 11146 # Number of squashed operands that are examined and possibly removed from graph 354system.cpu0.iq.iqSquashedNonSpecRemoved 408 # Number of squashed non-spec instructions that were removed 355system.cpu0.iq.issued_per_cycle::samples 188895 # Number of insts issued each cycle 356system.cpu0.iq.issued_per_cycle::mean 2.051060 # Number of insts issued each cycle 357system.cpu0.iq.issued_per_cycle::stdev 1.134423 # Number of insts issued each cycle 358system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 359system.cpu0.iq.issued_per_cycle::0 34285 18.15% 18.15% # Number of insts issued each cycle 360system.cpu0.iq.issued_per_cycle::1 4265 2.26% 20.41% # Number of insts issued each cycle 361system.cpu0.iq.issued_per_cycle::2 73704 39.02% 59.43% # Number of insts issued each cycle 362system.cpu0.iq.issued_per_cycle::3 73391 38.85% 98.28% # Number of insts issued each cycle 363system.cpu0.iq.issued_per_cycle::4 1671 0.88% 99.16% # Number of insts issued each cycle 364system.cpu0.iq.issued_per_cycle::5 904 0.48% 99.64% # Number of insts issued each cycle 365system.cpu0.iq.issued_per_cycle::6 416 0.22% 99.86% # Number of insts issued each cycle 366system.cpu0.iq.issued_per_cycle::7 183 0.10% 99.96% # Number of insts issued each cycle 367system.cpu0.iq.issued_per_cycle::8 76 0.04% 100.00% # Number of insts issued each cycle 368system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 369system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 370system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 371system.cpu0.iq.issued_per_cycle::total 188895 # Number of insts issued each cycle 372system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 373system.cpu0.iq.fu_full::IntAlu 90 32.14% 32.14% # attempts to use FU when none available 374system.cpu0.iq.fu_full::IntMult 0 0.00% 32.14% # attempts to use FU when none available 375system.cpu0.iq.fu_full::IntDiv 0 0.00% 32.14% # attempts to use FU when none available 376system.cpu0.iq.fu_full::FloatAdd 0 0.00% 32.14% # attempts to use FU when none available 377system.cpu0.iq.fu_full::FloatCmp 0 0.00% 32.14% # attempts to use FU when none available 378system.cpu0.iq.fu_full::FloatCvt 0 0.00% 32.14% # attempts to use FU when none available 379system.cpu0.iq.fu_full::FloatMult 0 0.00% 32.14% # attempts to use FU when none available 380system.cpu0.iq.fu_full::FloatDiv 0 0.00% 32.14% # attempts to use FU when none available 381system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 32.14% # attempts to use FU when none available 382system.cpu0.iq.fu_full::SimdAdd 0 0.00% 32.14% # attempts to use FU when none available 383system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 32.14% # attempts to use FU when none available 384system.cpu0.iq.fu_full::SimdAlu 0 0.00% 32.14% # attempts to use FU when none available 385system.cpu0.iq.fu_full::SimdCmp 0 0.00% 32.14% # attempts to use FU when none available 386system.cpu0.iq.fu_full::SimdCvt 0 0.00% 32.14% # attempts to use FU when none available 387system.cpu0.iq.fu_full::SimdMisc 0 0.00% 32.14% # attempts to use FU when none available 388system.cpu0.iq.fu_full::SimdMult 0 0.00% 32.14% # attempts to use FU when none available 389system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 32.14% # attempts to use FU when none available 390system.cpu0.iq.fu_full::SimdShift 0 0.00% 32.14% # attempts to use FU when none available 391system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 32.14% # attempts to use FU when none available 392system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 32.14% # attempts to use FU when none available 393system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 32.14% # attempts to use FU when none available 394system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 32.14% # attempts to use FU when none available 395system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 32.14% # attempts to use FU when none available 396system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 32.14% # attempts to use FU when none available 397system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 32.14% # attempts to use FU when none available 398system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 32.14% # attempts to use FU when none available 399system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 32.14% # attempts to use FU when none available 400system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.14% # attempts to use FU when none available 401system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 32.14% # attempts to use FU when none available 402system.cpu0.iq.fu_full::MemRead 85 30.36% 62.50% # attempts to use FU when none available 403system.cpu0.iq.fu_full::MemWrite 105 37.50% 100.00% # attempts to use FU when none available 404system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 405system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 406system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 407system.cpu0.iq.FU_type_0::IntAlu 164414 42.44% 42.44% # Type of FU issued 408system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.44% # Type of FU issued 409system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.44% # Type of FU issued 410system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.44% # Type of FU issued 411system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.44% # Type of FU issued 412system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.44% # Type of FU issued 413system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.44% # Type of FU issued 414system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.44% # Type of FU issued 415system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.44% # Type of FU issued 416system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.44% # Type of FU issued 417system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.44% # Type of FU issued 418system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.44% # Type of FU issued 419system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.44% # Type of FU issued 420system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.44% # Type of FU issued 421system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.44% # Type of FU issued 422system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.44% # Type of FU issued 423system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.44% # Type of FU issued 424system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.44% # Type of FU issued 425system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.44% # Type of FU issued 426system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.44% # Type of FU issued 427system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.44% # Type of FU issued 428system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.44% # Type of FU issued 429system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.44% # Type of FU issued 430system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.44% # Type of FU issued 431system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.44% # Type of FU issued 432system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.44% # Type of FU issued 433system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.44% # Type of FU issued 434system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.44% # Type of FU issued 435system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.44% # Type of FU issued 436system.cpu0.iq.FU_type_0::MemRead 148348 38.29% 80.73% # Type of FU issued 437system.cpu0.iq.FU_type_0::MemWrite 74673 19.27% 100.00% # Type of FU issued 438system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 439system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 440system.cpu0.iq.FU_type_0::total 387435 # Type of FU issued 441system.cpu0.iq.rate 1.795335 # Inst issue rate 442system.cpu0.iq.fu_busy_cnt 280 # FU busy when requested 443system.cpu0.iq.fu_busy_rate 0.000723 # FU busy rate (busy events/executed inst) 444system.cpu0.iq.int_inst_queue_reads 964068 # Number of integer instruction queue reads 445system.cpu0.iq.int_inst_queue_writes 404976 # Number of integer instruction queue writes 446system.cpu0.iq.int_inst_queue_wakeup_accesses 385522 # Number of integer instruction queue wakeup accesses 447system.cpu0.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads 448system.cpu0.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes 449system.cpu0.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses 450system.cpu0.iq.int_alu_accesses 387715 # Number of integer alu accesses 451system.cpu0.iq.fp_alu_accesses 0 # Number of floating point alu accesses 452system.cpu0.iew.lsq.thread0.forwLoads 71972 # Number of loads that had data forwarded from stores 453system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 454system.cpu0.iew.lsq.thread0.squashedLoads 2476 # Number of loads squashed 455system.cpu0.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed 456system.cpu0.iew.lsq.thread0.memOrderViolation 53 # Number of memory ordering violations 457system.cpu0.iew.lsq.thread0.squashedStores 1617 # Number of stores squashed 458system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 459system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 460system.cpu0.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 461system.cpu0.iew.lsq.thread0.cacheBlocked 9 # Number of times an access to memory failed due to the cache being blocked 462system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle 463system.cpu0.iew.iewSquashCycles 1355 # Number of cycles IEW is squashing 464system.cpu0.iew.iewBlockCycles 2123 # Number of cycles IEW is blocking 465system.cpu0.iew.iewUnblockCycles 37 # Number of cycles IEW is unblocking 466system.cpu0.iew.iewDispatchedInsts 464714 # Number of instructions dispatched to IQ 467system.cpu0.iew.iewDispSquashedInsts 184 # Number of squashed instructions skipped by dispatch 468system.cpu0.iew.iewDispLoadInsts 148895 # Number of dispatched load instructions 469system.cpu0.iew.iewDispStoreInsts 75333 # Number of dispatched store instructions 470system.cpu0.iew.iewDispNonSpecInsts 846 # Number of dispatched non-speculative instructions 471system.cpu0.iew.iewIQFullEvents 42 # Number of times the IQ has become full, causing a stall 472system.cpu0.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 473system.cpu0.iew.memOrderViolationEvents 53 # Number of memory order violations 474system.cpu0.iew.predictedTakenIncorrect 331 # Number of branches that were predicted taken incorrectly 475system.cpu0.iew.predictedNotTakenIncorrect 1113 # Number of branches that were predicted not taken incorrectly 476system.cpu0.iew.branchMispredicts 1444 # Number of branch mispredicts detected at execute 477system.cpu0.iew.iewExecutedInsts 386358 # Number of executed instructions 478system.cpu0.iew.iewExecLoadInsts 148024 # Number of load instructions executed 479system.cpu0.iew.iewExecSquashedInsts 1077 # Number of squashed instructions skipped in execute 480system.cpu0.iew.exec_swp 0 # number of swp insts executed 481system.cpu0.iew.exec_nop 72999 # number of nop insts executed 482system.cpu0.iew.exec_refs 222560 # number of memory reference insts executed 483system.cpu0.iew.exec_branches 76623 # Number of branches executed 484system.cpu0.iew.exec_stores 74536 # Number of stores executed 485system.cpu0.iew.exec_rate 1.790344 # Inst execution rate 486system.cpu0.iew.wb_sent 385902 # cumulative count of insts sent to commit 487system.cpu0.iew.wb_count 385522 # cumulative count of insts written-back 488system.cpu0.iew.wb_producers 228646 # num instructions producing a value 489system.cpu0.iew.wb_consumers 231982 # num instructions consuming a value 490system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 491system.cpu0.iew.wb_rate 1.786470 # insts written-back per cycle 492system.cpu0.iew.wb_fanout 0.985620 # average fanout of values written-back 493system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 494system.cpu0.commit.commitSquashedInsts 13812 # The number of squashed insts skipped by commit 495system.cpu0.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards 496system.cpu0.commit.branchMispredicts 1206 # The number of times a branch was mispredicted 497system.cpu0.commit.committed_per_cycle::samples 186239 # Number of insts commited each cycle 498system.cpu0.commit.committed_per_cycle::mean 2.420760 # Number of insts commited each cycle 499system.cpu0.commit.committed_per_cycle::stdev 2.150366 # Number of insts commited each cycle 500system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 501system.cpu0.commit.committed_per_cycle::0 34563 18.56% 18.56% # Number of insts commited each cycle 502system.cpu0.commit.committed_per_cycle::1 75593 40.59% 59.15% # Number of insts commited each cycle 503system.cpu0.commit.committed_per_cycle::2 1959 1.05% 60.20% # Number of insts commited each cycle 504system.cpu0.commit.committed_per_cycle::3 634 0.34% 60.54% # Number of insts commited each cycle 505system.cpu0.commit.committed_per_cycle::4 503 0.27% 60.81% # Number of insts commited each cycle 506system.cpu0.commit.committed_per_cycle::5 71729 38.51% 99.32% # Number of insts commited each cycle 507system.cpu0.commit.committed_per_cycle::6 522 0.28% 99.60% # Number of insts commited each cycle 508system.cpu0.commit.committed_per_cycle::7 250 0.13% 99.74% # Number of insts commited each cycle 509system.cpu0.commit.committed_per_cycle::8 486 0.26% 100.00% # Number of insts commited each cycle 510system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 511system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 512system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 513system.cpu0.commit.committed_per_cycle::total 186239 # Number of insts commited each cycle 514system.cpu0.commit.committedInsts 450840 # Number of instructions committed 515system.cpu0.commit.committedOps 450840 # Number of ops (including micro ops) committed 516system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed 517system.cpu0.commit.refs 220135 # Number of memory references committed 518system.cpu0.commit.loads 146419 # Number of loads committed 519system.cpu0.commit.membars 84 # Number of memory barriers committed 520system.cpu0.commit.branches 75603 # Number of branches committed 521system.cpu0.commit.fp_insts 0 # Number of committed floating point instructions. 522system.cpu0.commit.int_insts 303990 # Number of committed integer instructions. 523system.cpu0.commit.function_calls 223 # Number of function calls committed. 524system.cpu0.commit.op_class_0::No_OpClass 72335 16.04% 16.04% # Class of committed instruction 525system.cpu0.commit.op_class_0::IntAlu 158286 35.11% 51.15% # Class of committed instruction 526system.cpu0.commit.op_class_0::IntMult 0 0.00% 51.15% # Class of committed instruction 527system.cpu0.commit.op_class_0::IntDiv 0 0.00% 51.15% # Class of committed instruction 528system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 51.15% # Class of committed instruction 529system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 51.15% # Class of committed instruction 530system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 51.15% # Class of committed instruction 531system.cpu0.commit.op_class_0::FloatMult 0 0.00% 51.15% # Class of committed instruction 532system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 51.15% # Class of committed instruction 533system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 51.15% # Class of committed instruction 534system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 51.15% # Class of committed instruction 535system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 51.15% # Class of committed instruction 536system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 51.15% # Class of committed instruction 537system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 51.15% # Class of committed instruction 538system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 51.15% # Class of committed instruction 539system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 51.15% # Class of committed instruction 540system.cpu0.commit.op_class_0::SimdMult 0 0.00% 51.15% # Class of committed instruction 541system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 51.15% # Class of committed instruction 542system.cpu0.commit.op_class_0::SimdShift 0 0.00% 51.15% # Class of committed instruction 543system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 51.15% # Class of committed instruction 544system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 51.15% # Class of committed instruction 545system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 51.15% # Class of committed instruction 546system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 51.15% # Class of committed instruction 547system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 51.15% # Class of committed instruction 548system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 51.15% # Class of committed instruction 549system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 51.15% # Class of committed instruction 550system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 51.15% # Class of committed instruction 551system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 51.15% # Class of committed instruction 552system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 51.15% # Class of committed instruction 553system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 51.15% # Class of committed instruction 554system.cpu0.commit.op_class_0::MemRead 146503 32.50% 83.65% # Class of committed instruction 555system.cpu0.commit.op_class_0::MemWrite 73716 16.35% 100.00% # Class of committed instruction 556system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 557system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 558system.cpu0.commit.op_class_0::total 450840 # Class of committed instruction 559system.cpu0.commit.bw_lim_events 486 # number cycles where commit BW limit reached 560system.cpu0.rob.rob_reads 649244 # The number of ROB reads 561system.cpu0.rob.rob_writes 931981 # The number of ROB writes 562system.cpu0.timesIdled 314 # Number of times that the entire CPU went into an idle state and unscheduled itself 563system.cpu0.idleCycles 26906 # Total number of cycles that the CPU has spent unscheduled due to idling 564system.cpu0.committedInsts 378421 # Number of Instructions Simulated 565system.cpu0.committedOps 378421 # Number of Ops (including micro ops) Simulated 566system.cpu0.cpi 0.570267 # CPI: Cycles Per Instruction 567system.cpu0.cpi_total 0.570267 # CPI: Total CPI of All Threads 568system.cpu0.ipc 1.753565 # IPC: Instructions Per Cycle 569system.cpu0.ipc_total 1.753565 # IPC: Total IPC of All Threads 570system.cpu0.int_regfile_reads 690917 # number of integer regfile reads 571system.cpu0.int_regfile_writes 311762 # number of integer regfile writes 572system.cpu0.fp_regfile_reads 192 # number of floating regfile reads 573system.cpu0.misc_regfile_reads 224455 # number of misc regfile reads 574system.cpu0.misc_regfile_writes 564 # number of misc regfile writes 575system.cpu0.dcache.tags.replacements 2 # number of replacements 576system.cpu0.dcache.tags.tagsinuse 141.011743 # Cycle average of tags in use 577system.cpu0.dcache.tags.total_refs 148491 # Total number of references to valid blocks. 578system.cpu0.dcache.tags.sampled_refs 171 # Sample count of references to valid blocks. 579system.cpu0.dcache.tags.avg_refs 868.368421 # Average number of references to valid blocks. 580system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 581system.cpu0.dcache.tags.occ_blocks::cpu0.data 141.011743 # Average occupied blocks per requestor 582system.cpu0.dcache.tags.occ_percent::cpu0.data 0.275414 # Average percentage of cache occupancy 583system.cpu0.dcache.tags.occ_percent::total 0.275414 # Average percentage of cache occupancy 584system.cpu0.dcache.tags.occ_task_id_blocks::1024 169 # Occupied blocks per task id 585system.cpu0.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id 586system.cpu0.dcache.tags.age_task_id_blocks_1024::1 67 # Occupied blocks per task id 587system.cpu0.dcache.tags.age_task_id_blocks_1024::2 84 # Occupied blocks per task id 588system.cpu0.dcache.tags.occ_task_id_percent::1024 0.330078 # Percentage of cache occupancy per task id 589system.cpu0.dcache.tags.tag_accesses 599051 # Number of tag accesses 590system.cpu0.dcache.tags.data_accesses 599051 # Number of data accesses 591system.cpu0.dcache.ReadReq_hits::cpu0.data 75429 # number of ReadReq hits 592system.cpu0.dcache.ReadReq_hits::total 75429 # number of ReadReq hits 593system.cpu0.dcache.WriteReq_hits::cpu0.data 73130 # number of WriteReq hits 594system.cpu0.dcache.WriteReq_hits::total 73130 # number of WriteReq hits 595system.cpu0.dcache.SwapReq_hits::cpu0.data 21 # number of SwapReq hits 596system.cpu0.dcache.SwapReq_hits::total 21 # number of SwapReq hits 597system.cpu0.dcache.demand_hits::cpu0.data 148559 # number of demand (read+write) hits 598system.cpu0.dcache.demand_hits::total 148559 # number of demand (read+write) hits 599system.cpu0.dcache.overall_hits::cpu0.data 148559 # number of overall hits 600system.cpu0.dcache.overall_hits::total 148559 # number of overall hits 601system.cpu0.dcache.ReadReq_misses::cpu0.data 540 # number of ReadReq misses 602system.cpu0.dcache.ReadReq_misses::total 540 # number of ReadReq misses 603system.cpu0.dcache.WriteReq_misses::cpu0.data 544 # number of WriteReq misses 604system.cpu0.dcache.WriteReq_misses::total 544 # number of WriteReq misses 605system.cpu0.dcache.SwapReq_misses::cpu0.data 21 # number of SwapReq misses 606system.cpu0.dcache.SwapReq_misses::total 21 # number of SwapReq misses 607system.cpu0.dcache.demand_misses::cpu0.data 1084 # number of demand (read+write) misses 608system.cpu0.dcache.demand_misses::total 1084 # number of demand (read+write) misses 609system.cpu0.dcache.overall_misses::cpu0.data 1084 # number of overall misses 610system.cpu0.dcache.overall_misses::total 1084 # number of overall misses 611system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 16932500 # number of ReadReq miss cycles 612system.cpu0.dcache.ReadReq_miss_latency::total 16932500 # number of ReadReq miss cycles 613system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 35823993 # number of WriteReq miss cycles 614system.cpu0.dcache.WriteReq_miss_latency::total 35823993 # number of WriteReq miss cycles 615system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 460000 # number of SwapReq miss cycles 616system.cpu0.dcache.SwapReq_miss_latency::total 460000 # number of SwapReq miss cycles 617system.cpu0.dcache.demand_miss_latency::cpu0.data 52756493 # number of demand (read+write) miss cycles 618system.cpu0.dcache.demand_miss_latency::total 52756493 # number of demand (read+write) miss cycles 619system.cpu0.dcache.overall_miss_latency::cpu0.data 52756493 # number of overall miss cycles 620system.cpu0.dcache.overall_miss_latency::total 52756493 # number of overall miss cycles 621system.cpu0.dcache.ReadReq_accesses::cpu0.data 75969 # number of ReadReq accesses(hits+misses) 622system.cpu0.dcache.ReadReq_accesses::total 75969 # number of ReadReq accesses(hits+misses) 623system.cpu0.dcache.WriteReq_accesses::cpu0.data 73674 # number of WriteReq accesses(hits+misses) 624system.cpu0.dcache.WriteReq_accesses::total 73674 # number of WriteReq accesses(hits+misses) 625system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) 626system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) 627system.cpu0.dcache.demand_accesses::cpu0.data 149643 # number of demand (read+write) accesses 628system.cpu0.dcache.demand_accesses::total 149643 # number of demand (read+write) accesses 629system.cpu0.dcache.overall_accesses::cpu0.data 149643 # number of overall (read+write) accesses 630system.cpu0.dcache.overall_accesses::total 149643 # number of overall (read+write) accesses 631system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.007108 # miss rate for ReadReq accesses 632system.cpu0.dcache.ReadReq_miss_rate::total 0.007108 # miss rate for ReadReq accesses 633system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007384 # miss rate for WriteReq accesses 634system.cpu0.dcache.WriteReq_miss_rate::total 0.007384 # miss rate for WriteReq accesses 635system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.500000 # miss rate for SwapReq accesses 636system.cpu0.dcache.SwapReq_miss_rate::total 0.500000 # miss rate for SwapReq accesses 637system.cpu0.dcache.demand_miss_rate::cpu0.data 0.007244 # miss rate for demand accesses 638system.cpu0.dcache.demand_miss_rate::total 0.007244 # miss rate for demand accesses 639system.cpu0.dcache.overall_miss_rate::cpu0.data 0.007244 # miss rate for overall accesses 640system.cpu0.dcache.overall_miss_rate::total 0.007244 # miss rate for overall accesses 641system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 31356.481481 # average ReadReq miss latency 642system.cpu0.dcache.ReadReq_avg_miss_latency::total 31356.481481 # average ReadReq miss latency 643system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 65852.928309 # average WriteReq miss latency 644system.cpu0.dcache.WriteReq_avg_miss_latency::total 65852.928309 # average WriteReq miss latency 645system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 21904.761905 # average SwapReq miss latency 646system.cpu0.dcache.SwapReq_avg_miss_latency::total 21904.761905 # average SwapReq miss latency 647system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 48668.351476 # average overall miss latency 648system.cpu0.dcache.demand_avg_miss_latency::total 48668.351476 # average overall miss latency 649system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 48668.351476 # average overall miss latency 650system.cpu0.dcache.overall_avg_miss_latency::total 48668.351476 # average overall miss latency 651system.cpu0.dcache.blocked_cycles::no_mshrs 1048 # number of cycles access was blocked 652system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 653system.cpu0.dcache.blocked::no_mshrs 16 # number of cycles access was blocked 654system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 655system.cpu0.dcache.avg_blocked_cycles::no_mshrs 65.500000 # average number of cycles each access was blocked 656system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 657system.cpu0.dcache.fast_writes 0 # number of fast writes performed 658system.cpu0.dcache.cache_copies 0 # number of cache copies performed 659system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks 660system.cpu0.dcache.writebacks::total 1 # number of writebacks 661system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 357 # number of ReadReq MSHR hits 662system.cpu0.dcache.ReadReq_mshr_hits::total 357 # number of ReadReq MSHR hits 663system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 369 # number of WriteReq MSHR hits 664system.cpu0.dcache.WriteReq_mshr_hits::total 369 # number of WriteReq MSHR hits 665system.cpu0.dcache.demand_mshr_hits::cpu0.data 726 # number of demand (read+write) MSHR hits 666system.cpu0.dcache.demand_mshr_hits::total 726 # number of demand (read+write) MSHR hits 667system.cpu0.dcache.overall_mshr_hits::cpu0.data 726 # number of overall MSHR hits 668system.cpu0.dcache.overall_mshr_hits::total 726 # number of overall MSHR hits 669system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 183 # number of ReadReq MSHR misses 670system.cpu0.dcache.ReadReq_mshr_misses::total 183 # number of ReadReq MSHR misses 671system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 175 # number of WriteReq MSHR misses 672system.cpu0.dcache.WriteReq_mshr_misses::total 175 # number of WriteReq MSHR misses 673system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 21 # number of SwapReq MSHR misses 674system.cpu0.dcache.SwapReq_mshr_misses::total 21 # number of SwapReq MSHR misses 675system.cpu0.dcache.demand_mshr_misses::cpu0.data 358 # number of demand (read+write) MSHR misses 676system.cpu0.dcache.demand_mshr_misses::total 358 # number of demand (read+write) MSHR misses 677system.cpu0.dcache.overall_mshr_misses::cpu0.data 358 # number of overall MSHR misses 678system.cpu0.dcache.overall_mshr_misses::total 358 # number of overall MSHR misses 679system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 6813000 # number of ReadReq MSHR miss cycles 680system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6813000 # number of ReadReq MSHR miss cycles 681system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 8643000 # number of WriteReq MSHR miss cycles 682system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8643000 # number of WriteReq MSHR miss cycles 683system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 439000 # number of SwapReq MSHR miss cycles 684system.cpu0.dcache.SwapReq_mshr_miss_latency::total 439000 # number of SwapReq MSHR miss cycles 685system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 15456000 # number of demand (read+write) MSHR miss cycles 686system.cpu0.dcache.demand_mshr_miss_latency::total 15456000 # number of demand (read+write) MSHR miss cycles 687system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 15456000 # number of overall MSHR miss cycles 688system.cpu0.dcache.overall_mshr_miss_latency::total 15456000 # number of overall MSHR miss cycles 689system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002409 # mshr miss rate for ReadReq accesses 690system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002409 # mshr miss rate for ReadReq accesses 691system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002375 # mshr miss rate for WriteReq accesses 692system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002375 # mshr miss rate for WriteReq accesses 693system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.500000 # mshr miss rate for SwapReq accesses 694system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SwapReq accesses 695system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002392 # mshr miss rate for demand accesses 696system.cpu0.dcache.demand_mshr_miss_rate::total 0.002392 # mshr miss rate for demand accesses 697system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002392 # mshr miss rate for overall accesses 698system.cpu0.dcache.overall_mshr_miss_rate::total 0.002392 # mshr miss rate for overall accesses 699system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 37229.508197 # average ReadReq mshr miss latency 700system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 37229.508197 # average ReadReq mshr miss latency 701system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 49388.571429 # average WriteReq mshr miss latency 702system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 49388.571429 # average WriteReq mshr miss latency 703system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 20904.761905 # average SwapReq mshr miss latency 704system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 20904.761905 # average SwapReq mshr miss latency 705system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 43173.184358 # average overall mshr miss latency 706system.cpu0.dcache.demand_avg_mshr_miss_latency::total 43173.184358 # average overall mshr miss latency 707system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 43173.184358 # average overall mshr miss latency 708system.cpu0.dcache.overall_avg_mshr_miss_latency::total 43173.184358 # average overall mshr miss latency 709system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 710system.cpu0.icache.tags.replacements 323 # number of replacements 711system.cpu0.icache.tags.tagsinuse 240.334366 # Cycle average of tags in use 712system.cpu0.icache.tags.total_refs 6439 # Total number of references to valid blocks. 713system.cpu0.icache.tags.sampled_refs 614 # Sample count of references to valid blocks. 714system.cpu0.icache.tags.avg_refs 10.486971 # Average number of references to valid blocks. 715system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 716system.cpu0.icache.tags.occ_blocks::cpu0.inst 240.334366 # Average occupied blocks per requestor 717system.cpu0.icache.tags.occ_percent::cpu0.inst 0.469403 # Average percentage of cache occupancy 718system.cpu0.icache.tags.occ_percent::total 0.469403 # Average percentage of cache occupancy 719system.cpu0.icache.tags.occ_task_id_blocks::1024 291 # Occupied blocks per task id 720system.cpu0.icache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id 721system.cpu0.icache.tags.age_task_id_blocks_1024::1 174 # Occupied blocks per task id 722system.cpu0.icache.tags.age_task_id_blocks_1024::2 59 # Occupied blocks per task id 723system.cpu0.icache.tags.occ_task_id_percent::1024 0.568359 # Percentage of cache occupancy per task id 724system.cpu0.icache.tags.tag_accesses 7852 # Number of tag accesses 725system.cpu0.icache.tags.data_accesses 7852 # Number of data accesses 726system.cpu0.icache.ReadReq_hits::cpu0.inst 6439 # number of ReadReq hits 727system.cpu0.icache.ReadReq_hits::total 6439 # number of ReadReq hits 728system.cpu0.icache.demand_hits::cpu0.inst 6439 # number of demand (read+write) hits 729system.cpu0.icache.demand_hits::total 6439 # number of demand (read+write) hits 730system.cpu0.icache.overall_hits::cpu0.inst 6439 # number of overall hits 731system.cpu0.icache.overall_hits::total 6439 # number of overall hits 732system.cpu0.icache.ReadReq_misses::cpu0.inst 799 # number of ReadReq misses 733system.cpu0.icache.ReadReq_misses::total 799 # number of ReadReq misses 734system.cpu0.icache.demand_misses::cpu0.inst 799 # number of demand (read+write) misses 735system.cpu0.icache.demand_misses::total 799 # number of demand (read+write) misses 736system.cpu0.icache.overall_misses::cpu0.inst 799 # number of overall misses 737system.cpu0.icache.overall_misses::total 799 # number of overall misses 738system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 40829000 # number of ReadReq miss cycles 739system.cpu0.icache.ReadReq_miss_latency::total 40829000 # number of ReadReq miss cycles 740system.cpu0.icache.demand_miss_latency::cpu0.inst 40829000 # number of demand (read+write) miss cycles 741system.cpu0.icache.demand_miss_latency::total 40829000 # number of demand (read+write) miss cycles 742system.cpu0.icache.overall_miss_latency::cpu0.inst 40829000 # number of overall miss cycles 743system.cpu0.icache.overall_miss_latency::total 40829000 # number of overall miss cycles 744system.cpu0.icache.ReadReq_accesses::cpu0.inst 7238 # number of ReadReq accesses(hits+misses) 745system.cpu0.icache.ReadReq_accesses::total 7238 # number of ReadReq accesses(hits+misses) 746system.cpu0.icache.demand_accesses::cpu0.inst 7238 # number of demand (read+write) accesses 747system.cpu0.icache.demand_accesses::total 7238 # number of demand (read+write) accesses 748system.cpu0.icache.overall_accesses::cpu0.inst 7238 # number of overall (read+write) accesses 749system.cpu0.icache.overall_accesses::total 7238 # number of overall (read+write) accesses 750system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.110390 # miss rate for ReadReq accesses 751system.cpu0.icache.ReadReq_miss_rate::total 0.110390 # miss rate for ReadReq accesses 752system.cpu0.icache.demand_miss_rate::cpu0.inst 0.110390 # miss rate for demand accesses 753system.cpu0.icache.demand_miss_rate::total 0.110390 # miss rate for demand accesses 754system.cpu0.icache.overall_miss_rate::cpu0.inst 0.110390 # miss rate for overall accesses 755system.cpu0.icache.overall_miss_rate::total 0.110390 # miss rate for overall accesses 756system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 51100.125156 # average ReadReq miss latency 757system.cpu0.icache.ReadReq_avg_miss_latency::total 51100.125156 # average ReadReq miss latency 758system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 51100.125156 # average overall miss latency 759system.cpu0.icache.demand_avg_miss_latency::total 51100.125156 # average overall miss latency 760system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 51100.125156 # average overall miss latency 761system.cpu0.icache.overall_avg_miss_latency::total 51100.125156 # average overall miss latency 762system.cpu0.icache.blocked_cycles::no_mshrs 2 # number of cycles access was blocked 763system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 764system.cpu0.icache.blocked::no_mshrs 1 # number of cycles access was blocked 765system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 766system.cpu0.icache.avg_blocked_cycles::no_mshrs 2 # average number of cycles each access was blocked 767system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 768system.cpu0.icache.fast_writes 0 # number of fast writes performed 769system.cpu0.icache.cache_copies 0 # number of cache copies performed 770system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 184 # number of ReadReq MSHR hits 771system.cpu0.icache.ReadReq_mshr_hits::total 184 # number of ReadReq MSHR hits 772system.cpu0.icache.demand_mshr_hits::cpu0.inst 184 # number of demand (read+write) MSHR hits 773system.cpu0.icache.demand_mshr_hits::total 184 # number of demand (read+write) MSHR hits 774system.cpu0.icache.overall_mshr_hits::cpu0.inst 184 # number of overall MSHR hits 775system.cpu0.icache.overall_mshr_hits::total 184 # number of overall MSHR hits 776system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 615 # number of ReadReq MSHR misses 777system.cpu0.icache.ReadReq_mshr_misses::total 615 # number of ReadReq MSHR misses 778system.cpu0.icache.demand_mshr_misses::cpu0.inst 615 # number of demand (read+write) MSHR misses 779system.cpu0.icache.demand_mshr_misses::total 615 # number of demand (read+write) MSHR misses 780system.cpu0.icache.overall_mshr_misses::cpu0.inst 615 # number of overall MSHR misses 781system.cpu0.icache.overall_mshr_misses::total 615 # number of overall MSHR misses 782system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 31621000 # number of ReadReq MSHR miss cycles 783system.cpu0.icache.ReadReq_mshr_miss_latency::total 31621000 # number of ReadReq MSHR miss cycles 784system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 31621000 # number of demand (read+write) MSHR miss cycles 785system.cpu0.icache.demand_mshr_miss_latency::total 31621000 # number of demand (read+write) MSHR miss cycles 786system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 31621000 # number of overall MSHR miss cycles 787system.cpu0.icache.overall_mshr_miss_latency::total 31621000 # number of overall MSHR miss cycles 788system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.084968 # mshr miss rate for ReadReq accesses 789system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.084968 # mshr miss rate for ReadReq accesses 790system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.084968 # mshr miss rate for demand accesses 791system.cpu0.icache.demand_mshr_miss_rate::total 0.084968 # mshr miss rate for demand accesses 792system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.084968 # mshr miss rate for overall accesses 793system.cpu0.icache.overall_mshr_miss_rate::total 0.084968 # mshr miss rate for overall accesses 794system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 51416.260163 # average ReadReq mshr miss latency 795system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 51416.260163 # average ReadReq mshr miss latency 796system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 51416.260163 # average overall mshr miss latency 797system.cpu0.icache.demand_avg_mshr_miss_latency::total 51416.260163 # average overall mshr miss latency 798system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 51416.260163 # average overall mshr miss latency 799system.cpu0.icache.overall_avg_mshr_miss_latency::total 51416.260163 # average overall mshr miss latency 800system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 801system.cpu1.branchPred.lookups 53963 # Number of BP lookups 802system.cpu1.branchPred.condPredicted 50167 # Number of conditional branches predicted 803system.cpu1.branchPred.condIncorrect 1346 # Number of conditional branches incorrect 804system.cpu1.branchPred.BTBLookups 46229 # Number of BTB lookups 805system.cpu1.branchPred.BTBHits 44971 # Number of BTB hits 806system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 807system.cpu1.branchPred.BTBHitPct 97.278764 # BTB Hit Percentage 808system.cpu1.branchPred.usedRAS 927 # Number of times the RAS was used to get a target. 809system.cpu1.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions. 810system.cpu1.numCycles 162372 # number of cpu cycles simulated 811system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 812system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 813system.cpu1.fetch.icacheStallCycles 29926 # Number of cycles fetch is stalled on an Icache miss 814system.cpu1.fetch.Insts 299894 # Number of instructions fetch has processed 815system.cpu1.fetch.Branches 53963 # Number of branches that fetch encountered 816system.cpu1.fetch.predictedBranches 45898 # Number of branches that fetch has predicted taken 817system.cpu1.fetch.Cycles 123960 # Number of cycles fetch has run and was not squashing or blocked 818system.cpu1.fetch.SquashCycles 2845 # Number of cycles fetch has spent squashing 819system.cpu1.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 820system.cpu1.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from 821system.cpu1.fetch.PendingTrapStallCycles 1155 # Number of stall cycles due to pending traps 822system.cpu1.fetch.CacheLines 20576 # Number of cache lines fetched 823system.cpu1.fetch.IcacheSquashes 472 # Number of outstanding Icache misses that were squashed 824system.cpu1.fetch.rateDist::samples 156476 # Number of instructions fetched each cycle (Total) 825system.cpu1.fetch.rateDist::mean 1.916550 # Number of instructions fetched each cycle (Total) 826system.cpu1.fetch.rateDist::stdev 2.231802 # Number of instructions fetched each cycle (Total) 827system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 828system.cpu1.fetch.rateDist::0 52995 33.87% 33.87% # Number of instructions fetched each cycle (Total) 829system.cpu1.fetch.rateDist::1 51987 33.22% 67.09% # Number of instructions fetched each cycle (Total) 830system.cpu1.fetch.rateDist::2 5834 3.73% 70.82% # Number of instructions fetched each cycle (Total) 831system.cpu1.fetch.rateDist::3 3448 2.20% 73.02% # Number of instructions fetched each cycle (Total) 832system.cpu1.fetch.rateDist::4 958 0.61% 73.64% # Number of instructions fetched each cycle (Total) 833system.cpu1.fetch.rateDist::5 34873 22.29% 95.92% # Number of instructions fetched each cycle (Total) 834system.cpu1.fetch.rateDist::6 1256 0.80% 96.72% # Number of instructions fetched each cycle (Total) 835system.cpu1.fetch.rateDist::7 838 0.54% 97.26% # Number of instructions fetched each cycle (Total) 836system.cpu1.fetch.rateDist::8 4287 2.74% 100.00% # Number of instructions fetched each cycle (Total) 837system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 838system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 839system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 840system.cpu1.fetch.rateDist::total 156476 # Number of instructions fetched each cycle (Total) 841system.cpu1.fetch.branchRate 0.332342 # Number of branch fetches per cycle 842system.cpu1.fetch.rate 1.846956 # Number of inst fetches per cycle 843system.cpu1.decode.IdleCycles 18007 # Number of cycles decode is idle 844system.cpu1.decode.BlockedCycles 50929 # Number of cycles decode is blocked 845system.cpu1.decode.RunCycles 83026 # Number of cycles decode is running 846system.cpu1.decode.UnblockCycles 3082 # Number of cycles decode is unblocking 847system.cpu1.decode.SquashCycles 1422 # Number of cycles decode is squashing 848system.cpu1.decode.DecodedInsts 283749 # Number of instructions handled by decode 849system.cpu1.rename.SquashCycles 1422 # Number of cycles rename is squashing 850system.cpu1.rename.IdleCycles 18719 # Number of cycles rename is idle 851system.cpu1.rename.BlockCycles 22929 # Number of cycles rename is blocking 852system.cpu1.rename.serializeStallCycles 13387 # count of cycles rename stalled for serializing inst 853system.cpu1.rename.RunCycles 84356 # Number of cycles rename is running 854system.cpu1.rename.UnblockCycles 15653 # Number of cycles rename is unblocking 855system.cpu1.rename.RenamedInsts 280426 # Number of instructions processed by rename 856system.cpu1.rename.IQFullEvents 13898 # Number of times rename has blocked due to IQ full 857system.cpu1.rename.LQFullEvents 14 # Number of times rename has blocked due to LQ full 858system.cpu1.rename.FullRegisterEvents 6 # Number of times there has been no free registers 859system.cpu1.rename.RenamedOperands 198372 # Number of destination operands rename has renamed 860system.cpu1.rename.RenameLookups 540599 # Number of register rename lookups that rename has made 861system.cpu1.rename.int_rename_lookups 420692 # Number of integer rename lookups 862system.cpu1.rename.CommittedMaps 183271 # Number of HB maps that are committed 863system.cpu1.rename.UndoneMaps 15101 # Number of HB maps that are undone due to squashing 864system.cpu1.rename.serializingInsts 1203 # count of serializing insts renamed 865system.cpu1.rename.tempSerializingInsts 1280 # count of temporary serializing insts renamed 866system.cpu1.rename.skidInsts 20103 # count of insts added to the skid buffer 867system.cpu1.memDep0.insertedLoads 79058 # Number of loads inserted to the mem dependence unit. 868system.cpu1.memDep0.insertedStores 37890 # Number of stores inserted to the mem dependence unit. 869system.cpu1.memDep0.conflictingLoads 37399 # Number of conflicting loads. 870system.cpu1.memDep0.conflictingStores 32713 # Number of conflicting stores. 871system.cpu1.iq.iqInstsAdded 233810 # Number of instructions added to the IQ (excludes non-spec) 872system.cpu1.iq.iqNonSpecInstsAdded 5671 # Number of non-speculative instructions added to the IQ 873system.cpu1.iq.iqInstsIssued 234514 # Number of instructions issued 874system.cpu1.iq.iqSquashedInstsIssued 46 # Number of squashed instructions issued 875system.cpu1.iq.iqSquashedInstsExamined 14000 # Number of squashed instructions iterated over during squash; mainly for profiling 876system.cpu1.iq.iqSquashedOperandsExamined 11968 # Number of squashed operands that are examined and possibly removed from graph 877system.cpu1.iq.iqSquashedNonSpecRemoved 653 # Number of squashed non-spec instructions that were removed 878system.cpu1.iq.issued_per_cycle::samples 156476 # Number of insts issued each cycle 879system.cpu1.iq.issued_per_cycle::mean 1.498722 # Number of insts issued each cycle 880system.cpu1.iq.issued_per_cycle::stdev 1.383815 # Number of insts issued each cycle 881system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 882system.cpu1.iq.issued_per_cycle::0 56669 36.22% 36.22% # Number of insts issued each cycle 883system.cpu1.iq.issued_per_cycle::1 19562 12.50% 48.72% # Number of insts issued each cycle 884system.cpu1.iq.issued_per_cycle::2 37085 23.70% 72.42% # Number of insts issued each cycle 885system.cpu1.iq.issued_per_cycle::3 36801 23.52% 95.94% # Number of insts issued each cycle 886system.cpu1.iq.issued_per_cycle::4 3420 2.19% 98.12% # Number of insts issued each cycle 887system.cpu1.iq.issued_per_cycle::5 1602 1.02% 99.15% # Number of insts issued each cycle 888system.cpu1.iq.issued_per_cycle::6 884 0.56% 99.71% # Number of insts issued each cycle 889system.cpu1.iq.issued_per_cycle::7 239 0.15% 99.86% # Number of insts issued each cycle 890system.cpu1.iq.issued_per_cycle::8 214 0.14% 100.00% # Number of insts issued each cycle 891system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 892system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 893system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 894system.cpu1.iq.issued_per_cycle::total 156476 # Number of insts issued each cycle 895system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 896system.cpu1.iq.fu_full::IntAlu 87 24.58% 24.58% # attempts to use FU when none available 897system.cpu1.iq.fu_full::IntMult 0 0.00% 24.58% # attempts to use FU when none available 898system.cpu1.iq.fu_full::IntDiv 0 0.00% 24.58% # attempts to use FU when none available 899system.cpu1.iq.fu_full::FloatAdd 0 0.00% 24.58% # attempts to use FU when none available 900system.cpu1.iq.fu_full::FloatCmp 0 0.00% 24.58% # attempts to use FU when none available 901system.cpu1.iq.fu_full::FloatCvt 0 0.00% 24.58% # attempts to use FU when none available 902system.cpu1.iq.fu_full::FloatMult 0 0.00% 24.58% # attempts to use FU when none available 903system.cpu1.iq.fu_full::FloatDiv 0 0.00% 24.58% # attempts to use FU when none available 904system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 24.58% # attempts to use FU when none available 905system.cpu1.iq.fu_full::SimdAdd 0 0.00% 24.58% # attempts to use FU when none available 906system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 24.58% # attempts to use FU when none available 907system.cpu1.iq.fu_full::SimdAlu 0 0.00% 24.58% # attempts to use FU when none available 908system.cpu1.iq.fu_full::SimdCmp 0 0.00% 24.58% # attempts to use FU when none available 909system.cpu1.iq.fu_full::SimdCvt 0 0.00% 24.58% # attempts to use FU when none available 910system.cpu1.iq.fu_full::SimdMisc 0 0.00% 24.58% # attempts to use FU when none available 911system.cpu1.iq.fu_full::SimdMult 0 0.00% 24.58% # attempts to use FU when none available 912system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 24.58% # attempts to use FU when none available 913system.cpu1.iq.fu_full::SimdShift 0 0.00% 24.58% # attempts to use FU when none available 914system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 24.58% # attempts to use FU when none available 915system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 24.58% # attempts to use FU when none available 916system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 24.58% # attempts to use FU when none available 917system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 24.58% # attempts to use FU when none available 918system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 24.58% # attempts to use FU when none available 919system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 24.58% # attempts to use FU when none available 920system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 24.58% # attempts to use FU when none available 921system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 24.58% # attempts to use FU when none available 922system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 24.58% # attempts to use FU when none available 923system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 24.58% # attempts to use FU when none available 924system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 24.58% # attempts to use FU when none available 925system.cpu1.iq.fu_full::MemRead 58 16.38% 40.96% # attempts to use FU when none available 926system.cpu1.iq.fu_full::MemWrite 209 59.04% 100.00% # attempts to use FU when none available 927system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 928system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 929system.cpu1.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 930system.cpu1.iq.FU_type_0::IntAlu 114757 48.93% 48.93% # Type of FU issued 931system.cpu1.iq.FU_type_0::IntMult 0 0.00% 48.93% # Type of FU issued 932system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 48.93% # Type of FU issued 933system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 48.93% # Type of FU issued 934system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 48.93% # Type of FU issued 935system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 48.93% # Type of FU issued 936system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 48.93% # Type of FU issued 937system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 48.93% # Type of FU issued 938system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 48.93% # Type of FU issued 939system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 48.93% # Type of FU issued 940system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 48.93% # Type of FU issued 941system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 48.93% # Type of FU issued 942system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 48.93% # Type of FU issued 943system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 48.93% # Type of FU issued 944system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 48.93% # Type of FU issued 945system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 48.93% # Type of FU issued 946system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 48.93% # Type of FU issued 947system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 48.93% # Type of FU issued 948system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.93% # Type of FU issued 949system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 48.93% # Type of FU issued 950system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.93% # Type of FU issued 951system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.93% # Type of FU issued 952system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.93% # Type of FU issued 953system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.93% # Type of FU issued 954system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.93% # Type of FU issued 955system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.93% # Type of FU issued 956system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 48.93% # Type of FU issued 957system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.93% # Type of FU issued 958system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.93% # Type of FU issued 959system.cpu1.iq.FU_type_0::MemRead 82569 35.21% 84.14% # Type of FU issued 960system.cpu1.iq.FU_type_0::MemWrite 37188 15.86% 100.00% # Type of FU issued 961system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 962system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 963system.cpu1.iq.FU_type_0::total 234514 # Type of FU issued 964system.cpu1.iq.rate 1.444301 # Inst issue rate 965system.cpu1.iq.fu_busy_cnt 354 # FU busy when requested 966system.cpu1.iq.fu_busy_rate 0.001510 # FU busy rate (busy events/executed inst) 967system.cpu1.iq.int_inst_queue_reads 625904 # Number of integer instruction queue reads 968system.cpu1.iq.int_inst_queue_writes 253521 # Number of integer instruction queue writes 969system.cpu1.iq.int_inst_queue_wakeup_accesses 232777 # Number of integer instruction queue wakeup accesses 970system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads 971system.cpu1.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes 972system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses 973system.cpu1.iq.int_alu_accesses 234868 # Number of integer alu accesses 974system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses 975system.cpu1.iew.lsq.thread0.forwLoads 32465 # Number of loads that had data forwarded from stores 976system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 977system.cpu1.iew.lsq.thread0.squashedLoads 2830 # Number of loads squashed 978system.cpu1.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed 979system.cpu1.iew.lsq.thread0.memOrderViolation 40 # Number of memory ordering violations 980system.cpu1.iew.lsq.thread0.squashedStores 1669 # Number of stores squashed 981system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 982system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 983system.cpu1.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 984system.cpu1.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked 985system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle 986system.cpu1.iew.iewSquashCycles 1422 # Number of cycles IEW is squashing 987system.cpu1.iew.iewBlockCycles 6958 # Number of cycles IEW is blocking 988system.cpu1.iew.iewUnblockCycles 66 # Number of cycles IEW is unblocking 989system.cpu1.iew.iewDispatchedInsts 277649 # Number of instructions dispatched to IQ 990system.cpu1.iew.iewDispSquashedInsts 222 # Number of squashed instructions skipped by dispatch 991system.cpu1.iew.iewDispLoadInsts 79058 # Number of dispatched load instructions 992system.cpu1.iew.iewDispStoreInsts 37890 # Number of dispatched store instructions 993system.cpu1.iew.iewDispNonSpecInsts 1130 # Number of dispatched non-speculative instructions 994system.cpu1.iew.iewIQFullEvents 43 # Number of times the IQ has become full, causing a stall 995system.cpu1.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 996system.cpu1.iew.memOrderViolationEvents 40 # Number of memory order violations 997system.cpu1.iew.predictedTakenIncorrect 481 # Number of branches that were predicted taken incorrectly 998system.cpu1.iew.predictedNotTakenIncorrect 1106 # Number of branches that were predicted not taken incorrectly 999system.cpu1.iew.branchMispredicts 1587 # Number of branch mispredicts detected at execute 1000system.cpu1.iew.iewExecutedInsts 233397 # Number of executed instructions 1001system.cpu1.iew.iewExecLoadInsts 77941 # Number of load instructions executed 1002system.cpu1.iew.iewExecSquashedInsts 1117 # Number of squashed instructions skipped in execute 1003system.cpu1.iew.exec_swp 0 # number of swp insts executed 1004system.cpu1.iew.exec_nop 38168 # number of nop insts executed 1005system.cpu1.iew.exec_refs 115010 # number of memory reference insts executed 1006system.cpu1.iew.exec_branches 47577 # Number of branches executed 1007system.cpu1.iew.exec_stores 37069 # Number of stores executed 1008system.cpu1.iew.exec_rate 1.437421 # Inst execution rate 1009system.cpu1.iew.wb_sent 233106 # cumulative count of insts sent to commit 1010system.cpu1.iew.wb_count 232777 # cumulative count of insts written-back 1011system.cpu1.iew.wb_producers 132706 # num instructions producing a value 1012system.cpu1.iew.wb_consumers 139339 # num instructions consuming a value 1013system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 1014system.cpu1.iew.wb_rate 1.433603 # insts written-back per cycle 1015system.cpu1.iew.wb_fanout 0.952397 # average fanout of values written-back 1016system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 1017system.cpu1.commit.commitSquashedInsts 14853 # The number of squashed insts skipped by commit 1018system.cpu1.commit.commitNonSpecStalls 5018 # The number of times commit has been forced to stall to communicate backwards 1019system.cpu1.commit.branchMispredicts 1346 # The number of times a branch was mispredicted 1020system.cpu1.commit.committed_per_cycle::samples 153761 # Number of insts commited each cycle 1021system.cpu1.commit.committed_per_cycle::mean 1.708866 # Number of insts commited each cycle 1022system.cpu1.commit.committed_per_cycle::stdev 2.078798 # Number of insts commited each cycle 1023system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 1024system.cpu1.commit.committed_per_cycle::0 61362 39.91% 39.91% # Number of insts commited each cycle 1025system.cpu1.commit.committed_per_cycle::1 44235 28.77% 68.68% # Number of insts commited each cycle 1026system.cpu1.commit.committed_per_cycle::2 5219 3.39% 72.07% # Number of insts commited each cycle 1027system.cpu1.commit.committed_per_cycle::3 5854 3.81% 75.88% # Number of insts commited each cycle 1028system.cpu1.commit.committed_per_cycle::4 1519 0.99% 76.87% # Number of insts commited each cycle 1029system.cpu1.commit.committed_per_cycle::5 32513 21.15% 98.01% # Number of insts commited each cycle 1030system.cpu1.commit.committed_per_cycle::6 819 0.53% 98.54% # Number of insts commited each cycle 1031system.cpu1.commit.committed_per_cycle::7 953 0.62% 99.16% # Number of insts commited each cycle 1032system.cpu1.commit.committed_per_cycle::8 1287 0.84% 100.00% # Number of insts commited each cycle 1033system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 1034system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 1035system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 1036system.cpu1.commit.committed_per_cycle::total 153761 # Number of insts commited each cycle 1037system.cpu1.commit.committedInsts 262757 # Number of instructions committed 1038system.cpu1.commit.committedOps 262757 # Number of ops (including micro ops) committed 1039system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed 1040system.cpu1.commit.refs 112449 # Number of memory references committed 1041system.cpu1.commit.loads 76228 # Number of loads committed 1042system.cpu1.commit.membars 4303 # Number of memory barriers committed 1043system.cpu1.commit.branches 46487 # Number of branches committed 1044system.cpu1.commit.fp_insts 0 # Number of committed floating point instructions. 1045system.cpu1.commit.int_insts 181057 # Number of committed integer instructions. 1046system.cpu1.commit.function_calls 322 # Number of function calls committed. 1047system.cpu1.commit.op_class_0::No_OpClass 37276 14.19% 14.19% # Class of committed instruction 1048system.cpu1.commit.op_class_0::IntAlu 108729 41.38% 55.57% # Class of committed instruction 1049system.cpu1.commit.op_class_0::IntMult 0 0.00% 55.57% # Class of committed instruction 1050system.cpu1.commit.op_class_0::IntDiv 0 0.00% 55.57% # Class of committed instruction 1051system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 55.57% # Class of committed instruction 1052system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 55.57% # Class of committed instruction 1053system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 55.57% # Class of committed instruction 1054system.cpu1.commit.op_class_0::FloatMult 0 0.00% 55.57% # Class of committed instruction 1055system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 55.57% # Class of committed instruction 1056system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 55.57% # Class of committed instruction 1057system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 55.57% # Class of committed instruction 1058system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 55.57% # Class of committed instruction 1059system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 55.57% # Class of committed instruction 1060system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 55.57% # Class of committed instruction 1061system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 55.57% # Class of committed instruction 1062system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 55.57% # Class of committed instruction 1063system.cpu1.commit.op_class_0::SimdMult 0 0.00% 55.57% # Class of committed instruction 1064system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 55.57% # Class of committed instruction 1065system.cpu1.commit.op_class_0::SimdShift 0 0.00% 55.57% # Class of committed instruction 1066system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 55.57% # Class of committed instruction 1067system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 55.57% # Class of committed instruction 1068system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 55.57% # Class of committed instruction 1069system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 55.57% # Class of committed instruction 1070system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 55.57% # Class of committed instruction 1071system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 55.57% # Class of committed instruction 1072system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 55.57% # Class of committed instruction 1073system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 55.57% # Class of committed instruction 1074system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 55.57% # Class of committed instruction 1075system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.57% # Class of committed instruction 1076system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.57% # Class of committed instruction 1077system.cpu1.commit.op_class_0::MemRead 80531 30.65% 86.22% # Class of committed instruction 1078system.cpu1.commit.op_class_0::MemWrite 36221 13.78% 100.00% # Class of committed instruction 1079system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 1080system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 1081system.cpu1.commit.op_class_0::total 262757 # Class of committed instruction 1082system.cpu1.commit.bw_lim_events 1287 # number cycles where commit BW limit reached 1083system.cpu1.rob.rob_reads 429498 # The number of ROB reads 1084system.cpu1.rob.rob_writes 557934 # The number of ROB writes 1085system.cpu1.timesIdled 216 # Number of times that the entire CPU went into an idle state and unscheduled itself 1086system.cpu1.idleCycles 5896 # Total number of cycles that the CPU has spent unscheduled due to idling 1087system.cpu1.quiesceCycles 46085 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1088system.cpu1.committedInsts 221178 # Number of Instructions Simulated 1089system.cpu1.committedOps 221178 # Number of Ops (including micro ops) Simulated 1090system.cpu1.cpi 0.734124 # CPI: Cycles Per Instruction 1091system.cpu1.cpi_total 0.734124 # CPI: Total CPI of All Threads 1092system.cpu1.ipc 1.362168 # IPC: Instructions Per Cycle 1093system.cpu1.ipc_total 1.362168 # IPC: Total IPC of All Threads 1094system.cpu1.int_regfile_reads 405088 # number of integer regfile reads 1095system.cpu1.int_regfile_writes 189742 # number of integer regfile writes 1096system.cpu1.fp_regfile_writes 64 # number of floating regfile writes 1097system.cpu1.misc_regfile_reads 116634 # number of misc regfile reads 1098system.cpu1.misc_regfile_writes 648 # number of misc regfile writes 1099system.cpu1.dcache.tags.replacements 0 # number of replacements 1100system.cpu1.dcache.tags.tagsinuse 25.592984 # Cycle average of tags in use 1101system.cpu1.dcache.tags.total_refs 42361 # Total number of references to valid blocks. 1102system.cpu1.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks. 1103system.cpu1.dcache.tags.avg_refs 1512.892857 # Average number of references to valid blocks. 1104system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1105system.cpu1.dcache.tags.occ_blocks::cpu1.data 25.592984 # Average occupied blocks per requestor 1106system.cpu1.dcache.tags.occ_percent::cpu1.data 0.049986 # Average percentage of cache occupancy 1107system.cpu1.dcache.tags.occ_percent::total 0.049986 # Average percentage of cache occupancy 1108system.cpu1.dcache.tags.occ_task_id_blocks::1024 28 # Occupied blocks per task id 1109system.cpu1.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id 1110system.cpu1.dcache.tags.occ_task_id_percent::1024 0.054688 # Percentage of cache occupancy per task id 1111system.cpu1.dcache.tags.tag_accesses 326938 # Number of tag accesses 1112system.cpu1.dcache.tags.data_accesses 326938 # Number of data accesses 1113system.cpu1.dcache.ReadReq_hits::cpu1.data 44990 # number of ReadReq hits 1114system.cpu1.dcache.ReadReq_hits::total 44990 # number of ReadReq hits 1115system.cpu1.dcache.WriteReq_hits::cpu1.data 35982 # number of WriteReq hits 1116system.cpu1.dcache.WriteReq_hits::total 35982 # number of WriteReq hits 1117system.cpu1.dcache.SwapReq_hits::cpu1.data 13 # number of SwapReq hits 1118system.cpu1.dcache.SwapReq_hits::total 13 # number of SwapReq hits 1119system.cpu1.dcache.demand_hits::cpu1.data 80972 # number of demand (read+write) hits 1120system.cpu1.dcache.demand_hits::total 80972 # number of demand (read+write) hits 1121system.cpu1.dcache.overall_hits::cpu1.data 80972 # number of overall hits 1122system.cpu1.dcache.overall_hits::total 80972 # number of overall hits 1123system.cpu1.dcache.ReadReq_misses::cpu1.data 461 # number of ReadReq misses 1124system.cpu1.dcache.ReadReq_misses::total 461 # number of ReadReq misses 1125system.cpu1.dcache.WriteReq_misses::cpu1.data 170 # number of WriteReq misses 1126system.cpu1.dcache.WriteReq_misses::total 170 # number of WriteReq misses 1127system.cpu1.dcache.SwapReq_misses::cpu1.data 56 # number of SwapReq misses 1128system.cpu1.dcache.SwapReq_misses::total 56 # number of SwapReq misses 1129system.cpu1.dcache.demand_misses::cpu1.data 631 # number of demand (read+write) misses 1130system.cpu1.dcache.demand_misses::total 631 # number of demand (read+write) misses 1131system.cpu1.dcache.overall_misses::cpu1.data 631 # number of overall misses 1132system.cpu1.dcache.overall_misses::total 631 # number of overall misses 1133system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 8707500 # number of ReadReq miss cycles 1134system.cpu1.dcache.ReadReq_miss_latency::total 8707500 # number of ReadReq miss cycles 1135system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 4222000 # number of WriteReq miss cycles 1136system.cpu1.dcache.WriteReq_miss_latency::total 4222000 # number of WriteReq miss cycles 1137system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 652500 # number of SwapReq miss cycles 1138system.cpu1.dcache.SwapReq_miss_latency::total 652500 # number of SwapReq miss cycles 1139system.cpu1.dcache.demand_miss_latency::cpu1.data 12929500 # number of demand (read+write) miss cycles 1140system.cpu1.dcache.demand_miss_latency::total 12929500 # number of demand (read+write) miss cycles 1141system.cpu1.dcache.overall_miss_latency::cpu1.data 12929500 # number of overall miss cycles 1142system.cpu1.dcache.overall_miss_latency::total 12929500 # number of overall miss cycles 1143system.cpu1.dcache.ReadReq_accesses::cpu1.data 45451 # number of ReadReq accesses(hits+misses) 1144system.cpu1.dcache.ReadReq_accesses::total 45451 # number of ReadReq accesses(hits+misses) 1145system.cpu1.dcache.WriteReq_accesses::cpu1.data 36152 # number of WriteReq accesses(hits+misses) 1146system.cpu1.dcache.WriteReq_accesses::total 36152 # number of WriteReq accesses(hits+misses) 1147system.cpu1.dcache.SwapReq_accesses::cpu1.data 69 # number of SwapReq accesses(hits+misses) 1148system.cpu1.dcache.SwapReq_accesses::total 69 # number of SwapReq accesses(hits+misses) 1149system.cpu1.dcache.demand_accesses::cpu1.data 81603 # number of demand (read+write) accesses 1150system.cpu1.dcache.demand_accesses::total 81603 # number of demand (read+write) accesses 1151system.cpu1.dcache.overall_accesses::cpu1.data 81603 # number of overall (read+write) accesses 1152system.cpu1.dcache.overall_accesses::total 81603 # number of overall (read+write) accesses 1153system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.010143 # miss rate for ReadReq accesses 1154system.cpu1.dcache.ReadReq_miss_rate::total 0.010143 # miss rate for ReadReq accesses 1155system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.004702 # miss rate for WriteReq accesses 1156system.cpu1.dcache.WriteReq_miss_rate::total 0.004702 # miss rate for WriteReq accesses 1157system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.811594 # miss rate for SwapReq accesses 1158system.cpu1.dcache.SwapReq_miss_rate::total 0.811594 # miss rate for SwapReq accesses 1159system.cpu1.dcache.demand_miss_rate::cpu1.data 0.007733 # miss rate for demand accesses 1160system.cpu1.dcache.demand_miss_rate::total 0.007733 # miss rate for demand accesses 1161system.cpu1.dcache.overall_miss_rate::cpu1.data 0.007733 # miss rate for overall accesses 1162system.cpu1.dcache.overall_miss_rate::total 0.007733 # miss rate for overall accesses 1163system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 18888.286334 # average ReadReq miss latency 1164system.cpu1.dcache.ReadReq_avg_miss_latency::total 18888.286334 # average ReadReq miss latency 1165system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 24835.294118 # average WriteReq miss latency 1166system.cpu1.dcache.WriteReq_avg_miss_latency::total 24835.294118 # average WriteReq miss latency 1167system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 11651.785714 # average SwapReq miss latency 1168system.cpu1.dcache.SwapReq_avg_miss_latency::total 11651.785714 # average SwapReq miss latency 1169system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20490.491284 # average overall miss latency 1170system.cpu1.dcache.demand_avg_miss_latency::total 20490.491284 # average overall miss latency 1171system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20490.491284 # average overall miss latency 1172system.cpu1.dcache.overall_avg_miss_latency::total 20490.491284 # average overall miss latency 1173system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1174system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1175system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1176system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1177system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1178system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1179system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1180system.cpu1.dcache.cache_copies 0 # number of cache copies performed 1181system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 303 # number of ReadReq MSHR hits 1182system.cpu1.dcache.ReadReq_mshr_hits::total 303 # number of ReadReq MSHR hits 1183system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 62 # number of WriteReq MSHR hits 1184system.cpu1.dcache.WriteReq_mshr_hits::total 62 # number of WriteReq MSHR hits 1185system.cpu1.dcache.demand_mshr_hits::cpu1.data 365 # number of demand (read+write) MSHR hits 1186system.cpu1.dcache.demand_mshr_hits::total 365 # number of demand (read+write) MSHR hits 1187system.cpu1.dcache.overall_mshr_hits::cpu1.data 365 # number of overall MSHR hits 1188system.cpu1.dcache.overall_mshr_hits::total 365 # number of overall MSHR hits 1189system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 158 # number of ReadReq MSHR misses 1190system.cpu1.dcache.ReadReq_mshr_misses::total 158 # number of ReadReq MSHR misses 1191system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 108 # number of WriteReq MSHR misses 1192system.cpu1.dcache.WriteReq_mshr_misses::total 108 # number of WriteReq MSHR misses 1193system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 56 # number of SwapReq MSHR misses 1194system.cpu1.dcache.SwapReq_mshr_misses::total 56 # number of SwapReq MSHR misses 1195system.cpu1.dcache.demand_mshr_misses::cpu1.data 266 # number of demand (read+write) MSHR misses 1196system.cpu1.dcache.demand_mshr_misses::total 266 # number of demand (read+write) MSHR misses 1197system.cpu1.dcache.overall_mshr_misses::cpu1.data 266 # number of overall MSHR misses 1198system.cpu1.dcache.overall_mshr_misses::total 266 # number of overall MSHR misses 1199system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1924500 # number of ReadReq MSHR miss cycles 1200system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1924500 # number of ReadReq MSHR miss cycles 1201system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1959500 # number of WriteReq MSHR miss cycles 1202system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1959500 # number of WriteReq MSHR miss cycles 1203system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 596500 # number of SwapReq MSHR miss cycles 1204system.cpu1.dcache.SwapReq_mshr_miss_latency::total 596500 # number of SwapReq MSHR miss cycles 1205system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3884000 # number of demand (read+write) MSHR miss cycles 1206system.cpu1.dcache.demand_mshr_miss_latency::total 3884000 # number of demand (read+write) MSHR miss cycles 1207system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3884000 # number of overall MSHR miss cycles 1208system.cpu1.dcache.overall_mshr_miss_latency::total 3884000 # number of overall MSHR miss cycles 1209system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003476 # mshr miss rate for ReadReq accesses 1210system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003476 # mshr miss rate for ReadReq accesses 1211system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.002987 # mshr miss rate for WriteReq accesses 1212system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.002987 # mshr miss rate for WriteReq accesses 1213system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.811594 # mshr miss rate for SwapReq accesses 1214system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.811594 # mshr miss rate for SwapReq accesses 1215system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.003260 # mshr miss rate for demand accesses 1216system.cpu1.dcache.demand_mshr_miss_rate::total 0.003260 # mshr miss rate for demand accesses 1217system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.003260 # mshr miss rate for overall accesses 1218system.cpu1.dcache.overall_mshr_miss_rate::total 0.003260 # mshr miss rate for overall accesses 1219system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12180.379747 # average ReadReq mshr miss latency 1220system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12180.379747 # average ReadReq mshr miss latency 1221system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 18143.518519 # average WriteReq mshr miss latency 1222system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 18143.518519 # average WriteReq mshr miss latency 1223system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 10651.785714 # average SwapReq mshr miss latency 1224system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 10651.785714 # average SwapReq mshr miss latency 1225system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14601.503759 # average overall mshr miss latency 1226system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14601.503759 # average overall mshr miss latency 1227system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14601.503759 # average overall mshr miss latency 1228system.cpu1.dcache.overall_avg_mshr_miss_latency::total 14601.503759 # average overall mshr miss latency 1229system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1230system.cpu1.icache.tags.replacements 385 # number of replacements 1231system.cpu1.icache.tags.tagsinuse 85.488179 # Cycle average of tags in use 1232system.cpu1.icache.tags.total_refs 19990 # Total number of references to valid blocks. 1233system.cpu1.icache.tags.sampled_refs 500 # Sample count of references to valid blocks. 1234system.cpu1.icache.tags.avg_refs 39.980000 # Average number of references to valid blocks. 1235system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1236system.cpu1.icache.tags.occ_blocks::cpu1.inst 85.488179 # Average occupied blocks per requestor 1237system.cpu1.icache.tags.occ_percent::cpu1.inst 0.166969 # Average percentage of cache occupancy 1238system.cpu1.icache.tags.occ_percent::total 0.166969 # Average percentage of cache occupancy 1239system.cpu1.icache.tags.occ_task_id_blocks::1024 115 # Occupied blocks per task id 1240system.cpu1.icache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id 1241system.cpu1.icache.tags.age_task_id_blocks_1024::1 104 # Occupied blocks per task id 1242system.cpu1.icache.tags.occ_task_id_percent::1024 0.224609 # Percentage of cache occupancy per task id 1243system.cpu1.icache.tags.tag_accesses 21076 # Number of tag accesses 1244system.cpu1.icache.tags.data_accesses 21076 # Number of data accesses 1245system.cpu1.icache.ReadReq_hits::cpu1.inst 19990 # number of ReadReq hits 1246system.cpu1.icache.ReadReq_hits::total 19990 # number of ReadReq hits 1247system.cpu1.icache.demand_hits::cpu1.inst 19990 # number of demand (read+write) hits 1248system.cpu1.icache.demand_hits::total 19990 # number of demand (read+write) hits 1249system.cpu1.icache.overall_hits::cpu1.inst 19990 # number of overall hits 1250system.cpu1.icache.overall_hits::total 19990 # number of overall hits 1251system.cpu1.icache.ReadReq_misses::cpu1.inst 586 # number of ReadReq misses 1252system.cpu1.icache.ReadReq_misses::total 586 # number of ReadReq misses 1253system.cpu1.icache.demand_misses::cpu1.inst 586 # number of demand (read+write) misses 1254system.cpu1.icache.demand_misses::total 586 # number of demand (read+write) misses 1255system.cpu1.icache.overall_misses::cpu1.inst 586 # number of overall misses 1256system.cpu1.icache.overall_misses::total 586 # number of overall misses 1257system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 14253000 # number of ReadReq miss cycles 1258system.cpu1.icache.ReadReq_miss_latency::total 14253000 # number of ReadReq miss cycles 1259system.cpu1.icache.demand_miss_latency::cpu1.inst 14253000 # number of demand (read+write) miss cycles 1260system.cpu1.icache.demand_miss_latency::total 14253000 # number of demand (read+write) miss cycles 1261system.cpu1.icache.overall_miss_latency::cpu1.inst 14253000 # number of overall miss cycles 1262system.cpu1.icache.overall_miss_latency::total 14253000 # number of overall miss cycles 1263system.cpu1.icache.ReadReq_accesses::cpu1.inst 20576 # number of ReadReq accesses(hits+misses) 1264system.cpu1.icache.ReadReq_accesses::total 20576 # number of ReadReq accesses(hits+misses) 1265system.cpu1.icache.demand_accesses::cpu1.inst 20576 # number of demand (read+write) accesses 1266system.cpu1.icache.demand_accesses::total 20576 # number of demand (read+write) accesses 1267system.cpu1.icache.overall_accesses::cpu1.inst 20576 # number of overall (read+write) accesses 1268system.cpu1.icache.overall_accesses::total 20576 # number of overall (read+write) accesses 1269system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.028480 # miss rate for ReadReq accesses 1270system.cpu1.icache.ReadReq_miss_rate::total 0.028480 # miss rate for ReadReq accesses 1271system.cpu1.icache.demand_miss_rate::cpu1.inst 0.028480 # miss rate for demand accesses 1272system.cpu1.icache.demand_miss_rate::total 0.028480 # miss rate for demand accesses 1273system.cpu1.icache.overall_miss_rate::cpu1.inst 0.028480 # miss rate for overall accesses 1274system.cpu1.icache.overall_miss_rate::total 0.028480 # miss rate for overall accesses 1275system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 24322.525597 # average ReadReq miss latency 1276system.cpu1.icache.ReadReq_avg_miss_latency::total 24322.525597 # average ReadReq miss latency 1277system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 24322.525597 # average overall miss latency 1278system.cpu1.icache.demand_avg_miss_latency::total 24322.525597 # average overall miss latency 1279system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 24322.525597 # average overall miss latency 1280system.cpu1.icache.overall_avg_miss_latency::total 24322.525597 # average overall miss latency 1281system.cpu1.icache.blocked_cycles::no_mshrs 114 # number of cycles access was blocked 1282system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1283system.cpu1.icache.blocked::no_mshrs 2 # number of cycles access was blocked 1284system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1285system.cpu1.icache.avg_blocked_cycles::no_mshrs 57 # average number of cycles each access was blocked 1286system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1287system.cpu1.icache.fast_writes 0 # number of fast writes performed 1288system.cpu1.icache.cache_copies 0 # number of cache copies performed 1289system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 86 # number of ReadReq MSHR hits 1290system.cpu1.icache.ReadReq_mshr_hits::total 86 # number of ReadReq MSHR hits 1291system.cpu1.icache.demand_mshr_hits::cpu1.inst 86 # number of demand (read+write) MSHR hits 1292system.cpu1.icache.demand_mshr_hits::total 86 # number of demand (read+write) MSHR hits 1293system.cpu1.icache.overall_mshr_hits::cpu1.inst 86 # number of overall MSHR hits 1294system.cpu1.icache.overall_mshr_hits::total 86 # number of overall MSHR hits 1295system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 500 # number of ReadReq MSHR misses 1296system.cpu1.icache.ReadReq_mshr_misses::total 500 # number of ReadReq MSHR misses 1297system.cpu1.icache.demand_mshr_misses::cpu1.inst 500 # number of demand (read+write) MSHR misses 1298system.cpu1.icache.demand_mshr_misses::total 500 # number of demand (read+write) MSHR misses 1299system.cpu1.icache.overall_mshr_misses::cpu1.inst 500 # number of overall MSHR misses 1300system.cpu1.icache.overall_mshr_misses::total 500 # number of overall MSHR misses 1301system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 11778500 # number of ReadReq MSHR miss cycles 1302system.cpu1.icache.ReadReq_mshr_miss_latency::total 11778500 # number of ReadReq MSHR miss cycles 1303system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 11778500 # number of demand (read+write) MSHR miss cycles 1304system.cpu1.icache.demand_mshr_miss_latency::total 11778500 # number of demand (read+write) MSHR miss cycles 1305system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 11778500 # number of overall MSHR miss cycles 1306system.cpu1.icache.overall_mshr_miss_latency::total 11778500 # number of overall MSHR miss cycles 1307system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024300 # mshr miss rate for ReadReq accesses 1308system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024300 # mshr miss rate for ReadReq accesses 1309system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024300 # mshr miss rate for demand accesses 1310system.cpu1.icache.demand_mshr_miss_rate::total 0.024300 # mshr miss rate for demand accesses 1311system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024300 # mshr miss rate for overall accesses 1312system.cpu1.icache.overall_mshr_miss_rate::total 0.024300 # mshr miss rate for overall accesses 1313system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 23557 # average ReadReq mshr miss latency 1314system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 23557 # average ReadReq mshr miss latency 1315system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 23557 # average overall mshr miss latency 1316system.cpu1.icache.demand_avg_mshr_miss_latency::total 23557 # average overall mshr miss latency 1317system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 23557 # average overall mshr miss latency 1318system.cpu1.icache.overall_avg_mshr_miss_latency::total 23557 # average overall mshr miss latency 1319system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1320system.cpu2.branchPred.lookups 40179 # Number of BP lookups 1321system.cpu2.branchPred.condPredicted 36730 # Number of conditional branches predicted 1322system.cpu2.branchPred.condIncorrect 1284 # Number of conditional branches incorrect 1323system.cpu2.branchPred.BTBLookups 32851 # Number of BTB lookups 1324system.cpu2.branchPred.BTBHits 31814 # Number of BTB hits 1325system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 1326system.cpu2.branchPred.BTBHitPct 96.843323 # BTB Hit Percentage 1327system.cpu2.branchPred.usedRAS 891 # Number of times the RAS was used to get a target. 1328system.cpu2.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions. 1329system.cpu2.numCycles 162000 # number of cpu cycles simulated 1330system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started 1331system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed 1332system.cpu2.fetch.icacheStallCycles 38502 # Number of cycles fetch is stalled on an Icache miss 1333system.cpu2.fetch.Insts 208114 # Number of instructions fetch has processed 1334system.cpu2.fetch.Branches 40179 # Number of branches that fetch encountered 1335system.cpu2.fetch.predictedBranches 32705 # Number of branches that fetch has predicted taken 1336system.cpu2.fetch.Cycles 119095 # Number of cycles fetch has run and was not squashing or blocked 1337system.cpu2.fetch.SquashCycles 2725 # Number of cycles fetch has spent squashing 1338system.cpu2.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 1339system.cpu2.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from 1340system.cpu2.fetch.PendingTrapStallCycles 1151 # Number of stall cycles due to pending traps 1341system.cpu2.fetch.CacheLines 29772 # Number of cache lines fetched 1342system.cpu2.fetch.IcacheSquashes 430 # Number of outstanding Icache misses that were squashed 1343system.cpu2.fetch.rateDist::samples 160123 # Number of instructions fetched each cycle (Total) 1344system.cpu2.fetch.rateDist::mean 1.299713 # Number of instructions fetched each cycle (Total) 1345system.cpu2.fetch.rateDist::stdev 1.967894 # Number of instructions fetched each cycle (Total) 1346system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 1347system.cpu2.fetch.rateDist::0 78817 49.22% 49.22% # Number of instructions fetched each cycle (Total) 1348system.cpu2.fetch.rateDist::1 43234 27.00% 76.22% # Number of instructions fetched each cycle (Total) 1349system.cpu2.fetch.rateDist::2 10666 6.66% 82.88% # Number of instructions fetched each cycle (Total) 1350system.cpu2.fetch.rateDist::3 3447 2.15% 85.04% # Number of instructions fetched each cycle (Total) 1351system.cpu2.fetch.rateDist::4 1063 0.66% 85.70% # Number of instructions fetched each cycle (Total) 1352system.cpu2.fetch.rateDist::5 17019 10.63% 96.33% # Number of instructions fetched each cycle (Total) 1353system.cpu2.fetch.rateDist::6 1193 0.75% 97.07% # Number of instructions fetched each cycle (Total) 1354system.cpu2.fetch.rateDist::7 770 0.48% 97.56% # Number of instructions fetched each cycle (Total) 1355system.cpu2.fetch.rateDist::8 3914 2.44% 100.00% # Number of instructions fetched each cycle (Total) 1356system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 1357system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1358system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 1359system.cpu2.fetch.rateDist::total 160123 # Number of instructions fetched each cycle (Total) 1360system.cpu2.fetch.branchRate 0.248019 # Number of branch fetches per cycle 1361system.cpu2.fetch.rate 1.284654 # Number of inst fetches per cycle 1362system.cpu2.decode.IdleCycles 17927 # Number of cycles decode is idle 1363system.cpu2.decode.BlockedCycles 88037 # Number of cycles decode is blocked 1364system.cpu2.decode.RunCycles 47537 # Number of cycles decode is running 1365system.cpu2.decode.UnblockCycles 5250 # Number of cycles decode is unblocking 1366system.cpu2.decode.SquashCycles 1362 # Number of cycles decode is squashing 1367system.cpu2.decode.DecodedInsts 193193 # Number of instructions handled by decode 1368system.cpu2.rename.SquashCycles 1362 # Number of cycles rename is squashing 1369system.cpu2.rename.IdleCycles 18611 # Number of cycles rename is idle 1370system.cpu2.rename.BlockCycles 44936 # Number of cycles rename is blocking 1371system.cpu2.rename.serializeStallCycles 13295 # count of cycles rename stalled for serializing inst 1372system.cpu2.rename.RunCycles 49321 # Number of cycles rename is running 1373system.cpu2.rename.UnblockCycles 32588 # Number of cycles rename is unblocking 1374system.cpu2.rename.RenamedInsts 189743 # Number of instructions processed by rename 1375system.cpu2.rename.IQFullEvents 29082 # Number of times rename has blocked due to IQ full 1376system.cpu2.rename.LQFullEvents 12 # Number of times rename has blocked due to LQ full 1377system.cpu2.rename.FullRegisterEvents 2 # Number of times there has been no free registers 1378system.cpu2.rename.RenamedOperands 129905 # Number of destination operands rename has renamed 1379system.cpu2.rename.RenameLookups 340650 # Number of register rename lookups that rename has made 1380system.cpu2.rename.int_rename_lookups 270570 # Number of integer rename lookups 1381system.cpu2.rename.CommittedMaps 115581 # Number of HB maps that are committed 1382system.cpu2.rename.UndoneMaps 14324 # Number of HB maps that are undone due to squashing 1383system.cpu2.rename.serializingInsts 1221 # count of serializing insts renamed 1384system.cpu2.rename.tempSerializingInsts 1285 # count of temporary serializing insts renamed 1385system.cpu2.rename.skidInsts 37412 # count of insts added to the skid buffer 1386system.cpu2.memDep0.insertedLoads 47453 # Number of loads inserted to the mem dependence unit. 1387system.cpu2.memDep0.insertedStores 19802 # Number of stores inserted to the mem dependence unit. 1388system.cpu2.memDep0.conflictingLoads 23979 # Number of conflicting loads. 1389system.cpu2.memDep0.conflictingStores 14667 # Number of conflicting stores. 1390system.cpu2.iq.iqInstsAdded 152040 # Number of instructions added to the IQ (excludes non-spec) 1391system.cpu2.iq.iqNonSpecInstsAdded 10334 # Number of non-speculative instructions added to the IQ 1392system.cpu2.iq.iqInstsIssued 157175 # Number of instructions issued 1393system.cpu2.iq.iqSquashedInstsIssued 54 # Number of squashed instructions issued 1394system.cpu2.iq.iqSquashedInstsExamined 13577 # Number of squashed instructions iterated over during squash; mainly for profiling 1395system.cpu2.iq.iqSquashedOperandsExamined 11994 # Number of squashed operands that are examined and possibly removed from graph 1396system.cpu2.iq.iqSquashedNonSpecRemoved 781 # Number of squashed non-spec instructions that were removed 1397system.cpu2.iq.issued_per_cycle::samples 160123 # Number of insts issued each cycle 1398system.cpu2.iq.issued_per_cycle::mean 0.981589 # Number of insts issued each cycle 1399system.cpu2.iq.issued_per_cycle::stdev 1.305622 # Number of insts issued each cycle 1400system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 1401system.cpu2.iq.issued_per_cycle::0 83163 51.94% 51.94% # Number of insts issued each cycle 1402system.cpu2.iq.issued_per_cycle::1 32837 20.51% 72.44% # Number of insts issued each cycle 1403system.cpu2.iq.issued_per_cycle::2 19129 11.95% 84.39% # Number of insts issued each cycle 1404system.cpu2.iq.issued_per_cycle::3 18742 11.70% 96.10% # Number of insts issued each cycle 1405system.cpu2.iq.issued_per_cycle::4 3350 2.09% 98.19% # Number of insts issued each cycle 1406system.cpu2.iq.issued_per_cycle::5 1588 0.99% 99.18% # Number of insts issued each cycle 1407system.cpu2.iq.issued_per_cycle::6 888 0.55% 99.73% # Number of insts issued each cycle 1408system.cpu2.iq.issued_per_cycle::7 222 0.14% 99.87% # Number of insts issued each cycle 1409system.cpu2.iq.issued_per_cycle::8 204 0.13% 100.00% # Number of insts issued each cycle 1410system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1411system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1412system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 1413system.cpu2.iq.issued_per_cycle::total 160123 # Number of insts issued each cycle 1414system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 1415system.cpu2.iq.fu_full::IntAlu 85 23.42% 23.42% # attempts to use FU when none available 1416system.cpu2.iq.fu_full::IntMult 0 0.00% 23.42% # attempts to use FU when none available 1417system.cpu2.iq.fu_full::IntDiv 0 0.00% 23.42% # attempts to use FU when none available 1418system.cpu2.iq.fu_full::FloatAdd 0 0.00% 23.42% # attempts to use FU when none available 1419system.cpu2.iq.fu_full::FloatCmp 0 0.00% 23.42% # attempts to use FU when none available 1420system.cpu2.iq.fu_full::FloatCvt 0 0.00% 23.42% # attempts to use FU when none available 1421system.cpu2.iq.fu_full::FloatMult 0 0.00% 23.42% # attempts to use FU when none available 1422system.cpu2.iq.fu_full::FloatDiv 0 0.00% 23.42% # attempts to use FU when none available 1423system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 23.42% # attempts to use FU when none available 1424system.cpu2.iq.fu_full::SimdAdd 0 0.00% 23.42% # attempts to use FU when none available 1425system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 23.42% # attempts to use FU when none available 1426system.cpu2.iq.fu_full::SimdAlu 0 0.00% 23.42% # attempts to use FU when none available 1427system.cpu2.iq.fu_full::SimdCmp 0 0.00% 23.42% # attempts to use FU when none available 1428system.cpu2.iq.fu_full::SimdCvt 0 0.00% 23.42% # attempts to use FU when none available 1429system.cpu2.iq.fu_full::SimdMisc 0 0.00% 23.42% # attempts to use FU when none available 1430system.cpu2.iq.fu_full::SimdMult 0 0.00% 23.42% # attempts to use FU when none available 1431system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 23.42% # attempts to use FU when none available 1432system.cpu2.iq.fu_full::SimdShift 0 0.00% 23.42% # attempts to use FU when none available 1433system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 23.42% # attempts to use FU when none available 1434system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 23.42% # attempts to use FU when none available 1435system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 23.42% # attempts to use FU when none available 1436system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 23.42% # attempts to use FU when none available 1437system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 23.42% # attempts to use FU when none available 1438system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 23.42% # attempts to use FU when none available 1439system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 23.42% # attempts to use FU when none available 1440system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 23.42% # attempts to use FU when none available 1441system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 23.42% # attempts to use FU when none available 1442system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 23.42% # attempts to use FU when none available 1443system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 23.42% # attempts to use FU when none available 1444system.cpu2.iq.fu_full::MemRead 69 19.01% 42.42% # attempts to use FU when none available 1445system.cpu2.iq.fu_full::MemWrite 209 57.58% 100.00% # attempts to use FU when none available 1446system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 1447system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 1448system.cpu2.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 1449system.cpu2.iq.FU_type_0::IntAlu 82729 52.63% 52.63% # Type of FU issued 1450system.cpu2.iq.FU_type_0::IntMult 0 0.00% 52.63% # Type of FU issued 1451system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 52.63% # Type of FU issued 1452system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 52.63% # Type of FU issued 1453system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 52.63% # Type of FU issued 1454system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 52.63% # Type of FU issued 1455system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 52.63% # Type of FU issued 1456system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 52.63% # Type of FU issued 1457system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 52.63% # Type of FU issued 1458system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 52.63% # Type of FU issued 1459system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 52.63% # Type of FU issued 1460system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 52.63% # Type of FU issued 1461system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 52.63% # Type of FU issued 1462system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 52.63% # Type of FU issued 1463system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 52.63% # Type of FU issued 1464system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 52.63% # Type of FU issued 1465system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 52.63% # Type of FU issued 1466system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 52.63% # Type of FU issued 1467system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.63% # Type of FU issued 1468system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 52.63% # Type of FU issued 1469system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.63% # Type of FU issued 1470system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.63% # Type of FU issued 1471system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 52.63% # Type of FU issued 1472system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.63% # Type of FU issued 1473system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.63% # Type of FU issued 1474system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 52.63% # Type of FU issued 1475system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 52.63% # Type of FU issued 1476system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.63% # Type of FU issued 1477system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.63% # Type of FU issued 1478system.cpu2.iq.FU_type_0::MemRead 55347 35.21% 87.85% # Type of FU issued 1479system.cpu2.iq.FU_type_0::MemWrite 19099 12.15% 100.00% # Type of FU issued 1480system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 1481system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 1482system.cpu2.iq.FU_type_0::total 157175 # Type of FU issued 1483system.cpu2.iq.rate 0.970216 # Inst issue rate 1484system.cpu2.iq.fu_busy_cnt 363 # FU busy when requested 1485system.cpu2.iq.fu_busy_rate 0.002310 # FU busy rate (busy events/executed inst) 1486system.cpu2.iq.int_inst_queue_reads 474890 # Number of integer instruction queue reads 1487system.cpu2.iq.int_inst_queue_writes 175995 # Number of integer instruction queue writes 1488system.cpu2.iq.int_inst_queue_wakeup_accesses 155491 # Number of integer instruction queue wakeup accesses 1489system.cpu2.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads 1490system.cpu2.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes 1491system.cpu2.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses 1492system.cpu2.iq.int_alu_accesses 157538 # Number of integer alu accesses 1493system.cpu2.iq.fp_alu_accesses 0 # Number of floating point alu accesses 1494system.cpu2.iew.lsq.thread0.forwLoads 14398 # Number of loads that had data forwarded from stores 1495system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 1496system.cpu2.iew.lsq.thread0.squashedLoads 2822 # Number of loads squashed 1497system.cpu2.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed 1498system.cpu2.iew.lsq.thread0.memOrderViolation 44 # Number of memory ordering violations 1499system.cpu2.iew.lsq.thread0.squashedStores 1616 # Number of stores squashed 1500system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 1501system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 1502system.cpu2.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 1503system.cpu2.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked 1504system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle 1505system.cpu2.iew.iewSquashCycles 1362 # Number of cycles IEW is squashing 1506system.cpu2.iew.iewBlockCycles 11555 # Number of cycles IEW is blocking 1507system.cpu2.iew.iewUnblockCycles 80 # Number of cycles IEW is unblocking 1508system.cpu2.iew.iewDispatchedInsts 187117 # Number of instructions dispatched to IQ 1509system.cpu2.iew.iewDispSquashedInsts 206 # Number of squashed instructions skipped by dispatch 1510system.cpu2.iew.iewDispLoadInsts 47453 # Number of dispatched load instructions 1511system.cpu2.iew.iewDispStoreInsts 19802 # Number of dispatched store instructions 1512system.cpu2.iew.iewDispNonSpecInsts 1131 # Number of dispatched non-speculative instructions 1513system.cpu2.iew.iewIQFullEvents 44 # Number of times the IQ has become full, causing a stall 1514system.cpu2.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 1515system.cpu2.iew.memOrderViolationEvents 44 # Number of memory order violations 1516system.cpu2.iew.predictedTakenIncorrect 462 # Number of branches that were predicted taken incorrectly 1517system.cpu2.iew.predictedNotTakenIncorrect 1028 # Number of branches that were predicted not taken incorrectly 1518system.cpu2.iew.branchMispredicts 1490 # Number of branch mispredicts detected at execute 1519system.cpu2.iew.iewExecutedInsts 156065 # Number of executed instructions 1520system.cpu2.iew.iewExecLoadInsts 46210 # Number of load instructions executed 1521system.cpu2.iew.iewExecSquashedInsts 1110 # Number of squashed instructions skipped in execute 1522system.cpu2.iew.exec_swp 0 # number of swp insts executed 1523system.cpu2.iew.exec_nop 24743 # number of nop insts executed 1524system.cpu2.iew.exec_refs 65197 # number of memory reference insts executed 1525system.cpu2.iew.exec_branches 33975 # Number of branches executed 1526system.cpu2.iew.exec_stores 18987 # Number of stores executed 1527system.cpu2.iew.exec_rate 0.963364 # Inst execution rate 1528system.cpu2.iew.wb_sent 155796 # cumulative count of insts sent to commit 1529system.cpu2.iew.wb_count 155491 # cumulative count of insts written-back 1530system.cpu2.iew.wb_producers 82775 # num instructions producing a value 1531system.cpu2.iew.wb_consumers 89322 # num instructions consuming a value 1532system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 1533system.cpu2.iew.wb_rate 0.959821 # insts written-back per cycle 1534system.cpu2.iew.wb_fanout 0.926703 # average fanout of values written-back 1535system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 1536system.cpu2.commit.commitSquashedInsts 14525 # The number of squashed insts skipped by commit 1537system.cpu2.commit.commitNonSpecStalls 9553 # The number of times commit has been forced to stall to communicate backwards 1538system.cpu2.commit.branchMispredicts 1284 # The number of times a branch was mispredicted 1539system.cpu2.commit.committed_per_cycle::samples 157478 # Number of insts commited each cycle 1540system.cpu2.commit.committed_per_cycle::mean 1.095639 # Number of insts commited each cycle 1541system.cpu2.commit.committed_per_cycle::stdev 1.783689 # Number of insts commited each cycle 1542system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 1543system.cpu2.commit.committed_per_cycle::0 92218 58.56% 58.56% # Number of insts commited each cycle 1544system.cpu2.commit.committed_per_cycle::1 30640 19.46% 78.02% # Number of insts commited each cycle 1545system.cpu2.commit.committed_per_cycle::2 5207 3.31% 81.32% # Number of insts commited each cycle 1546system.cpu2.commit.committed_per_cycle::3 10311 6.55% 87.87% # Number of insts commited each cycle 1547system.cpu2.commit.committed_per_cycle::4 1532 0.97% 88.84% # Number of insts commited each cycle 1548system.cpu2.commit.committed_per_cycle::5 14554 9.24% 98.08% # Number of insts commited each cycle 1549system.cpu2.commit.committed_per_cycle::6 759 0.48% 98.57% # Number of insts commited each cycle 1550system.cpu2.commit.committed_per_cycle::7 956 0.61% 99.17% # Number of insts commited each cycle 1551system.cpu2.commit.committed_per_cycle::8 1301 0.83% 100.00% # Number of insts commited each cycle 1552system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 1553system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 1554system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 1555system.cpu2.commit.committed_per_cycle::total 157478 # Number of insts commited each cycle 1556system.cpu2.commit.committedInsts 172539 # Number of instructions committed 1557system.cpu2.commit.committedOps 172539 # Number of ops (including micro ops) committed 1558system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed 1559system.cpu2.commit.refs 62817 # Number of memory references committed 1560system.cpu2.commit.loads 44631 # Number of loads committed 1561system.cpu2.commit.membars 8825 # Number of memory barriers committed 1562system.cpu2.commit.branches 32966 # Number of branches committed 1563system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions. 1564system.cpu2.commit.int_insts 117894 # Number of committed integer instructions. 1565system.cpu2.commit.function_calls 322 # Number of function calls committed. 1566system.cpu2.commit.op_class_0::No_OpClass 23742 13.76% 13.76% # Class of committed instruction 1567system.cpu2.commit.op_class_0::IntAlu 77155 44.72% 58.48% # Class of committed instruction 1568system.cpu2.commit.op_class_0::IntMult 0 0.00% 58.48% # Class of committed instruction 1569system.cpu2.commit.op_class_0::IntDiv 0 0.00% 58.48% # Class of committed instruction 1570system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 58.48% # Class of committed instruction 1571system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 58.48% # Class of committed instruction 1572system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 58.48% # Class of committed instruction 1573system.cpu2.commit.op_class_0::FloatMult 0 0.00% 58.48% # Class of committed instruction 1574system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 58.48% # Class of committed instruction 1575system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 58.48% # Class of committed instruction 1576system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 58.48% # Class of committed instruction 1577system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 58.48% # Class of committed instruction 1578system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 58.48% # Class of committed instruction 1579system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 58.48% # Class of committed instruction 1580system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 58.48% # Class of committed instruction 1581system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 58.48% # Class of committed instruction 1582system.cpu2.commit.op_class_0::SimdMult 0 0.00% 58.48% # Class of committed instruction 1583system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 58.48% # Class of committed instruction 1584system.cpu2.commit.op_class_0::SimdShift 0 0.00% 58.48% # Class of committed instruction 1585system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 58.48% # Class of committed instruction 1586system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 58.48% # Class of committed instruction 1587system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 58.48% # Class of committed instruction 1588system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 58.48% # Class of committed instruction 1589system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 58.48% # Class of committed instruction 1590system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 58.48% # Class of committed instruction 1591system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 58.48% # Class of committed instruction 1592system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 58.48% # Class of committed instruction 1593system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 58.48% # Class of committed instruction 1594system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 58.48% # Class of committed instruction 1595system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 58.48% # Class of committed instruction 1596system.cpu2.commit.op_class_0::MemRead 53456 30.98% 89.46% # Class of committed instruction 1597system.cpu2.commit.op_class_0::MemWrite 18186 10.54% 100.00% # Class of committed instruction 1598system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 1599system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 1600system.cpu2.commit.op_class_0::total 172539 # Class of committed instruction 1601system.cpu2.commit.bw_lim_events 1301 # number cycles where commit BW limit reached 1602system.cpu2.rob.rob_reads 342655 # The number of ROB reads 1603system.cpu2.rob.rob_writes 376773 # The number of ROB writes 1604system.cpu2.timesIdled 206 # Number of times that the entire CPU went into an idle state and unscheduled itself 1605system.cpu2.idleCycles 1877 # Total number of cycles that the CPU has spent unscheduled due to idling 1606system.cpu2.quiesceCycles 46457 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1607system.cpu2.committedInsts 139972 # Number of Instructions Simulated 1608system.cpu2.committedOps 139972 # Number of Ops (including micro ops) Simulated 1609system.cpu2.cpi 1.157374 # CPI: Cycles Per Instruction 1610system.cpu2.cpi_total 1.157374 # CPI: Total CPI of All Threads 1611system.cpu2.ipc 0.864025 # IPC: Instructions Per Cycle 1612system.cpu2.ipc_total 0.864025 # IPC: Total IPC of All Threads 1613system.cpu2.int_regfile_reads 255225 # number of integer regfile reads 1614system.cpu2.int_regfile_writes 121437 # number of integer regfile writes 1615system.cpu2.fp_regfile_writes 64 # number of floating regfile writes 1616system.cpu2.misc_regfile_reads 66781 # number of misc regfile reads 1617system.cpu2.misc_regfile_writes 648 # number of misc regfile writes 1618system.cpu2.dcache.tags.replacements 0 # number of replacements 1619system.cpu2.dcache.tags.tagsinuse 23.055357 # Cycle average of tags in use 1620system.cpu2.dcache.tags.total_refs 24315 # Total number of references to valid blocks. 1621system.cpu2.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. 1622system.cpu2.dcache.tags.avg_refs 838.448276 # Average number of references to valid blocks. 1623system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1624system.cpu2.dcache.tags.occ_blocks::cpu2.data 23.055357 # Average occupied blocks per requestor 1625system.cpu2.dcache.tags.occ_percent::cpu2.data 0.045030 # Average percentage of cache occupancy 1626system.cpu2.dcache.tags.occ_percent::total 0.045030 # Average percentage of cache occupancy 1627system.cpu2.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id 1628system.cpu2.dcache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id 1629system.cpu2.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id 1630system.cpu2.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id 1631system.cpu2.dcache.tags.tag_accesses 200189 # Number of tag accesses 1632system.cpu2.dcache.tags.data_accesses 200189 # Number of data accesses 1633system.cpu2.dcache.ReadReq_hits::cpu2.data 31354 # number of ReadReq hits 1634system.cpu2.dcache.ReadReq_hits::total 31354 # number of ReadReq hits 1635system.cpu2.dcache.WriteReq_hits::cpu2.data 17953 # number of WriteReq hits 1636system.cpu2.dcache.WriteReq_hits::total 17953 # number of WriteReq hits 1637system.cpu2.dcache.SwapReq_hits::cpu2.data 17 # number of SwapReq hits 1638system.cpu2.dcache.SwapReq_hits::total 17 # number of SwapReq hits 1639system.cpu2.dcache.demand_hits::cpu2.data 49307 # number of demand (read+write) hits 1640system.cpu2.dcache.demand_hits::total 49307 # number of demand (read+write) hits 1641system.cpu2.dcache.overall_hits::cpu2.data 49307 # number of overall hits 1642system.cpu2.dcache.overall_hits::total 49307 # number of overall hits 1643system.cpu2.dcache.ReadReq_misses::cpu2.data 441 # number of ReadReq misses 1644system.cpu2.dcache.ReadReq_misses::total 441 # number of ReadReq misses 1645system.cpu2.dcache.WriteReq_misses::cpu2.data 151 # number of WriteReq misses 1646system.cpu2.dcache.WriteReq_misses::total 151 # number of WriteReq misses 1647system.cpu2.dcache.SwapReq_misses::cpu2.data 65 # number of SwapReq misses 1648system.cpu2.dcache.SwapReq_misses::total 65 # number of SwapReq misses 1649system.cpu2.dcache.demand_misses::cpu2.data 592 # number of demand (read+write) misses 1650system.cpu2.dcache.demand_misses::total 592 # number of demand (read+write) misses 1651system.cpu2.dcache.overall_misses::cpu2.data 592 # number of overall misses 1652system.cpu2.dcache.overall_misses::total 592 # number of overall misses 1653system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 6519500 # number of ReadReq miss cycles 1654system.cpu2.dcache.ReadReq_miss_latency::total 6519500 # number of ReadReq miss cycles 1655system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 3142000 # number of WriteReq miss cycles 1656system.cpu2.dcache.WriteReq_miss_latency::total 3142000 # number of WriteReq miss cycles 1657system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 710000 # number of SwapReq miss cycles 1658system.cpu2.dcache.SwapReq_miss_latency::total 710000 # number of SwapReq miss cycles 1659system.cpu2.dcache.demand_miss_latency::cpu2.data 9661500 # number of demand (read+write) miss cycles 1660system.cpu2.dcache.demand_miss_latency::total 9661500 # number of demand (read+write) miss cycles 1661system.cpu2.dcache.overall_miss_latency::cpu2.data 9661500 # number of overall miss cycles 1662system.cpu2.dcache.overall_miss_latency::total 9661500 # number of overall miss cycles 1663system.cpu2.dcache.ReadReq_accesses::cpu2.data 31795 # number of ReadReq accesses(hits+misses) 1664system.cpu2.dcache.ReadReq_accesses::total 31795 # number of ReadReq accesses(hits+misses) 1665system.cpu2.dcache.WriteReq_accesses::cpu2.data 18104 # number of WriteReq accesses(hits+misses) 1666system.cpu2.dcache.WriteReq_accesses::total 18104 # number of WriteReq accesses(hits+misses) 1667system.cpu2.dcache.SwapReq_accesses::cpu2.data 82 # number of SwapReq accesses(hits+misses) 1668system.cpu2.dcache.SwapReq_accesses::total 82 # number of SwapReq accesses(hits+misses) 1669system.cpu2.dcache.demand_accesses::cpu2.data 49899 # number of demand (read+write) accesses 1670system.cpu2.dcache.demand_accesses::total 49899 # number of demand (read+write) accesses 1671system.cpu2.dcache.overall_accesses::cpu2.data 49899 # number of overall (read+write) accesses 1672system.cpu2.dcache.overall_accesses::total 49899 # number of overall (read+write) accesses 1673system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.013870 # miss rate for ReadReq accesses 1674system.cpu2.dcache.ReadReq_miss_rate::total 0.013870 # miss rate for ReadReq accesses 1675system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.008341 # miss rate for WriteReq accesses 1676system.cpu2.dcache.WriteReq_miss_rate::total 0.008341 # miss rate for WriteReq accesses 1677system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.792683 # miss rate for SwapReq accesses 1678system.cpu2.dcache.SwapReq_miss_rate::total 0.792683 # miss rate for SwapReq accesses 1679system.cpu2.dcache.demand_miss_rate::cpu2.data 0.011864 # miss rate for demand accesses 1680system.cpu2.dcache.demand_miss_rate::total 0.011864 # miss rate for demand accesses 1681system.cpu2.dcache.overall_miss_rate::cpu2.data 0.011864 # miss rate for overall accesses 1682system.cpu2.dcache.overall_miss_rate::total 0.011864 # miss rate for overall accesses 1683system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 14783.446712 # average ReadReq miss latency 1684system.cpu2.dcache.ReadReq_avg_miss_latency::total 14783.446712 # average ReadReq miss latency 1685system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 20807.947020 # average WriteReq miss latency 1686system.cpu2.dcache.WriteReq_avg_miss_latency::total 20807.947020 # average WriteReq miss latency 1687system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 10923.076923 # average SwapReq miss latency 1688system.cpu2.dcache.SwapReq_avg_miss_latency::total 10923.076923 # average SwapReq miss latency 1689system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 16320.101351 # average overall miss latency 1690system.cpu2.dcache.demand_avg_miss_latency::total 16320.101351 # average overall miss latency 1691system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 16320.101351 # average overall miss latency 1692system.cpu2.dcache.overall_avg_miss_latency::total 16320.101351 # average overall miss latency 1693system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1694system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1695system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1696system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked 1697system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1698system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1699system.cpu2.dcache.fast_writes 0 # number of fast writes performed 1700system.cpu2.dcache.cache_copies 0 # number of cache copies performed 1701system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 267 # number of ReadReq MSHR hits 1702system.cpu2.dcache.ReadReq_mshr_hits::total 267 # number of ReadReq MSHR hits 1703system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 54 # number of WriteReq MSHR hits 1704system.cpu2.dcache.WriteReq_mshr_hits::total 54 # number of WriteReq MSHR hits 1705system.cpu2.dcache.demand_mshr_hits::cpu2.data 321 # number of demand (read+write) MSHR hits 1706system.cpu2.dcache.demand_mshr_hits::total 321 # number of demand (read+write) MSHR hits 1707system.cpu2.dcache.overall_mshr_hits::cpu2.data 321 # number of overall MSHR hits 1708system.cpu2.dcache.overall_mshr_hits::total 321 # number of overall MSHR hits 1709system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 174 # number of ReadReq MSHR misses 1710system.cpu2.dcache.ReadReq_mshr_misses::total 174 # number of ReadReq MSHR misses 1711system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 97 # number of WriteReq MSHR misses 1712system.cpu2.dcache.WriteReq_mshr_misses::total 97 # number of WriteReq MSHR misses 1713system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 65 # number of SwapReq MSHR misses 1714system.cpu2.dcache.SwapReq_mshr_misses::total 65 # number of SwapReq MSHR misses 1715system.cpu2.dcache.demand_mshr_misses::cpu2.data 271 # number of demand (read+write) MSHR misses 1716system.cpu2.dcache.demand_mshr_misses::total 271 # number of demand (read+write) MSHR misses 1717system.cpu2.dcache.overall_mshr_misses::cpu2.data 271 # number of overall MSHR misses 1718system.cpu2.dcache.overall_mshr_misses::total 271 # number of overall MSHR misses 1719system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1675000 # number of ReadReq MSHR miss cycles 1720system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1675000 # number of ReadReq MSHR miss cycles 1721system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1750000 # number of WriteReq MSHR miss cycles 1722system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1750000 # number of WriteReq MSHR miss cycles 1723system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 645000 # number of SwapReq MSHR miss cycles 1724system.cpu2.dcache.SwapReq_mshr_miss_latency::total 645000 # number of SwapReq MSHR miss cycles 1725system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3425000 # number of demand (read+write) MSHR miss cycles 1726system.cpu2.dcache.demand_mshr_miss_latency::total 3425000 # number of demand (read+write) MSHR miss cycles 1727system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3425000 # number of overall MSHR miss cycles 1728system.cpu2.dcache.overall_mshr_miss_latency::total 3425000 # number of overall MSHR miss cycles 1729system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.005473 # mshr miss rate for ReadReq accesses 1730system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.005473 # mshr miss rate for ReadReq accesses 1731system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.005358 # mshr miss rate for WriteReq accesses 1732system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.005358 # mshr miss rate for WriteReq accesses 1733system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.792683 # mshr miss rate for SwapReq accesses 1734system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.792683 # mshr miss rate for SwapReq accesses 1735system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.005431 # mshr miss rate for demand accesses 1736system.cpu2.dcache.demand_mshr_miss_rate::total 0.005431 # mshr miss rate for demand accesses 1737system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.005431 # mshr miss rate for overall accesses 1738system.cpu2.dcache.overall_mshr_miss_rate::total 0.005431 # mshr miss rate for overall accesses 1739system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 9626.436782 # average ReadReq mshr miss latency 1740system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 9626.436782 # average ReadReq mshr miss latency 1741system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 18041.237113 # average WriteReq mshr miss latency 1742system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 18041.237113 # average WriteReq mshr miss latency 1743system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 9923.076923 # average SwapReq mshr miss latency 1744system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 9923.076923 # average SwapReq mshr miss latency 1745system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 12638.376384 # average overall mshr miss latency 1746system.cpu2.dcache.demand_avg_mshr_miss_latency::total 12638.376384 # average overall mshr miss latency 1747system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 12638.376384 # average overall mshr miss latency 1748system.cpu2.dcache.overall_avg_mshr_miss_latency::total 12638.376384 # average overall mshr miss latency 1749system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1750system.cpu2.icache.tags.replacements 387 # number of replacements 1751system.cpu2.icache.tags.tagsinuse 74.683777 # Cycle average of tags in use 1752system.cpu2.icache.tags.total_refs 29208 # Total number of references to valid blocks. 1753system.cpu2.icache.tags.sampled_refs 496 # Sample count of references to valid blocks. 1754system.cpu2.icache.tags.avg_refs 58.887097 # Average number of references to valid blocks. 1755system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1756system.cpu2.icache.tags.occ_blocks::cpu2.inst 74.683777 # Average occupied blocks per requestor 1757system.cpu2.icache.tags.occ_percent::cpu2.inst 0.145867 # Average percentage of cache occupancy 1758system.cpu2.icache.tags.occ_percent::total 0.145867 # Average percentage of cache occupancy 1759system.cpu2.icache.tags.occ_task_id_blocks::1024 109 # Occupied blocks per task id 1760system.cpu2.icache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id 1761system.cpu2.icache.tags.age_task_id_blocks_1024::1 98 # Occupied blocks per task id 1762system.cpu2.icache.tags.occ_task_id_percent::1024 0.212891 # Percentage of cache occupancy per task id 1763system.cpu2.icache.tags.tag_accesses 30268 # Number of tag accesses 1764system.cpu2.icache.tags.data_accesses 30268 # Number of data accesses 1765system.cpu2.icache.ReadReq_hits::cpu2.inst 29208 # number of ReadReq hits 1766system.cpu2.icache.ReadReq_hits::total 29208 # number of ReadReq hits 1767system.cpu2.icache.demand_hits::cpu2.inst 29208 # number of demand (read+write) hits 1768system.cpu2.icache.demand_hits::total 29208 # number of demand (read+write) hits 1769system.cpu2.icache.overall_hits::cpu2.inst 29208 # number of overall hits 1770system.cpu2.icache.overall_hits::total 29208 # number of overall hits 1771system.cpu2.icache.ReadReq_misses::cpu2.inst 564 # number of ReadReq misses 1772system.cpu2.icache.ReadReq_misses::total 564 # number of ReadReq misses 1773system.cpu2.icache.demand_misses::cpu2.inst 564 # number of demand (read+write) misses 1774system.cpu2.icache.demand_misses::total 564 # number of demand (read+write) misses 1775system.cpu2.icache.overall_misses::cpu2.inst 564 # number of overall misses 1776system.cpu2.icache.overall_misses::total 564 # number of overall misses 1777system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 7822000 # number of ReadReq miss cycles 1778system.cpu2.icache.ReadReq_miss_latency::total 7822000 # number of ReadReq miss cycles 1779system.cpu2.icache.demand_miss_latency::cpu2.inst 7822000 # number of demand (read+write) miss cycles 1780system.cpu2.icache.demand_miss_latency::total 7822000 # number of demand (read+write) miss cycles 1781system.cpu2.icache.overall_miss_latency::cpu2.inst 7822000 # number of overall miss cycles 1782system.cpu2.icache.overall_miss_latency::total 7822000 # number of overall miss cycles 1783system.cpu2.icache.ReadReq_accesses::cpu2.inst 29772 # number of ReadReq accesses(hits+misses) 1784system.cpu2.icache.ReadReq_accesses::total 29772 # number of ReadReq accesses(hits+misses) 1785system.cpu2.icache.demand_accesses::cpu2.inst 29772 # number of demand (read+write) accesses 1786system.cpu2.icache.demand_accesses::total 29772 # number of demand (read+write) accesses 1787system.cpu2.icache.overall_accesses::cpu2.inst 29772 # number of overall (read+write) accesses 1788system.cpu2.icache.overall_accesses::total 29772 # number of overall (read+write) accesses 1789system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.018944 # miss rate for ReadReq accesses 1790system.cpu2.icache.ReadReq_miss_rate::total 0.018944 # miss rate for ReadReq accesses 1791system.cpu2.icache.demand_miss_rate::cpu2.inst 0.018944 # miss rate for demand accesses 1792system.cpu2.icache.demand_miss_rate::total 0.018944 # miss rate for demand accesses 1793system.cpu2.icache.overall_miss_rate::cpu2.inst 0.018944 # miss rate for overall accesses 1794system.cpu2.icache.overall_miss_rate::total 0.018944 # miss rate for overall accesses 1795system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 13868.794326 # average ReadReq miss latency 1796system.cpu2.icache.ReadReq_avg_miss_latency::total 13868.794326 # average ReadReq miss latency 1797system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 13868.794326 # average overall miss latency 1798system.cpu2.icache.demand_avg_miss_latency::total 13868.794326 # average overall miss latency 1799system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 13868.794326 # average overall miss latency 1800system.cpu2.icache.overall_avg_miss_latency::total 13868.794326 # average overall miss latency 1801system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1802system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1803system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1804system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked 1805system.cpu2.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1806system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1807system.cpu2.icache.fast_writes 0 # number of fast writes performed 1808system.cpu2.icache.cache_copies 0 # number of cache copies performed 1809system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 68 # number of ReadReq MSHR hits 1810system.cpu2.icache.ReadReq_mshr_hits::total 68 # number of ReadReq MSHR hits 1811system.cpu2.icache.demand_mshr_hits::cpu2.inst 68 # number of demand (read+write) MSHR hits 1812system.cpu2.icache.demand_mshr_hits::total 68 # number of demand (read+write) MSHR hits 1813system.cpu2.icache.overall_mshr_hits::cpu2.inst 68 # number of overall MSHR hits 1814system.cpu2.icache.overall_mshr_hits::total 68 # number of overall MSHR hits 1815system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 496 # number of ReadReq MSHR misses 1816system.cpu2.icache.ReadReq_mshr_misses::total 496 # number of ReadReq MSHR misses 1817system.cpu2.icache.demand_mshr_misses::cpu2.inst 496 # number of demand (read+write) MSHR misses 1818system.cpu2.icache.demand_mshr_misses::total 496 # number of demand (read+write) MSHR misses 1819system.cpu2.icache.overall_mshr_misses::cpu2.inst 496 # number of overall MSHR misses 1820system.cpu2.icache.overall_mshr_misses::total 496 # number of overall MSHR misses 1821system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 6709500 # number of ReadReq MSHR miss cycles 1822system.cpu2.icache.ReadReq_mshr_miss_latency::total 6709500 # number of ReadReq MSHR miss cycles 1823system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 6709500 # number of demand (read+write) MSHR miss cycles 1824system.cpu2.icache.demand_mshr_miss_latency::total 6709500 # number of demand (read+write) MSHR miss cycles 1825system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 6709500 # number of overall MSHR miss cycles 1826system.cpu2.icache.overall_mshr_miss_latency::total 6709500 # number of overall MSHR miss cycles 1827system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.016660 # mshr miss rate for ReadReq accesses 1828system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.016660 # mshr miss rate for ReadReq accesses 1829system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.016660 # mshr miss rate for demand accesses 1830system.cpu2.icache.demand_mshr_miss_rate::total 0.016660 # mshr miss rate for demand accesses 1831system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.016660 # mshr miss rate for overall accesses 1832system.cpu2.icache.overall_mshr_miss_rate::total 0.016660 # mshr miss rate for overall accesses 1833system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 13527.217742 # average ReadReq mshr miss latency 1834system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 13527.217742 # average ReadReq mshr miss latency 1835system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 13527.217742 # average overall mshr miss latency 1836system.cpu2.icache.demand_avg_mshr_miss_latency::total 13527.217742 # average overall mshr miss latency 1837system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 13527.217742 # average overall mshr miss latency 1838system.cpu2.icache.overall_avg_mshr_miss_latency::total 13527.217742 # average overall mshr miss latency 1839system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1840system.cpu3.branchPred.lookups 59537 # Number of BP lookups 1841system.cpu3.branchPred.condPredicted 56113 # Number of conditional branches predicted 1842system.cpu3.branchPred.condIncorrect 1261 # Number of conditional branches incorrect 1843system.cpu3.branchPred.BTBLookups 52336 # Number of BTB lookups 1844system.cpu3.branchPred.BTBHits 51268 # Number of BTB hits 1845system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 1846system.cpu3.branchPred.BTBHitPct 97.959340 # BTB Hit Percentage 1847system.cpu3.branchPred.usedRAS 894 # Number of times the RAS was used to get a target. 1848system.cpu3.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions. 1849system.cpu3.numCycles 161647 # number of cpu cycles simulated 1850system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started 1851system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed 1852system.cpu3.fetch.icacheStallCycles 26901 # Number of cycles fetch is stalled on an Icache miss 1853system.cpu3.fetch.Insts 335954 # Number of instructions fetch has processed 1854system.cpu3.fetch.Branches 59537 # Number of branches that fetch encountered 1855system.cpu3.fetch.predictedBranches 52162 # Number of branches that fetch has predicted taken 1856system.cpu3.fetch.Cycles 130682 # Number of cycles fetch has run and was not squashing or blocked 1857system.cpu3.fetch.SquashCycles 2681 # Number of cycles fetch has spent squashing 1858system.cpu3.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 1859system.cpu3.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from 1860system.cpu3.fetch.PendingTrapStallCycles 1202 # Number of stall cycles due to pending traps 1861system.cpu3.fetch.IcacheWaitRetryStallCycles 14 # Number of stall cycles due to full MSHR 1862system.cpu3.fetch.CacheLines 18139 # Number of cache lines fetched 1863system.cpu3.fetch.IcacheSquashes 423 # Number of outstanding Icache misses that were squashed 1864system.cpu3.fetch.rateDist::samples 160153 # Number of instructions fetched each cycle (Total) 1865system.cpu3.fetch.rateDist::mean 2.097707 # Number of instructions fetched each cycle (Total) 1866system.cpu3.fetch.rateDist::stdev 2.240976 # Number of instructions fetched each cycle (Total) 1867system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 1868system.cpu3.fetch.rateDist::0 45773 28.58% 28.58% # Number of instructions fetched each cycle (Total) 1869system.cpu3.fetch.rateDist::1 56940 35.55% 64.13% # Number of instructions fetched each cycle (Total) 1870system.cpu3.fetch.rateDist::2 4846 3.03% 67.16% # Number of instructions fetched each cycle (Total) 1871system.cpu3.fetch.rateDist::3 3496 2.18% 69.34% # Number of instructions fetched each cycle (Total) 1872system.cpu3.fetch.rateDist::4 1060 0.66% 70.00% # Number of instructions fetched each cycle (Total) 1873system.cpu3.fetch.rateDist::5 42180 26.34% 96.34% # Number of instructions fetched each cycle (Total) 1874system.cpu3.fetch.rateDist::6 1201 0.75% 97.09% # Number of instructions fetched each cycle (Total) 1875system.cpu3.fetch.rateDist::7 768 0.48% 97.57% # Number of instructions fetched each cycle (Total) 1876system.cpu3.fetch.rateDist::8 3889 2.43% 100.00% # Number of instructions fetched each cycle (Total) 1877system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 1878system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1879system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 1880system.cpu3.fetch.rateDist::total 160153 # Number of instructions fetched each cycle (Total) 1881system.cpu3.fetch.branchRate 0.368315 # Number of branch fetches per cycle 1882system.cpu3.fetch.rate 2.078319 # Number of inst fetches per cycle 1883system.cpu3.decode.IdleCycles 16971 # Number of cycles decode is idle 1884system.cpu3.decode.BlockedCycles 42083 # Number of cycles decode is blocked 1885system.cpu3.decode.RunCycles 97172 # Number of cycles decode is running 1886system.cpu3.decode.UnblockCycles 2577 # Number of cycles decode is unblocking 1887system.cpu3.decode.SquashCycles 1340 # Number of cycles decode is squashing 1888system.cpu3.decode.DecodedInsts 322134 # Number of instructions handled by decode 1889system.cpu3.rename.SquashCycles 1340 # Number of cycles rename is squashing 1890system.cpu3.rename.IdleCycles 17645 # Number of cycles rename is idle 1891system.cpu3.rename.BlockCycles 17747 # Number of cycles rename is blocking 1892system.cpu3.rename.serializeStallCycles 12855 # count of cycles rename stalled for serializing inst 1893system.cpu3.rename.RunCycles 98257 # Number of cycles rename is running 1894system.cpu3.rename.UnblockCycles 12299 # Number of cycles rename is unblocking 1895system.cpu3.rename.RenamedInsts 318864 # Number of instructions processed by rename 1896system.cpu3.rename.IQFullEvents 10783 # Number of times rename has blocked due to IQ full 1897system.cpu3.rename.LQFullEvents 17 # Number of times rename has blocked due to LQ full 1898system.cpu3.rename.FullRegisterEvents 2 # Number of times there has been no free registers 1899system.cpu3.rename.RenamedOperands 225541 # Number of destination operands rename has renamed 1900system.cpu3.rename.RenameLookups 621446 # Number of register rename lookups that rename has made 1901system.cpu3.rename.int_rename_lookups 481213 # Number of integer rename lookups 1902system.cpu3.rename.CommittedMaps 211532 # Number of HB maps that are committed 1903system.cpu3.rename.UndoneMaps 14009 # Number of HB maps that are undone due to squashing 1904system.cpu3.rename.serializingInsts 1171 # count of serializing insts renamed 1905system.cpu3.rename.tempSerializingInsts 1234 # count of temporary serializing insts renamed 1906system.cpu3.rename.skidInsts 16730 # count of insts added to the skid buffer 1907system.cpu3.memDep0.insertedLoads 92339 # Number of loads inserted to the mem dependence unit. 1908system.cpu3.memDep0.insertedStores 45060 # Number of stores inserted to the mem dependence unit. 1909system.cpu3.memDep0.conflictingLoads 43467 # Number of conflicting loads. 1910system.cpu3.memDep0.conflictingStores 39931 # Number of conflicting stores. 1911system.cpu3.iq.iqInstsAdded 267326 # Number of instructions added to the IQ (excludes non-spec) 1912system.cpu3.iq.iqNonSpecInstsAdded 4600 # Number of non-speculative instructions added to the IQ 1913system.cpu3.iq.iqInstsIssued 267770 # Number of instructions issued 1914system.cpu3.iq.iqSquashedInstsExamined 12807 # Number of squashed instructions iterated over during squash; mainly for profiling 1915system.cpu3.iq.iqSquashedOperandsExamined 10139 # Number of squashed operands that are examined and possibly removed from graph 1916system.cpu3.iq.iqSquashedNonSpecRemoved 551 # Number of squashed non-spec instructions that were removed 1917system.cpu3.iq.issued_per_cycle::samples 160153 # Number of insts issued each cycle 1918system.cpu3.iq.issued_per_cycle::mean 1.671964 # Number of insts issued each cycle 1919system.cpu3.iq.issued_per_cycle::stdev 1.354316 # Number of insts issued each cycle 1920system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 1921system.cpu3.iq.issued_per_cycle::0 48755 30.44% 30.44% # Number of insts issued each cycle 1922system.cpu3.iq.issued_per_cycle::1 16655 10.40% 40.84% # Number of insts issued each cycle 1923system.cpu3.iq.issued_per_cycle::2 44376 27.71% 68.55% # Number of insts issued each cycle 1924system.cpu3.iq.issued_per_cycle::3 43948 27.44% 95.99% # Number of insts issued each cycle 1925system.cpu3.iq.issued_per_cycle::4 3484 2.18% 98.17% # Number of insts issued each cycle 1926system.cpu3.iq.issued_per_cycle::5 1651 1.03% 99.20% # Number of insts issued each cycle 1927system.cpu3.iq.issued_per_cycle::6 861 0.54% 99.74% # Number of insts issued each cycle 1928system.cpu3.iq.issued_per_cycle::7 222 0.14% 99.87% # Number of insts issued each cycle 1929system.cpu3.iq.issued_per_cycle::8 201 0.13% 100.00% # Number of insts issued each cycle 1930system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1931system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1932system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 1933system.cpu3.iq.issued_per_cycle::total 160153 # Number of insts issued each cycle 1934system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 1935system.cpu3.iq.fu_full::IntAlu 86 25.67% 25.67% # attempts to use FU when none available 1936system.cpu3.iq.fu_full::IntMult 0 0.00% 25.67% # attempts to use FU when none available 1937system.cpu3.iq.fu_full::IntDiv 0 0.00% 25.67% # attempts to use FU when none available 1938system.cpu3.iq.fu_full::FloatAdd 0 0.00% 25.67% # attempts to use FU when none available 1939system.cpu3.iq.fu_full::FloatCmp 0 0.00% 25.67% # attempts to use FU when none available 1940system.cpu3.iq.fu_full::FloatCvt 0 0.00% 25.67% # attempts to use FU when none available 1941system.cpu3.iq.fu_full::FloatMult 0 0.00% 25.67% # attempts to use FU when none available 1942system.cpu3.iq.fu_full::FloatDiv 0 0.00% 25.67% # attempts to use FU when none available 1943system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 25.67% # attempts to use FU when none available 1944system.cpu3.iq.fu_full::SimdAdd 0 0.00% 25.67% # attempts to use FU when none available 1945system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 25.67% # attempts to use FU when none available 1946system.cpu3.iq.fu_full::SimdAlu 0 0.00% 25.67% # attempts to use FU when none available 1947system.cpu3.iq.fu_full::SimdCmp 0 0.00% 25.67% # attempts to use FU when none available 1948system.cpu3.iq.fu_full::SimdCvt 0 0.00% 25.67% # attempts to use FU when none available 1949system.cpu3.iq.fu_full::SimdMisc 0 0.00% 25.67% # attempts to use FU when none available 1950system.cpu3.iq.fu_full::SimdMult 0 0.00% 25.67% # attempts to use FU when none available 1951system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 25.67% # attempts to use FU when none available 1952system.cpu3.iq.fu_full::SimdShift 0 0.00% 25.67% # attempts to use FU when none available 1953system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 25.67% # attempts to use FU when none available 1954system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 25.67% # attempts to use FU when none available 1955system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 25.67% # attempts to use FU when none available 1956system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 25.67% # attempts to use FU when none available 1957system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 25.67% # attempts to use FU when none available 1958system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 25.67% # attempts to use FU when none available 1959system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 25.67% # attempts to use FU when none available 1960system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 25.67% # attempts to use FU when none available 1961system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 25.67% # attempts to use FU when none available 1962system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.67% # attempts to use FU when none available 1963system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 25.67% # attempts to use FU when none available 1964system.cpu3.iq.fu_full::MemRead 40 11.94% 37.61% # attempts to use FU when none available 1965system.cpu3.iq.fu_full::MemWrite 209 62.39% 100.00% # attempts to use FU when none available 1966system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 1967system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 1968system.cpu3.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 1969system.cpu3.iq.FU_type_0::IntAlu 128178 47.87% 47.87% # Type of FU issued 1970system.cpu3.iq.FU_type_0::IntMult 0 0.00% 47.87% # Type of FU issued 1971system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 47.87% # Type of FU issued 1972system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 47.87% # Type of FU issued 1973system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 47.87% # Type of FU issued 1974system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 47.87% # Type of FU issued 1975system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 47.87% # Type of FU issued 1976system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 47.87% # Type of FU issued 1977system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 47.87% # Type of FU issued 1978system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 47.87% # Type of FU issued 1979system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 47.87% # Type of FU issued 1980system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 47.87% # Type of FU issued 1981system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 47.87% # Type of FU issued 1982system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 47.87% # Type of FU issued 1983system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 47.87% # Type of FU issued 1984system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 47.87% # Type of FU issued 1985system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 47.87% # Type of FU issued 1986system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 47.87% # Type of FU issued 1987system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 47.87% # Type of FU issued 1988system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 47.87% # Type of FU issued 1989system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.87% # Type of FU issued 1990system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.87% # Type of FU issued 1991system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.87% # Type of FU issued 1992system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.87% # Type of FU issued 1993system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.87% # Type of FU issued 1994system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 47.87% # Type of FU issued 1995system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 47.87% # Type of FU issued 1996system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.87% # Type of FU issued 1997system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.87% # Type of FU issued 1998system.cpu3.iq.FU_type_0::MemRead 95149 35.53% 83.40% # Type of FU issued 1999system.cpu3.iq.FU_type_0::MemWrite 44443 16.60% 100.00% # Type of FU issued 2000system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 2001system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 2002system.cpu3.iq.FU_type_0::total 267770 # Type of FU issued 2003system.cpu3.iq.rate 1.656511 # Inst issue rate 2004system.cpu3.iq.fu_busy_cnt 335 # FU busy when requested 2005system.cpu3.iq.fu_busy_rate 0.001251 # FU busy rate (busy events/executed inst) 2006system.cpu3.iq.int_inst_queue_reads 696028 # Number of integer instruction queue reads 2007system.cpu3.iq.int_inst_queue_writes 284773 # Number of integer instruction queue writes 2008system.cpu3.iq.int_inst_queue_wakeup_accesses 266078 # Number of integer instruction queue wakeup accesses 2009system.cpu3.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads 2010system.cpu3.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes 2011system.cpu3.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses 2012system.cpu3.iq.int_alu_accesses 268105 # Number of integer alu accesses 2013system.cpu3.iq.fp_alu_accesses 0 # Number of floating point alu accesses 2014system.cpu3.iew.lsq.thread0.forwLoads 39763 # Number of loads that had data forwarded from stores 2015system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 2016system.cpu3.iew.lsq.thread0.squashedLoads 2450 # Number of loads squashed 2017system.cpu3.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed 2018system.cpu3.iew.lsq.thread0.memOrderViolation 40 # Number of memory ordering violations 2019system.cpu3.iew.lsq.thread0.squashedStores 1547 # Number of stores squashed 2020system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 2021system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 2022system.cpu3.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 2023system.cpu3.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked 2024system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle 2025system.cpu3.iew.iewSquashCycles 1340 # Number of cycles IEW is squashing 2026system.cpu3.iew.iewBlockCycles 5357 # Number of cycles IEW is blocking 2027system.cpu3.iew.iewUnblockCycles 49 # Number of cycles IEW is unblocking 2028system.cpu3.iew.iewDispatchedInsts 316296 # Number of instructions dispatched to IQ 2029system.cpu3.iew.iewDispSquashedInsts 170 # Number of squashed instructions skipped by dispatch 2030system.cpu3.iew.iewDispLoadInsts 92339 # Number of dispatched load instructions 2031system.cpu3.iew.iewDispStoreInsts 45060 # Number of dispatched store instructions 2032system.cpu3.iew.iewDispNonSpecInsts 1094 # Number of dispatched non-speculative instructions 2033system.cpu3.iew.iewIQFullEvents 36 # Number of times the IQ has become full, causing a stall 2034system.cpu3.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 2035system.cpu3.iew.memOrderViolationEvents 40 # Number of memory order violations 2036system.cpu3.iew.predictedTakenIncorrect 466 # Number of branches that were predicted taken incorrectly 2037system.cpu3.iew.predictedNotTakenIncorrect 1001 # Number of branches that were predicted not taken incorrectly 2038system.cpu3.iew.branchMispredicts 1467 # Number of branch mispredicts detected at execute 2039system.cpu3.iew.iewExecutedInsts 266621 # Number of executed instructions 2040system.cpu3.iew.iewExecLoadInsts 91475 # Number of load instructions executed 2041system.cpu3.iew.iewExecSquashedInsts 1149 # Number of squashed instructions skipped in execute 2042system.cpu3.iew.exec_swp 0 # number of swp insts executed 2043system.cpu3.iew.exec_nop 44370 # number of nop insts executed 2044system.cpu3.iew.exec_refs 135810 # number of memory reference insts executed 2045system.cpu3.iew.exec_branches 53906 # Number of branches executed 2046system.cpu3.iew.exec_stores 44335 # Number of stores executed 2047system.cpu3.iew.exec_rate 1.649403 # Inst execution rate 2048system.cpu3.iew.wb_sent 266372 # cumulative count of insts sent to commit 2049system.cpu3.iew.wb_count 266078 # cumulative count of insts written-back 2050system.cpu3.iew.wb_producers 153535 # num instructions producing a value 2051system.cpu3.iew.wb_consumers 160065 # num instructions consuming a value 2052system.cpu3.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 2053system.cpu3.iew.wb_rate 1.646044 # insts written-back per cycle 2054system.cpu3.iew.wb_fanout 0.959204 # average fanout of values written-back 2055system.cpu3.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 2056system.cpu3.commit.commitSquashedInsts 13497 # The number of squashed insts skipped by commit 2057system.cpu3.commit.commitNonSpecStalls 4049 # The number of times commit has been forced to stall to communicate backwards 2058system.cpu3.commit.branchMispredicts 1261 # The number of times a branch was mispredicted 2059system.cpu3.commit.committed_per_cycle::samples 157643 # Number of insts commited each cycle 2060system.cpu3.commit.committed_per_cycle::mean 1.920440 # Number of insts commited each cycle 2061system.cpu3.commit.committed_per_cycle::stdev 2.127029 # Number of insts commited each cycle 2062system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 2063system.cpu3.commit.committed_per_cycle::0 52663 33.41% 33.41% # Number of insts commited each cycle 2064system.cpu3.commit.committed_per_cycle::1 50442 32.00% 65.40% # Number of insts commited each cycle 2065system.cpu3.commit.committed_per_cycle::2 5240 3.32% 68.73% # Number of insts commited each cycle 2066system.cpu3.commit.committed_per_cycle::3 4903 3.11% 71.84% # Number of insts commited each cycle 2067system.cpu3.commit.committed_per_cycle::4 1534 0.97% 72.81% # Number of insts commited each cycle 2068system.cpu3.commit.committed_per_cycle::5 39716 25.19% 98.00% # Number of insts commited each cycle 2069system.cpu3.commit.committed_per_cycle::6 903 0.57% 98.58% # Number of insts commited each cycle 2070system.cpu3.commit.committed_per_cycle::7 957 0.61% 99.18% # Number of insts commited each cycle 2071system.cpu3.commit.committed_per_cycle::8 1285 0.82% 100.00% # Number of insts commited each cycle 2072system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 2073system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 2074system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 2075system.cpu3.commit.committed_per_cycle::total 157643 # Number of insts commited each cycle 2076system.cpu3.commit.committedInsts 302744 # Number of instructions committed 2077system.cpu3.commit.committedOps 302744 # Number of ops (including micro ops) committed 2078system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed 2079system.cpu3.commit.refs 133402 # Number of memory references committed 2080system.cpu3.commit.loads 89889 # Number of loads committed 2081system.cpu3.commit.membars 3344 # Number of memory barriers committed 2082system.cpu3.commit.branches 52826 # Number of branches committed 2083system.cpu3.commit.fp_insts 0 # Number of committed floating point instructions. 2084system.cpu3.commit.int_insts 208356 # Number of committed integer instructions. 2085system.cpu3.commit.function_calls 322 # Number of function calls committed. 2086system.cpu3.commit.op_class_0::No_OpClass 43625 14.41% 14.41% # Class of committed instruction 2087system.cpu3.commit.op_class_0::IntAlu 122373 40.42% 54.83% # Class of committed instruction 2088system.cpu3.commit.op_class_0::IntMult 0 0.00% 54.83% # Class of committed instruction 2089system.cpu3.commit.op_class_0::IntDiv 0 0.00% 54.83% # Class of committed instruction 2090system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 54.83% # Class of committed instruction 2091system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 54.83% # Class of committed instruction 2092system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 54.83% # Class of committed instruction 2093system.cpu3.commit.op_class_0::FloatMult 0 0.00% 54.83% # Class of committed instruction 2094system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 54.83% # Class of committed instruction 2095system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 54.83% # Class of committed instruction 2096system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 54.83% # Class of committed instruction 2097system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 54.83% # Class of committed instruction 2098system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 54.83% # Class of committed instruction 2099system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 54.83% # Class of committed instruction 2100system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 54.83% # Class of committed instruction 2101system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 54.83% # Class of committed instruction 2102system.cpu3.commit.op_class_0::SimdMult 0 0.00% 54.83% # Class of committed instruction 2103system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 54.83% # Class of committed instruction 2104system.cpu3.commit.op_class_0::SimdShift 0 0.00% 54.83% # Class of committed instruction 2105system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 54.83% # Class of committed instruction 2106system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 54.83% # Class of committed instruction 2107system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 54.83% # Class of committed instruction 2108system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 54.83% # Class of committed instruction 2109system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 54.83% # Class of committed instruction 2110system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 54.83% # Class of committed instruction 2111system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 54.83% # Class of committed instruction 2112system.cpu3.commit.op_class_0::SimdFloatMisc 0 0.00% 54.83% # Class of committed instruction 2113system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 54.83% # Class of committed instruction 2114system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 54.83% # Class of committed instruction 2115system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 54.83% # Class of committed instruction 2116system.cpu3.commit.op_class_0::MemRead 93233 30.80% 85.63% # Class of committed instruction 2117system.cpu3.commit.op_class_0::MemWrite 43513 14.37% 100.00% # Class of committed instruction 2118system.cpu3.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 2119system.cpu3.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 2120system.cpu3.commit.op_class_0::total 302744 # Class of committed instruction 2121system.cpu3.commit.bw_lim_events 1285 # number cycles where commit BW limit reached 2122system.cpu3.rob.rob_reads 472013 # The number of ROB reads 2123system.cpu3.rob.rob_writes 634991 # The number of ROB writes 2124system.cpu3.timesIdled 206 # Number of times that the entire CPU went into an idle state and unscheduled itself 2125system.cpu3.idleCycles 1494 # Total number of cycles that the CPU has spent unscheduled due to idling 2126system.cpu3.quiesceCycles 46809 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 2127system.cpu3.committedInsts 255775 # Number of Instructions Simulated 2128system.cpu3.committedOps 255775 # Number of Ops (including micro ops) Simulated 2129system.cpu3.cpi 0.631989 # CPI: Cycles Per Instruction 2130system.cpu3.cpi_total 0.631989 # CPI: Total CPI of All Threads 2131system.cpu3.ipc 1.582306 # IPC: Instructions Per Cycle 2132system.cpu3.ipc_total 1.582306 # IPC: Total IPC of All Threads 2133system.cpu3.int_regfile_reads 467282 # number of integer regfile reads 2134system.cpu3.int_regfile_writes 217631 # number of integer regfile writes 2135system.cpu3.fp_regfile_writes 64 # number of floating regfile writes 2136system.cpu3.misc_regfile_reads 137439 # number of misc regfile reads 2137system.cpu3.misc_regfile_writes 648 # number of misc regfile writes 2138system.cpu3.dcache.tags.replacements 0 # number of replacements 2139system.cpu3.dcache.tags.tagsinuse 24.171664 # Cycle average of tags in use 2140system.cpu3.dcache.tags.total_refs 49547 # Total number of references to valid blocks. 2141system.cpu3.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks. 2142system.cpu3.dcache.tags.avg_refs 1769.535714 # Average number of references to valid blocks. 2143system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 2144system.cpu3.dcache.tags.occ_blocks::cpu3.data 24.171664 # Average occupied blocks per requestor 2145system.cpu3.dcache.tags.occ_percent::cpu3.data 0.047210 # Average percentage of cache occupancy 2146system.cpu3.dcache.tags.occ_percent::total 0.047210 # Average percentage of cache occupancy 2147system.cpu3.dcache.tags.occ_task_id_blocks::1024 28 # Occupied blocks per task id 2148system.cpu3.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id 2149system.cpu3.dcache.tags.occ_task_id_percent::1024 0.054688 # Percentage of cache occupancy per task id 2150system.cpu3.dcache.tags.tag_accesses 381069 # Number of tag accesses 2151system.cpu3.dcache.tags.data_accesses 381069 # Number of data accesses 2152system.cpu3.dcache.ReadReq_hits::cpu3.data 51168 # number of ReadReq hits 2153system.cpu3.dcache.ReadReq_hits::total 51168 # number of ReadReq hits 2154system.cpu3.dcache.WriteReq_hits::cpu3.data 43290 # number of WriteReq hits 2155system.cpu3.dcache.WriteReq_hits::total 43290 # number of WriteReq hits 2156system.cpu3.dcache.SwapReq_hits::cpu3.data 10 # number of SwapReq hits 2157system.cpu3.dcache.SwapReq_hits::total 10 # number of SwapReq hits 2158system.cpu3.dcache.demand_hits::cpu3.data 94458 # number of demand (read+write) hits 2159system.cpu3.dcache.demand_hits::total 94458 # number of demand (read+write) hits 2160system.cpu3.dcache.overall_hits::cpu3.data 94458 # number of overall hits 2161system.cpu3.dcache.overall_hits::total 94458 # number of overall hits 2162system.cpu3.dcache.ReadReq_misses::cpu3.data 527 # number of ReadReq misses 2163system.cpu3.dcache.ReadReq_misses::total 527 # number of ReadReq misses 2164system.cpu3.dcache.WriteReq_misses::cpu3.data 164 # number of WriteReq misses 2165system.cpu3.dcache.WriteReq_misses::total 164 # number of WriteReq misses 2166system.cpu3.dcache.SwapReq_misses::cpu3.data 49 # number of SwapReq misses 2167system.cpu3.dcache.SwapReq_misses::total 49 # number of SwapReq misses 2168system.cpu3.dcache.demand_misses::cpu3.data 691 # number of demand (read+write) misses 2169system.cpu3.dcache.demand_misses::total 691 # number of demand (read+write) misses 2170system.cpu3.dcache.overall_misses::cpu3.data 691 # number of overall misses 2171system.cpu3.dcache.overall_misses::total 691 # number of overall misses 2172system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 8076500 # number of ReadReq miss cycles 2173system.cpu3.dcache.ReadReq_miss_latency::total 8076500 # number of ReadReq miss cycles 2174system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 3222500 # number of WriteReq miss cycles 2175system.cpu3.dcache.WriteReq_miss_latency::total 3222500 # number of WriteReq miss cycles 2176system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 607500 # number of SwapReq miss cycles 2177system.cpu3.dcache.SwapReq_miss_latency::total 607500 # number of SwapReq miss cycles 2178system.cpu3.dcache.demand_miss_latency::cpu3.data 11299000 # number of demand (read+write) miss cycles 2179system.cpu3.dcache.demand_miss_latency::total 11299000 # number of demand (read+write) miss cycles 2180system.cpu3.dcache.overall_miss_latency::cpu3.data 11299000 # number of overall miss cycles 2181system.cpu3.dcache.overall_miss_latency::total 11299000 # number of overall miss cycles 2182system.cpu3.dcache.ReadReq_accesses::cpu3.data 51695 # number of ReadReq accesses(hits+misses) 2183system.cpu3.dcache.ReadReq_accesses::total 51695 # number of ReadReq accesses(hits+misses) 2184system.cpu3.dcache.WriteReq_accesses::cpu3.data 43454 # number of WriteReq accesses(hits+misses) 2185system.cpu3.dcache.WriteReq_accesses::total 43454 # number of WriteReq accesses(hits+misses) 2186system.cpu3.dcache.SwapReq_accesses::cpu3.data 59 # number of SwapReq accesses(hits+misses) 2187system.cpu3.dcache.SwapReq_accesses::total 59 # number of SwapReq accesses(hits+misses) 2188system.cpu3.dcache.demand_accesses::cpu3.data 95149 # number of demand (read+write) accesses 2189system.cpu3.dcache.demand_accesses::total 95149 # number of demand (read+write) accesses 2190system.cpu3.dcache.overall_accesses::cpu3.data 95149 # number of overall (read+write) accesses 2191system.cpu3.dcache.overall_accesses::total 95149 # number of overall (read+write) accesses 2192system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.010194 # miss rate for ReadReq accesses 2193system.cpu3.dcache.ReadReq_miss_rate::total 0.010194 # miss rate for ReadReq accesses 2194system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.003774 # miss rate for WriteReq accesses 2195system.cpu3.dcache.WriteReq_miss_rate::total 0.003774 # miss rate for WriteReq accesses 2196system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.830508 # miss rate for SwapReq accesses 2197system.cpu3.dcache.SwapReq_miss_rate::total 0.830508 # miss rate for SwapReq accesses 2198system.cpu3.dcache.demand_miss_rate::cpu3.data 0.007262 # miss rate for demand accesses 2199system.cpu3.dcache.demand_miss_rate::total 0.007262 # miss rate for demand accesses 2200system.cpu3.dcache.overall_miss_rate::cpu3.data 0.007262 # miss rate for overall accesses 2201system.cpu3.dcache.overall_miss_rate::total 0.007262 # miss rate for overall accesses 2202system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 15325.426945 # average ReadReq miss latency 2203system.cpu3.dcache.ReadReq_avg_miss_latency::total 15325.426945 # average ReadReq miss latency 2204system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 19649.390244 # average WriteReq miss latency 2205system.cpu3.dcache.WriteReq_avg_miss_latency::total 19649.390244 # average WriteReq miss latency 2206system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 12397.959184 # average SwapReq miss latency 2207system.cpu3.dcache.SwapReq_avg_miss_latency::total 12397.959184 # average SwapReq miss latency 2208system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 16351.664255 # average overall miss latency 2209system.cpu3.dcache.demand_avg_miss_latency::total 16351.664255 # average overall miss latency 2210system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 16351.664255 # average overall miss latency 2211system.cpu3.dcache.overall_avg_miss_latency::total 16351.664255 # average overall miss latency 2212system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2213system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2214system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 2215system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked 2216system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2217system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2218system.cpu3.dcache.fast_writes 0 # number of fast writes performed 2219system.cpu3.dcache.cache_copies 0 # number of cache copies performed 2220system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 382 # number of ReadReq MSHR hits 2221system.cpu3.dcache.ReadReq_mshr_hits::total 382 # number of ReadReq MSHR hits 2222system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 52 # number of WriteReq MSHR hits 2223system.cpu3.dcache.WriteReq_mshr_hits::total 52 # number of WriteReq MSHR hits 2224system.cpu3.dcache.demand_mshr_hits::cpu3.data 434 # number of demand (read+write) MSHR hits 2225system.cpu3.dcache.demand_mshr_hits::total 434 # number of demand (read+write) MSHR hits 2226system.cpu3.dcache.overall_mshr_hits::cpu3.data 434 # number of overall MSHR hits 2227system.cpu3.dcache.overall_mshr_hits::total 434 # number of overall MSHR hits 2228system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 145 # number of ReadReq MSHR misses 2229system.cpu3.dcache.ReadReq_mshr_misses::total 145 # number of ReadReq MSHR misses 2230system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 112 # number of WriteReq MSHR misses 2231system.cpu3.dcache.WriteReq_mshr_misses::total 112 # number of WriteReq MSHR misses 2232system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 49 # number of SwapReq MSHR misses 2233system.cpu3.dcache.SwapReq_mshr_misses::total 49 # number of SwapReq MSHR misses 2234system.cpu3.dcache.demand_mshr_misses::cpu3.data 257 # number of demand (read+write) MSHR misses 2235system.cpu3.dcache.demand_mshr_misses::total 257 # number of demand (read+write) MSHR misses 2236system.cpu3.dcache.overall_mshr_misses::cpu3.data 257 # number of overall MSHR misses 2237system.cpu3.dcache.overall_mshr_misses::total 257 # number of overall MSHR misses 2238system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1368000 # number of ReadReq MSHR miss cycles 2239system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1368000 # number of ReadReq MSHR miss cycles 2240system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1719500 # number of WriteReq MSHR miss cycles 2241system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1719500 # number of WriteReq MSHR miss cycles 2242system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 558500 # number of SwapReq MSHR miss cycles 2243system.cpu3.dcache.SwapReq_mshr_miss_latency::total 558500 # number of SwapReq MSHR miss cycles 2244system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 3087500 # number of demand (read+write) MSHR miss cycles 2245system.cpu3.dcache.demand_mshr_miss_latency::total 3087500 # number of demand (read+write) MSHR miss cycles 2246system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 3087500 # number of overall MSHR miss cycles 2247system.cpu3.dcache.overall_mshr_miss_latency::total 3087500 # number of overall MSHR miss cycles 2248system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.002805 # mshr miss rate for ReadReq accesses 2249system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.002805 # mshr miss rate for ReadReq accesses 2250system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.002577 # mshr miss rate for WriteReq accesses 2251system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.002577 # mshr miss rate for WriteReq accesses 2252system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.830508 # mshr miss rate for SwapReq accesses 2253system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.830508 # mshr miss rate for SwapReq accesses 2254system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.002701 # mshr miss rate for demand accesses 2255system.cpu3.dcache.demand_mshr_miss_rate::total 0.002701 # mshr miss rate for demand accesses 2256system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.002701 # mshr miss rate for overall accesses 2257system.cpu3.dcache.overall_mshr_miss_rate::total 0.002701 # mshr miss rate for overall accesses 2258system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 9434.482759 # average ReadReq mshr miss latency 2259system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 9434.482759 # average ReadReq mshr miss latency 2260system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 15352.678571 # average WriteReq mshr miss latency 2261system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 15352.678571 # average WriteReq mshr miss latency 2262system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 11397.959184 # average SwapReq mshr miss latency 2263system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 11397.959184 # average SwapReq mshr miss latency 2264system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 12013.618677 # average overall mshr miss latency 2265system.cpu3.dcache.demand_avg_mshr_miss_latency::total 12013.618677 # average overall mshr miss latency 2266system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 12013.618677 # average overall mshr miss latency 2267system.cpu3.dcache.overall_avg_mshr_miss_latency::total 12013.618677 # average overall mshr miss latency 2268system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 2269system.cpu3.icache.tags.replacements 388 # number of replacements 2270system.cpu3.icache.tags.tagsinuse 77.972544 # Cycle average of tags in use 2271system.cpu3.icache.tags.total_refs 17573 # Total number of references to valid blocks. 2272system.cpu3.icache.tags.sampled_refs 498 # Sample count of references to valid blocks. 2273system.cpu3.icache.tags.avg_refs 35.287149 # Average number of references to valid blocks. 2274system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 2275system.cpu3.icache.tags.occ_blocks::cpu3.inst 77.972544 # Average occupied blocks per requestor 2276system.cpu3.icache.tags.occ_percent::cpu3.inst 0.152290 # Average percentage of cache occupancy 2277system.cpu3.icache.tags.occ_percent::total 0.152290 # Average percentage of cache occupancy 2278system.cpu3.icache.tags.occ_task_id_blocks::1024 110 # Occupied blocks per task id 2279system.cpu3.icache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id 2280system.cpu3.icache.tags.age_task_id_blocks_1024::1 99 # Occupied blocks per task id 2281system.cpu3.icache.tags.occ_task_id_percent::1024 0.214844 # Percentage of cache occupancy per task id 2282system.cpu3.icache.tags.tag_accesses 18637 # Number of tag accesses 2283system.cpu3.icache.tags.data_accesses 18637 # Number of data accesses 2284system.cpu3.icache.ReadReq_hits::cpu3.inst 17573 # number of ReadReq hits 2285system.cpu3.icache.ReadReq_hits::total 17573 # number of ReadReq hits 2286system.cpu3.icache.demand_hits::cpu3.inst 17573 # number of demand (read+write) hits 2287system.cpu3.icache.demand_hits::total 17573 # number of demand (read+write) hits 2288system.cpu3.icache.overall_hits::cpu3.inst 17573 # number of overall hits 2289system.cpu3.icache.overall_hits::total 17573 # number of overall hits 2290system.cpu3.icache.ReadReq_misses::cpu3.inst 566 # number of ReadReq misses 2291system.cpu3.icache.ReadReq_misses::total 566 # number of ReadReq misses 2292system.cpu3.icache.demand_misses::cpu3.inst 566 # number of demand (read+write) misses 2293system.cpu3.icache.demand_misses::total 566 # number of demand (read+write) misses 2294system.cpu3.icache.overall_misses::cpu3.inst 566 # number of overall misses 2295system.cpu3.icache.overall_misses::total 566 # number of overall misses 2296system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 7887000 # number of ReadReq miss cycles 2297system.cpu3.icache.ReadReq_miss_latency::total 7887000 # number of ReadReq miss cycles 2298system.cpu3.icache.demand_miss_latency::cpu3.inst 7887000 # number of demand (read+write) miss cycles 2299system.cpu3.icache.demand_miss_latency::total 7887000 # number of demand (read+write) miss cycles 2300system.cpu3.icache.overall_miss_latency::cpu3.inst 7887000 # number of overall miss cycles 2301system.cpu3.icache.overall_miss_latency::total 7887000 # number of overall miss cycles 2302system.cpu3.icache.ReadReq_accesses::cpu3.inst 18139 # number of ReadReq accesses(hits+misses) 2303system.cpu3.icache.ReadReq_accesses::total 18139 # number of ReadReq accesses(hits+misses) 2304system.cpu3.icache.demand_accesses::cpu3.inst 18139 # number of demand (read+write) accesses 2305system.cpu3.icache.demand_accesses::total 18139 # number of demand (read+write) accesses 2306system.cpu3.icache.overall_accesses::cpu3.inst 18139 # number of overall (read+write) accesses 2307system.cpu3.icache.overall_accesses::total 18139 # number of overall (read+write) accesses 2308system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.031203 # miss rate for ReadReq accesses 2309system.cpu3.icache.ReadReq_miss_rate::total 0.031203 # miss rate for ReadReq accesses 2310system.cpu3.icache.demand_miss_rate::cpu3.inst 0.031203 # miss rate for demand accesses 2311system.cpu3.icache.demand_miss_rate::total 0.031203 # miss rate for demand accesses 2312system.cpu3.icache.overall_miss_rate::cpu3.inst 0.031203 # miss rate for overall accesses 2313system.cpu3.icache.overall_miss_rate::total 0.031203 # miss rate for overall accesses 2314system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13934.628975 # average ReadReq miss latency 2315system.cpu3.icache.ReadReq_avg_miss_latency::total 13934.628975 # average ReadReq miss latency 2316system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13934.628975 # average overall miss latency 2317system.cpu3.icache.demand_avg_miss_latency::total 13934.628975 # average overall miss latency 2318system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13934.628975 # average overall miss latency 2319system.cpu3.icache.overall_avg_miss_latency::total 13934.628975 # average overall miss latency 2320system.cpu3.icache.blocked_cycles::no_mshrs 48 # number of cycles access was blocked 2321system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2322system.cpu3.icache.blocked::no_mshrs 2 # number of cycles access was blocked 2323system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked 2324system.cpu3.icache.avg_blocked_cycles::no_mshrs 24 # average number of cycles each access was blocked 2325system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2326system.cpu3.icache.fast_writes 0 # number of fast writes performed 2327system.cpu3.icache.cache_copies 0 # number of cache copies performed 2328system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 68 # number of ReadReq MSHR hits 2329system.cpu3.icache.ReadReq_mshr_hits::total 68 # number of ReadReq MSHR hits 2330system.cpu3.icache.demand_mshr_hits::cpu3.inst 68 # number of demand (read+write) MSHR hits 2331system.cpu3.icache.demand_mshr_hits::total 68 # number of demand (read+write) MSHR hits 2332system.cpu3.icache.overall_mshr_hits::cpu3.inst 68 # number of overall MSHR hits 2333system.cpu3.icache.overall_mshr_hits::total 68 # number of overall MSHR hits 2334system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 498 # number of ReadReq MSHR misses 2335system.cpu3.icache.ReadReq_mshr_misses::total 498 # number of ReadReq MSHR misses 2336system.cpu3.icache.demand_mshr_misses::cpu3.inst 498 # number of demand (read+write) MSHR misses 2337system.cpu3.icache.demand_mshr_misses::total 498 # number of demand (read+write) MSHR misses 2338system.cpu3.icache.overall_mshr_misses::cpu3.inst 498 # number of overall MSHR misses 2339system.cpu3.icache.overall_mshr_misses::total 498 # number of overall MSHR misses 2340system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 6839000 # number of ReadReq MSHR miss cycles 2341system.cpu3.icache.ReadReq_mshr_miss_latency::total 6839000 # number of ReadReq MSHR miss cycles 2342system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 6839000 # number of demand (read+write) MSHR miss cycles 2343system.cpu3.icache.demand_mshr_miss_latency::total 6839000 # number of demand (read+write) MSHR miss cycles 2344system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 6839000 # number of overall MSHR miss cycles 2345system.cpu3.icache.overall_mshr_miss_latency::total 6839000 # number of overall MSHR miss cycles 2346system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.027455 # mshr miss rate for ReadReq accesses 2347system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.027455 # mshr miss rate for ReadReq accesses 2348system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.027455 # mshr miss rate for demand accesses 2349system.cpu3.icache.demand_mshr_miss_rate::total 0.027455 # mshr miss rate for demand accesses 2350system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.027455 # mshr miss rate for overall accesses 2351system.cpu3.icache.overall_mshr_miss_rate::total 0.027455 # mshr miss rate for overall accesses 2352system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 13732.931727 # average ReadReq mshr miss latency 2353system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 13732.931727 # average ReadReq mshr miss latency 2354system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 13732.931727 # average overall mshr miss latency 2355system.cpu3.icache.demand_avg_mshr_miss_latency::total 13732.931727 # average overall mshr miss latency 2356system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 13732.931727 # average overall mshr miss latency 2357system.cpu3.icache.overall_avg_mshr_miss_latency::total 13732.931727 # average overall mshr miss latency 2358system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate 2359system.l2c.tags.replacements 0 # number of replacements 2360system.l2c.tags.tagsinuse 422.903421 # Cycle average of tags in use 2361system.l2c.tags.total_refs 2336 # Total number of references to valid blocks. 2362system.l2c.tags.sampled_refs 538 # Sample count of references to valid blocks. 2363system.l2c.tags.avg_refs 4.342007 # Average number of references to valid blocks. 2364system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 2365system.l2c.tags.occ_blocks::writebacks 0.784815 # Average occupied blocks per requestor 2366system.l2c.tags.occ_blocks::cpu0.inst 289.208824 # Average occupied blocks per requestor 2367system.l2c.tags.occ_blocks::cpu0.data 58.009977 # Average occupied blocks per requestor 2368system.l2c.tags.occ_blocks::cpu1.inst 62.701446 # Average occupied blocks per requestor 2369system.l2c.tags.occ_blocks::cpu1.data 5.295227 # Average occupied blocks per requestor 2370system.l2c.tags.occ_blocks::cpu2.data 0.676960 # Average occupied blocks per requestor 2371system.l2c.tags.occ_blocks::cpu3.inst 5.511844 # Average occupied blocks per requestor 2372system.l2c.tags.occ_blocks::cpu3.data 0.714328 # Average occupied blocks per requestor 2373system.l2c.tags.occ_percent::writebacks 0.000012 # Average percentage of cache occupancy 2374system.l2c.tags.occ_percent::cpu0.inst 0.004413 # Average percentage of cache occupancy 2375system.l2c.tags.occ_percent::cpu0.data 0.000885 # Average percentage of cache occupancy 2376system.l2c.tags.occ_percent::cpu1.inst 0.000957 # Average percentage of cache occupancy 2377system.l2c.tags.occ_percent::cpu1.data 0.000081 # Average percentage of cache occupancy 2378system.l2c.tags.occ_percent::cpu2.data 0.000010 # Average percentage of cache occupancy 2379system.l2c.tags.occ_percent::cpu3.inst 0.000084 # Average percentage of cache occupancy 2380system.l2c.tags.occ_percent::cpu3.data 0.000011 # Average percentage of cache occupancy 2381system.l2c.tags.occ_percent::total 0.006453 # Average percentage of cache occupancy 2382system.l2c.tags.occ_task_id_blocks::1024 538 # Occupied blocks per task id 2383system.l2c.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id 2384system.l2c.tags.age_task_id_blocks_1024::1 348 # Occupied blocks per task id 2385system.l2c.tags.age_task_id_blocks_1024::2 139 # Occupied blocks per task id 2386system.l2c.tags.occ_task_id_percent::1024 0.008209 # Percentage of cache occupancy per task id 2387system.l2c.tags.tag_accesses 25512 # Number of tag accesses 2388system.l2c.tags.data_accesses 25512 # Number of data accesses 2389system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits 2390system.l2c.Writeback_hits::total 1 # number of Writeback hits 2391system.l2c.UpgradeReq_hits::cpu0.data 3 # number of UpgradeReq hits 2392system.l2c.UpgradeReq_hits::total 3 # number of UpgradeReq hits 2393system.l2c.ReadCleanReq_hits::cpu0.inst 251 # number of ReadCleanReq hits 2394system.l2c.ReadCleanReq_hits::cpu1.inst 412 # number of ReadCleanReq hits 2395system.l2c.ReadCleanReq_hits::cpu2.inst 486 # number of ReadCleanReq hits 2396system.l2c.ReadCleanReq_hits::cpu3.inst 485 # number of ReadCleanReq hits 2397system.l2c.ReadCleanReq_hits::total 1634 # number of ReadCleanReq hits 2398system.l2c.ReadSharedReq_hits::cpu0.data 5 # number of ReadSharedReq hits 2399system.l2c.ReadSharedReq_hits::cpu1.data 5 # number of ReadSharedReq hits 2400system.l2c.ReadSharedReq_hits::cpu2.data 11 # number of ReadSharedReq hits 2401system.l2c.ReadSharedReq_hits::cpu3.data 11 # number of ReadSharedReq hits 2402system.l2c.ReadSharedReq_hits::total 32 # number of ReadSharedReq hits 2403system.l2c.demand_hits::cpu0.inst 251 # number of demand (read+write) hits 2404system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits 2405system.l2c.demand_hits::cpu1.inst 412 # number of demand (read+write) hits 2406system.l2c.demand_hits::cpu1.data 5 # number of demand (read+write) hits 2407system.l2c.demand_hits::cpu2.inst 486 # number of demand (read+write) hits 2408system.l2c.demand_hits::cpu2.data 11 # number of demand (read+write) hits 2409system.l2c.demand_hits::cpu3.inst 485 # number of demand (read+write) hits 2410system.l2c.demand_hits::cpu3.data 11 # number of demand (read+write) hits 2411system.l2c.demand_hits::total 1666 # number of demand (read+write) hits 2412system.l2c.overall_hits::cpu0.inst 251 # number of overall hits 2413system.l2c.overall_hits::cpu0.data 5 # number of overall hits 2414system.l2c.overall_hits::cpu1.inst 412 # number of overall hits 2415system.l2c.overall_hits::cpu1.data 5 # number of overall hits 2416system.l2c.overall_hits::cpu2.inst 486 # number of overall hits 2417system.l2c.overall_hits::cpu2.data 11 # number of overall hits 2418system.l2c.overall_hits::cpu3.inst 485 # number of overall hits 2419system.l2c.overall_hits::cpu3.data 11 # number of overall hits 2420system.l2c.overall_hits::total 1666 # number of overall hits 2421system.l2c.UpgradeReq_misses::cpu0.data 22 # number of UpgradeReq misses 2422system.l2c.UpgradeReq_misses::cpu1.data 19 # number of UpgradeReq misses 2423system.l2c.UpgradeReq_misses::cpu2.data 14 # number of UpgradeReq misses 2424system.l2c.UpgradeReq_misses::cpu3.data 20 # number of UpgradeReq misses 2425system.l2c.UpgradeReq_misses::total 75 # number of UpgradeReq misses 2426system.l2c.ReadExReq_misses::cpu0.data 94 # number of ReadExReq misses 2427system.l2c.ReadExReq_misses::cpu1.data 13 # number of ReadExReq misses 2428system.l2c.ReadExReq_misses::cpu2.data 12 # number of ReadExReq misses 2429system.l2c.ReadExReq_misses::cpu3.data 12 # number of ReadExReq misses 2430system.l2c.ReadExReq_misses::total 131 # number of ReadExReq misses 2431system.l2c.ReadCleanReq_misses::cpu0.inst 364 # number of ReadCleanReq misses 2432system.l2c.ReadCleanReq_misses::cpu1.inst 88 # number of ReadCleanReq misses 2433system.l2c.ReadCleanReq_misses::cpu2.inst 10 # number of ReadCleanReq misses 2434system.l2c.ReadCleanReq_misses::cpu3.inst 13 # number of ReadCleanReq misses 2435system.l2c.ReadCleanReq_misses::total 475 # number of ReadCleanReq misses 2436system.l2c.ReadSharedReq_misses::cpu0.data 75 # number of ReadSharedReq misses 2437system.l2c.ReadSharedReq_misses::cpu1.data 7 # number of ReadSharedReq misses 2438system.l2c.ReadSharedReq_misses::cpu2.data 1 # number of ReadSharedReq misses 2439system.l2c.ReadSharedReq_misses::cpu3.data 1 # number of ReadSharedReq misses 2440system.l2c.ReadSharedReq_misses::total 84 # number of ReadSharedReq misses 2441system.l2c.demand_misses::cpu0.inst 364 # number of demand (read+write) misses 2442system.l2c.demand_misses::cpu0.data 169 # number of demand (read+write) misses 2443system.l2c.demand_misses::cpu1.inst 88 # number of demand (read+write) misses 2444system.l2c.demand_misses::cpu1.data 20 # number of demand (read+write) misses 2445system.l2c.demand_misses::cpu2.inst 10 # number of demand (read+write) misses 2446system.l2c.demand_misses::cpu2.data 13 # number of demand (read+write) misses 2447system.l2c.demand_misses::cpu3.inst 13 # number of demand (read+write) misses 2448system.l2c.demand_misses::cpu3.data 13 # number of demand (read+write) misses 2449system.l2c.demand_misses::total 690 # number of demand (read+write) misses 2450system.l2c.overall_misses::cpu0.inst 364 # number of overall misses 2451system.l2c.overall_misses::cpu0.data 169 # number of overall misses 2452system.l2c.overall_misses::cpu1.inst 88 # number of overall misses 2453system.l2c.overall_misses::cpu1.data 20 # number of overall misses 2454system.l2c.overall_misses::cpu2.inst 10 # number of overall misses 2455system.l2c.overall_misses::cpu2.data 13 # number of overall misses 2456system.l2c.overall_misses::cpu3.inst 13 # number of overall misses 2457system.l2c.overall_misses::cpu3.data 13 # number of overall misses 2458system.l2c.overall_misses::total 690 # number of overall misses 2459system.l2c.ReadExReq_miss_latency::cpu0.data 7927500 # number of ReadExReq miss cycles 2460system.l2c.ReadExReq_miss_latency::cpu1.data 1298500 # number of ReadExReq miss cycles 2461system.l2c.ReadExReq_miss_latency::cpu2.data 1175000 # number of ReadExReq miss cycles 2462system.l2c.ReadExReq_miss_latency::cpu3.data 1075000 # number of ReadExReq miss cycles 2463system.l2c.ReadExReq_miss_latency::total 11476000 # number of ReadExReq miss cycles 2464system.l2c.ReadCleanReq_miss_latency::cpu0.inst 28062500 # number of ReadCleanReq miss cycles 2465system.l2c.ReadCleanReq_miss_latency::cpu1.inst 6697000 # number of ReadCleanReq miss cycles 2466system.l2c.ReadCleanReq_miss_latency::cpu2.inst 853500 # number of ReadCleanReq miss cycles 2467system.l2c.ReadCleanReq_miss_latency::cpu3.inst 993000 # number of ReadCleanReq miss cycles 2468system.l2c.ReadCleanReq_miss_latency::total 36606000 # number of ReadCleanReq miss cycles 2469system.l2c.ReadSharedReq_miss_latency::cpu0.data 5987000 # number of ReadSharedReq miss cycles 2470system.l2c.ReadSharedReq_miss_latency::cpu1.data 551500 # number of ReadSharedReq miss cycles 2471system.l2c.ReadSharedReq_miss_latency::cpu2.data 82500 # number of ReadSharedReq miss cycles 2472system.l2c.ReadSharedReq_miss_latency::cpu3.data 96500 # number of ReadSharedReq miss cycles 2473system.l2c.ReadSharedReq_miss_latency::total 6717500 # number of ReadSharedReq miss cycles 2474system.l2c.demand_miss_latency::cpu0.inst 28062500 # number of demand (read+write) miss cycles 2475system.l2c.demand_miss_latency::cpu0.data 13914500 # number of demand (read+write) miss cycles 2476system.l2c.demand_miss_latency::cpu1.inst 6697000 # number of demand (read+write) miss cycles 2477system.l2c.demand_miss_latency::cpu1.data 1850000 # number of demand (read+write) miss cycles 2478system.l2c.demand_miss_latency::cpu2.inst 853500 # number of demand (read+write) miss cycles 2479system.l2c.demand_miss_latency::cpu2.data 1257500 # number of demand (read+write) miss cycles 2480system.l2c.demand_miss_latency::cpu3.inst 993000 # number of demand (read+write) miss cycles 2481system.l2c.demand_miss_latency::cpu3.data 1171500 # number of demand (read+write) miss cycles 2482system.l2c.demand_miss_latency::total 54799500 # number of demand (read+write) miss cycles 2483system.l2c.overall_miss_latency::cpu0.inst 28062500 # number of overall miss cycles 2484system.l2c.overall_miss_latency::cpu0.data 13914500 # number of overall miss cycles 2485system.l2c.overall_miss_latency::cpu1.inst 6697000 # number of overall miss cycles 2486system.l2c.overall_miss_latency::cpu1.data 1850000 # number of overall miss cycles 2487system.l2c.overall_miss_latency::cpu2.inst 853500 # number of overall miss cycles 2488system.l2c.overall_miss_latency::cpu2.data 1257500 # number of overall miss cycles 2489system.l2c.overall_miss_latency::cpu3.inst 993000 # number of overall miss cycles 2490system.l2c.overall_miss_latency::cpu3.data 1171500 # number of overall miss cycles 2491system.l2c.overall_miss_latency::total 54799500 # number of overall miss cycles 2492system.l2c.Writeback_accesses::writebacks 1 # number of Writeback accesses(hits+misses) 2493system.l2c.Writeback_accesses::total 1 # number of Writeback accesses(hits+misses) 2494system.l2c.UpgradeReq_accesses::cpu0.data 25 # number of UpgradeReq accesses(hits+misses) 2495system.l2c.UpgradeReq_accesses::cpu1.data 19 # number of UpgradeReq accesses(hits+misses) 2496system.l2c.UpgradeReq_accesses::cpu2.data 14 # number of UpgradeReq accesses(hits+misses) 2497system.l2c.UpgradeReq_accesses::cpu3.data 20 # number of UpgradeReq accesses(hits+misses) 2498system.l2c.UpgradeReq_accesses::total 78 # number of UpgradeReq accesses(hits+misses) 2499system.l2c.ReadExReq_accesses::cpu0.data 94 # number of ReadExReq accesses(hits+misses) 2500system.l2c.ReadExReq_accesses::cpu1.data 13 # number of ReadExReq accesses(hits+misses) 2501system.l2c.ReadExReq_accesses::cpu2.data 12 # number of ReadExReq accesses(hits+misses) 2502system.l2c.ReadExReq_accesses::cpu3.data 12 # number of ReadExReq accesses(hits+misses) 2503system.l2c.ReadExReq_accesses::total 131 # number of ReadExReq accesses(hits+misses) 2504system.l2c.ReadCleanReq_accesses::cpu0.inst 615 # number of ReadCleanReq accesses(hits+misses) 2505system.l2c.ReadCleanReq_accesses::cpu1.inst 500 # number of ReadCleanReq accesses(hits+misses) 2506system.l2c.ReadCleanReq_accesses::cpu2.inst 496 # number of ReadCleanReq accesses(hits+misses) 2507system.l2c.ReadCleanReq_accesses::cpu3.inst 498 # number of ReadCleanReq accesses(hits+misses) 2508system.l2c.ReadCleanReq_accesses::total 2109 # number of ReadCleanReq accesses(hits+misses) 2509system.l2c.ReadSharedReq_accesses::cpu0.data 80 # number of ReadSharedReq accesses(hits+misses) 2510system.l2c.ReadSharedReq_accesses::cpu1.data 12 # number of ReadSharedReq accesses(hits+misses) 2511system.l2c.ReadSharedReq_accesses::cpu2.data 12 # number of ReadSharedReq accesses(hits+misses) 2512system.l2c.ReadSharedReq_accesses::cpu3.data 12 # number of ReadSharedReq accesses(hits+misses) 2513system.l2c.ReadSharedReq_accesses::total 116 # number of ReadSharedReq accesses(hits+misses) 2514system.l2c.demand_accesses::cpu0.inst 615 # number of demand (read+write) accesses 2515system.l2c.demand_accesses::cpu0.data 174 # number of demand (read+write) accesses 2516system.l2c.demand_accesses::cpu1.inst 500 # number of demand (read+write) accesses 2517system.l2c.demand_accesses::cpu1.data 25 # number of demand (read+write) accesses 2518system.l2c.demand_accesses::cpu2.inst 496 # number of demand (read+write) accesses 2519system.l2c.demand_accesses::cpu2.data 24 # number of demand (read+write) accesses 2520system.l2c.demand_accesses::cpu3.inst 498 # number of demand (read+write) accesses 2521system.l2c.demand_accesses::cpu3.data 24 # number of demand (read+write) accesses 2522system.l2c.demand_accesses::total 2356 # number of demand (read+write) accesses 2523system.l2c.overall_accesses::cpu0.inst 615 # number of overall (read+write) accesses 2524system.l2c.overall_accesses::cpu0.data 174 # number of overall (read+write) accesses 2525system.l2c.overall_accesses::cpu1.inst 500 # number of overall (read+write) accesses 2526system.l2c.overall_accesses::cpu1.data 25 # number of overall (read+write) accesses 2527system.l2c.overall_accesses::cpu2.inst 496 # number of overall (read+write) accesses 2528system.l2c.overall_accesses::cpu2.data 24 # number of overall (read+write) accesses 2529system.l2c.overall_accesses::cpu3.inst 498 # number of overall (read+write) accesses 2530system.l2c.overall_accesses::cpu3.data 24 # number of overall (read+write) accesses 2531system.l2c.overall_accesses::total 2356 # number of overall (read+write) accesses 2532system.l2c.UpgradeReq_miss_rate::cpu0.data 0.880000 # miss rate for UpgradeReq accesses 2533system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses 2534system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses 2535system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses 2536system.l2c.UpgradeReq_miss_rate::total 0.961538 # miss rate for UpgradeReq accesses 2537system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses 2538system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses 2539system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses 2540system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses 2541system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 2542system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.591870 # miss rate for ReadCleanReq accesses 2543system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.176000 # miss rate for ReadCleanReq accesses 2544system.l2c.ReadCleanReq_miss_rate::cpu2.inst 0.020161 # miss rate for ReadCleanReq accesses 2545system.l2c.ReadCleanReq_miss_rate::cpu3.inst 0.026104 # miss rate for ReadCleanReq accesses 2546system.l2c.ReadCleanReq_miss_rate::total 0.225225 # miss rate for ReadCleanReq accesses 2547system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.937500 # miss rate for ReadSharedReq accesses 2548system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.583333 # miss rate for ReadSharedReq accesses 2549system.l2c.ReadSharedReq_miss_rate::cpu2.data 0.083333 # miss rate for ReadSharedReq accesses 2550system.l2c.ReadSharedReq_miss_rate::cpu3.data 0.083333 # miss rate for ReadSharedReq accesses 2551system.l2c.ReadSharedReq_miss_rate::total 0.724138 # miss rate for ReadSharedReq accesses 2552system.l2c.demand_miss_rate::cpu0.inst 0.591870 # miss rate for demand accesses 2553system.l2c.demand_miss_rate::cpu0.data 0.971264 # miss rate for demand accesses 2554system.l2c.demand_miss_rate::cpu1.inst 0.176000 # miss rate for demand accesses 2555system.l2c.demand_miss_rate::cpu1.data 0.800000 # miss rate for demand accesses 2556system.l2c.demand_miss_rate::cpu2.inst 0.020161 # miss rate for demand accesses 2557system.l2c.demand_miss_rate::cpu2.data 0.541667 # miss rate for demand accesses 2558system.l2c.demand_miss_rate::cpu3.inst 0.026104 # miss rate for demand accesses 2559system.l2c.demand_miss_rate::cpu3.data 0.541667 # miss rate for demand accesses 2560system.l2c.demand_miss_rate::total 0.292869 # miss rate for demand accesses 2561system.l2c.overall_miss_rate::cpu0.inst 0.591870 # miss rate for overall accesses 2562system.l2c.overall_miss_rate::cpu0.data 0.971264 # miss rate for overall accesses 2563system.l2c.overall_miss_rate::cpu1.inst 0.176000 # miss rate for overall accesses 2564system.l2c.overall_miss_rate::cpu1.data 0.800000 # miss rate for overall accesses 2565system.l2c.overall_miss_rate::cpu2.inst 0.020161 # miss rate for overall accesses 2566system.l2c.overall_miss_rate::cpu2.data 0.541667 # miss rate for overall accesses 2567system.l2c.overall_miss_rate::cpu3.inst 0.026104 # miss rate for overall accesses 2568system.l2c.overall_miss_rate::cpu3.data 0.541667 # miss rate for overall accesses 2569system.l2c.overall_miss_rate::total 0.292869 # miss rate for overall accesses 2570system.l2c.ReadExReq_avg_miss_latency::cpu0.data 84335.106383 # average ReadExReq miss latency 2571system.l2c.ReadExReq_avg_miss_latency::cpu1.data 99884.615385 # average ReadExReq miss latency 2572system.l2c.ReadExReq_avg_miss_latency::cpu2.data 97916.666667 # average ReadExReq miss latency 2573system.l2c.ReadExReq_avg_miss_latency::cpu3.data 89583.333333 # average ReadExReq miss latency 2574system.l2c.ReadExReq_avg_miss_latency::total 87603.053435 # average ReadExReq miss latency 2575system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 77094.780220 # average ReadCleanReq miss latency 2576system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 76102.272727 # average ReadCleanReq miss latency 2577system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 85350 # average ReadCleanReq miss latency 2578system.l2c.ReadCleanReq_avg_miss_latency::cpu3.inst 76384.615385 # average ReadCleanReq miss latency 2579system.l2c.ReadCleanReq_avg_miss_latency::total 77065.263158 # average ReadCleanReq miss latency 2580system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 79826.666667 # average ReadSharedReq miss latency 2581system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 78785.714286 # average ReadSharedReq miss latency 2582system.l2c.ReadSharedReq_avg_miss_latency::cpu2.data 82500 # average ReadSharedReq miss latency 2583system.l2c.ReadSharedReq_avg_miss_latency::cpu3.data 96500 # average ReadSharedReq miss latency 2584system.l2c.ReadSharedReq_avg_miss_latency::total 79970.238095 # average ReadSharedReq miss latency 2585system.l2c.demand_avg_miss_latency::cpu0.inst 77094.780220 # average overall miss latency 2586system.l2c.demand_avg_miss_latency::cpu0.data 82334.319527 # average overall miss latency 2587system.l2c.demand_avg_miss_latency::cpu1.inst 76102.272727 # average overall miss latency 2588system.l2c.demand_avg_miss_latency::cpu1.data 92500 # average overall miss latency 2589system.l2c.demand_avg_miss_latency::cpu2.inst 85350 # average overall miss latency 2590system.l2c.demand_avg_miss_latency::cpu2.data 96730.769231 # average overall miss latency 2591system.l2c.demand_avg_miss_latency::cpu3.inst 76384.615385 # average overall miss latency 2592system.l2c.demand_avg_miss_latency::cpu3.data 90115.384615 # average overall miss latency 2593system.l2c.demand_avg_miss_latency::total 79419.565217 # average overall miss latency 2594system.l2c.overall_avg_miss_latency::cpu0.inst 77094.780220 # average overall miss latency 2595system.l2c.overall_avg_miss_latency::cpu0.data 82334.319527 # average overall miss latency 2596system.l2c.overall_avg_miss_latency::cpu1.inst 76102.272727 # average overall miss latency 2597system.l2c.overall_avg_miss_latency::cpu1.data 92500 # average overall miss latency 2598system.l2c.overall_avg_miss_latency::cpu2.inst 85350 # average overall miss latency 2599system.l2c.overall_avg_miss_latency::cpu2.data 96730.769231 # average overall miss latency 2600system.l2c.overall_avg_miss_latency::cpu3.inst 76384.615385 # average overall miss latency 2601system.l2c.overall_avg_miss_latency::cpu3.data 90115.384615 # average overall miss latency 2602system.l2c.overall_avg_miss_latency::total 79419.565217 # average overall miss latency 2603system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2604system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 2605system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 2606system.l2c.blocked::no_targets 0 # number of cycles access was blocked 2607system.l2c.avg_blocked_cycles::no_mshrs nan # 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number of demand (read+write) MSHR hits 2620system.l2c.demand_mshr_hits::total 18 # number of demand (read+write) MSHR hits 2621system.l2c.overall_mshr_hits::cpu0.inst 1 # number of overall MSHR hits 2622system.l2c.overall_mshr_hits::cpu1.inst 3 # number of overall MSHR hits 2623system.l2c.overall_mshr_hits::cpu2.inst 10 # number of overall MSHR hits 2624system.l2c.overall_mshr_hits::cpu3.inst 4 # number of overall MSHR hits 2625system.l2c.overall_mshr_hits::total 18 # number of overall MSHR hits 2626system.l2c.UpgradeReq_mshr_misses::cpu0.data 22 # number of UpgradeReq MSHR misses 2627system.l2c.UpgradeReq_mshr_misses::cpu1.data 19 # number of UpgradeReq MSHR misses 2628system.l2c.UpgradeReq_mshr_misses::cpu2.data 14 # number of UpgradeReq MSHR misses 2629system.l2c.UpgradeReq_mshr_misses::cpu3.data 20 # number of UpgradeReq MSHR misses 2630system.l2c.UpgradeReq_mshr_misses::total 75 # number of UpgradeReq MSHR misses 2631system.l2c.ReadExReq_mshr_misses::cpu0.data 94 # number of ReadExReq MSHR misses 2632system.l2c.ReadExReq_mshr_misses::cpu1.data 13 # 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number of ReadSharedReq MSHR miss cycles 2678system.l2c.ReadSharedReq_mshr_miss_latency::cpu3.data 86500 # number of ReadSharedReq MSHR miss cycles 2679system.l2c.ReadSharedReq_mshr_miss_latency::total 5877500 # number of ReadSharedReq MSHR miss cycles 2680system.l2c.demand_mshr_miss_latency::cpu0.inst 24396000 # number of demand (read+write) MSHR miss cycles 2681system.l2c.demand_mshr_miss_latency::cpu0.data 12224500 # number of demand (read+write) MSHR miss cycles 2682system.l2c.demand_mshr_miss_latency::cpu1.inst 5728000 # number of demand (read+write) MSHR miss cycles 2683system.l2c.demand_mshr_miss_latency::cpu1.data 1650000 # number of demand (read+write) MSHR miss cycles 2684system.l2c.demand_mshr_miss_latency::cpu2.data 1127500 # number of demand (read+write) MSHR miss cycles 2685system.l2c.demand_mshr_miss_latency::cpu3.inst 584500 # number of demand (read+write) MSHR miss cycles 2686system.l2c.demand_mshr_miss_latency::cpu3.data 1041500 # number of demand (read+write) MSHR miss cycles 2687system.l2c.demand_mshr_miss_latency::total 46752000 # number of demand (read+write) MSHR miss cycles 2688system.l2c.overall_mshr_miss_latency::cpu0.inst 24396000 # number of overall MSHR miss cycles 2689system.l2c.overall_mshr_miss_latency::cpu0.data 12224500 # number of overall MSHR miss cycles 2690system.l2c.overall_mshr_miss_latency::cpu1.inst 5728000 # number of overall MSHR miss cycles 2691system.l2c.overall_mshr_miss_latency::cpu1.data 1650000 # number of overall MSHR miss cycles 2692system.l2c.overall_mshr_miss_latency::cpu2.data 1127500 # number of overall MSHR miss cycles 2693system.l2c.overall_mshr_miss_latency::cpu3.inst 584500 # number of overall MSHR miss cycles 2694system.l2c.overall_mshr_miss_latency::cpu3.data 1041500 # number of overall MSHR miss cycles 2695system.l2c.overall_mshr_miss_latency::total 46752000 # number of overall MSHR miss cycles 2696system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.880000 # mshr miss rate for UpgradeReq accesses 2697system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses 2698system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for UpgradeReq accesses 2699system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for UpgradeReq accesses 2700system.l2c.UpgradeReq_mshr_miss_rate::total 0.961538 # mshr miss rate for UpgradeReq accesses 2701system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses 2702system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses 2703system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses 2704system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for ReadExReq accesses 2705system.l2c.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 2706system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.590244 # mshr miss rate for ReadCleanReq accesses 2707system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.170000 # mshr miss rate for ReadCleanReq accesses 2708system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst 0.018072 # mshr miss rate for ReadCleanReq accesses 2709system.l2c.ReadCleanReq_mshr_miss_rate::total 0.216690 # mshr miss rate for ReadCleanReq accesses 2710system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.937500 # mshr miss rate for ReadSharedReq accesses 2711system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.583333 # mshr miss rate for ReadSharedReq accesses 2712system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data 0.083333 # mshr miss rate for ReadSharedReq accesses 2713system.l2c.ReadSharedReq_mshr_miss_rate::cpu3.data 0.083333 # mshr miss rate for ReadSharedReq accesses 2714system.l2c.ReadSharedReq_mshr_miss_rate::total 0.724138 # mshr miss rate for ReadSharedReq accesses 2715system.l2c.demand_mshr_miss_rate::cpu0.inst 0.590244 # mshr miss rate for demand accesses 2716system.l2c.demand_mshr_miss_rate::cpu0.data 0.971264 # mshr miss rate for demand accesses 2717system.l2c.demand_mshr_miss_rate::cpu1.inst 0.170000 # mshr miss rate for demand accesses 2718system.l2c.demand_mshr_miss_rate::cpu1.data 0.800000 # mshr miss rate for demand accesses 2719system.l2c.demand_mshr_miss_rate::cpu2.data 0.541667 # mshr miss rate for demand accesses 2720system.l2c.demand_mshr_miss_rate::cpu3.inst 0.018072 # mshr miss rate for demand accesses 2721system.l2c.demand_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for demand accesses 2722system.l2c.demand_mshr_miss_rate::total 0.285229 # mshr miss rate for demand accesses 2723system.l2c.overall_mshr_miss_rate::cpu0.inst 0.590244 # mshr miss rate for overall accesses 2724system.l2c.overall_mshr_miss_rate::cpu0.data 0.971264 # mshr miss rate for overall accesses 2725system.l2c.overall_mshr_miss_rate::cpu1.inst 0.170000 # mshr miss rate for overall accesses 2726system.l2c.overall_mshr_miss_rate::cpu1.data 0.800000 # mshr miss rate for overall accesses 2727system.l2c.overall_mshr_miss_rate::cpu2.data 0.541667 # mshr miss rate for overall accesses 2728system.l2c.overall_mshr_miss_rate::cpu3.inst 0.018072 # mshr miss rate for overall accesses 2729system.l2c.overall_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for overall accesses 2730system.l2c.overall_mshr_miss_rate::total 0.285229 # mshr miss rate for overall accesses 2731system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20750 # average UpgradeReq mshr miss latency 2732system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20815.789474 # average UpgradeReq mshr miss latency 2733system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 20785.500000 # average UpgradeReq mshr miss latency 2734system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 20850 # average UpgradeReq mshr miss latency 2735system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20799.960000 # average UpgradeReq mshr miss latency 2736system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 74335.106383 # average ReadExReq mshr miss latency 2737system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 89884.615385 # average ReadExReq mshr miss latency 2738system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 87916.666667 # average ReadExReq mshr miss latency 2739system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 79583.333333 # average ReadExReq mshr miss latency 2740system.l2c.ReadExReq_avg_mshr_miss_latency::total 77603.053435 # average ReadExReq mshr miss latency 2741system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 67206.611570 # average ReadCleanReq mshr miss latency 2742system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 67388.235294 # average ReadCleanReq mshr miss latency 2743system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 64944.444444 # average ReadCleanReq mshr miss latency 2744system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 67195.842451 # average ReadCleanReq mshr miss latency 2745system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 69826.666667 # average ReadSharedReq mshr miss latency 2746system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 68785.714286 # average ReadSharedReq mshr miss latency 2747system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 72500 # average ReadSharedReq mshr miss latency 2748system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 86500 # average ReadSharedReq mshr miss latency 2749system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 69970.238095 # average ReadSharedReq mshr miss latency 2750system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 67206.611570 # average overall mshr miss latency 2751system.l2c.demand_avg_mshr_miss_latency::cpu0.data 72334.319527 # average overall mshr miss latency 2752system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 67388.235294 # average overall mshr miss latency 2753system.l2c.demand_avg_mshr_miss_latency::cpu1.data 82500 # average overall mshr miss latency 2754system.l2c.demand_avg_mshr_miss_latency::cpu2.data 86730.769231 # average overall mshr miss latency 2755system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 64944.444444 # average overall mshr miss latency 2756system.l2c.demand_avg_mshr_miss_latency::cpu3.data 80115.384615 # average overall mshr miss latency 2757system.l2c.demand_avg_mshr_miss_latency::total 69571.428571 # average overall mshr miss latency 2758system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 67206.611570 # average overall mshr miss latency 2759system.l2c.overall_avg_mshr_miss_latency::cpu0.data 72334.319527 # average overall mshr miss latency 2760system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 67388.235294 # average overall mshr miss latency 2761system.l2c.overall_avg_mshr_miss_latency::cpu1.data 82500 # average overall mshr miss latency 2762system.l2c.overall_avg_mshr_miss_latency::cpu2.data 86730.769231 # average overall mshr miss latency 2763system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 64944.444444 # average overall mshr miss latency 2764system.l2c.overall_avg_mshr_miss_latency::cpu3.data 80115.384615 # average overall mshr miss latency 2765system.l2c.overall_avg_mshr_miss_latency::total 69571.428571 # average overall mshr miss latency 2766system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 2767system.membus.trans_dist::ReadResp 540 # Transaction distribution 2768system.membus.trans_dist::UpgradeReq 281 # Transaction distribution 2769system.membus.trans_dist::UpgradeResp 75 # Transaction distribution 2770system.membus.trans_dist::ReadExReq 168 # Transaction distribution 2771system.membus.trans_dist::ReadExResp 131 # Transaction distribution 2772system.membus.trans_dist::ReadSharedReq 541 # Transaction distribution 2773system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1736 # Packet count per connected master and slave (bytes) 2774system.membus.pkt_count::total 1736 # Packet count per connected master and slave (bytes) 2775system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 42944 # Cumulative packet size per connected master and slave (bytes) 2776system.membus.pkt_size::total 42944 # Cumulative packet size per connected master and slave (bytes) 2777system.membus.snoops 243 # Total snoops (count) 2778system.membus.snoop_fanout::samples 990 # Request fanout histogram 2779system.membus.snoop_fanout::mean 0 # Request fanout histogram 2780system.membus.snoop_fanout::stdev 0 # Request fanout histogram 2781system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2782system.membus.snoop_fanout::0 990 100.00% 100.00% # Request fanout histogram 2783system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 2784system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2785system.membus.snoop_fanout::min_value 0 # Request fanout histogram 2786system.membus.snoop_fanout::max_value 0 # Request fanout histogram 2787system.membus.snoop_fanout::total 990 # Request fanout histogram 2788system.membus.reqLayer0.occupancy 926003 # Layer occupancy (ticks) 2789system.membus.reqLayer0.utilization 0.9 # Layer utilization (%) 2790system.membus.respLayer1.occupancy 3714925 # Layer occupancy (ticks) 2791system.membus.respLayer1.utilization 3.4 # Layer utilization (%) 2792system.toL2Bus.trans_dist::ReadResp 2768 # Transaction distribution 2793system.toL2Bus.trans_dist::Writeback 1 # Transaction distribution 2794system.toL2Bus.trans_dist::CleanEvict 670 # Transaction distribution 2795system.toL2Bus.trans_dist::UpgradeReq 284 # Transaction distribution 2796system.toL2Bus.trans_dist::UpgradeResp 284 # Transaction distribution 2797system.toL2Bus.trans_dist::ReadExReq 403 # Transaction distribution 2798system.toL2Bus.trans_dist::ReadExResp 403 # Transaction distribution 2799system.toL2Bus.trans_dist::ReadCleanReq 2109 # Transaction distribution 2800system.toL2Bus.trans_dist::ReadSharedReq 660 # Transaction distribution 2801system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1469 # Packet count per connected master and slave (bytes) 2802system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 583 # Packet count per connected master and slave (bytes) 2803system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1144 # Packet count per connected master and slave (bytes) 2804system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 366 # Packet count per connected master and slave (bytes) 2805system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 1137 # Packet count per connected master and slave (bytes) 2806system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 375 # Packet count per connected master and slave (bytes) 2807system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 1136 # Packet count per connected master and slave (bytes) 2808system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 350 # Packet count per connected master and slave (bytes) 2809system.toL2Bus.pkt_count::total 6560 # Packet count per connected master and slave (bytes) 2810system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 39296 # Cumulative packet size per connected master and slave (bytes) 2811system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 11200 # Cumulative packet size per connected master and slave (bytes) 2812system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 32000 # Cumulative packet size per connected master and slave (bytes) 2813system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes) 2814system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 31744 # Cumulative packet size per connected master and slave (bytes) 2815system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 1536 # Cumulative packet size per connected master and slave (bytes) 2816system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 31872 # Cumulative packet size per connected master and slave (bytes) 2817system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 1536 # Cumulative packet size per connected master and slave (bytes) 2818system.toL2Bus.pkt_size::total 150784 # Cumulative packet size per connected master and slave (bytes) 2819system.toL2Bus.snoops 1022 # Total snoops (count) 2820system.toL2Bus.snoop_fanout::samples 4941 # Request fanout histogram 2821system.toL2Bus.snoop_fanout::mean 7 # Request fanout histogram 2822system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram 2823system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2824system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 2825system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 2826system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 2827system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 2828system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 2829system.toL2Bus.snoop_fanout::5 0 0.00% 0.00% # Request fanout histogram 2830system.toL2Bus.snoop_fanout::6 0 0.00% 0.00% # Request fanout histogram 2831system.toL2Bus.snoop_fanout::7 4941 100.00% 100.00% # Request fanout histogram 2832system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram 2833system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2834system.toL2Bus.snoop_fanout::min_value 7 # Request fanout histogram 2835system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram 2836system.toL2Bus.snoop_fanout::total 4941 # Request fanout histogram 2837system.toL2Bus.reqLayer0.occupancy 2489462 # Layer occupancy (ticks) 2838system.toL2Bus.reqLayer0.utilization 2.3 # Layer utilization (%) 2839system.toL2Bus.respLayer0.occupancy 921499 # Layer occupancy (ticks) 2840system.toL2Bus.respLayer0.utilization 0.9 # Layer utilization (%) 2841system.toL2Bus.respLayer1.occupancy 506002 # Layer occupancy (ticks) 2842system.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) 2843system.toL2Bus.respLayer2.occupancy 751497 # Layer occupancy (ticks) 2844system.toL2Bus.respLayer2.utilization 0.7 # Layer utilization (%) 2845system.toL2Bus.respLayer3.occupancy 425967 # Layer occupancy (ticks) 2846system.toL2Bus.respLayer3.utilization 0.4 # Layer utilization (%) 2847system.toL2Bus.respLayer4.occupancy 748987 # Layer occupancy (ticks) 2848system.toL2Bus.respLayer4.utilization 0.7 # Layer utilization (%) 2849system.toL2Bus.respLayer5.occupancy 449462 # Layer occupancy (ticks) 2850system.toL2Bus.respLayer5.utilization 0.4 # Layer utilization (%) 2851system.toL2Bus.respLayer6.occupancy 748992 # Layer occupancy (ticks) 2852system.toL2Bus.respLayer6.utilization 0.7 # Layer utilization (%) 2853system.toL2Bus.respLayer7.occupancy 400481 # Layer occupancy (ticks) 2854system.toL2Bus.respLayer7.utilization 0.4 # Layer utilization (%) 2855 2856---------- End Simulation Statistics ---------- 2857