stats.txt revision 10220:9eab5efc02e8
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000111 # Number of seconds simulated 4sim_ticks 110872500 # Number of ticks simulated 5final_tick 110872500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 118027 # Simulator instruction rate (inst/s) 8host_op_rate 118027 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 12557410 # Simulator tick rate (ticks/s) 10host_mem_usage 289008 # Number of bytes of host memory used 11host_seconds 8.83 # Real time elapsed on the host 12sim_insts 1042088 # Number of instructions simulated 13sim_ops 1042088 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu0.inst 22784 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.data 10752 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu1.inst 640 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu1.data 832 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu2.inst 4608 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu2.data 1280 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu3.inst 448 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu3.data 832 # Number of bytes read from this memory 24system.physmem.bytes_read::total 42176 # Number of bytes read from this memory 25system.physmem.bytes_inst_read::cpu0.inst 22784 # Number of instructions bytes read from this memory 26system.physmem.bytes_inst_read::cpu1.inst 640 # Number of instructions bytes read from this memory 27system.physmem.bytes_inst_read::cpu2.inst 4608 # Number of instructions bytes read from this memory 28system.physmem.bytes_inst_read::cpu3.inst 448 # Number of instructions bytes read from this memory 29system.physmem.bytes_inst_read::total 28480 # Number of instructions bytes read from this memory 30system.physmem.num_reads::cpu0.inst 356 # Number of read requests responded to by this memory 31system.physmem.num_reads::cpu0.data 168 # Number of read requests responded to by this memory 32system.physmem.num_reads::cpu1.inst 10 # Number of read requests responded to by this memory 33system.physmem.num_reads::cpu1.data 13 # Number of read requests responded to by this memory 34system.physmem.num_reads::cpu2.inst 72 # Number of read requests responded to by this memory 35system.physmem.num_reads::cpu2.data 20 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu3.inst 7 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu3.data 13 # Number of read requests responded to by this memory 38system.physmem.num_reads::total 659 # Number of read requests responded to by this memory 39system.physmem.bw_read::cpu0.inst 205497305 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::cpu0.data 96976257 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::cpu1.inst 5772396 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_read::cpu1.data 7504115 # Total read bandwidth from this memory (bytes/s) 43system.physmem.bw_read::cpu2.inst 41561253 # Total read bandwidth from this memory (bytes/s) 44system.physmem.bw_read::cpu2.data 11544792 # Total read bandwidth from this memory (bytes/s) 45system.physmem.bw_read::cpu3.inst 4040677 # Total read bandwidth from this memory (bytes/s) 46system.physmem.bw_read::cpu3.data 7504115 # Total read bandwidth from this memory (bytes/s) 47system.physmem.bw_read::total 380400911 # Total read bandwidth from this memory (bytes/s) 48system.physmem.bw_inst_read::cpu0.inst 205497305 # Instruction read bandwidth from this memory (bytes/s) 49system.physmem.bw_inst_read::cpu1.inst 5772396 # Instruction read bandwidth from this memory (bytes/s) 50system.physmem.bw_inst_read::cpu2.inst 41561253 # Instruction read bandwidth from this memory (bytes/s) 51system.physmem.bw_inst_read::cpu3.inst 4040677 # Instruction read bandwidth from this memory (bytes/s) 52system.physmem.bw_inst_read::total 256871632 # Instruction read bandwidth from this memory (bytes/s) 53system.physmem.bw_total::cpu0.inst 205497305 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.bw_total::cpu0.data 96976257 # Total bandwidth to/from this memory (bytes/s) 55system.physmem.bw_total::cpu1.inst 5772396 # Total bandwidth to/from this memory (bytes/s) 56system.physmem.bw_total::cpu1.data 7504115 # Total bandwidth to/from this memory (bytes/s) 57system.physmem.bw_total::cpu2.inst 41561253 # Total bandwidth to/from this memory (bytes/s) 58system.physmem.bw_total::cpu2.data 11544792 # Total bandwidth to/from this memory (bytes/s) 59system.physmem.bw_total::cpu3.inst 4040677 # Total bandwidth to/from this memory (bytes/s) 60system.physmem.bw_total::cpu3.data 7504115 # Total bandwidth to/from this memory (bytes/s) 61system.physmem.bw_total::total 380400911 # Total bandwidth to/from this memory (bytes/s) 62system.physmem.readReqs 660 # Number of read requests accepted 63system.physmem.writeReqs 0 # Number of write requests accepted 64system.physmem.readBursts 660 # Number of DRAM read bursts, including those serviced by the write queue 65system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 66system.physmem.bytesReadDRAM 42240 # Total number of bytes read from DRAM 67system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 68system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 69system.physmem.bytesReadSys 42240 # Total read bytes from the system interface side 70system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 71system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 72system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 73system.physmem.neitherReadNorWriteReqs 77 # Number of requests that are neither read nor write 74system.physmem.perBankRdBursts::0 115 # Per bank write bursts 75system.physmem.perBankRdBursts::1 39 # Per bank write bursts 76system.physmem.perBankRdBursts::2 29 # Per bank write bursts 77system.physmem.perBankRdBursts::3 60 # Per bank write bursts 78system.physmem.perBankRdBursts::4 65 # Per bank write bursts 79system.physmem.perBankRdBursts::5 27 # Per bank write bursts 80system.physmem.perBankRdBursts::6 18 # Per bank write bursts 81system.physmem.perBankRdBursts::7 24 # Per bank write bursts 82system.physmem.perBankRdBursts::8 7 # Per bank write bursts 83system.physmem.perBankRdBursts::9 28 # Per bank write bursts 84system.physmem.perBankRdBursts::10 23 # Per bank write bursts 85system.physmem.perBankRdBursts::11 12 # Per bank write bursts 86system.physmem.perBankRdBursts::12 60 # Per bank write bursts 87system.physmem.perBankRdBursts::13 38 # Per bank write bursts 88system.physmem.perBankRdBursts::14 17 # Per bank write bursts 89system.physmem.perBankRdBursts::15 98 # Per bank write bursts 90system.physmem.perBankWrBursts::0 0 # Per bank write bursts 91system.physmem.perBankWrBursts::1 0 # Per bank write bursts 92system.physmem.perBankWrBursts::2 0 # Per bank write bursts 93system.physmem.perBankWrBursts::3 0 # Per bank write bursts 94system.physmem.perBankWrBursts::4 0 # Per bank write bursts 95system.physmem.perBankWrBursts::5 0 # Per bank write bursts 96system.physmem.perBankWrBursts::6 0 # Per bank write bursts 97system.physmem.perBankWrBursts::7 0 # Per bank write bursts 98system.physmem.perBankWrBursts::8 0 # Per bank write bursts 99system.physmem.perBankWrBursts::9 0 # Per bank write bursts 100system.physmem.perBankWrBursts::10 0 # Per bank write bursts 101system.physmem.perBankWrBursts::11 0 # Per bank write bursts 102system.physmem.perBankWrBursts::12 0 # Per bank write bursts 103system.physmem.perBankWrBursts::13 0 # Per bank write bursts 104system.physmem.perBankWrBursts::14 0 # Per bank write bursts 105system.physmem.perBankWrBursts::15 0 # Per bank write bursts 106system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 107system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 108system.physmem.totGap 110844500 # Total gap between requests 109system.physmem.readPktSize::0 0 # Read request sizes (log2) 110system.physmem.readPktSize::1 0 # Read request sizes (log2) 111system.physmem.readPktSize::2 0 # Read request sizes (log2) 112system.physmem.readPktSize::3 0 # Read request sizes (log2) 113system.physmem.readPktSize::4 0 # Read request sizes (log2) 114system.physmem.readPktSize::5 0 # Read request sizes (log2) 115system.physmem.readPktSize::6 660 # Read request sizes (log2) 116system.physmem.writePktSize::0 0 # Write request sizes (log2) 117system.physmem.writePktSize::1 0 # Write request sizes (log2) 118system.physmem.writePktSize::2 0 # Write request sizes (log2) 119system.physmem.writePktSize::3 0 # Write request sizes (log2) 120system.physmem.writePktSize::4 0 # Write request sizes (log2) 121system.physmem.writePktSize::5 0 # Write request sizes (log2) 122system.physmem.writePktSize::6 0 # Write request sizes (log2) 123system.physmem.rdQLenPdf::0 403 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::1 194 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::2 51 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::3 10 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 155system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 218system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 219system.physmem.bytesPerActivate::samples 148 # Bytes accessed per row activation 220system.physmem.bytesPerActivate::mean 275.027027 # Bytes accessed per row activation 221system.physmem.bytesPerActivate::gmean 186.656156 # Bytes accessed per row activation 222system.physmem.bytesPerActivate::stdev 254.302887 # Bytes accessed per row activation 223system.physmem.bytesPerActivate::0-127 45 30.41% 30.41% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::128-255 43 29.05% 59.46% # Bytes accessed per row activation 225system.physmem.bytesPerActivate::256-383 21 14.19% 73.65% # Bytes accessed per row activation 226system.physmem.bytesPerActivate::384-511 12 8.11% 81.76% # Bytes accessed per row activation 227system.physmem.bytesPerActivate::512-639 10 6.76% 88.51% # Bytes accessed per row activation 228system.physmem.bytesPerActivate::640-767 5 3.38% 91.89% # Bytes accessed per row activation 229system.physmem.bytesPerActivate::768-895 5 3.38% 95.27% # Bytes accessed per row activation 230system.physmem.bytesPerActivate::896-1023 1 0.68% 95.95% # Bytes accessed per row activation 231system.physmem.bytesPerActivate::1024-1151 6 4.05% 100.00% # Bytes accessed per row activation 232system.physmem.bytesPerActivate::total 148 # Bytes accessed per row activation 233system.physmem.totQLat 5597750 # Total ticks spent queuing 234system.physmem.totMemAccLat 17972750 # Total ticks spent from burst creation until serviced by the DRAM 235system.physmem.totBusLat 3300000 # Total ticks spent in databus transfers 236system.physmem.avgQLat 8481.44 # Average queueing delay per DRAM burst 237system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 238system.physmem.avgMemAccLat 27231.44 # Average memory access latency per DRAM burst 239system.physmem.avgRdBW 380.98 # Average DRAM read bandwidth in MiByte/s 240system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 241system.physmem.avgRdBWSys 380.98 # Average system read bandwidth in MiByte/s 242system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 243system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 244system.physmem.busUtil 2.98 # Data bus utilization in percentage 245system.physmem.busUtilRead 2.98 # Data bus utilization in percentage for reads 246system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 247system.physmem.avgRdQLen 1.21 # Average read queue length when enqueuing 248system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 249system.physmem.readRowHits 505 # Number of row buffer hits during reads 250system.physmem.writeRowHits 0 # Number of row buffer hits during writes 251system.physmem.readRowHitRate 76.52 # Row buffer hit rate for reads 252system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 253system.physmem.avgGap 167946.21 # Average gap between requests 254system.physmem.pageHitRate 76.52 # Row buffer hit rate, read and write combined 255system.physmem.memoryStateTime::IDLE 48028250 # Time in different power states 256system.physmem.memoryStateTime::REF 3640000 # Time in different power states 257system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states 258system.physmem.memoryStateTime::ACT 57613000 # Time in different power states 259system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states 260system.membus.throughput 380400911 # Throughput (bytes/s) 261system.membus.trans_dist::ReadReq 529 # Transaction distribution 262system.membus.trans_dist::ReadResp 528 # Transaction distribution 263system.membus.trans_dist::UpgradeReq 287 # Transaction distribution 264system.membus.trans_dist::UpgradeResp 77 # Transaction distribution 265system.membus.trans_dist::ReadExReq 163 # Transaction distribution 266system.membus.trans_dist::ReadExResp 131 # Transaction distribution 267system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1715 # Packet count per connected master and slave (bytes) 268system.membus.pkt_count::total 1715 # Packet count per connected master and slave (bytes) 269system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 42176 # Cumulative packet size per connected master and slave (bytes) 270system.membus.tot_pkt_size::total 42176 # Cumulative packet size per connected master and slave (bytes) 271system.membus.data_through_bus 42176 # Total data (bytes) 272system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 273system.membus.reqLayer0.occupancy 925500 # Layer occupancy (ticks) 274system.membus.reqLayer0.utilization 0.8 # Layer utilization (%) 275system.membus.respLayer1.occupancy 6302174 # Layer occupancy (ticks) 276system.membus.respLayer1.utilization 5.7 # Layer utilization (%) 277system.cpu_clk_domain.clock 500 # Clock period in ticks 278system.l2c.tags.replacements 0 # number of replacements 279system.l2c.tags.tagsinuse 417.213115 # Cycle average of tags in use 280system.l2c.tags.total_refs 1443 # Total number of references to valid blocks. 281system.l2c.tags.sampled_refs 526 # Sample count of references to valid blocks. 282system.l2c.tags.avg_refs 2.743346 # Average number of references to valid blocks. 283system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 284system.l2c.tags.occ_blocks::writebacks 0.799585 # Average occupied blocks per requestor 285system.l2c.tags.occ_blocks::cpu0.inst 285.091922 # Average occupied blocks per requestor 286system.l2c.tags.occ_blocks::cpu0.data 58.421534 # Average occupied blocks per requestor 287system.l2c.tags.occ_blocks::cpu1.inst 7.040102 # Average occupied blocks per requestor 288system.l2c.tags.occ_blocks::cpu1.data 0.695019 # Average occupied blocks per requestor 289system.l2c.tags.occ_blocks::cpu2.inst 55.399606 # Average occupied blocks per requestor 290system.l2c.tags.occ_blocks::cpu2.data 5.410902 # Average occupied blocks per requestor 291system.l2c.tags.occ_blocks::cpu3.inst 3.621924 # Average occupied blocks per requestor 292system.l2c.tags.occ_blocks::cpu3.data 0.732522 # Average occupied blocks per requestor 293system.l2c.tags.occ_percent::writebacks 0.000012 # Average percentage of cache occupancy 294system.l2c.tags.occ_percent::cpu0.inst 0.004350 # Average percentage of cache occupancy 295system.l2c.tags.occ_percent::cpu0.data 0.000891 # Average percentage of cache occupancy 296system.l2c.tags.occ_percent::cpu1.inst 0.000107 # Average percentage of cache occupancy 297system.l2c.tags.occ_percent::cpu1.data 0.000011 # Average percentage of cache occupancy 298system.l2c.tags.occ_percent::cpu2.inst 0.000845 # Average percentage of cache occupancy 299system.l2c.tags.occ_percent::cpu2.data 0.000083 # Average percentage of cache occupancy 300system.l2c.tags.occ_percent::cpu3.inst 0.000055 # Average percentage of cache occupancy 301system.l2c.tags.occ_percent::cpu3.data 0.000011 # Average percentage of cache occupancy 302system.l2c.tags.occ_percent::total 0.006366 # Average percentage of cache occupancy 303system.l2c.tags.occ_task_id_blocks::1024 526 # Occupied blocks per task id 304system.l2c.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id 305system.l2c.tags.age_task_id_blocks_1024::1 296 # Occupied blocks per task id 306system.l2c.tags.age_task_id_blocks_1024::2 179 # Occupied blocks per task id 307system.l2c.tags.occ_task_id_percent::1024 0.008026 # Percentage of cache occupancy per task id 308system.l2c.tags.tag_accesses 18244 # Number of tag accesses 309system.l2c.tags.data_accesses 18244 # Number of data accesses 310system.l2c.ReadReq_hits::cpu0.inst 229 # number of ReadReq hits 311system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits 312system.l2c.ReadReq_hits::cpu1.inst 413 # number of ReadReq hits 313system.l2c.ReadReq_hits::cpu1.data 11 # number of ReadReq hits 314system.l2c.ReadReq_hits::cpu2.inst 349 # number of ReadReq hits 315system.l2c.ReadReq_hits::cpu2.data 5 # number of ReadReq hits 316system.l2c.ReadReq_hits::cpu3.inst 420 # number of ReadReq hits 317system.l2c.ReadReq_hits::cpu3.data 11 # number of ReadReq hits 318system.l2c.ReadReq_hits::total 1443 # number of ReadReq hits 319system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits 320system.l2c.Writeback_hits::total 1 # number of Writeback hits 321system.l2c.UpgradeReq_hits::cpu0.data 3 # number of UpgradeReq hits 322system.l2c.UpgradeReq_hits::total 3 # number of UpgradeReq hits 323system.l2c.demand_hits::cpu0.inst 229 # number of demand (read+write) hits 324system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits 325system.l2c.demand_hits::cpu1.inst 413 # number of demand (read+write) hits 326system.l2c.demand_hits::cpu1.data 11 # number of demand (read+write) hits 327system.l2c.demand_hits::cpu2.inst 349 # number of demand (read+write) hits 328system.l2c.demand_hits::cpu2.data 5 # number of demand (read+write) hits 329system.l2c.demand_hits::cpu3.inst 420 # number of demand (read+write) hits 330system.l2c.demand_hits::cpu3.data 11 # number of demand (read+write) hits 331system.l2c.demand_hits::total 1443 # number of demand (read+write) hits 332system.l2c.overall_hits::cpu0.inst 229 # number of overall hits 333system.l2c.overall_hits::cpu0.data 5 # number of overall hits 334system.l2c.overall_hits::cpu1.inst 413 # number of overall hits 335system.l2c.overall_hits::cpu1.data 11 # number of overall hits 336system.l2c.overall_hits::cpu2.inst 349 # number of overall hits 337system.l2c.overall_hits::cpu2.data 5 # number of overall hits 338system.l2c.overall_hits::cpu3.inst 420 # number of overall hits 339system.l2c.overall_hits::cpu3.data 11 # number of overall hits 340system.l2c.overall_hits::total 1443 # number of overall hits 341system.l2c.ReadReq_misses::cpu0.inst 359 # number of ReadReq misses 342system.l2c.ReadReq_misses::cpu0.data 74 # number of ReadReq misses 343system.l2c.ReadReq_misses::cpu1.inst 15 # number of ReadReq misses 344system.l2c.ReadReq_misses::cpu1.data 1 # number of ReadReq misses 345system.l2c.ReadReq_misses::cpu2.inst 76 # number of ReadReq misses 346system.l2c.ReadReq_misses::cpu2.data 7 # number of ReadReq misses 347system.l2c.ReadReq_misses::cpu3.inst 10 # number of ReadReq misses 348system.l2c.ReadReq_misses::cpu3.data 1 # number of ReadReq misses 349system.l2c.ReadReq_misses::total 543 # number of ReadReq misses 350system.l2c.UpgradeReq_misses::cpu0.data 22 # number of UpgradeReq misses 351system.l2c.UpgradeReq_misses::cpu1.data 19 # number of UpgradeReq misses 352system.l2c.UpgradeReq_misses::cpu2.data 16 # number of UpgradeReq misses 353system.l2c.UpgradeReq_misses::cpu3.data 20 # number of UpgradeReq misses 354system.l2c.UpgradeReq_misses::total 77 # number of UpgradeReq misses 355system.l2c.ReadExReq_misses::cpu0.data 94 # number of ReadExReq misses 356system.l2c.ReadExReq_misses::cpu1.data 12 # number of ReadExReq misses 357system.l2c.ReadExReq_misses::cpu2.data 13 # number of ReadExReq misses 358system.l2c.ReadExReq_misses::cpu3.data 12 # number of ReadExReq misses 359system.l2c.ReadExReq_misses::total 131 # number of ReadExReq misses 360system.l2c.demand_misses::cpu0.inst 359 # number of demand (read+write) misses 361system.l2c.demand_misses::cpu0.data 168 # number of demand (read+write) misses 362system.l2c.demand_misses::cpu1.inst 15 # number of demand (read+write) misses 363system.l2c.demand_misses::cpu1.data 13 # number of demand (read+write) misses 364system.l2c.demand_misses::cpu2.inst 76 # number of demand (read+write) misses 365system.l2c.demand_misses::cpu2.data 20 # number of demand (read+write) misses 366system.l2c.demand_misses::cpu3.inst 10 # number of demand (read+write) misses 367system.l2c.demand_misses::cpu3.data 13 # number of demand (read+write) misses 368system.l2c.demand_misses::total 674 # number of demand (read+write) misses 369system.l2c.overall_misses::cpu0.inst 359 # number of overall misses 370system.l2c.overall_misses::cpu0.data 168 # number of overall misses 371system.l2c.overall_misses::cpu1.inst 15 # number of overall misses 372system.l2c.overall_misses::cpu1.data 13 # number of overall misses 373system.l2c.overall_misses::cpu2.inst 76 # number of overall misses 374system.l2c.overall_misses::cpu2.data 20 # number of overall misses 375system.l2c.overall_misses::cpu3.inst 10 # number of overall misses 376system.l2c.overall_misses::cpu3.data 13 # number of overall misses 377system.l2c.overall_misses::total 674 # number of overall misses 378system.l2c.ReadReq_miss_latency::cpu0.inst 24533250 # number of ReadReq miss cycles 379system.l2c.ReadReq_miss_latency::cpu0.data 5569000 # number of ReadReq miss cycles 380system.l2c.ReadReq_miss_latency::cpu1.inst 1122250 # number of ReadReq miss cycles 381system.l2c.ReadReq_miss_latency::cpu1.data 74500 # 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number of ReadReq accesses(hits+misses) 417system.l2c.ReadReq_accesses::cpu3.data 12 # number of ReadReq accesses(hits+misses) 418system.l2c.ReadReq_accesses::total 1986 # number of ReadReq accesses(hits+misses) 419system.l2c.Writeback_accesses::writebacks 1 # number of Writeback accesses(hits+misses) 420system.l2c.Writeback_accesses::total 1 # number of Writeback accesses(hits+misses) 421system.l2c.UpgradeReq_accesses::cpu0.data 25 # number of UpgradeReq accesses(hits+misses) 422system.l2c.UpgradeReq_accesses::cpu1.data 19 # number of UpgradeReq accesses(hits+misses) 423system.l2c.UpgradeReq_accesses::cpu2.data 16 # number of UpgradeReq accesses(hits+misses) 424system.l2c.UpgradeReq_accesses::cpu3.data 20 # number of UpgradeReq accesses(hits+misses) 425system.l2c.UpgradeReq_accesses::total 80 # number of UpgradeReq accesses(hits+misses) 426system.l2c.ReadExReq_accesses::cpu0.data 94 # number of ReadExReq accesses(hits+misses) 427system.l2c.ReadExReq_accesses::cpu1.data 12 # number of ReadExReq accesses(hits+misses) 428system.l2c.ReadExReq_accesses::cpu2.data 13 # number of ReadExReq accesses(hits+misses) 429system.l2c.ReadExReq_accesses::cpu3.data 12 # number of ReadExReq accesses(hits+misses) 430system.l2c.ReadExReq_accesses::total 131 # number of ReadExReq accesses(hits+misses) 431system.l2c.demand_accesses::cpu0.inst 588 # number of demand (read+write) accesses 432system.l2c.demand_accesses::cpu0.data 173 # number of demand (read+write) accesses 433system.l2c.demand_accesses::cpu1.inst 428 # number of demand (read+write) accesses 434system.l2c.demand_accesses::cpu1.data 24 # number of demand (read+write) accesses 435system.l2c.demand_accesses::cpu2.inst 425 # number of demand (read+write) accesses 436system.l2c.demand_accesses::cpu2.data 25 # number of demand (read+write) accesses 437system.l2c.demand_accesses::cpu3.inst 430 # number of demand (read+write) accesses 438system.l2c.demand_accesses::cpu3.data 24 # number of demand (read+write) accesses 439system.l2c.demand_accesses::total 2117 # number of demand (read+write) accesses 440system.l2c.overall_accesses::cpu0.inst 588 # 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number of demand (read+write) MSHR misses 562system.l2c.demand_mshr_misses::cpu1.inst 10 # number of demand (read+write) MSHR misses 563system.l2c.demand_mshr_misses::cpu1.data 13 # number of demand (read+write) MSHR misses 564system.l2c.demand_mshr_misses::cpu2.inst 72 # number of demand (read+write) MSHR misses 565system.l2c.demand_mshr_misses::cpu2.data 20 # number of demand (read+write) MSHR misses 566system.l2c.demand_mshr_misses::cpu3.inst 7 # number of demand (read+write) MSHR misses 567system.l2c.demand_mshr_misses::cpu3.data 13 # number of demand (read+write) MSHR misses 568system.l2c.demand_mshr_misses::total 660 # number of demand (read+write) MSHR misses 569system.l2c.overall_mshr_misses::cpu0.inst 357 # number of overall MSHR misses 570system.l2c.overall_mshr_misses::cpu0.data 168 # number of overall MSHR misses 571system.l2c.overall_mshr_misses::cpu1.inst 10 # number of overall MSHR misses 572system.l2c.overall_mshr_misses::cpu1.data 13 # number of overall MSHR misses 573system.l2c.overall_mshr_misses::cpu2.inst 72 # number of overall MSHR misses 574system.l2c.overall_mshr_misses::cpu2.data 20 # number of overall MSHR misses 575system.l2c.overall_mshr_misses::cpu3.inst 7 # number of overall MSHR misses 576system.l2c.overall_mshr_misses::cpu3.data 13 # number of overall MSHR misses 577system.l2c.overall_mshr_misses::total 660 # number of overall MSHR misses 578system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 19962500 # number of ReadReq MSHR miss cycles 579system.l2c.ReadReq_mshr_miss_latency::cpu0.data 4657000 # number of ReadReq MSHR miss cycles 580system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 698750 # number of ReadReq MSHR miss cycles 581system.l2c.ReadReq_mshr_miss_latency::cpu1.data 62500 # number of ReadReq MSHR miss cycles 582system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 4160750 # number of ReadReq MSHR miss cycles 583system.l2c.ReadReq_mshr_miss_latency::cpu2.data 408750 # number of ReadReq MSHR miss cycles 584system.l2c.ReadReq_mshr_miss_latency::cpu3.inst 431250 # number of ReadReq MSHR miss cycles 585system.l2c.ReadReq_mshr_miss_latency::cpu3.data 62500 # number of ReadReq MSHR miss cycles 586system.l2c.ReadReq_mshr_miss_latency::total 30444000 # number of ReadReq MSHR miss cycles 587system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 220022 # number of UpgradeReq MSHR miss cycles 588system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 199518 # number of UpgradeReq MSHR miss cycles 589system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 160016 # number of UpgradeReq MSHR miss cycles 590system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 200020 # number of UpgradeReq MSHR miss cycles 591system.l2c.UpgradeReq_mshr_miss_latency::total 779576 # number of UpgradeReq MSHR miss cycles 592system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 5606500 # number of ReadExReq MSHR miss cycles 593system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 701750 # number of ReadExReq MSHR miss cycles 594system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 928000 # number of ReadExReq MSHR miss cycles 595system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 792500 # number of ReadExReq MSHR miss cycles 596system.l2c.ReadExReq_mshr_miss_latency::total 8028750 # number of ReadExReq MSHR miss cycles 597system.l2c.demand_mshr_miss_latency::cpu0.inst 19962500 # number of demand (read+write) MSHR miss cycles 598system.l2c.demand_mshr_miss_latency::cpu0.data 10263500 # number of demand (read+write) MSHR miss cycles 599system.l2c.demand_mshr_miss_latency::cpu1.inst 698750 # number of demand (read+write) MSHR miss cycles 600system.l2c.demand_mshr_miss_latency::cpu1.data 764250 # number of demand (read+write) MSHR miss cycles 601system.l2c.demand_mshr_miss_latency::cpu2.inst 4160750 # number of demand (read+write) MSHR miss cycles 602system.l2c.demand_mshr_miss_latency::cpu2.data 1336750 # number of demand (read+write) MSHR miss cycles 603system.l2c.demand_mshr_miss_latency::cpu3.inst 431250 # number of demand (read+write) MSHR miss cycles 604system.l2c.demand_mshr_miss_latency::cpu3.data 855000 # number of demand (read+write) MSHR miss cycles 605system.l2c.demand_mshr_miss_latency::total 38472750 # number of demand (read+write) MSHR miss cycles 606system.l2c.overall_mshr_miss_latency::cpu0.inst 19962500 # number of overall MSHR miss cycles 607system.l2c.overall_mshr_miss_latency::cpu0.data 10263500 # number of overall MSHR miss cycles 608system.l2c.overall_mshr_miss_latency::cpu1.inst 698750 # number of overall MSHR miss cycles 609system.l2c.overall_mshr_miss_latency::cpu1.data 764250 # number of overall MSHR miss cycles 610system.l2c.overall_mshr_miss_latency::cpu2.inst 4160750 # number of overall MSHR miss cycles 611system.l2c.overall_mshr_miss_latency::cpu2.data 1336750 # number of overall MSHR miss cycles 612system.l2c.overall_mshr_miss_latency::cpu3.inst 431250 # number of overall MSHR miss cycles 613system.l2c.overall_mshr_miss_latency::cpu3.data 855000 # number of overall MSHR miss cycles 614system.l2c.overall_mshr_miss_latency::total 38472750 # number of overall MSHR miss cycles 615system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.607143 # mshr miss rate for ReadReq accesses 616system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.936709 # mshr miss rate for ReadReq accesses 617system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.023364 # mshr miss rate for ReadReq accesses 618system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.083333 # mshr miss rate for ReadReq accesses 619system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.169412 # mshr miss rate for ReadReq accesses 620system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.583333 # mshr miss rate for ReadReq accesses 621system.l2c.ReadReq_mshr_miss_rate::cpu3.inst 0.016279 # mshr miss rate for ReadReq accesses 622system.l2c.ReadReq_mshr_miss_rate::cpu3.data 0.083333 # mshr miss rate for ReadReq accesses 623system.l2c.ReadReq_mshr_miss_rate::total 0.266365 # mshr miss rate for ReadReq accesses 624system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.880000 # mshr miss rate for UpgradeReq accesses 625system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses 626system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for UpgradeReq accesses 627system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for UpgradeReq accesses 628system.l2c.UpgradeReq_mshr_miss_rate::total 0.962500 # mshr miss rate for UpgradeReq accesses 629system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses 630system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses 631system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses 632system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for ReadExReq accesses 633system.l2c.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 634system.l2c.demand_mshr_miss_rate::cpu0.inst 0.607143 # mshr miss rate for demand accesses 635system.l2c.demand_mshr_miss_rate::cpu0.data 0.971098 # mshr miss rate for demand accesses 636system.l2c.demand_mshr_miss_rate::cpu1.inst 0.023364 # mshr miss rate for demand accesses 637system.l2c.demand_mshr_miss_rate::cpu1.data 0.541667 # mshr miss rate for demand accesses 638system.l2c.demand_mshr_miss_rate::cpu2.inst 0.169412 # mshr miss rate for demand accesses 639system.l2c.demand_mshr_miss_rate::cpu2.data 0.800000 # mshr miss rate for demand accesses 640system.l2c.demand_mshr_miss_rate::cpu3.inst 0.016279 # mshr miss rate for demand accesses 641system.l2c.demand_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for demand accesses 642system.l2c.demand_mshr_miss_rate::total 0.311762 # mshr miss rate for demand accesses 643system.l2c.overall_mshr_miss_rate::cpu0.inst 0.607143 # mshr miss rate for overall accesses 644system.l2c.overall_mshr_miss_rate::cpu0.data 0.971098 # mshr miss rate for overall accesses 645system.l2c.overall_mshr_miss_rate::cpu1.inst 0.023364 # mshr miss rate for overall accesses 646system.l2c.overall_mshr_miss_rate::cpu1.data 0.541667 # mshr miss rate for overall accesses 647system.l2c.overall_mshr_miss_rate::cpu2.inst 0.169412 # mshr miss rate for overall accesses 648system.l2c.overall_mshr_miss_rate::cpu2.data 0.800000 # mshr miss rate for overall accesses 649system.l2c.overall_mshr_miss_rate::cpu3.inst 0.016279 # mshr miss rate for overall accesses 650system.l2c.overall_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for overall accesses 651system.l2c.overall_mshr_miss_rate::total 0.311762 # mshr miss rate for overall accesses 652system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 55917.366947 # average ReadReq mshr miss latency 653system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 62932.432432 # average ReadReq mshr miss latency 654system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 69875 # average ReadReq mshr miss latency 655system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 62500 # average ReadReq mshr miss latency 656system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 57788.194444 # average ReadReq mshr miss latency 657system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 58392.857143 # average ReadReq mshr miss latency 658system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 61607.142857 # average ReadReq mshr miss latency 659system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 62500 # average ReadReq mshr miss latency 660system.l2c.ReadReq_avg_mshr_miss_latency::total 57550.094518 # average ReadReq mshr miss latency 661system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average UpgradeReq mshr miss latency 662system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10500.947368 # average UpgradeReq mshr miss latency 663system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10001 # average UpgradeReq mshr miss latency 664system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 10001 # average UpgradeReq mshr miss latency 665system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10124.363636 # average UpgradeReq mshr miss latency 666system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 59643.617021 # average ReadExReq mshr miss latency 667system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 58479.166667 # average ReadExReq mshr miss latency 668system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 71384.615385 # average ReadExReq mshr miss latency 669system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 66041.666667 # average ReadExReq mshr miss latency 670system.l2c.ReadExReq_avg_mshr_miss_latency::total 61288.167939 # average ReadExReq mshr miss latency 671system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 55917.366947 # average overall mshr miss latency 672system.l2c.demand_avg_mshr_miss_latency::cpu0.data 61092.261905 # average overall mshr miss latency 673system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 69875 # average overall mshr miss latency 674system.l2c.demand_avg_mshr_miss_latency::cpu1.data 58788.461538 # average overall mshr miss latency 675system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 57788.194444 # average overall mshr miss latency 676system.l2c.demand_avg_mshr_miss_latency::cpu2.data 66837.500000 # average overall mshr miss latency 677system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 61607.142857 # average overall mshr miss latency 678system.l2c.demand_avg_mshr_miss_latency::cpu3.data 65769.230769 # average overall mshr miss latency 679system.l2c.demand_avg_mshr_miss_latency::total 58292.045455 # average overall mshr miss latency 680system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 55917.366947 # average overall mshr miss latency 681system.l2c.overall_avg_mshr_miss_latency::cpu0.data 61092.261905 # average overall mshr miss latency 682system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 69875 # average overall mshr miss latency 683system.l2c.overall_avg_mshr_miss_latency::cpu1.data 58788.461538 # average overall mshr miss latency 684system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 57788.194444 # average overall mshr miss latency 685system.l2c.overall_avg_mshr_miss_latency::cpu2.data 66837.500000 # average overall mshr miss latency 686system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 61607.142857 # average overall mshr miss latency 687system.l2c.overall_avg_mshr_miss_latency::cpu3.data 65769.230769 # average overall mshr miss latency 688system.l2c.overall_avg_mshr_miss_latency::total 58292.045455 # average overall mshr miss latency 689system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 690system.toL2Bus.throughput 1690157613 # Throughput (bytes/s) 691system.toL2Bus.trans_dist::ReadReq 2536 # Transaction distribution 692system.toL2Bus.trans_dist::ReadResp 2535 # Transaction distribution 693system.toL2Bus.trans_dist::Writeback 1 # Transaction distribution 694system.toL2Bus.trans_dist::UpgradeReq 290 # Transaction distribution 695system.toL2Bus.trans_dist::UpgradeResp 290 # Transaction distribution 696system.toL2Bus.trans_dist::ReadExReq 392 # Transaction distribution 697system.toL2Bus.trans_dist::ReadExResp 392 # Transaction distribution 698system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1175 # Packet count per connected master and slave (bytes) 699system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 587 # Packet count per connected master and slave (bytes) 700system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 856 # Packet count per connected master and slave (bytes) 701system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 360 # Packet count per connected master and slave (bytes) 702system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 850 # Packet count per connected master and slave (bytes) 703system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 371 # Packet count per connected master and slave (bytes) 704system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 860 # Packet count per connected master and slave (bytes) 705system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 356 # Packet count per connected master and slave (bytes) 706system.toL2Bus.pkt_count::total 5415 # Packet count per connected master and slave (bytes) 707system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 37568 # Cumulative packet size per connected master and slave (bytes) 708system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 11136 # Cumulative packet size per connected master and slave (bytes) 709system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 27392 # Cumulative packet size per connected master and slave (bytes) 710system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1536 # Cumulative packet size per connected master and slave (bytes) 711system.toL2Bus.tot_pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 27200 # Cumulative packet size per connected master and slave (bytes) 712system.toL2Bus.tot_pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes) 713system.toL2Bus.tot_pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 27520 # Cumulative packet size per connected master and slave (bytes) 714system.toL2Bus.tot_pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 1536 # Cumulative packet size per connected master and slave (bytes) 715system.toL2Bus.tot_pkt_size::total 135488 # Cumulative packet size per connected master and slave (bytes) 716system.toL2Bus.data_through_bus 135488 # Total data (bytes) 717system.toL2Bus.snoop_data_through_bus 51904 # Total snoop data (bytes) 718system.toL2Bus.reqLayer0.occupancy 1624477 # Layer occupancy (ticks) 719system.toL2Bus.reqLayer0.utilization 1.5 # Layer utilization (%) 720system.toL2Bus.respLayer0.occupancy 2708498 # Layer occupancy (ticks) 721system.toL2Bus.respLayer0.utilization 2.4 # Layer utilization (%) 722system.toL2Bus.respLayer1.occupancy 1467012 # Layer occupancy (ticks) 723system.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) 724system.toL2Bus.respLayer2.occupancy 1928746 # Layer occupancy (ticks) 725system.toL2Bus.respLayer2.utilization 1.7 # Layer utilization (%) 726system.toL2Bus.respLayer3.occupancy 1148249 # Layer occupancy (ticks) 727system.toL2Bus.respLayer3.utilization 1.0 # Layer utilization (%) 728system.toL2Bus.respLayer4.occupancy 1927493 # Layer occupancy (ticks) 729system.toL2Bus.respLayer4.utilization 1.7 # Layer utilization (%) 730system.toL2Bus.respLayer5.occupancy 1209237 # Layer occupancy (ticks) 731system.toL2Bus.respLayer5.utilization 1.1 # Layer utilization (%) 732system.toL2Bus.respLayer6.occupancy 1936745 # Layer occupancy (ticks) 733system.toL2Bus.respLayer6.utilization 1.7 # Layer utilization (%) 734system.toL2Bus.respLayer7.occupancy 1133003 # Layer occupancy (ticks) 735system.toL2Bus.respLayer7.utilization 1.0 # Layer utilization (%) 736system.cpu0.branchPred.lookups 82981 # Number of BP lookups 737system.cpu0.branchPred.condPredicted 80783 # Number of conditional branches predicted 738system.cpu0.branchPred.condIncorrect 1218 # Number of conditional branches incorrect 739system.cpu0.branchPred.BTBLookups 80310 # Number of BTB lookups 740system.cpu0.branchPred.BTBHits 78265 # Number of BTB hits 741system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 742system.cpu0.branchPred.BTBHitPct 97.453617 # BTB Hit Percentage 743system.cpu0.branchPred.usedRAS 512 # Number of times the RAS was used to get a target. 744system.cpu0.branchPred.RASInCorrect 132 # Number of incorrect RAS predictions. 745system.cpu0.workload.num_syscalls 89 # Number of system calls 746system.cpu0.numCycles 221746 # number of cpu cycles simulated 747system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 748system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 749system.cpu0.fetch.icacheStallCycles 17234 # Number of cycles fetch is stalled on an Icache miss 750system.cpu0.fetch.Insts 492474 # Number of instructions fetch has processed 751system.cpu0.fetch.Branches 82981 # Number of branches that fetch encountered 752system.cpu0.fetch.predictedBranches 78777 # Number of branches that fetch has predicted taken 753system.cpu0.fetch.Cycles 161662 # Number of cycles fetch has run and was not squashing or blocked 754system.cpu0.fetch.SquashCycles 3811 # Number of cycles fetch has spent squashing 755system.cpu0.fetch.BlockedCycles 13862 # Number of cycles fetch has spent blocked 756system.cpu0.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 757system.cpu0.fetch.PendingTrapStallCycles 1512 # Number of stall cycles due to pending traps 758system.cpu0.fetch.CacheLines 5835 # Number of cache lines fetched 759system.cpu0.fetch.IcacheSquashes 492 # Number of outstanding Icache misses that were squashed 760system.cpu0.fetch.rateDist::samples 196720 # Number of instructions fetched each cycle (Total) 761system.cpu0.fetch.rateDist::mean 2.503426 # Number of instructions fetched each cycle (Total) 762system.cpu0.fetch.rateDist::stdev 2.215057 # Number of instructions fetched each cycle (Total) 763system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 764system.cpu0.fetch.rateDist::0 35058 17.82% 17.82% # Number of instructions fetched each cycle (Total) 765system.cpu0.fetch.rateDist::1 80078 40.71% 58.53% # Number of instructions fetched each cycle (Total) 766system.cpu0.fetch.rateDist::2 578 0.29% 58.82% # Number of instructions fetched each cycle (Total) 767system.cpu0.fetch.rateDist::3 973 0.49% 59.32% # Number of instructions fetched each cycle (Total) 768system.cpu0.fetch.rateDist::4 477 0.24% 59.56% # Number of instructions fetched each cycle (Total) 769system.cpu0.fetch.rateDist::5 76182 38.73% 98.28% # Number of instructions fetched each cycle (Total) 770system.cpu0.fetch.rateDist::6 570 0.29% 98.57% # Number of instructions fetched each cycle (Total) 771system.cpu0.fetch.rateDist::7 349 0.18% 98.75% # Number of instructions fetched each cycle (Total) 772system.cpu0.fetch.rateDist::8 2455 1.25% 100.00% # Number of instructions fetched each cycle (Total) 773system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 774system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 775system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 776system.cpu0.fetch.rateDist::total 196720 # Number of instructions fetched each cycle (Total) 777system.cpu0.fetch.branchRate 0.374216 # Number of branch fetches per cycle 778system.cpu0.fetch.rate 2.220892 # Number of inst fetches per cycle 779system.cpu0.decode.IdleCycles 17819 # Number of cycles decode is idle 780system.cpu0.decode.BlockedCycles 15483 # Number of cycles decode is blocked 781system.cpu0.decode.RunCycles 160693 # Number of cycles decode is running 782system.cpu0.decode.UnblockCycles 280 # Number of cycles decode is unblocking 783system.cpu0.decode.SquashCycles 2445 # Number of cycles decode is squashing 784system.cpu0.decode.DecodedInsts 489648 # Number of instructions handled by decode 785system.cpu0.rename.SquashCycles 2445 # Number of cycles rename is squashing 786system.cpu0.rename.IdleCycles 18474 # Number of cycles rename is idle 787system.cpu0.rename.BlockCycles 866 # Number of cycles rename is blocking 788system.cpu0.rename.serializeStallCycles 14003 # count of cycles rename stalled for serializing inst 789system.cpu0.rename.RunCycles 160341 # Number of cycles rename is running 790system.cpu0.rename.UnblockCycles 591 # Number of cycles rename is unblocking 791system.cpu0.rename.RenamedInsts 486805 # Number of instructions processed by rename 792system.cpu0.rename.LSQFullEvents 216 # Number of times rename has blocked due to LSQ full 793system.cpu0.rename.RenamedOperands 332880 # Number of destination operands rename has renamed 794system.cpu0.rename.RenameLookups 970801 # Number of register rename lookups that rename has made 795system.cpu0.rename.int_rename_lookups 733282 # Number of integer rename lookups 796system.cpu0.rename.CommittedMaps 319911 # Number of HB maps that are committed 797system.cpu0.rename.UndoneMaps 12969 # Number of HB maps that are undone due to squashing 798system.cpu0.rename.serializingInsts 866 # count of serializing insts renamed 799system.cpu0.rename.tempSerializingInsts 886 # count of temporary serializing insts renamed 800system.cpu0.rename.skidInsts 3624 # count of insts added to the skid buffer 801system.cpu0.memDep0.insertedLoads 155743 # Number of loads inserted to the mem dependence unit. 802system.cpu0.memDep0.insertedStores 78707 # Number of stores inserted to the mem dependence unit. 803system.cpu0.memDep0.conflictingLoads 75959 # Number of conflicting loads. 804system.cpu0.memDep0.conflictingStores 75775 # Number of conflicting stores. 805system.cpu0.iq.iqInstsAdded 407094 # Number of instructions added to the IQ (excludes non-spec) 806system.cpu0.iq.iqNonSpecInstsAdded 910 # Number of non-speculative instructions added to the IQ 807system.cpu0.iq.iqInstsIssued 404367 # Number of instructions issued 808system.cpu0.iq.iqSquashedInstsIssued 132 # Number of squashed instructions issued 809system.cpu0.iq.iqSquashedInstsExamined 10771 # Number of squashed instructions iterated over during squash; mainly for profiling 810system.cpu0.iq.iqSquashedOperandsExamined 9755 # Number of squashed operands that are examined and possibly removed from graph 811system.cpu0.iq.iqSquashedNonSpecRemoved 351 # Number of squashed non-spec instructions that were removed 812system.cpu0.iq.issued_per_cycle::samples 196720 # Number of insts issued each cycle 813system.cpu0.iq.issued_per_cycle::mean 2.055546 # Number of insts issued each cycle 814system.cpu0.iq.issued_per_cycle::stdev 1.097437 # Number of insts issued each cycle 815system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 816system.cpu0.iq.issued_per_cycle::0 34036 17.30% 17.30% # Number of insts issued each cycle 817system.cpu0.iq.issued_per_cycle::1 4955 2.52% 19.82% # Number of insts issued each cycle 818system.cpu0.iq.issued_per_cycle::2 77877 39.59% 59.41% # Number of insts issued each cycle 819system.cpu0.iq.issued_per_cycle::3 77259 39.27% 98.68% # Number of insts issued each cycle 820system.cpu0.iq.issued_per_cycle::4 1573 0.80% 99.48% # Number of insts issued each cycle 821system.cpu0.iq.issued_per_cycle::5 652 0.33% 99.81% # Number of insts issued each cycle 822system.cpu0.iq.issued_per_cycle::6 264 0.13% 99.95% # Number of insts issued each cycle 823system.cpu0.iq.issued_per_cycle::7 87 0.04% 99.99% # Number of insts issued each cycle 824system.cpu0.iq.issued_per_cycle::8 17 0.01% 100.00% # Number of insts issued each cycle 825system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 826system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 827system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 828system.cpu0.iq.issued_per_cycle::total 196720 # Number of insts issued each cycle 829system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 830system.cpu0.iq.fu_full::IntAlu 57 25.79% 25.79% # attempts to use FU when none available 831system.cpu0.iq.fu_full::IntMult 0 0.00% 25.79% # attempts to use FU when none available 832system.cpu0.iq.fu_full::IntDiv 0 0.00% 25.79% # attempts to use FU when none available 833system.cpu0.iq.fu_full::FloatAdd 0 0.00% 25.79% # attempts to use FU when none available 834system.cpu0.iq.fu_full::FloatCmp 0 0.00% 25.79% # attempts to use FU when none available 835system.cpu0.iq.fu_full::FloatCvt 0 0.00% 25.79% # attempts to use FU when none available 836system.cpu0.iq.fu_full::FloatMult 0 0.00% 25.79% # attempts to use FU when none available 837system.cpu0.iq.fu_full::FloatDiv 0 0.00% 25.79% # attempts to use FU when none available 838system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 25.79% # attempts to use FU when none available 839system.cpu0.iq.fu_full::SimdAdd 0 0.00% 25.79% # attempts to use FU when none available 840system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 25.79% # attempts to use FU when none available 841system.cpu0.iq.fu_full::SimdAlu 0 0.00% 25.79% # attempts to use FU when none available 842system.cpu0.iq.fu_full::SimdCmp 0 0.00% 25.79% # attempts to use FU when none available 843system.cpu0.iq.fu_full::SimdCvt 0 0.00% 25.79% # attempts to use FU when none available 844system.cpu0.iq.fu_full::SimdMisc 0 0.00% 25.79% # attempts to use FU when none available 845system.cpu0.iq.fu_full::SimdMult 0 0.00% 25.79% # attempts to use FU when none available 846system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 25.79% # attempts to use FU when none available 847system.cpu0.iq.fu_full::SimdShift 0 0.00% 25.79% # attempts to use FU when none available 848system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 25.79% # attempts to use FU when none available 849system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 25.79% # attempts to use FU when none available 850system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 25.79% # attempts to use FU when none available 851system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 25.79% # attempts to use FU when none available 852system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 25.79% # attempts to use FU when none available 853system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 25.79% # attempts to use FU when none available 854system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 25.79% # attempts to use FU when none available 855system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 25.79% # attempts to use FU when none available 856system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 25.79% # attempts to use FU when none available 857system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.79% # attempts to use FU when none available 858system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 25.79% # attempts to use FU when none available 859system.cpu0.iq.fu_full::MemRead 52 23.53% 49.32% # attempts to use FU when none available 860system.cpu0.iq.fu_full::MemWrite 112 50.68% 100.00% # attempts to use FU when none available 861system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 862system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 863system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 864system.cpu0.iq.FU_type_0::IntAlu 170970 42.28% 42.28% # Type of FU issued 865system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.28% # Type of FU issued 866system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.28% # Type of FU issued 867system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.28% # Type of FU issued 868system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.28% # Type of FU issued 869system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.28% # Type of FU issued 870system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.28% # Type of FU issued 871system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.28% # Type of FU issued 872system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.28% # Type of FU issued 873system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.28% # Type of FU issued 874system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.28% # Type of FU issued 875system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.28% # Type of FU issued 876system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.28% # Type of FU issued 877system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.28% # Type of FU issued 878system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.28% # Type of FU issued 879system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.28% # Type of FU issued 880system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.28% # Type of FU issued 881system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.28% # Type of FU issued 882system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.28% # Type of FU issued 883system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.28% # Type of FU issued 884system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.28% # Type of FU issued 885system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.28% # Type of FU issued 886system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.28% # Type of FU issued 887system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.28% # Type of FU issued 888system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.28% # Type of FU issued 889system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.28% # Type of FU issued 890system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.28% # Type of FU issued 891system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.28% # Type of FU issued 892system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.28% # Type of FU issued 893system.cpu0.iq.FU_type_0::MemRead 155279 38.40% 80.68% # Type of FU issued 894system.cpu0.iq.FU_type_0::MemWrite 78118 19.32% 100.00% # Type of FU issued 895system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 896system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 897system.cpu0.iq.FU_type_0::total 404367 # Type of FU issued 898system.cpu0.iq.rate 1.823559 # Inst issue rate 899system.cpu0.iq.fu_busy_cnt 221 # FU busy when requested 900system.cpu0.iq.fu_busy_rate 0.000547 # FU busy rate (busy events/executed inst) 901system.cpu0.iq.int_inst_queue_reads 1005807 # Number of integer instruction queue reads 902system.cpu0.iq.int_inst_queue_writes 418829 # Number of integer instruction queue writes 903system.cpu0.iq.int_inst_queue_wakeup_accesses 402541 # Number of integer instruction queue wakeup accesses 904system.cpu0.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads 905system.cpu0.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes 906system.cpu0.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses 907system.cpu0.iq.int_alu_accesses 404588 # Number of integer alu accesses 908system.cpu0.iq.fp_alu_accesses 0 # Number of floating point alu accesses 909system.cpu0.iew.lsq.thread0.forwLoads 75486 # Number of loads that had data forwarded from stores 910system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 911system.cpu0.iew.lsq.thread0.squashedLoads 2198 # Number of loads squashed 912system.cpu0.iew.lsq.thread0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed 913system.cpu0.iew.lsq.thread0.memOrderViolation 54 # Number of memory ordering violations 914system.cpu0.iew.lsq.thread0.squashedStores 1428 # Number of stores squashed 915system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 916system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 917system.cpu0.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 918system.cpu0.iew.lsq.thread0.cacheBlocked 18 # Number of times an access to memory failed due to the cache being blocked 919system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle 920system.cpu0.iew.iewSquashCycles 2445 # Number of cycles IEW is squashing 921system.cpu0.iew.iewBlockCycles 400 # Number of cycles IEW is blocking 922system.cpu0.iew.iewUnblockCycles 35 # Number of cycles IEW is unblocking 923system.cpu0.iew.iewDispatchedInsts 484514 # Number of instructions dispatched to IQ 924system.cpu0.iew.iewDispSquashedInsts 312 # Number of squashed instructions skipped by dispatch 925system.cpu0.iew.iewDispLoadInsts 155743 # Number of dispatched load instructions 926system.cpu0.iew.iewDispStoreInsts 78707 # Number of dispatched store instructions 927system.cpu0.iew.iewDispNonSpecInsts 798 # Number of dispatched non-speculative instructions 928system.cpu0.iew.iewIQFullEvents 40 # Number of times the IQ has become full, causing a stall 929system.cpu0.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 930system.cpu0.iew.memOrderViolationEvents 54 # Number of memory order violations 931system.cpu0.iew.predictedTakenIncorrect 343 # Number of branches that were predicted taken incorrectly 932system.cpu0.iew.predictedNotTakenIncorrect 1106 # Number of branches that were predicted not taken incorrectly 933system.cpu0.iew.branchMispredicts 1449 # Number of branch mispredicts detected at execute 934system.cpu0.iew.iewExecutedInsts 403298 # Number of executed instructions 935system.cpu0.iew.iewExecLoadInsts 154949 # Number of load instructions executed 936system.cpu0.iew.iewExecSquashedInsts 1069 # Number of squashed instructions skipped in execute 937system.cpu0.iew.exec_swp 0 # number of swp insts executed 938system.cpu0.iew.exec_nop 76510 # number of nop insts executed 939system.cpu0.iew.exec_refs 232965 # number of memory reference insts executed 940system.cpu0.iew.exec_branches 80120 # Number of branches executed 941system.cpu0.iew.exec_stores 78016 # Number of stores executed 942system.cpu0.iew.exec_rate 1.818739 # Inst execution rate 943system.cpu0.iew.wb_sent 402871 # cumulative count of insts sent to commit 944system.cpu0.iew.wb_count 402541 # cumulative count of insts written-back 945system.cpu0.iew.wb_producers 238524 # num instructions producing a value 946system.cpu0.iew.wb_consumers 240975 # num instructions consuming a value 947system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 948system.cpu0.iew.wb_rate 1.815325 # insts written-back per cycle 949system.cpu0.iew.wb_fanout 0.989829 # average fanout of values written-back 950system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 951system.cpu0.commit.commitSquashedInsts 12269 # The number of squashed insts skipped by commit 952system.cpu0.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards 953system.cpu0.commit.branchMispredicts 1218 # The number of times a branch was mispredicted 954system.cpu0.commit.committed_per_cycle::samples 194275 # Number of insts commited each cycle 955system.cpu0.commit.committed_per_cycle::mean 2.430668 # Number of insts commited each cycle 956system.cpu0.commit.committed_per_cycle::stdev 2.136401 # Number of insts commited each cycle 957system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 958system.cpu0.commit.committed_per_cycle::0 34469 17.74% 17.74% # Number of insts commited each cycle 959system.cpu0.commit.committed_per_cycle::1 79913 41.13% 58.88% # Number of insts commited each cycle 960system.cpu0.commit.committed_per_cycle::2 2377 1.22% 60.10% # Number of insts commited each cycle 961system.cpu0.commit.committed_per_cycle::3 686 0.35% 60.45% # Number of insts commited each cycle 962system.cpu0.commit.committed_per_cycle::4 532 0.27% 60.73% # Number of insts commited each cycle 963system.cpu0.commit.committed_per_cycle::5 75283 38.75% 99.48% # Number of insts commited each cycle 964system.cpu0.commit.committed_per_cycle::6 460 0.24% 99.71% # Number of insts commited each cycle 965system.cpu0.commit.committed_per_cycle::7 250 0.13% 99.84% # Number of insts commited each cycle 966system.cpu0.commit.committed_per_cycle::8 305 0.16% 100.00% # Number of insts commited each cycle 967system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 968system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 969system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 970system.cpu0.commit.committed_per_cycle::total 194275 # Number of insts commited each cycle 971system.cpu0.commit.committedInsts 472218 # Number of instructions committed 972system.cpu0.commit.committedOps 472218 # Number of ops (including micro ops) committed 973system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed 974system.cpu0.commit.refs 230824 # Number of memory references committed 975system.cpu0.commit.loads 153545 # Number of loads committed 976system.cpu0.commit.membars 84 # Number of memory barriers committed 977system.cpu0.commit.branches 79166 # Number of branches committed 978system.cpu0.commit.fp_insts 0 # Number of committed floating point instructions. 979system.cpu0.commit.int_insts 318242 # Number of committed integer instructions. 980system.cpu0.commit.function_calls 223 # Number of function calls committed. 981system.cpu0.commit.op_class_0::No_OpClass 75898 16.07% 16.07% # Class of committed instruction 982system.cpu0.commit.op_class_0::IntAlu 165412 35.03% 51.10% # Class of committed instruction 983system.cpu0.commit.op_class_0::IntMult 0 0.00% 51.10% # Class of committed instruction 984system.cpu0.commit.op_class_0::IntDiv 0 0.00% 51.10% # Class of committed instruction 985system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 51.10% # Class of committed instruction 986system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 51.10% # Class of committed instruction 987system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 51.10% # Class of committed instruction 988system.cpu0.commit.op_class_0::FloatMult 0 0.00% 51.10% # Class of committed instruction 989system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 51.10% # Class of committed instruction 990system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 51.10% # Class of committed instruction 991system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 51.10% # Class of committed instruction 992system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 51.10% # Class of committed instruction 993system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 51.10% # Class of committed instruction 994system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 51.10% # Class of committed instruction 995system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 51.10% # Class of committed instruction 996system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 51.10% # Class of committed instruction 997system.cpu0.commit.op_class_0::SimdMult 0 0.00% 51.10% # Class of committed instruction 998system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 51.10% # Class of committed instruction 999system.cpu0.commit.op_class_0::SimdShift 0 0.00% 51.10% # Class of committed instruction 1000system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 51.10% # Class of committed instruction 1001system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 51.10% # Class of committed instruction 1002system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 51.10% # Class of committed instruction 1003system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 51.10% # Class of committed instruction 1004system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 51.10% # Class of committed instruction 1005system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 51.10% # Class of committed instruction 1006system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 51.10% # Class of committed instruction 1007system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 51.10% # Class of committed instruction 1008system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 51.10% # Class of committed instruction 1009system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 51.10% # Class of committed instruction 1010system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 51.10% # Class of committed instruction 1011system.cpu0.commit.op_class_0::MemRead 153629 32.53% 83.63% # Class of committed instruction 1012system.cpu0.commit.op_class_0::MemWrite 77279 16.37% 100.00% # Class of committed instruction 1013system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 1014system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 1015system.cpu0.commit.op_class_0::total 472218 # Class of committed instruction 1016system.cpu0.commit.bw_lim_events 305 # number cycles where commit BW limit reached 1017system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits 1018system.cpu0.rob.rob_reads 677296 # The number of ROB reads 1019system.cpu0.rob.rob_writes 971436 # The number of ROB writes 1020system.cpu0.timesIdled 327 # Number of times that the entire CPU went into an idle state and unscheduled itself 1021system.cpu0.idleCycles 25026 # Total number of cycles that the CPU has spent unscheduled due to idling 1022system.cpu0.committedInsts 396236 # Number of Instructions Simulated 1023system.cpu0.committedOps 396236 # Number of Ops (including micro ops) Simulated 1024system.cpu0.committedInsts_total 396236 # Number of Instructions Simulated 1025system.cpu0.cpi 0.559631 # CPI: Cycles Per Instruction 1026system.cpu0.cpi_total 0.559631 # CPI: Total CPI of All Threads 1027system.cpu0.ipc 1.786891 # IPC: Instructions Per Cycle 1028system.cpu0.ipc_total 1.786891 # IPC: Total IPC of All Threads 1029system.cpu0.int_regfile_reads 721496 # number of integer regfile reads 1030system.cpu0.int_regfile_writes 325166 # number of integer regfile writes 1031system.cpu0.fp_regfile_reads 192 # number of floating regfile reads 1032system.cpu0.misc_regfile_reads 234788 # number of misc regfile reads 1033system.cpu0.misc_regfile_writes 564 # number of misc regfile writes 1034system.cpu0.icache.tags.replacements 297 # number of replacements 1035system.cpu0.icache.tags.tagsinuse 241.323737 # Cycle average of tags in use 1036system.cpu0.icache.tags.total_refs 5079 # Total number of references to valid blocks. 1037system.cpu0.icache.tags.sampled_refs 587 # Sample count of references to valid blocks. 1038system.cpu0.icache.tags.avg_refs 8.652470 # Average number of references to valid blocks. 1039system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1040system.cpu0.icache.tags.occ_blocks::cpu0.inst 241.323737 # Average occupied blocks per requestor 1041system.cpu0.icache.tags.occ_percent::cpu0.inst 0.471335 # Average percentage of cache occupancy 1042system.cpu0.icache.tags.occ_percent::total 0.471335 # Average percentage of cache occupancy 1043system.cpu0.icache.tags.occ_task_id_blocks::1024 290 # Occupied blocks per task id 1044system.cpu0.icache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id 1045system.cpu0.icache.tags.age_task_id_blocks_1024::1 145 # Occupied blocks per task id 1046system.cpu0.icache.tags.age_task_id_blocks_1024::2 85 # Occupied blocks per task id 1047system.cpu0.icache.tags.occ_task_id_percent::1024 0.566406 # Percentage of cache occupancy per task id 1048system.cpu0.icache.tags.tag_accesses 6422 # Number of tag accesses 1049system.cpu0.icache.tags.data_accesses 6422 # Number of data accesses 1050system.cpu0.icache.ReadReq_hits::cpu0.inst 5079 # number of ReadReq hits 1051system.cpu0.icache.ReadReq_hits::total 5079 # number of ReadReq hits 1052system.cpu0.icache.demand_hits::cpu0.inst 5079 # number of demand (read+write) hits 1053system.cpu0.icache.demand_hits::total 5079 # number of demand (read+write) hits 1054system.cpu0.icache.overall_hits::cpu0.inst 5079 # number of overall hits 1055system.cpu0.icache.overall_hits::total 5079 # number of overall hits 1056system.cpu0.icache.ReadReq_misses::cpu0.inst 756 # number of ReadReq misses 1057system.cpu0.icache.ReadReq_misses::total 756 # number of ReadReq misses 1058system.cpu0.icache.demand_misses::cpu0.inst 756 # number of demand (read+write) misses 1059system.cpu0.icache.demand_misses::total 756 # number of demand (read+write) misses 1060system.cpu0.icache.overall_misses::cpu0.inst 756 # number of overall misses 1061system.cpu0.icache.overall_misses::total 756 # number of overall misses 1062system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 35655495 # number of ReadReq miss cycles 1063system.cpu0.icache.ReadReq_miss_latency::total 35655495 # number of ReadReq miss cycles 1064system.cpu0.icache.demand_miss_latency::cpu0.inst 35655495 # number of demand (read+write) miss cycles 1065system.cpu0.icache.demand_miss_latency::total 35655495 # number of demand (read+write) miss cycles 1066system.cpu0.icache.overall_miss_latency::cpu0.inst 35655495 # number of overall miss cycles 1067system.cpu0.icache.overall_miss_latency::total 35655495 # number of overall miss cycles 1068system.cpu0.icache.ReadReq_accesses::cpu0.inst 5835 # number of ReadReq accesses(hits+misses) 1069system.cpu0.icache.ReadReq_accesses::total 5835 # number of ReadReq accesses(hits+misses) 1070system.cpu0.icache.demand_accesses::cpu0.inst 5835 # number of demand (read+write) accesses 1071system.cpu0.icache.demand_accesses::total 5835 # number of demand (read+write) accesses 1072system.cpu0.icache.overall_accesses::cpu0.inst 5835 # number of overall (read+write) accesses 1073system.cpu0.icache.overall_accesses::total 5835 # number of overall (read+write) accesses 1074system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.129563 # miss rate for ReadReq accesses 1075system.cpu0.icache.ReadReq_miss_rate::total 0.129563 # miss rate for ReadReq accesses 1076system.cpu0.icache.demand_miss_rate::cpu0.inst 0.129563 # miss rate for demand accesses 1077system.cpu0.icache.demand_miss_rate::total 0.129563 # miss rate for demand accesses 1078system.cpu0.icache.overall_miss_rate::cpu0.inst 0.129563 # miss rate for overall accesses 1079system.cpu0.icache.overall_miss_rate::total 0.129563 # miss rate for overall accesses 1080system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 47163.353175 # average ReadReq miss latency 1081system.cpu0.icache.ReadReq_avg_miss_latency::total 47163.353175 # average ReadReq miss latency 1082system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 47163.353175 # average overall miss latency 1083system.cpu0.icache.demand_avg_miss_latency::total 47163.353175 # average overall miss latency 1084system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 47163.353175 # average overall miss latency 1085system.cpu0.icache.overall_avg_miss_latency::total 47163.353175 # average overall miss latency 1086system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1087system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1088system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1089system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 1090system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1091system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1092system.cpu0.icache.fast_writes 0 # number of fast writes performed 1093system.cpu0.icache.cache_copies 0 # number of cache copies performed 1094system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 168 # number of ReadReq MSHR hits 1095system.cpu0.icache.ReadReq_mshr_hits::total 168 # number of ReadReq MSHR hits 1096system.cpu0.icache.demand_mshr_hits::cpu0.inst 168 # number of demand (read+write) MSHR hits 1097system.cpu0.icache.demand_mshr_hits::total 168 # number of demand (read+write) MSHR hits 1098system.cpu0.icache.overall_mshr_hits::cpu0.inst 168 # number of overall MSHR hits 1099system.cpu0.icache.overall_mshr_hits::total 168 # number of overall MSHR hits 1100system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 588 # number of ReadReq MSHR misses 1101system.cpu0.icache.ReadReq_mshr_misses::total 588 # number of ReadReq MSHR misses 1102system.cpu0.icache.demand_mshr_misses::cpu0.inst 588 # number of demand (read+write) MSHR misses 1103system.cpu0.icache.demand_mshr_misses::total 588 # number of demand (read+write) MSHR misses 1104system.cpu0.icache.overall_mshr_misses::cpu0.inst 588 # number of overall MSHR misses 1105system.cpu0.icache.overall_mshr_misses::total 588 # number of overall MSHR misses 1106system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 27420002 # number of ReadReq MSHR miss cycles 1107system.cpu0.icache.ReadReq_mshr_miss_latency::total 27420002 # number of ReadReq MSHR miss cycles 1108system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 27420002 # number of demand (read+write) MSHR miss cycles 1109system.cpu0.icache.demand_mshr_miss_latency::total 27420002 # number of demand (read+write) MSHR miss cycles 1110system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 27420002 # number of overall MSHR miss cycles 1111system.cpu0.icache.overall_mshr_miss_latency::total 27420002 # number of overall MSHR miss cycles 1112system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.100771 # mshr miss rate for ReadReq accesses 1113system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.100771 # mshr miss rate for ReadReq accesses 1114system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.100771 # mshr miss rate for demand accesses 1115system.cpu0.icache.demand_mshr_miss_rate::total 0.100771 # mshr miss rate for demand accesses 1116system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.100771 # mshr miss rate for overall accesses 1117system.cpu0.icache.overall_mshr_miss_rate::total 0.100771 # mshr miss rate for overall accesses 1118system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 46632.656463 # average ReadReq mshr miss latency 1119system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 46632.656463 # average ReadReq mshr miss latency 1120system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 46632.656463 # average overall mshr miss latency 1121system.cpu0.icache.demand_avg_mshr_miss_latency::total 46632.656463 # average overall mshr miss latency 1122system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 46632.656463 # average overall mshr miss latency 1123system.cpu0.icache.overall_avg_mshr_miss_latency::total 46632.656463 # average overall mshr miss latency 1124system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1125system.cpu0.dcache.tags.replacements 2 # number of replacements 1126system.cpu0.dcache.tags.tagsinuse 142.026535 # Cycle average of tags in use 1127system.cpu0.dcache.tags.total_refs 155594 # Total number of references to valid blocks. 1128system.cpu0.dcache.tags.sampled_refs 170 # Sample count of references to valid blocks. 1129system.cpu0.dcache.tags.avg_refs 915.258824 # Average number of references to valid blocks. 1130system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1131system.cpu0.dcache.tags.occ_blocks::cpu0.data 142.026535 # Average occupied blocks per requestor 1132system.cpu0.dcache.tags.occ_percent::cpu0.data 0.277396 # Average percentage of cache occupancy 1133system.cpu0.dcache.tags.occ_percent::total 0.277396 # Average percentage of cache occupancy 1134system.cpu0.dcache.tags.occ_task_id_blocks::1024 168 # Occupied blocks per task id 1135system.cpu0.dcache.tags.age_task_id_blocks_1024::0 17 # Occupied blocks per task id 1136system.cpu0.dcache.tags.age_task_id_blocks_1024::1 52 # Occupied blocks per task id 1137system.cpu0.dcache.tags.age_task_id_blocks_1024::2 99 # Occupied blocks per task id 1138system.cpu0.dcache.tags.occ_task_id_percent::1024 0.328125 # Percentage of cache occupancy per task id 1139system.cpu0.dcache.tags.tag_accesses 627036 # Number of tag accesses 1140system.cpu0.dcache.tags.data_accesses 627036 # Number of data accesses 1141system.cpu0.dcache.ReadReq_hits::cpu0.data 78986 # number of ReadReq hits 1142system.cpu0.dcache.ReadReq_hits::total 78986 # number of ReadReq hits 1143system.cpu0.dcache.WriteReq_hits::cpu0.data 76692 # number of WriteReq hits 1144system.cpu0.dcache.WriteReq_hits::total 76692 # number of WriteReq hits 1145system.cpu0.dcache.SwapReq_hits::cpu0.data 21 # number of SwapReq hits 1146system.cpu0.dcache.SwapReq_hits::total 21 # number of SwapReq hits 1147system.cpu0.dcache.demand_hits::cpu0.data 155678 # number of demand (read+write) hits 1148system.cpu0.dcache.demand_hits::total 155678 # number of demand (read+write) hits 1149system.cpu0.dcache.overall_hits::cpu0.data 155678 # number of overall hits 1150system.cpu0.dcache.overall_hits::total 155678 # number of overall hits 1151system.cpu0.dcache.ReadReq_misses::cpu0.data 416 # number of ReadReq misses 1152system.cpu0.dcache.ReadReq_misses::total 416 # number of ReadReq misses 1153system.cpu0.dcache.WriteReq_misses::cpu0.data 545 # number of WriteReq misses 1154system.cpu0.dcache.WriteReq_misses::total 545 # number of WriteReq misses 1155system.cpu0.dcache.SwapReq_misses::cpu0.data 21 # number of SwapReq misses 1156system.cpu0.dcache.SwapReq_misses::total 21 # number of SwapReq misses 1157system.cpu0.dcache.demand_misses::cpu0.data 961 # number of demand (read+write) misses 1158system.cpu0.dcache.demand_misses::total 961 # number of demand (read+write) misses 1159system.cpu0.dcache.overall_misses::cpu0.data 961 # number of overall misses 1160system.cpu0.dcache.overall_misses::total 961 # number of overall misses 1161system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 13375931 # number of ReadReq miss cycles 1162system.cpu0.dcache.ReadReq_miss_latency::total 13375931 # number of ReadReq miss cycles 1163system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 32683256 # number of WriteReq miss cycles 1164system.cpu0.dcache.WriteReq_miss_latency::total 32683256 # number of WriteReq miss cycles 1165system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 404750 # number of SwapReq miss cycles 1166system.cpu0.dcache.SwapReq_miss_latency::total 404750 # number of SwapReq miss cycles 1167system.cpu0.dcache.demand_miss_latency::cpu0.data 46059187 # number of demand (read+write) miss cycles 1168system.cpu0.dcache.demand_miss_latency::total 46059187 # number of demand (read+write) miss cycles 1169system.cpu0.dcache.overall_miss_latency::cpu0.data 46059187 # number of overall miss cycles 1170system.cpu0.dcache.overall_miss_latency::total 46059187 # number of overall miss cycles 1171system.cpu0.dcache.ReadReq_accesses::cpu0.data 79402 # number of ReadReq accesses(hits+misses) 1172system.cpu0.dcache.ReadReq_accesses::total 79402 # number of ReadReq accesses(hits+misses) 1173system.cpu0.dcache.WriteReq_accesses::cpu0.data 77237 # number of WriteReq accesses(hits+misses) 1174system.cpu0.dcache.WriteReq_accesses::total 77237 # number of WriteReq accesses(hits+misses) 1175system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) 1176system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) 1177system.cpu0.dcache.demand_accesses::cpu0.data 156639 # number of demand (read+write) accesses 1178system.cpu0.dcache.demand_accesses::total 156639 # number of demand (read+write) accesses 1179system.cpu0.dcache.overall_accesses::cpu0.data 156639 # number of overall (read+write) accesses 1180system.cpu0.dcache.overall_accesses::total 156639 # number of overall (read+write) accesses 1181system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.005239 # miss rate for ReadReq accesses 1182system.cpu0.dcache.ReadReq_miss_rate::total 0.005239 # miss rate for ReadReq accesses 1183system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007056 # miss rate for WriteReq accesses 1184system.cpu0.dcache.WriteReq_miss_rate::total 0.007056 # miss rate for WriteReq accesses 1185system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.500000 # miss rate for SwapReq accesses 1186system.cpu0.dcache.SwapReq_miss_rate::total 0.500000 # miss rate for SwapReq accesses 1187system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006135 # miss rate for demand accesses 1188system.cpu0.dcache.demand_miss_rate::total 0.006135 # miss rate for demand accesses 1189system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006135 # miss rate for overall accesses 1190system.cpu0.dcache.overall_miss_rate::total 0.006135 # miss rate for overall accesses 1191system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 32153.680288 # average ReadReq miss latency 1192system.cpu0.dcache.ReadReq_avg_miss_latency::total 32153.680288 # average ReadReq miss latency 1193system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 59969.277064 # average WriteReq miss latency 1194system.cpu0.dcache.WriteReq_avg_miss_latency::total 59969.277064 # average WriteReq miss latency 1195system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 19273.809524 # average SwapReq miss latency 1196system.cpu0.dcache.SwapReq_avg_miss_latency::total 19273.809524 # average SwapReq miss latency 1197system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 47928.394381 # average overall miss latency 1198system.cpu0.dcache.demand_avg_miss_latency::total 47928.394381 # average overall miss latency 1199system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 47928.394381 # average overall miss latency 1200system.cpu0.dcache.overall_avg_miss_latency::total 47928.394381 # average overall miss latency 1201system.cpu0.dcache.blocked_cycles::no_mshrs 512 # number of cycles access was blocked 1202system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1203system.cpu0.dcache.blocked::no_mshrs 21 # number of cycles access was blocked 1204system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 1205system.cpu0.dcache.avg_blocked_cycles::no_mshrs 24.380952 # average number of cycles each access was blocked 1206system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1207system.cpu0.dcache.fast_writes 0 # number of fast writes performed 1208system.cpu0.dcache.cache_copies 0 # number of cache copies performed 1209system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks 1210system.cpu0.dcache.writebacks::total 1 # number of writebacks 1211system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 228 # number of ReadReq MSHR hits 1212system.cpu0.dcache.ReadReq_mshr_hits::total 228 # number of ReadReq MSHR hits 1213system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 370 # number of WriteReq MSHR hits 1214system.cpu0.dcache.WriteReq_mshr_hits::total 370 # number of WriteReq MSHR hits 1215system.cpu0.dcache.demand_mshr_hits::cpu0.data 598 # number of demand (read+write) MSHR hits 1216system.cpu0.dcache.demand_mshr_hits::total 598 # number of demand (read+write) MSHR hits 1217system.cpu0.dcache.overall_mshr_hits::cpu0.data 598 # number of overall MSHR hits 1218system.cpu0.dcache.overall_mshr_hits::total 598 # number of overall MSHR hits 1219system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 188 # number of ReadReq MSHR misses 1220system.cpu0.dcache.ReadReq_mshr_misses::total 188 # number of ReadReq MSHR misses 1221system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 175 # number of WriteReq MSHR misses 1222system.cpu0.dcache.WriteReq_mshr_misses::total 175 # number of WriteReq MSHR misses 1223system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 21 # number of SwapReq MSHR misses 1224system.cpu0.dcache.SwapReq_mshr_misses::total 21 # number of SwapReq MSHR misses 1225system.cpu0.dcache.demand_mshr_misses::cpu0.data 363 # number of demand (read+write) MSHR misses 1226system.cpu0.dcache.demand_mshr_misses::total 363 # number of demand (read+write) MSHR misses 1227system.cpu0.dcache.overall_mshr_misses::cpu0.data 363 # number of overall MSHR misses 1228system.cpu0.dcache.overall_mshr_misses::total 363 # number of overall MSHR misses 1229system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 6192510 # number of ReadReq MSHR miss cycles 1230system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6192510 # number of ReadReq MSHR miss cycles 1231system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7258228 # number of WriteReq MSHR miss cycles 1232system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7258228 # number of WriteReq MSHR miss cycles 1233system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 361250 # number of SwapReq MSHR miss cycles 1234system.cpu0.dcache.SwapReq_mshr_miss_latency::total 361250 # number of SwapReq MSHR miss cycles 1235system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 13450738 # number of demand (read+write) MSHR miss cycles 1236system.cpu0.dcache.demand_mshr_miss_latency::total 13450738 # number of demand (read+write) MSHR miss cycles 1237system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 13450738 # number of overall MSHR miss cycles 1238system.cpu0.dcache.overall_mshr_miss_latency::total 13450738 # number of overall MSHR miss cycles 1239system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002368 # mshr miss rate for ReadReq accesses 1240system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002368 # mshr miss rate for ReadReq accesses 1241system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002266 # mshr miss rate for WriteReq accesses 1242system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002266 # mshr miss rate for WriteReq accesses 1243system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.500000 # mshr miss rate for SwapReq accesses 1244system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SwapReq accesses 1245system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002317 # mshr miss rate for demand accesses 1246system.cpu0.dcache.demand_mshr_miss_rate::total 0.002317 # mshr miss rate for demand accesses 1247system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002317 # mshr miss rate for overall accesses 1248system.cpu0.dcache.overall_mshr_miss_rate::total 0.002317 # mshr miss rate for overall accesses 1249system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 32938.882979 # average ReadReq mshr miss latency 1250system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 32938.882979 # average ReadReq mshr miss latency 1251system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 41475.588571 # average WriteReq mshr miss latency 1252system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 41475.588571 # average WriteReq mshr miss latency 1253system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 17202.380952 # average SwapReq mshr miss latency 1254system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 17202.380952 # average SwapReq mshr miss latency 1255system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 37054.374656 # average overall mshr miss latency 1256system.cpu0.dcache.demand_avg_mshr_miss_latency::total 37054.374656 # average overall mshr miss latency 1257system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 37054.374656 # average overall mshr miss latency 1258system.cpu0.dcache.overall_avg_mshr_miss_latency::total 37054.374656 # average overall mshr miss latency 1259system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1260system.cpu1.branchPred.lookups 49222 # Number of BP lookups 1261system.cpu1.branchPred.condPredicted 46474 # Number of conditional branches predicted 1262system.cpu1.branchPred.condIncorrect 1275 # Number of conditional branches incorrect 1263system.cpu1.branchPred.BTBLookups 43117 # Number of BTB lookups 1264system.cpu1.branchPred.BTBHits 42310 # Number of BTB hits 1265system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 1266system.cpu1.branchPred.BTBHitPct 98.128348 # BTB Hit Percentage 1267system.cpu1.branchPred.usedRAS 644 # Number of times the RAS was used to get a target. 1268system.cpu1.branchPred.RASInCorrect 232 # Number of incorrect RAS predictions. 1269system.cpu1.numCycles 177641 # number of cpu cycles simulated 1270system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1271system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 1272system.cpu1.fetch.icacheStallCycles 30689 # Number of cycles fetch is stalled on an Icache miss 1273system.cpu1.fetch.Insts 271480 # Number of instructions fetch has processed 1274system.cpu1.fetch.Branches 49222 # Number of branches that fetch encountered 1275system.cpu1.fetch.predictedBranches 42954 # Number of branches that fetch has predicted taken 1276system.cpu1.fetch.Cycles 98036 # Number of cycles fetch has run and was not squashing or blocked 1277system.cpu1.fetch.SquashCycles 3712 # Number of cycles fetch has spent squashing 1278system.cpu1.fetch.BlockedCycles 35816 # Number of cycles fetch has spent blocked 1279system.cpu1.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 1280system.cpu1.fetch.NoActiveThreadStallCycles 7751 # Number of stall cycles due to no active thread to fetch from 1281system.cpu1.fetch.PendingTrapStallCycles 775 # Number of stall cycles due to pending traps 1282system.cpu1.fetch.CacheLines 22336 # Number of cache lines fetched 1283system.cpu1.fetch.IcacheSquashes 259 # Number of outstanding Icache misses that were squashed 1284system.cpu1.fetch.rateDist::samples 175432 # Number of instructions fetched each cycle (Total) 1285system.cpu1.fetch.rateDist::mean 1.547494 # Number of instructions fetched each cycle (Total) 1286system.cpu1.fetch.rateDist::stdev 2.089471 # Number of instructions fetched each cycle (Total) 1287system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 1288system.cpu1.fetch.rateDist::0 77396 44.12% 44.12% # Number of instructions fetched each cycle (Total) 1289system.cpu1.fetch.rateDist::1 50499 28.79% 72.90% # Number of instructions fetched each cycle (Total) 1290system.cpu1.fetch.rateDist::2 7414 4.23% 77.13% # Number of instructions fetched each cycle (Total) 1291system.cpu1.fetch.rateDist::3 3189 1.82% 78.95% # Number of instructions fetched each cycle (Total) 1292system.cpu1.fetch.rateDist::4 704 0.40% 79.35% # Number of instructions fetched each cycle (Total) 1293system.cpu1.fetch.rateDist::5 30975 17.66% 97.00% # Number of instructions fetched each cycle (Total) 1294system.cpu1.fetch.rateDist::6 1193 0.68% 97.68% # Number of instructions fetched each cycle (Total) 1295system.cpu1.fetch.rateDist::7 759 0.43% 98.12% # Number of instructions fetched each cycle (Total) 1296system.cpu1.fetch.rateDist::8 3303 1.88% 100.00% # Number of instructions fetched each cycle (Total) 1297system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 1298system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1299system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 1300system.cpu1.fetch.rateDist::total 175432 # Number of instructions fetched each cycle (Total) 1301system.cpu1.fetch.branchRate 0.277087 # Number of branch fetches per cycle 1302system.cpu1.fetch.rate 1.528251 # Number of inst fetches per cycle 1303system.cpu1.decode.IdleCycles 37161 # Number of cycles decode is idle 1304system.cpu1.decode.BlockedCycles 30981 # Number of cycles decode is blocked 1305system.cpu1.decode.RunCycles 90858 # Number of cycles decode is running 1306system.cpu1.decode.UnblockCycles 6321 # Number of cycles decode is unblocking 1307system.cpu1.decode.SquashCycles 2360 # Number of cycles decode is squashing 1308system.cpu1.decode.DecodedInsts 267812 # Number of instructions handled by decode 1309system.cpu1.rename.SquashCycles 2360 # Number of cycles rename is squashing 1310system.cpu1.rename.IdleCycles 37844 # Number of cycles rename is idle 1311system.cpu1.rename.BlockCycles 18525 # Number of cycles rename is blocking 1312system.cpu1.rename.serializeStallCycles 11702 # count of cycles rename stalled for serializing inst 1313system.cpu1.rename.RunCycles 84806 # Number of cycles rename is running 1314system.cpu1.rename.UnblockCycles 12444 # Number of cycles rename is unblocking 1315system.cpu1.rename.RenamedInsts 265497 # Number of instructions processed by rename 1316system.cpu1.rename.IQFullEvents 1 # Number of times rename has blocked due to IQ full 1317system.cpu1.rename.LSQFullEvents 21 # Number of times rename has blocked due to LSQ full 1318system.cpu1.rename.RenamedOperands 184374 # Number of destination operands rename has renamed 1319system.cpu1.rename.RenameLookups 502466 # Number of register rename lookups that rename has made 1320system.cpu1.rename.int_rename_lookups 391647 # Number of integer rename lookups 1321system.cpu1.rename.CommittedMaps 171546 # Number of HB maps that are committed 1322system.cpu1.rename.UndoneMaps 12828 # Number of HB maps that are undone due to squashing 1323system.cpu1.rename.serializingInsts 1100 # count of serializing insts renamed 1324system.cpu1.rename.tempSerializingInsts 1220 # count of temporary serializing insts renamed 1325system.cpu1.rename.skidInsts 15168 # count of insts added to the skid buffer 1326system.cpu1.memDep0.insertedLoads 73767 # Number of loads inserted to the mem dependence unit. 1327system.cpu1.memDep0.insertedStores 34233 # Number of stores inserted to the mem dependence unit. 1328system.cpu1.memDep0.conflictingLoads 35724 # Number of conflicting loads. 1329system.cpu1.memDep0.conflictingStores 29188 # Number of conflicting stores. 1330system.cpu1.iq.iqInstsAdded 218285 # Number of instructions added to the IQ (excludes non-spec) 1331system.cpu1.iq.iqNonSpecInstsAdded 7630 # Number of non-speculative instructions added to the IQ 1332system.cpu1.iq.iqInstsIssued 221655 # Number of instructions issued 1333system.cpu1.iq.iqSquashedInstsIssued 99 # Number of squashed instructions issued 1334system.cpu1.iq.iqSquashedInstsExamined 10737 # Number of squashed instructions iterated over during squash; mainly for profiling 1335system.cpu1.iq.iqSquashedOperandsExamined 10712 # Number of squashed operands that are examined and possibly removed from graph 1336system.cpu1.iq.iqSquashedNonSpecRemoved 591 # Number of squashed non-spec instructions that were removed 1337system.cpu1.iq.issued_per_cycle::samples 175432 # Number of insts issued each cycle 1338system.cpu1.iq.issued_per_cycle::mean 1.263481 # Number of insts issued each cycle 1339system.cpu1.iq.issued_per_cycle::stdev 1.299438 # Number of insts issued each cycle 1340system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 1341system.cpu1.iq.issued_per_cycle::0 74808 42.64% 42.64% # Number of insts issued each cycle 1342system.cpu1.iq.issued_per_cycle::1 26276 14.98% 57.62% # Number of insts issued each cycle 1343system.cpu1.iq.issued_per_cycle::2 34476 19.65% 77.27% # Number of insts issued each cycle 1344system.cpu1.iq.issued_per_cycle::3 35104 20.01% 97.28% # Number of insts issued each cycle 1345system.cpu1.iq.issued_per_cycle::4 3248 1.85% 99.13% # Number of insts issued each cycle 1346system.cpu1.iq.issued_per_cycle::5 1161 0.66% 99.80% # Number of insts issued each cycle 1347system.cpu1.iq.issued_per_cycle::6 252 0.14% 99.94% # Number of insts issued each cycle 1348system.cpu1.iq.issued_per_cycle::7 50 0.03% 99.97% # Number of insts issued each cycle 1349system.cpu1.iq.issued_per_cycle::8 57 0.03% 100.00% # Number of insts issued each cycle 1350system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1351system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1352system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 1353system.cpu1.iq.issued_per_cycle::total 175432 # Number of insts issued each cycle 1354system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 1355system.cpu1.iq.fu_full::IntAlu 12 4.51% 4.51% # attempts to use FU when none available 1356system.cpu1.iq.fu_full::IntMult 0 0.00% 4.51% # attempts to use FU when none available 1357system.cpu1.iq.fu_full::IntDiv 0 0.00% 4.51% # attempts to use FU when none available 1358system.cpu1.iq.fu_full::FloatAdd 0 0.00% 4.51% # attempts to use FU when none available 1359system.cpu1.iq.fu_full::FloatCmp 0 0.00% 4.51% # attempts to use FU when none available 1360system.cpu1.iq.fu_full::FloatCvt 0 0.00% 4.51% # attempts to use FU when none available 1361system.cpu1.iq.fu_full::FloatMult 0 0.00% 4.51% # attempts to use FU when none available 1362system.cpu1.iq.fu_full::FloatDiv 0 0.00% 4.51% # attempts to use FU when none available 1363system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 4.51% # attempts to use FU when none available 1364system.cpu1.iq.fu_full::SimdAdd 0 0.00% 4.51% # attempts to use FU when none available 1365system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 4.51% # attempts to use FU when none available 1366system.cpu1.iq.fu_full::SimdAlu 0 0.00% 4.51% # attempts to use FU when none available 1367system.cpu1.iq.fu_full::SimdCmp 0 0.00% 4.51% # attempts to use FU when none available 1368system.cpu1.iq.fu_full::SimdCvt 0 0.00% 4.51% # attempts to use FU when none available 1369system.cpu1.iq.fu_full::SimdMisc 0 0.00% 4.51% # attempts to use FU when none available 1370system.cpu1.iq.fu_full::SimdMult 0 0.00% 4.51% # attempts to use FU when none available 1371system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 4.51% # attempts to use FU when none available 1372system.cpu1.iq.fu_full::SimdShift 0 0.00% 4.51% # attempts to use FU when none available 1373system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 4.51% # attempts to use FU when none available 1374system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 4.51% # attempts to use FU when none available 1375system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 4.51% # attempts to use FU when none available 1376system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 4.51% # attempts to use FU when none available 1377system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 4.51% # attempts to use FU when none available 1378system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 4.51% # attempts to use FU when none available 1379system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 4.51% # attempts to use FU when none available 1380system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 4.51% # attempts to use FU when none available 1381system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 4.51% # attempts to use FU when none available 1382system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.51% # attempts to use FU when none available 1383system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 4.51% # attempts to use FU when none available 1384system.cpu1.iq.fu_full::MemRead 44 16.54% 21.05% # attempts to use FU when none available 1385system.cpu1.iq.fu_full::MemWrite 210 78.95% 100.00% # attempts to use FU when none available 1386system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 1387system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 1388system.cpu1.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 1389system.cpu1.iq.FU_type_0::IntAlu 108760 49.07% 49.07% # Type of FU issued 1390system.cpu1.iq.FU_type_0::IntMult 0 0.00% 49.07% # Type of FU issued 1391system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 49.07% # Type of FU issued 1392system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 49.07% # Type of FU issued 1393system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 49.07% # Type of FU issued 1394system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 49.07% # Type of FU issued 1395system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 49.07% # Type of FU issued 1396system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 49.07% # Type of FU issued 1397system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 49.07% # Type of FU issued 1398system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 49.07% # Type of FU issued 1399system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 49.07% # Type of FU issued 1400system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 49.07% # Type of FU issued 1401system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 49.07% # Type of FU issued 1402system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 49.07% # Type of FU issued 1403system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 49.07% # Type of FU issued 1404system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 49.07% # Type of FU issued 1405system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 49.07% # Type of FU issued 1406system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 49.07% # Type of FU issued 1407system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.07% # Type of FU issued 1408system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 49.07% # Type of FU issued 1409system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.07% # Type of FU issued 1410system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.07% # Type of FU issued 1411system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.07% # Type of FU issued 1412system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.07% # Type of FU issued 1413system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.07% # Type of FU issued 1414system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.07% # Type of FU issued 1415system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 49.07% # Type of FU issued 1416system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.07% # Type of FU issued 1417system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.07% # Type of FU issued 1418system.cpu1.iq.FU_type_0::MemRead 79356 35.80% 84.87% # Type of FU issued 1419system.cpu1.iq.FU_type_0::MemWrite 33539 15.13% 100.00% # Type of FU issued 1420system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 1421system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 1422system.cpu1.iq.FU_type_0::total 221655 # Type of FU issued 1423system.cpu1.iq.rate 1.247769 # Inst issue rate 1424system.cpu1.iq.fu_busy_cnt 266 # FU busy when requested 1425system.cpu1.iq.fu_busy_rate 0.001200 # FU busy rate (busy events/executed inst) 1426system.cpu1.iq.int_inst_queue_reads 619107 # Number of integer instruction queue reads 1427system.cpu1.iq.int_inst_queue_writes 236695 # Number of integer instruction queue writes 1428system.cpu1.iq.int_inst_queue_wakeup_accesses 219827 # Number of integer instruction queue wakeup accesses 1429system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads 1430system.cpu1.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes 1431system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses 1432system.cpu1.iq.int_alu_accesses 221921 # Number of integer alu accesses 1433system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses 1434system.cpu1.iew.lsq.thread0.forwLoads 28930 # Number of loads that had data forwarded from stores 1435system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 1436system.cpu1.iew.lsq.thread0.squashedLoads 2394 # Number of loads squashed 1437system.cpu1.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed 1438system.cpu1.iew.lsq.thread0.memOrderViolation 43 # Number of memory ordering violations 1439system.cpu1.iew.lsq.thread0.squashedStores 1444 # Number of stores squashed 1440system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 1441system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 1442system.cpu1.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 1443system.cpu1.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked 1444system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle 1445system.cpu1.iew.iewSquashCycles 2360 # Number of cycles IEW is squashing 1446system.cpu1.iew.iewBlockCycles 686 # Number of cycles IEW is blocking 1447system.cpu1.iew.iewUnblockCycles 42 # Number of cycles IEW is unblocking 1448system.cpu1.iew.iewDispatchedInsts 262565 # Number of instructions dispatched to IQ 1449system.cpu1.iew.iewDispSquashedInsts 349 # Number of squashed instructions skipped by dispatch 1450system.cpu1.iew.iewDispLoadInsts 73767 # Number of dispatched load instructions 1451system.cpu1.iew.iewDispStoreInsts 34233 # Number of dispatched store instructions 1452system.cpu1.iew.iewDispNonSpecInsts 1056 # Number of dispatched non-speculative instructions 1453system.cpu1.iew.iewIQFullEvents 42 # Number of times the IQ has become full, causing a stall 1454system.cpu1.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 1455system.cpu1.iew.memOrderViolationEvents 43 # Number of memory order violations 1456system.cpu1.iew.predictedTakenIncorrect 467 # Number of branches that were predicted taken incorrectly 1457system.cpu1.iew.predictedNotTakenIncorrect 918 # Number of branches that were predicted not taken incorrectly 1458system.cpu1.iew.branchMispredicts 1385 # Number of branch mispredicts detected at execute 1459system.cpu1.iew.iewExecutedInsts 220479 # Number of executed instructions 1460system.cpu1.iew.iewExecLoadInsts 72759 # Number of load instructions executed 1461system.cpu1.iew.iewExecSquashedInsts 1176 # Number of squashed instructions skipped in execute 1462system.cpu1.iew.exec_swp 0 # number of swp insts executed 1463system.cpu1.iew.exec_nop 36650 # number of nop insts executed 1464system.cpu1.iew.exec_refs 106217 # number of memory reference insts executed 1465system.cpu1.iew.exec_branches 45894 # Number of branches executed 1466system.cpu1.iew.exec_stores 33458 # Number of stores executed 1467system.cpu1.iew.exec_rate 1.241149 # Inst execution rate 1468system.cpu1.iew.wb_sent 220112 # cumulative count of insts sent to commit 1469system.cpu1.iew.wb_count 219827 # cumulative count of insts written-back 1470system.cpu1.iew.wb_producers 122951 # num instructions producing a value 1471system.cpu1.iew.wb_consumers 127610 # num instructions consuming a value 1472system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 1473system.cpu1.iew.wb_rate 1.237479 # insts written-back per cycle 1474system.cpu1.iew.wb_fanout 0.963490 # average fanout of values written-back 1475system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 1476system.cpu1.commit.commitSquashedInsts 12326 # The number of squashed insts skipped by commit 1477system.cpu1.commit.commitNonSpecStalls 7039 # The number of times commit has been forced to stall to communicate backwards 1478system.cpu1.commit.branchMispredicts 1275 # The number of times a branch was mispredicted 1479system.cpu1.commit.committed_per_cycle::samples 165321 # Number of insts commited each cycle 1480system.cpu1.commit.committed_per_cycle::mean 1.513546 # Number of insts commited each cycle 1481system.cpu1.commit.committed_per_cycle::stdev 1.970448 # Number of insts commited each cycle 1482system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 1483system.cpu1.commit.committed_per_cycle::0 73866 44.68% 44.68% # Number of insts commited each cycle 1484system.cpu1.commit.committed_per_cycle::1 44045 26.64% 71.32% # Number of insts commited each cycle 1485system.cpu1.commit.committed_per_cycle::2 6103 3.69% 75.01% # Number of insts commited each cycle 1486system.cpu1.commit.committed_per_cycle::3 7953 4.81% 79.82% # Number of insts commited each cycle 1487system.cpu1.commit.committed_per_cycle::4 1564 0.95% 80.77% # Number of insts commited each cycle 1488system.cpu1.commit.committed_per_cycle::5 29501 17.84% 98.62% # Number of insts commited each cycle 1489system.cpu1.commit.committed_per_cycle::6 477 0.29% 98.90% # Number of insts commited each cycle 1490system.cpu1.commit.committed_per_cycle::7 1008 0.61% 99.51% # Number of insts commited each cycle 1491system.cpu1.commit.committed_per_cycle::8 804 0.49% 100.00% # Number of insts commited each cycle 1492system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 1493system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 1494system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 1495system.cpu1.commit.committed_per_cycle::total 165321 # Number of insts commited each cycle 1496system.cpu1.commit.committedInsts 250221 # Number of instructions committed 1497system.cpu1.commit.committedOps 250221 # Number of ops (including micro ops) committed 1498system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed 1499system.cpu1.commit.refs 104162 # Number of memory references committed 1500system.cpu1.commit.loads 71373 # Number of loads committed 1501system.cpu1.commit.membars 6322 # Number of memory barriers committed 1502system.cpu1.commit.branches 45072 # Number of branches committed 1503system.cpu1.commit.fp_insts 0 # Number of committed floating point instructions. 1504system.cpu1.commit.int_insts 171353 # Number of committed integer instructions. 1505system.cpu1.commit.function_calls 322 # Number of function calls committed. 1506system.cpu1.commit.op_class_0::No_OpClass 35859 14.33% 14.33% # Class of committed instruction 1507system.cpu1.commit.op_class_0::IntAlu 103878 41.51% 55.85% # Class of committed instruction 1508system.cpu1.commit.op_class_0::IntMult 0 0.00% 55.85% # Class of committed instruction 1509system.cpu1.commit.op_class_0::IntDiv 0 0.00% 55.85% # Class of committed instruction 1510system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 55.85% # Class of committed instruction 1511system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 55.85% # Class of committed instruction 1512system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 55.85% # Class of committed instruction 1513system.cpu1.commit.op_class_0::FloatMult 0 0.00% 55.85% # Class of committed instruction 1514system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 55.85% # Class of committed instruction 1515system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 55.85% # Class of committed instruction 1516system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 55.85% # Class of committed instruction 1517system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 55.85% # Class of committed instruction 1518system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 55.85% # Class of committed instruction 1519system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 55.85% # Class of committed instruction 1520system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 55.85% # Class of committed instruction 1521system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 55.85% # Class of committed instruction 1522system.cpu1.commit.op_class_0::SimdMult 0 0.00% 55.85% # Class of committed instruction 1523system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 55.85% # Class of committed instruction 1524system.cpu1.commit.op_class_0::SimdShift 0 0.00% 55.85% # Class of committed instruction 1525system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 55.85% # Class of committed instruction 1526system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 55.85% # Class of committed instruction 1527system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 55.85% # Class of committed instruction 1528system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 55.85% # Class of committed instruction 1529system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 55.85% # Class of committed instruction 1530system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 55.85% # Class of committed instruction 1531system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 55.85% # Class of committed instruction 1532system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 55.85% # Class of committed instruction 1533system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 55.85% # Class of committed instruction 1534system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.85% # Class of committed instruction 1535system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.85% # Class of committed instruction 1536system.cpu1.commit.op_class_0::MemRead 77695 31.05% 86.90% # Class of committed instruction 1537system.cpu1.commit.op_class_0::MemWrite 32789 13.10% 100.00% # Class of committed instruction 1538system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 1539system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 1540system.cpu1.commit.op_class_0::total 250221 # Class of committed instruction 1541system.cpu1.commit.bw_lim_events 804 # number cycles where commit BW limit reached 1542system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits 1543system.cpu1.rob.rob_reads 426477 # The number of ROB reads 1544system.cpu1.rob.rob_writes 527460 # The number of ROB writes 1545system.cpu1.timesIdled 216 # Number of times that the entire CPU went into an idle state and unscheduled itself 1546system.cpu1.idleCycles 2209 # Total number of cycles that the CPU has spent unscheduled due to idling 1547system.cpu1.quiesceCycles 44103 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1548system.cpu1.committedInsts 208040 # Number of Instructions Simulated 1549system.cpu1.committedOps 208040 # Number of Ops (including micro ops) Simulated 1550system.cpu1.committedInsts_total 208040 # Number of Instructions Simulated 1551system.cpu1.cpi 0.853879 # CPI: Cycles Per Instruction 1552system.cpu1.cpi_total 0.853879 # CPI: Total CPI of All Threads 1553system.cpu1.ipc 1.171126 # IPC: Instructions Per Cycle 1554system.cpu1.ipc_total 1.171126 # IPC: Total IPC of All Threads 1555system.cpu1.int_regfile_reads 377205 # number of integer regfile reads 1556system.cpu1.int_regfile_writes 176304 # number of integer regfile writes 1557system.cpu1.fp_regfile_writes 64 # number of floating regfile writes 1558system.cpu1.misc_regfile_reads 107775 # number of misc regfile reads 1559system.cpu1.misc_regfile_writes 648 # number of misc regfile writes 1560system.cpu1.icache.tags.replacements 318 # number of replacements 1561system.cpu1.icache.tags.tagsinuse 76.769709 # Cycle average of tags in use 1562system.cpu1.icache.tags.total_refs 21861 # Total number of references to valid blocks. 1563system.cpu1.icache.tags.sampled_refs 428 # Sample count of references to valid blocks. 1564system.cpu1.icache.tags.avg_refs 51.077103 # Average number of references to valid blocks. 1565system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1566system.cpu1.icache.tags.occ_blocks::cpu1.inst 76.769709 # Average occupied blocks per requestor 1567system.cpu1.icache.tags.occ_percent::cpu1.inst 0.149941 # Average percentage of cache occupancy 1568system.cpu1.icache.tags.occ_percent::total 0.149941 # Average percentage of cache occupancy 1569system.cpu1.icache.tags.occ_task_id_blocks::1024 110 # Occupied blocks per task id 1570system.cpu1.icache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id 1571system.cpu1.icache.tags.age_task_id_blocks_1024::1 99 # Occupied blocks per task id 1572system.cpu1.icache.tags.occ_task_id_percent::1024 0.214844 # Percentage of cache occupancy per task id 1573system.cpu1.icache.tags.tag_accesses 22764 # Number of tag accesses 1574system.cpu1.icache.tags.data_accesses 22764 # Number of data accesses 1575system.cpu1.icache.ReadReq_hits::cpu1.inst 21861 # number of ReadReq hits 1576system.cpu1.icache.ReadReq_hits::total 21861 # number of ReadReq hits 1577system.cpu1.icache.demand_hits::cpu1.inst 21861 # number of demand (read+write) hits 1578system.cpu1.icache.demand_hits::total 21861 # number of demand (read+write) hits 1579system.cpu1.icache.overall_hits::cpu1.inst 21861 # number of overall hits 1580system.cpu1.icache.overall_hits::total 21861 # number of overall hits 1581system.cpu1.icache.ReadReq_misses::cpu1.inst 475 # number of ReadReq misses 1582system.cpu1.icache.ReadReq_misses::total 475 # number of ReadReq misses 1583system.cpu1.icache.demand_misses::cpu1.inst 475 # number of demand (read+write) misses 1584system.cpu1.icache.demand_misses::total 475 # number of demand (read+write) misses 1585system.cpu1.icache.overall_misses::cpu1.inst 475 # number of overall misses 1586system.cpu1.icache.overall_misses::total 475 # number of overall misses 1587system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7146245 # number of ReadReq miss cycles 1588system.cpu1.icache.ReadReq_miss_latency::total 7146245 # number of ReadReq miss cycles 1589system.cpu1.icache.demand_miss_latency::cpu1.inst 7146245 # number of demand (read+write) miss cycles 1590system.cpu1.icache.demand_miss_latency::total 7146245 # number of demand (read+write) miss cycles 1591system.cpu1.icache.overall_miss_latency::cpu1.inst 7146245 # number of overall miss cycles 1592system.cpu1.icache.overall_miss_latency::total 7146245 # number of overall miss cycles 1593system.cpu1.icache.ReadReq_accesses::cpu1.inst 22336 # number of ReadReq accesses(hits+misses) 1594system.cpu1.icache.ReadReq_accesses::total 22336 # number of ReadReq accesses(hits+misses) 1595system.cpu1.icache.demand_accesses::cpu1.inst 22336 # number of demand (read+write) accesses 1596system.cpu1.icache.demand_accesses::total 22336 # number of demand (read+write) accesses 1597system.cpu1.icache.overall_accesses::cpu1.inst 22336 # number of overall (read+write) accesses 1598system.cpu1.icache.overall_accesses::total 22336 # number of overall (read+write) accesses 1599system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.021266 # miss rate for ReadReq accesses 1600system.cpu1.icache.ReadReq_miss_rate::total 0.021266 # miss rate for ReadReq accesses 1601system.cpu1.icache.demand_miss_rate::cpu1.inst 0.021266 # miss rate for demand accesses 1602system.cpu1.icache.demand_miss_rate::total 0.021266 # miss rate for demand accesses 1603system.cpu1.icache.overall_miss_rate::cpu1.inst 0.021266 # miss rate for overall accesses 1604system.cpu1.icache.overall_miss_rate::total 0.021266 # miss rate for overall accesses 1605system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15044.726316 # average ReadReq miss latency 1606system.cpu1.icache.ReadReq_avg_miss_latency::total 15044.726316 # average ReadReq miss latency 1607system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15044.726316 # average overall miss latency 1608system.cpu1.icache.demand_avg_miss_latency::total 15044.726316 # average overall miss latency 1609system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15044.726316 # average overall miss latency 1610system.cpu1.icache.overall_avg_miss_latency::total 15044.726316 # average overall miss latency 1611system.cpu1.icache.blocked_cycles::no_mshrs 26 # number of cycles access was blocked 1612system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1613system.cpu1.icache.blocked::no_mshrs 2 # number of cycles access was blocked 1614system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1615system.cpu1.icache.avg_blocked_cycles::no_mshrs 13 # average number of cycles each access was blocked 1616system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1617system.cpu1.icache.fast_writes 0 # number of fast writes performed 1618system.cpu1.icache.cache_copies 0 # number of cache copies performed 1619system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 47 # number of ReadReq MSHR hits 1620system.cpu1.icache.ReadReq_mshr_hits::total 47 # number of ReadReq MSHR hits 1621system.cpu1.icache.demand_mshr_hits::cpu1.inst 47 # number of demand (read+write) MSHR hits 1622system.cpu1.icache.demand_mshr_hits::total 47 # number of demand (read+write) MSHR hits 1623system.cpu1.icache.overall_mshr_hits::cpu1.inst 47 # number of overall MSHR hits 1624system.cpu1.icache.overall_mshr_hits::total 47 # number of overall MSHR hits 1625system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 428 # number of ReadReq MSHR misses 1626system.cpu1.icache.ReadReq_mshr_misses::total 428 # number of ReadReq MSHR misses 1627system.cpu1.icache.demand_mshr_misses::cpu1.inst 428 # number of demand (read+write) MSHR misses 1628system.cpu1.icache.demand_mshr_misses::total 428 # number of demand (read+write) MSHR misses 1629system.cpu1.icache.overall_mshr_misses::cpu1.inst 428 # number of overall MSHR misses 1630system.cpu1.icache.overall_mshr_misses::total 428 # number of overall MSHR misses 1631system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5694254 # number of ReadReq MSHR miss cycles 1632system.cpu1.icache.ReadReq_mshr_miss_latency::total 5694254 # number of ReadReq MSHR miss cycles 1633system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5694254 # number of demand (read+write) MSHR miss cycles 1634system.cpu1.icache.demand_mshr_miss_latency::total 5694254 # number of demand (read+write) MSHR miss cycles 1635system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5694254 # number of overall MSHR miss cycles 1636system.cpu1.icache.overall_mshr_miss_latency::total 5694254 # number of overall MSHR miss cycles 1637system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.019162 # mshr miss rate for ReadReq accesses 1638system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.019162 # mshr miss rate for ReadReq accesses 1639system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.019162 # mshr miss rate for demand accesses 1640system.cpu1.icache.demand_mshr_miss_rate::total 0.019162 # mshr miss rate for demand accesses 1641system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.019162 # mshr miss rate for overall accesses 1642system.cpu1.icache.overall_mshr_miss_rate::total 0.019162 # mshr miss rate for overall accesses 1643system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13304.331776 # average ReadReq mshr miss latency 1644system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13304.331776 # average ReadReq mshr miss latency 1645system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13304.331776 # average overall mshr miss latency 1646system.cpu1.icache.demand_avg_mshr_miss_latency::total 13304.331776 # average overall mshr miss latency 1647system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13304.331776 # average overall mshr miss latency 1648system.cpu1.icache.overall_avg_mshr_miss_latency::total 13304.331776 # average overall mshr miss latency 1649system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1650system.cpu1.dcache.tags.replacements 0 # number of replacements 1651system.cpu1.dcache.tags.tagsinuse 23.645460 # Cycle average of tags in use 1652system.cpu1.dcache.tags.total_refs 38791 # Total number of references to valid blocks. 1653system.cpu1.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks. 1654system.cpu1.dcache.tags.avg_refs 1385.392857 # Average number of references to valid blocks. 1655system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1656system.cpu1.dcache.tags.occ_blocks::cpu1.data 23.645460 # Average occupied blocks per requestor 1657system.cpu1.dcache.tags.occ_percent::cpu1.data 0.046183 # Average percentage of cache occupancy 1658system.cpu1.dcache.tags.occ_percent::total 0.046183 # Average percentage of cache occupancy 1659system.cpu1.dcache.tags.occ_task_id_blocks::1024 28 # Occupied blocks per task id 1660system.cpu1.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id 1661system.cpu1.dcache.tags.occ_task_id_percent::1024 0.054688 # Percentage of cache occupancy per task id 1662system.cpu1.dcache.tags.tag_accesses 306653 # Number of tag accesses 1663system.cpu1.dcache.tags.data_accesses 306653 # Number of data accesses 1664system.cpu1.dcache.ReadReq_hits::cpu1.data 43477 # number of ReadReq hits 1665system.cpu1.dcache.ReadReq_hits::total 43477 # number of ReadReq hits 1666system.cpu1.dcache.WriteReq_hits::cpu1.data 32586 # number of WriteReq hits 1667system.cpu1.dcache.WriteReq_hits::total 32586 # number of WriteReq hits 1668system.cpu1.dcache.SwapReq_hits::cpu1.data 14 # number of SwapReq hits 1669system.cpu1.dcache.SwapReq_hits::total 14 # number of SwapReq hits 1670system.cpu1.dcache.demand_hits::cpu1.data 76063 # number of demand (read+write) hits 1671system.cpu1.dcache.demand_hits::total 76063 # number of demand (read+write) hits 1672system.cpu1.dcache.overall_hits::cpu1.data 76063 # number of overall hits 1673system.cpu1.dcache.overall_hits::total 76063 # number of overall hits 1674system.cpu1.dcache.ReadReq_misses::cpu1.data 336 # number of ReadReq misses 1675system.cpu1.dcache.ReadReq_misses::total 336 # number of ReadReq misses 1676system.cpu1.dcache.WriteReq_misses::cpu1.data 132 # number of WriteReq misses 1677system.cpu1.dcache.WriteReq_misses::total 132 # number of WriteReq misses 1678system.cpu1.dcache.SwapReq_misses::cpu1.data 57 # number of SwapReq misses 1679system.cpu1.dcache.SwapReq_misses::total 57 # number of SwapReq misses 1680system.cpu1.dcache.demand_misses::cpu1.data 468 # number of demand (read+write) misses 1681system.cpu1.dcache.demand_misses::total 468 # number of demand (read+write) misses 1682system.cpu1.dcache.overall_misses::cpu1.data 468 # number of overall misses 1683system.cpu1.dcache.overall_misses::total 468 # number of overall misses 1684system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 4177635 # number of ReadReq miss cycles 1685system.cpu1.dcache.ReadReq_miss_latency::total 4177635 # number of ReadReq miss cycles 1686system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2763761 # number of WriteReq miss cycles 1687system.cpu1.dcache.WriteReq_miss_latency::total 2763761 # number of WriteReq miss cycles 1688system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 521507 # number of SwapReq miss cycles 1689system.cpu1.dcache.SwapReq_miss_latency::total 521507 # number of SwapReq miss cycles 1690system.cpu1.dcache.demand_miss_latency::cpu1.data 6941396 # number of demand (read+write) miss cycles 1691system.cpu1.dcache.demand_miss_latency::total 6941396 # number of demand (read+write) miss cycles 1692system.cpu1.dcache.overall_miss_latency::cpu1.data 6941396 # number of overall miss cycles 1693system.cpu1.dcache.overall_miss_latency::total 6941396 # number of overall miss cycles 1694system.cpu1.dcache.ReadReq_accesses::cpu1.data 43813 # number of ReadReq accesses(hits+misses) 1695system.cpu1.dcache.ReadReq_accesses::total 43813 # number of ReadReq accesses(hits+misses) 1696system.cpu1.dcache.WriteReq_accesses::cpu1.data 32718 # number of WriteReq accesses(hits+misses) 1697system.cpu1.dcache.WriteReq_accesses::total 32718 # number of WriteReq accesses(hits+misses) 1698system.cpu1.dcache.SwapReq_accesses::cpu1.data 71 # number of SwapReq accesses(hits+misses) 1699system.cpu1.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses) 1700system.cpu1.dcache.demand_accesses::cpu1.data 76531 # number of demand (read+write) accesses 1701system.cpu1.dcache.demand_accesses::total 76531 # number of demand (read+write) accesses 1702system.cpu1.dcache.overall_accesses::cpu1.data 76531 # number of overall (read+write) accesses 1703system.cpu1.dcache.overall_accesses::total 76531 # number of overall (read+write) accesses 1704system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.007669 # miss rate for ReadReq accesses 1705system.cpu1.dcache.ReadReq_miss_rate::total 0.007669 # miss rate for ReadReq accesses 1706system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.004034 # miss rate for WriteReq accesses 1707system.cpu1.dcache.WriteReq_miss_rate::total 0.004034 # miss rate for WriteReq accesses 1708system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.802817 # miss rate for SwapReq accesses 1709system.cpu1.dcache.SwapReq_miss_rate::total 0.802817 # miss rate for SwapReq accesses 1710system.cpu1.dcache.demand_miss_rate::cpu1.data 0.006115 # miss rate for demand accesses 1711system.cpu1.dcache.demand_miss_rate::total 0.006115 # miss rate for demand accesses 1712system.cpu1.dcache.overall_miss_rate::cpu1.data 0.006115 # miss rate for overall accesses 1713system.cpu1.dcache.overall_miss_rate::total 0.006115 # miss rate for overall accesses 1714system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12433.437500 # average ReadReq miss latency 1715system.cpu1.dcache.ReadReq_avg_miss_latency::total 12433.437500 # average ReadReq miss latency 1716system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 20937.583333 # average WriteReq miss latency 1717system.cpu1.dcache.WriteReq_avg_miss_latency::total 20937.583333 # average WriteReq miss latency 1718system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 9149.245614 # average SwapReq miss latency 1719system.cpu1.dcache.SwapReq_avg_miss_latency::total 9149.245614 # average SwapReq miss latency 1720system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14832.042735 # average overall miss latency 1721system.cpu1.dcache.demand_avg_miss_latency::total 14832.042735 # average overall miss latency 1722system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14832.042735 # average overall miss latency 1723system.cpu1.dcache.overall_avg_miss_latency::total 14832.042735 # average overall miss latency 1724system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1725system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1726system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1727system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1728system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1729system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1730system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1731system.cpu1.dcache.cache_copies 0 # number of cache copies performed 1732system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 178 # number of ReadReq MSHR hits 1733system.cpu1.dcache.ReadReq_mshr_hits::total 178 # number of ReadReq MSHR hits 1734system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 30 # number of WriteReq MSHR hits 1735system.cpu1.dcache.WriteReq_mshr_hits::total 30 # number of WriteReq MSHR hits 1736system.cpu1.dcache.demand_mshr_hits::cpu1.data 208 # number of demand (read+write) MSHR hits 1737system.cpu1.dcache.demand_mshr_hits::total 208 # number of demand (read+write) MSHR hits 1738system.cpu1.dcache.overall_mshr_hits::cpu1.data 208 # number of overall MSHR hits 1739system.cpu1.dcache.overall_mshr_hits::total 208 # number of overall MSHR hits 1740system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 158 # number of ReadReq MSHR misses 1741system.cpu1.dcache.ReadReq_mshr_misses::total 158 # number of ReadReq MSHR misses 1742system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 102 # number of WriteReq MSHR misses 1743system.cpu1.dcache.WriteReq_mshr_misses::total 102 # number of WriteReq MSHR misses 1744system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 57 # number of SwapReq MSHR misses 1745system.cpu1.dcache.SwapReq_mshr_misses::total 57 # number of SwapReq MSHR misses 1746system.cpu1.dcache.demand_mshr_misses::cpu1.data 260 # number of demand (read+write) MSHR misses 1747system.cpu1.dcache.demand_mshr_misses::total 260 # number of demand (read+write) MSHR misses 1748system.cpu1.dcache.overall_mshr_misses::cpu1.data 260 # number of overall MSHR misses 1749system.cpu1.dcache.overall_mshr_misses::total 260 # number of overall MSHR misses 1750system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1076519 # number of ReadReq MSHR miss cycles 1751system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1076519 # number of ReadReq MSHR miss cycles 1752system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1313739 # number of WriteReq MSHR miss cycles 1753system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1313739 # number of WriteReq MSHR miss cycles 1754system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 407493 # number of SwapReq MSHR miss cycles 1755system.cpu1.dcache.SwapReq_mshr_miss_latency::total 407493 # number of SwapReq MSHR miss cycles 1756system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2390258 # number of demand (read+write) MSHR miss cycles 1757system.cpu1.dcache.demand_mshr_miss_latency::total 2390258 # number of demand (read+write) MSHR miss cycles 1758system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2390258 # number of overall MSHR miss cycles 1759system.cpu1.dcache.overall_mshr_miss_latency::total 2390258 # number of overall MSHR miss cycles 1760system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003606 # mshr miss rate for ReadReq accesses 1761system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003606 # mshr miss rate for ReadReq accesses 1762system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.003118 # mshr miss rate for WriteReq accesses 1763system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.003118 # mshr miss rate for WriteReq accesses 1764system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.802817 # mshr miss rate for SwapReq accesses 1765system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.802817 # mshr miss rate for SwapReq accesses 1766system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.003397 # mshr miss rate for demand accesses 1767system.cpu1.dcache.demand_mshr_miss_rate::total 0.003397 # mshr miss rate for demand accesses 1768system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.003397 # mshr miss rate for overall accesses 1769system.cpu1.dcache.overall_mshr_miss_rate::total 0.003397 # mshr miss rate for overall accesses 1770system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 6813.411392 # average ReadReq mshr miss latency 1771system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 6813.411392 # average ReadReq mshr miss latency 1772system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 12879.794118 # average WriteReq mshr miss latency 1773system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 12879.794118 # average WriteReq mshr miss latency 1774system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 7149 # average SwapReq mshr miss latency 1775system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 7149 # average SwapReq mshr miss latency 1776system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 9193.300000 # average overall mshr miss latency 1777system.cpu1.dcache.demand_avg_mshr_miss_latency::total 9193.300000 # average overall mshr miss latency 1778system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 9193.300000 # average overall mshr miss latency 1779system.cpu1.dcache.overall_avg_mshr_miss_latency::total 9193.300000 # average overall mshr miss latency 1780system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1781system.cpu2.branchPred.lookups 47728 # Number of BP lookups 1782system.cpu2.branchPred.condPredicted 45021 # Number of conditional branches predicted 1783system.cpu2.branchPred.condIncorrect 1300 # Number of conditional branches incorrect 1784system.cpu2.branchPred.BTBLookups 41568 # Number of BTB lookups 1785system.cpu2.branchPred.BTBHits 40861 # Number of BTB hits 1786system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 1787system.cpu2.branchPred.BTBHitPct 98.299172 # BTB Hit Percentage 1788system.cpu2.branchPred.usedRAS 682 # Number of times the RAS was used to get a target. 1789system.cpu2.branchPred.RASInCorrect 232 # Number of incorrect RAS predictions. 1790system.cpu2.numCycles 177276 # number of cpu cycles simulated 1791system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started 1792system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed 1793system.cpu2.fetch.icacheStallCycles 30843 # Number of cycles fetch is stalled on an Icache miss 1794system.cpu2.fetch.Insts 263204 # Number of instructions fetch has processed 1795system.cpu2.fetch.Branches 47728 # Number of branches that fetch encountered 1796system.cpu2.fetch.predictedBranches 41543 # Number of branches that fetch has predicted taken 1797system.cpu2.fetch.Cycles 94904 # Number of cycles fetch has run and was not squashing or blocked 1798system.cpu2.fetch.SquashCycles 3824 # Number of cycles fetch has spent squashing 1799system.cpu2.fetch.BlockedCycles 35041 # Number of cycles fetch has spent blocked 1800system.cpu2.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 1801system.cpu2.fetch.NoActiveThreadStallCycles 7749 # Number of stall cycles due to no active thread to fetch from 1802system.cpu2.fetch.PendingTrapStallCycles 807 # Number of stall cycles due to pending traps 1803system.cpu2.fetch.CacheLines 21784 # Number of cache lines fetched 1804system.cpu2.fetch.IcacheSquashes 264 # Number of outstanding Icache misses that were squashed 1805system.cpu2.fetch.rateDist::samples 171794 # Number of instructions fetched each cycle (Total) 1806system.cpu2.fetch.rateDist::mean 1.532091 # Number of instructions fetched each cycle (Total) 1807system.cpu2.fetch.rateDist::stdev 2.088011 # Number of instructions fetched each cycle (Total) 1808system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 1809system.cpu2.fetch.rateDist::0 76890 44.76% 44.76% # Number of instructions fetched each cycle (Total) 1810system.cpu2.fetch.rateDist::1 48833 28.43% 73.18% # Number of instructions fetched each cycle (Total) 1811system.cpu2.fetch.rateDist::2 7151 4.16% 77.34% # Number of instructions fetched each cycle (Total) 1812system.cpu2.fetch.rateDist::3 3183 1.85% 79.20% # Number of instructions fetched each cycle (Total) 1813system.cpu2.fetch.rateDist::4 686 0.40% 79.60% # Number of instructions fetched each cycle (Total) 1814system.cpu2.fetch.rateDist::5 29845 17.37% 96.97% # Number of instructions fetched each cycle (Total) 1815system.cpu2.fetch.rateDist::6 1160 0.68% 97.64% # Number of instructions fetched each cycle (Total) 1816system.cpu2.fetch.rateDist::7 777 0.45% 98.10% # Number of instructions fetched each cycle (Total) 1817system.cpu2.fetch.rateDist::8 3269 1.90% 100.00% # Number of instructions fetched each cycle (Total) 1818system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 1819system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1820system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 1821system.cpu2.fetch.rateDist::total 171794 # Number of instructions fetched each cycle (Total) 1822system.cpu2.fetch.branchRate 0.269230 # Number of branch fetches per cycle 1823system.cpu2.fetch.rate 1.484713 # Number of inst fetches per cycle 1824system.cpu2.decode.IdleCycles 36742 # Number of cycles decode is idle 1825system.cpu2.decode.BlockedCycles 30806 # Number of cycles decode is blocked 1826system.cpu2.decode.RunCycles 88081 # Number of cycles decode is running 1827system.cpu2.decode.UnblockCycles 5970 # Number of cycles decode is unblocking 1828system.cpu2.decode.SquashCycles 2446 # Number of cycles decode is squashing 1829system.cpu2.decode.DecodedInsts 259729 # Number of instructions handled by decode 1830system.cpu2.rename.SquashCycles 2446 # Number of cycles rename is squashing 1831system.cpu2.rename.IdleCycles 37466 # Number of cycles rename is idle 1832system.cpu2.rename.BlockCycles 17718 # Number of cycles rename is blocking 1833system.cpu2.rename.serializeStallCycles 12322 # count of cycles rename stalled for serializing inst 1834system.cpu2.rename.RunCycles 82351 # Number of cycles rename is running 1835system.cpu2.rename.UnblockCycles 11742 # Number of cycles rename is unblocking 1836system.cpu2.rename.RenamedInsts 257457 # Number of instructions processed by rename 1837system.cpu2.rename.LSQFullEvents 21 # Number of times rename has blocked due to LSQ full 1838system.cpu2.rename.RenamedOperands 179534 # Number of destination operands rename has renamed 1839system.cpu2.rename.RenameLookups 487570 # Number of register rename lookups that rename has made 1840system.cpu2.rename.int_rename_lookups 380512 # Number of integer rename lookups 1841system.cpu2.rename.CommittedMaps 166403 # Number of HB maps that are committed 1842system.cpu2.rename.UndoneMaps 13131 # Number of HB maps that are undone due to squashing 1843system.cpu2.rename.serializingInsts 1114 # count of serializing insts renamed 1844system.cpu2.rename.tempSerializingInsts 1238 # count of temporary serializing insts renamed 1845system.cpu2.rename.skidInsts 14439 # count of insts added to the skid buffer 1846system.cpu2.memDep0.insertedLoads 71183 # Number of loads inserted to the mem dependence unit. 1847system.cpu2.memDep0.insertedStores 33053 # Number of stores inserted to the mem dependence unit. 1848system.cpu2.memDep0.conflictingLoads 34319 # Number of conflicting loads. 1849system.cpu2.memDep0.conflictingStores 28008 # Number of conflicting stores. 1850system.cpu2.iq.iqInstsAdded 212034 # Number of instructions added to the IQ (excludes non-spec) 1851system.cpu2.iq.iqNonSpecInstsAdded 7370 # Number of non-speculative instructions added to the IQ 1852system.cpu2.iq.iqInstsIssued 214866 # Number of instructions issued 1853system.cpu2.iq.iqSquashedInstsIssued 106 # Number of squashed instructions issued 1854system.cpu2.iq.iqSquashedInstsExamined 11214 # Number of squashed instructions iterated over during squash; mainly for profiling 1855system.cpu2.iq.iqSquashedOperandsExamined 11199 # Number of squashed operands that are examined and possibly removed from graph 1856system.cpu2.iq.iqSquashedNonSpecRemoved 648 # Number of squashed non-spec instructions that were removed 1857system.cpu2.iq.issued_per_cycle::samples 171794 # Number of insts issued each cycle 1858system.cpu2.iq.issued_per_cycle::mean 1.250719 # Number of insts issued each cycle 1859system.cpu2.iq.issued_per_cycle::stdev 1.303691 # Number of insts issued each cycle 1860system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 1861system.cpu2.iq.issued_per_cycle::0 74486 43.36% 43.36% # Number of insts issued each cycle 1862system.cpu2.iq.issued_per_cycle::1 25336 14.75% 58.11% # Number of insts issued each cycle 1863system.cpu2.iq.issued_per_cycle::2 33280 19.37% 77.48% # Number of insts issued each cycle 1864system.cpu2.iq.issued_per_cycle::3 33902 19.73% 97.21% # Number of insts issued each cycle 1865system.cpu2.iq.issued_per_cycle::4 3243 1.89% 99.10% # Number of insts issued each cycle 1866system.cpu2.iq.issued_per_cycle::5 1160 0.68% 99.77% # Number of insts issued each cycle 1867system.cpu2.iq.issued_per_cycle::6 274 0.16% 99.93% # Number of insts issued each cycle 1868system.cpu2.iq.issued_per_cycle::7 56 0.03% 99.97% # Number of insts issued each cycle 1869system.cpu2.iq.issued_per_cycle::8 57 0.03% 100.00% # Number of insts issued each cycle 1870system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1871system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1872system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 1873system.cpu2.iq.issued_per_cycle::total 171794 # Number of insts issued each cycle 1874system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 1875system.cpu2.iq.fu_full::IntAlu 17 6.18% 6.18% # attempts to use FU when none available 1876system.cpu2.iq.fu_full::IntMult 0 0.00% 6.18% # attempts to use FU when none available 1877system.cpu2.iq.fu_full::IntDiv 0 0.00% 6.18% # attempts to use FU when none available 1878system.cpu2.iq.fu_full::FloatAdd 0 0.00% 6.18% # attempts to use FU when none available 1879system.cpu2.iq.fu_full::FloatCmp 0 0.00% 6.18% # attempts to use FU when none available 1880system.cpu2.iq.fu_full::FloatCvt 0 0.00% 6.18% # attempts to use FU when none available 1881system.cpu2.iq.fu_full::FloatMult 0 0.00% 6.18% # attempts to use FU when none available 1882system.cpu2.iq.fu_full::FloatDiv 0 0.00% 6.18% # attempts to use FU when none available 1883system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 6.18% # attempts to use FU when none available 1884system.cpu2.iq.fu_full::SimdAdd 0 0.00% 6.18% # attempts to use FU when none available 1885system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 6.18% # attempts to use FU when none available 1886system.cpu2.iq.fu_full::SimdAlu 0 0.00% 6.18% # attempts to use FU when none available 1887system.cpu2.iq.fu_full::SimdCmp 0 0.00% 6.18% # attempts to use FU when none available 1888system.cpu2.iq.fu_full::SimdCvt 0 0.00% 6.18% # attempts to use FU when none available 1889system.cpu2.iq.fu_full::SimdMisc 0 0.00% 6.18% # attempts to use FU when none available 1890system.cpu2.iq.fu_full::SimdMult 0 0.00% 6.18% # attempts to use FU when none available 1891system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 6.18% # attempts to use FU when none available 1892system.cpu2.iq.fu_full::SimdShift 0 0.00% 6.18% # attempts to use FU when none available 1893system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 6.18% # attempts to use FU when none available 1894system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 6.18% # attempts to use FU when none available 1895system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 6.18% # attempts to use FU when none available 1896system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 6.18% # attempts to use FU when none available 1897system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 6.18% # attempts to use FU when none available 1898system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 6.18% # attempts to use FU when none available 1899system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 6.18% # attempts to use FU when none available 1900system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 6.18% # attempts to use FU when none available 1901system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 6.18% # attempts to use FU when none available 1902system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.18% # attempts to use FU when none available 1903system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 6.18% # attempts to use FU when none available 1904system.cpu2.iq.fu_full::MemRead 48 17.45% 23.64% # attempts to use FU when none available 1905system.cpu2.iq.fu_full::MemWrite 210 76.36% 100.00% # attempts to use FU when none available 1906system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 1907system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 1908system.cpu2.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 1909system.cpu2.iq.FU_type_0::IntAlu 106150 49.40% 49.40% # Type of FU issued 1910system.cpu2.iq.FU_type_0::IntMult 0 0.00% 49.40% # Type of FU issued 1911system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 49.40% # Type of FU issued 1912system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 49.40% # Type of FU issued 1913system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 49.40% # Type of FU issued 1914system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 49.40% # Type of FU issued 1915system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 49.40% # Type of FU issued 1916system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 49.40% # Type of FU issued 1917system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 49.40% # Type of FU issued 1918system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 49.40% # Type of FU issued 1919system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 49.40% # Type of FU issued 1920system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 49.40% # Type of FU issued 1921system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 49.40% # Type of FU issued 1922system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 49.40% # Type of FU issued 1923system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 49.40% # Type of FU issued 1924system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 49.40% # Type of FU issued 1925system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 49.40% # Type of FU issued 1926system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 49.40% # Type of FU issued 1927system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.40% # Type of FU issued 1928system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 49.40% # Type of FU issued 1929system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.40% # Type of FU issued 1930system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.40% # Type of FU issued 1931system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.40% # Type of FU issued 1932system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.40% # Type of FU issued 1933system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.40% # Type of FU issued 1934system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.40% # Type of FU issued 1935system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 49.40% # Type of FU issued 1936system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.40% # Type of FU issued 1937system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.40% # Type of FU issued 1938system.cpu2.iq.FU_type_0::MemRead 76361 35.54% 84.94% # Type of FU issued 1939system.cpu2.iq.FU_type_0::MemWrite 32355 15.06% 100.00% # Type of FU issued 1940system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 1941system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 1942system.cpu2.iq.FU_type_0::total 214866 # Type of FU issued 1943system.cpu2.iq.rate 1.212042 # Inst issue rate 1944system.cpu2.iq.fu_busy_cnt 275 # FU busy when requested 1945system.cpu2.iq.fu_busy_rate 0.001280 # FU busy rate (busy events/executed inst) 1946system.cpu2.iq.int_inst_queue_reads 601907 # Number of integer instruction queue reads 1947system.cpu2.iq.int_inst_queue_writes 230666 # Number of integer instruction queue writes 1948system.cpu2.iq.int_inst_queue_wakeup_accesses 213047 # Number of integer instruction queue wakeup accesses 1949system.cpu2.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads 1950system.cpu2.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes 1951system.cpu2.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses 1952system.cpu2.iq.int_alu_accesses 215141 # Number of integer alu accesses 1953system.cpu2.iq.fp_alu_accesses 0 # Number of floating point alu accesses 1954system.cpu2.iew.lsq.thread0.forwLoads 27720 # Number of loads that had data forwarded from stores 1955system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 1956system.cpu2.iew.lsq.thread0.squashedLoads 2543 # Number of loads squashed 1957system.cpu2.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed 1958system.cpu2.iew.lsq.thread0.memOrderViolation 48 # Number of memory ordering violations 1959system.cpu2.iew.lsq.thread0.squashedStores 1469 # Number of stores squashed 1960system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 1961system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 1962system.cpu2.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 1963system.cpu2.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked 1964system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle 1965system.cpu2.iew.iewSquashCycles 2446 # Number of cycles IEW is squashing 1966system.cpu2.iew.iewBlockCycles 916 # Number of cycles IEW is blocking 1967system.cpu2.iew.iewUnblockCycles 52 # Number of cycles IEW is unblocking 1968system.cpu2.iew.iewDispatchedInsts 254607 # Number of instructions dispatched to IQ 1969system.cpu2.iew.iewDispSquashedInsts 365 # Number of squashed instructions skipped by dispatch 1970system.cpu2.iew.iewDispLoadInsts 71183 # Number of dispatched load instructions 1971system.cpu2.iew.iewDispStoreInsts 33053 # Number of dispatched store instructions 1972system.cpu2.iew.iewDispNonSpecInsts 1074 # Number of dispatched non-speculative instructions 1973system.cpu2.iew.iewIQFullEvents 52 # Number of times the IQ has become full, causing a stall 1974system.cpu2.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 1975system.cpu2.iew.memOrderViolationEvents 48 # Number of memory order violations 1976system.cpu2.iew.predictedTakenIncorrect 458 # Number of branches that were predicted taken incorrectly 1977system.cpu2.iew.predictedNotTakenIncorrect 967 # Number of branches that were predicted not taken incorrectly 1978system.cpu2.iew.branchMispredicts 1425 # Number of branch mispredicts detected at execute 1979system.cpu2.iew.iewExecutedInsts 213716 # Number of executed instructions 1980system.cpu2.iew.iewExecLoadInsts 70082 # Number of load instructions executed 1981system.cpu2.iew.iewExecSquashedInsts 1150 # Number of squashed instructions skipped in execute 1982system.cpu2.iew.exec_swp 0 # number of swp insts executed 1983system.cpu2.iew.exec_nop 35203 # number of nop insts executed 1984system.cpu2.iew.exec_refs 102354 # number of memory reference insts executed 1985system.cpu2.iew.exec_branches 44387 # Number of branches executed 1986system.cpu2.iew.exec_stores 32272 # Number of stores executed 1987system.cpu2.iew.exec_rate 1.205555 # Inst execution rate 1988system.cpu2.iew.wb_sent 213334 # cumulative count of insts sent to commit 1989system.cpu2.iew.wb_count 213047 # cumulative count of insts written-back 1990system.cpu2.iew.wb_producers 119124 # num instructions producing a value 1991system.cpu2.iew.wb_consumers 123829 # num instructions consuming a value 1992system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 1993system.cpu2.iew.wb_rate 1.201781 # insts written-back per cycle 1994system.cpu2.iew.wb_fanout 0.962004 # average fanout of values written-back 1995system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 1996system.cpu2.commit.commitSquashedInsts 12897 # The number of squashed insts skipped by commit 1997system.cpu2.commit.commitNonSpecStalls 6722 # The number of times commit has been forced to stall to communicate backwards 1998system.cpu2.commit.branchMispredicts 1300 # The number of times a branch was mispredicted 1999system.cpu2.commit.committed_per_cycle::samples 161599 # Number of insts commited each cycle 2000system.cpu2.commit.committed_per_cycle::mean 1.495727 # Number of insts commited each cycle 2001system.cpu2.commit.committed_per_cycle::stdev 1.966465 # Number of insts commited each cycle 2002system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 2003system.cpu2.commit.committed_per_cycle::0 73205 45.30% 45.30% # Number of insts commited each cycle 2004system.cpu2.commit.committed_per_cycle::1 42525 26.32% 71.62% # Number of insts commited each cycle 2005system.cpu2.commit.committed_per_cycle::2 6095 3.77% 75.39% # Number of insts commited each cycle 2006system.cpu2.commit.committed_per_cycle::3 7628 4.72% 80.11% # Number of insts commited each cycle 2007system.cpu2.commit.committed_per_cycle::4 1558 0.96% 81.07% # Number of insts commited each cycle 2008system.cpu2.commit.committed_per_cycle::5 28296 17.51% 98.58% # Number of insts commited each cycle 2009system.cpu2.commit.committed_per_cycle::6 469 0.29% 98.87% # Number of insts commited each cycle 2010system.cpu2.commit.committed_per_cycle::7 1001 0.62% 99.49% # Number of insts commited each cycle 2011system.cpu2.commit.committed_per_cycle::8 822 0.51% 100.00% # Number of insts commited each cycle 2012system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 2013system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 2014system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 2015system.cpu2.commit.committed_per_cycle::total 161599 # Number of insts commited each cycle 2016system.cpu2.commit.committedInsts 241708 # Number of instructions committed 2017system.cpu2.commit.committedOps 241708 # Number of ops (including micro ops) committed 2018system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed 2019system.cpu2.commit.refs 100224 # Number of memory references committed 2020system.cpu2.commit.loads 68640 # Number of loads committed 2021system.cpu2.commit.membars 6003 # Number of memory barriers committed 2022system.cpu2.commit.branches 43548 # Number of branches committed 2023system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions. 2024system.cpu2.commit.int_insts 165890 # Number of committed integer instructions. 2025system.cpu2.commit.function_calls 322 # Number of function calls committed. 2026system.cpu2.commit.op_class_0::No_OpClass 34333 14.20% 14.20% # Class of committed instruction 2027system.cpu2.commit.op_class_0::IntAlu 101148 41.85% 56.05% # Class of committed instruction 2028system.cpu2.commit.op_class_0::IntMult 0 0.00% 56.05% # Class of committed instruction 2029system.cpu2.commit.op_class_0::IntDiv 0 0.00% 56.05% # Class of committed instruction 2030system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 56.05% # Class of committed instruction 2031system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 56.05% # Class of committed instruction 2032system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 56.05% # Class of committed instruction 2033system.cpu2.commit.op_class_0::FloatMult 0 0.00% 56.05% # Class of committed instruction 2034system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 56.05% # Class of committed instruction 2035system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 56.05% # Class of committed instruction 2036system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 56.05% # Class of committed instruction 2037system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 56.05% # Class of committed instruction 2038system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 56.05% # Class of committed instruction 2039system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 56.05% # Class of committed instruction 2040system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 56.05% # Class of committed instruction 2041system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 56.05% # Class of committed instruction 2042system.cpu2.commit.op_class_0::SimdMult 0 0.00% 56.05% # Class of committed instruction 2043system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 56.05% # Class of committed instruction 2044system.cpu2.commit.op_class_0::SimdShift 0 0.00% 56.05% # Class of committed instruction 2045system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 56.05% # Class of committed instruction 2046system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 56.05% # Class of committed instruction 2047system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 56.05% # Class of committed instruction 2048system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 56.05% # Class of committed instruction 2049system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 56.05% # Class of committed instruction 2050system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 56.05% # Class of committed instruction 2051system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 56.05% # Class of committed instruction 2052system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 56.05% # Class of committed instruction 2053system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 56.05% # Class of committed instruction 2054system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 56.05% # Class of committed instruction 2055system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 56.05% # Class of committed instruction 2056system.cpu2.commit.op_class_0::MemRead 74643 30.88% 86.93% # Class of committed instruction 2057system.cpu2.commit.op_class_0::MemWrite 31584 13.07% 100.00% # Class of committed instruction 2058system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 2059system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 2060system.cpu2.commit.op_class_0::total 241708 # Class of committed instruction 2061system.cpu2.commit.bw_lim_events 822 # number cycles where commit BW limit reached 2062system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits 2063system.cpu2.rob.rob_reads 414795 # The number of ROB reads 2064system.cpu2.rob.rob_writes 511661 # The number of ROB writes 2065system.cpu2.timesIdled 225 # Number of times that the entire CPU went into an idle state and unscheduled itself 2066system.cpu2.idleCycles 5482 # Total number of cycles that the CPU has spent unscheduled due to idling 2067system.cpu2.quiesceCycles 44468 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 2068system.cpu2.committedInsts 201372 # Number of Instructions Simulated 2069system.cpu2.committedOps 201372 # Number of Ops (including micro ops) Simulated 2070system.cpu2.committedInsts_total 201372 # Number of Instructions Simulated 2071system.cpu2.cpi 0.880341 # CPI: Cycles Per Instruction 2072system.cpu2.cpi_total 0.880341 # CPI: Total CPI of All Threads 2073system.cpu2.ipc 1.135924 # IPC: Instructions Per Cycle 2074system.cpu2.ipc_total 1.135924 # IPC: Total IPC of All Threads 2075system.cpu2.int_regfile_reads 365782 # number of integer regfile reads 2076system.cpu2.int_regfile_writes 171355 # number of integer regfile writes 2077system.cpu2.fp_regfile_writes 64 # number of floating regfile writes 2078system.cpu2.misc_regfile_reads 103916 # number of misc regfile reads 2079system.cpu2.misc_regfile_writes 648 # number of misc regfile writes 2080system.cpu2.icache.tags.replacements 317 # number of replacements 2081system.cpu2.icache.tags.tagsinuse 82.236907 # Cycle average of tags in use 2082system.cpu2.icache.tags.total_refs 21297 # Total number of references to valid blocks. 2083system.cpu2.icache.tags.sampled_refs 425 # Sample count of references to valid blocks. 2084system.cpu2.icache.tags.avg_refs 50.110588 # Average number of references to valid blocks. 2085system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 2086system.cpu2.icache.tags.occ_blocks::cpu2.inst 82.236907 # Average occupied blocks per requestor 2087system.cpu2.icache.tags.occ_percent::cpu2.inst 0.160619 # Average percentage of cache occupancy 2088system.cpu2.icache.tags.occ_percent::total 0.160619 # Average percentage of cache occupancy 2089system.cpu2.icache.tags.occ_task_id_blocks::1024 108 # Occupied blocks per task id 2090system.cpu2.icache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id 2091system.cpu2.icache.tags.age_task_id_blocks_1024::1 97 # Occupied blocks per task id 2092system.cpu2.icache.tags.occ_task_id_percent::1024 0.210938 # Percentage of cache occupancy per task id 2093system.cpu2.icache.tags.tag_accesses 22209 # Number of tag accesses 2094system.cpu2.icache.tags.data_accesses 22209 # Number of data accesses 2095system.cpu2.icache.ReadReq_hits::cpu2.inst 21297 # number of ReadReq hits 2096system.cpu2.icache.ReadReq_hits::total 21297 # number of ReadReq hits 2097system.cpu2.icache.demand_hits::cpu2.inst 21297 # number of demand (read+write) hits 2098system.cpu2.icache.demand_hits::total 21297 # number of demand (read+write) hits 2099system.cpu2.icache.overall_hits::cpu2.inst 21297 # number of overall hits 2100system.cpu2.icache.overall_hits::total 21297 # number of overall hits 2101system.cpu2.icache.ReadReq_misses::cpu2.inst 487 # number of ReadReq misses 2102system.cpu2.icache.ReadReq_misses::total 487 # number of ReadReq misses 2103system.cpu2.icache.demand_misses::cpu2.inst 487 # number of demand (read+write) misses 2104system.cpu2.icache.demand_misses::total 487 # number of demand (read+write) misses 2105system.cpu2.icache.overall_misses::cpu2.inst 487 # number of overall misses 2106system.cpu2.icache.overall_misses::total 487 # number of overall misses 2107system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 11521239 # number of ReadReq miss cycles 2108system.cpu2.icache.ReadReq_miss_latency::total 11521239 # number of ReadReq miss cycles 2109system.cpu2.icache.demand_miss_latency::cpu2.inst 11521239 # number of demand (read+write) miss cycles 2110system.cpu2.icache.demand_miss_latency::total 11521239 # number of demand (read+write) miss cycles 2111system.cpu2.icache.overall_miss_latency::cpu2.inst 11521239 # number of overall miss cycles 2112system.cpu2.icache.overall_miss_latency::total 11521239 # number of overall miss cycles 2113system.cpu2.icache.ReadReq_accesses::cpu2.inst 21784 # number of ReadReq accesses(hits+misses) 2114system.cpu2.icache.ReadReq_accesses::total 21784 # number of ReadReq accesses(hits+misses) 2115system.cpu2.icache.demand_accesses::cpu2.inst 21784 # number of demand (read+write) accesses 2116system.cpu2.icache.demand_accesses::total 21784 # number of demand (read+write) accesses 2117system.cpu2.icache.overall_accesses::cpu2.inst 21784 # number of overall (read+write) accesses 2118system.cpu2.icache.overall_accesses::total 21784 # number of overall (read+write) accesses 2119system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.022356 # miss rate for ReadReq accesses 2120system.cpu2.icache.ReadReq_miss_rate::total 0.022356 # miss rate for ReadReq accesses 2121system.cpu2.icache.demand_miss_rate::cpu2.inst 0.022356 # miss rate for demand accesses 2122system.cpu2.icache.demand_miss_rate::total 0.022356 # miss rate for demand accesses 2123system.cpu2.icache.overall_miss_rate::cpu2.inst 0.022356 # miss rate for overall accesses 2124system.cpu2.icache.overall_miss_rate::total 0.022356 # miss rate for overall accesses 2125system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 23657.574949 # average ReadReq miss latency 2126system.cpu2.icache.ReadReq_avg_miss_latency::total 23657.574949 # average ReadReq miss latency 2127system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 23657.574949 # average overall miss latency 2128system.cpu2.icache.demand_avg_miss_latency::total 23657.574949 # average overall miss latency 2129system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 23657.574949 # average overall miss latency 2130system.cpu2.icache.overall_avg_miss_latency::total 23657.574949 # average overall miss latency 2131system.cpu2.icache.blocked_cycles::no_mshrs 85 # number of cycles access was blocked 2132system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2133system.cpu2.icache.blocked::no_mshrs 1 # number of cycles access was blocked 2134system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked 2135system.cpu2.icache.avg_blocked_cycles::no_mshrs 85 # average number of cycles each access was blocked 2136system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2137system.cpu2.icache.fast_writes 0 # number of fast writes performed 2138system.cpu2.icache.cache_copies 0 # number of cache copies performed 2139system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 62 # number of ReadReq MSHR hits 2140system.cpu2.icache.ReadReq_mshr_hits::total 62 # number of ReadReq MSHR hits 2141system.cpu2.icache.demand_mshr_hits::cpu2.inst 62 # number of demand (read+write) MSHR hits 2142system.cpu2.icache.demand_mshr_hits::total 62 # number of demand (read+write) MSHR hits 2143system.cpu2.icache.overall_mshr_hits::cpu2.inst 62 # number of overall MSHR hits 2144system.cpu2.icache.overall_mshr_hits::total 62 # number of overall MSHR hits 2145system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 425 # number of ReadReq MSHR misses 2146system.cpu2.icache.ReadReq_mshr_misses::total 425 # number of ReadReq MSHR misses 2147system.cpu2.icache.demand_mshr_misses::cpu2.inst 425 # number of demand (read+write) MSHR misses 2148system.cpu2.icache.demand_mshr_misses::total 425 # number of demand (read+write) MSHR misses 2149system.cpu2.icache.overall_mshr_misses::cpu2.inst 425 # number of overall MSHR misses 2150system.cpu2.icache.overall_mshr_misses::total 425 # number of overall MSHR misses 2151system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 9226007 # number of ReadReq MSHR miss cycles 2152system.cpu2.icache.ReadReq_mshr_miss_latency::total 9226007 # number of ReadReq MSHR miss cycles 2153system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 9226007 # number of demand (read+write) MSHR miss cycles 2154system.cpu2.icache.demand_mshr_miss_latency::total 9226007 # number of demand (read+write) MSHR miss cycles 2155system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 9226007 # number of overall MSHR miss cycles 2156system.cpu2.icache.overall_mshr_miss_latency::total 9226007 # number of overall MSHR miss cycles 2157system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.019510 # mshr miss rate for ReadReq accesses 2158system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.019510 # mshr miss rate for ReadReq accesses 2159system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.019510 # mshr miss rate for demand accesses 2160system.cpu2.icache.demand_mshr_miss_rate::total 0.019510 # mshr miss rate for demand accesses 2161system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.019510 # mshr miss rate for overall accesses 2162system.cpu2.icache.overall_mshr_miss_rate::total 0.019510 # mshr miss rate for overall accesses 2163system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 21708.251765 # average ReadReq mshr miss latency 2164system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 21708.251765 # average ReadReq mshr miss latency 2165system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 21708.251765 # average overall mshr miss latency 2166system.cpu2.icache.demand_avg_mshr_miss_latency::total 21708.251765 # average overall mshr miss latency 2167system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 21708.251765 # average overall mshr miss latency 2168system.cpu2.icache.overall_avg_mshr_miss_latency::total 21708.251765 # average overall mshr miss latency 2169system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate 2170system.cpu2.dcache.tags.replacements 0 # number of replacements 2171system.cpu2.dcache.tags.tagsinuse 26.169210 # Cycle average of tags in use 2172system.cpu2.dcache.tags.total_refs 37730 # Total number of references to valid blocks. 2173system.cpu2.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. 2174system.cpu2.dcache.tags.avg_refs 1301.034483 # Average number of references to valid blocks. 2175system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 2176system.cpu2.dcache.tags.occ_blocks::cpu2.data 26.169210 # Average occupied blocks per requestor 2177system.cpu2.dcache.tags.occ_percent::cpu2.data 0.051112 # Average percentage of cache occupancy 2178system.cpu2.dcache.tags.occ_percent::total 0.051112 # Average percentage of cache occupancy 2179system.cpu2.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id 2180system.cpu2.dcache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id 2181system.cpu2.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id 2182system.cpu2.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id 2183system.cpu2.dcache.tags.tag_accesses 295974 # Number of tag accesses 2184system.cpu2.dcache.tags.data_accesses 295974 # Number of data accesses 2185system.cpu2.dcache.ReadReq_hits::cpu2.data 42003 # number of ReadReq hits 2186system.cpu2.dcache.ReadReq_hits::total 42003 # number of ReadReq hits 2187system.cpu2.dcache.WriteReq_hits::cpu2.data 31371 # number of WriteReq hits 2188system.cpu2.dcache.WriteReq_hits::total 31371 # number of WriteReq hits 2189system.cpu2.dcache.SwapReq_hits::cpu2.data 14 # number of SwapReq hits 2190system.cpu2.dcache.SwapReq_hits::total 14 # number of SwapReq hits 2191system.cpu2.dcache.demand_hits::cpu2.data 73374 # number of demand (read+write) hits 2192system.cpu2.dcache.demand_hits::total 73374 # number of demand (read+write) hits 2193system.cpu2.dcache.overall_hits::cpu2.data 73374 # number of overall hits 2194system.cpu2.dcache.overall_hits::total 73374 # number of overall hits 2195system.cpu2.dcache.ReadReq_misses::cpu2.data 342 # number of ReadReq misses 2196system.cpu2.dcache.ReadReq_misses::total 342 # number of ReadReq misses 2197system.cpu2.dcache.WriteReq_misses::cpu2.data 140 # number of WriteReq misses 2198system.cpu2.dcache.WriteReq_misses::total 140 # number of WriteReq misses 2199system.cpu2.dcache.SwapReq_misses::cpu2.data 59 # number of SwapReq misses 2200system.cpu2.dcache.SwapReq_misses::total 59 # number of SwapReq misses 2201system.cpu2.dcache.demand_misses::cpu2.data 482 # number of demand (read+write) misses 2202system.cpu2.dcache.demand_misses::total 482 # number of demand (read+write) misses 2203system.cpu2.dcache.overall_misses::cpu2.data 482 # number of overall misses 2204system.cpu2.dcache.overall_misses::total 482 # number of overall misses 2205system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 5435581 # number of ReadReq miss cycles 2206system.cpu2.dcache.ReadReq_miss_latency::total 5435581 # number of ReadReq miss cycles 2207system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 3139010 # number of WriteReq miss cycles 2208system.cpu2.dcache.WriteReq_miss_latency::total 3139010 # number of WriteReq miss cycles 2209system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 574505 # number of SwapReq miss cycles 2210system.cpu2.dcache.SwapReq_miss_latency::total 574505 # number of SwapReq miss cycles 2211system.cpu2.dcache.demand_miss_latency::cpu2.data 8574591 # number of demand (read+write) miss cycles 2212system.cpu2.dcache.demand_miss_latency::total 8574591 # number of demand (read+write) miss cycles 2213system.cpu2.dcache.overall_miss_latency::cpu2.data 8574591 # number of overall miss cycles 2214system.cpu2.dcache.overall_miss_latency::total 8574591 # number of overall miss cycles 2215system.cpu2.dcache.ReadReq_accesses::cpu2.data 42345 # number of ReadReq accesses(hits+misses) 2216system.cpu2.dcache.ReadReq_accesses::total 42345 # number of ReadReq accesses(hits+misses) 2217system.cpu2.dcache.WriteReq_accesses::cpu2.data 31511 # number of WriteReq accesses(hits+misses) 2218system.cpu2.dcache.WriteReq_accesses::total 31511 # number of WriteReq accesses(hits+misses) 2219system.cpu2.dcache.SwapReq_accesses::cpu2.data 73 # number of SwapReq accesses(hits+misses) 2220system.cpu2.dcache.SwapReq_accesses::total 73 # number of SwapReq accesses(hits+misses) 2221system.cpu2.dcache.demand_accesses::cpu2.data 73856 # number of demand (read+write) accesses 2222system.cpu2.dcache.demand_accesses::total 73856 # number of demand (read+write) accesses 2223system.cpu2.dcache.overall_accesses::cpu2.data 73856 # number of overall (read+write) accesses 2224system.cpu2.dcache.overall_accesses::total 73856 # number of overall (read+write) accesses 2225system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.008077 # miss rate for ReadReq accesses 2226system.cpu2.dcache.ReadReq_miss_rate::total 0.008077 # miss rate for ReadReq accesses 2227system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.004443 # miss rate for WriteReq accesses 2228system.cpu2.dcache.WriteReq_miss_rate::total 0.004443 # miss rate for WriteReq accesses 2229system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.808219 # miss rate for SwapReq accesses 2230system.cpu2.dcache.SwapReq_miss_rate::total 0.808219 # miss rate for SwapReq accesses 2231system.cpu2.dcache.demand_miss_rate::cpu2.data 0.006526 # miss rate for demand accesses 2232system.cpu2.dcache.demand_miss_rate::total 0.006526 # miss rate for demand accesses 2233system.cpu2.dcache.overall_miss_rate::cpu2.data 0.006526 # miss rate for overall accesses 2234system.cpu2.dcache.overall_miss_rate::total 0.006526 # miss rate for overall accesses 2235system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 15893.511696 # average ReadReq miss latency 2236system.cpu2.dcache.ReadReq_avg_miss_latency::total 15893.511696 # average ReadReq miss latency 2237system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 22421.500000 # average WriteReq miss latency 2238system.cpu2.dcache.WriteReq_avg_miss_latency::total 22421.500000 # average WriteReq miss latency 2239system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 9737.372881 # average SwapReq miss latency 2240system.cpu2.dcache.SwapReq_avg_miss_latency::total 9737.372881 # average SwapReq miss latency 2241system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 17789.607884 # average overall miss latency 2242system.cpu2.dcache.demand_avg_miss_latency::total 17789.607884 # average overall miss latency 2243system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 17789.607884 # average overall miss latency 2244system.cpu2.dcache.overall_avg_miss_latency::total 17789.607884 # average overall miss latency 2245system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2246system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2247system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 2248system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked 2249system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2250system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2251system.cpu2.dcache.fast_writes 0 # number of fast writes performed 2252system.cpu2.dcache.cache_copies 0 # number of cache copies performed 2253system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 177 # number of ReadReq MSHR hits 2254system.cpu2.dcache.ReadReq_mshr_hits::total 177 # number of ReadReq MSHR hits 2255system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 34 # number of WriteReq MSHR hits 2256system.cpu2.dcache.WriteReq_mshr_hits::total 34 # number of WriteReq MSHR hits 2257system.cpu2.dcache.demand_mshr_hits::cpu2.data 211 # number of demand (read+write) MSHR hits 2258system.cpu2.dcache.demand_mshr_hits::total 211 # number of demand (read+write) MSHR hits 2259system.cpu2.dcache.overall_mshr_hits::cpu2.data 211 # number of overall MSHR hits 2260system.cpu2.dcache.overall_mshr_hits::total 211 # number of overall MSHR hits 2261system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 165 # number of ReadReq MSHR misses 2262system.cpu2.dcache.ReadReq_mshr_misses::total 165 # number of ReadReq MSHR misses 2263system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 106 # number of WriteReq MSHR misses 2264system.cpu2.dcache.WriteReq_mshr_misses::total 106 # number of WriteReq MSHR misses 2265system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 59 # number of SwapReq MSHR misses 2266system.cpu2.dcache.SwapReq_mshr_misses::total 59 # number of SwapReq MSHR misses 2267system.cpu2.dcache.demand_mshr_misses::cpu2.data 271 # number of demand (read+write) MSHR misses 2268system.cpu2.dcache.demand_mshr_misses::total 271 # number of demand (read+write) MSHR misses 2269system.cpu2.dcache.overall_mshr_misses::cpu2.data 271 # number of overall MSHR misses 2270system.cpu2.dcache.overall_mshr_misses::total 271 # number of overall MSHR misses 2271system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1515278 # number of ReadReq MSHR miss cycles 2272system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1515278 # number of ReadReq MSHR miss cycles 2273system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1527990 # number of WriteReq MSHR miss cycles 2274system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1527990 # number of WriteReq MSHR miss cycles 2275system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 456495 # number of SwapReq MSHR miss cycles 2276system.cpu2.dcache.SwapReq_mshr_miss_latency::total 456495 # number of SwapReq MSHR miss cycles 2277system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3043268 # number of demand (read+write) MSHR miss cycles 2278system.cpu2.dcache.demand_mshr_miss_latency::total 3043268 # number of demand (read+write) MSHR miss cycles 2279system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3043268 # number of overall MSHR miss cycles 2280system.cpu2.dcache.overall_mshr_miss_latency::total 3043268 # number of overall MSHR miss cycles 2281system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003897 # mshr miss rate for ReadReq accesses 2282system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003897 # mshr miss rate for ReadReq accesses 2283system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.003364 # mshr miss rate for WriteReq accesses 2284system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.003364 # mshr miss rate for WriteReq accesses 2285system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.808219 # mshr miss rate for SwapReq accesses 2286system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.808219 # mshr miss rate for SwapReq accesses 2287system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.003669 # mshr miss rate for demand accesses 2288system.cpu2.dcache.demand_mshr_miss_rate::total 0.003669 # mshr miss rate for demand accesses 2289system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.003669 # mshr miss rate for overall accesses 2290system.cpu2.dcache.overall_mshr_miss_rate::total 0.003669 # mshr miss rate for overall accesses 2291system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 9183.503030 # average ReadReq mshr miss latency 2292system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 9183.503030 # average ReadReq mshr miss latency 2293system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 14415 # average WriteReq mshr miss latency 2294system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 14415 # average WriteReq mshr miss latency 2295system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 7737.203390 # average SwapReq mshr miss latency 2296system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 7737.203390 # average SwapReq mshr miss latency 2297system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 11229.771218 # average overall mshr miss latency 2298system.cpu2.dcache.demand_avg_mshr_miss_latency::total 11229.771218 # average overall mshr miss latency 2299system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 11229.771218 # average overall mshr miss latency 2300system.cpu2.dcache.overall_avg_mshr_miss_latency::total 11229.771218 # average overall mshr miss latency 2301system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 2302system.cpu3.branchPred.lookups 53964 # Number of BP lookups 2303system.cpu3.branchPred.condPredicted 51232 # Number of conditional branches predicted 2304system.cpu3.branchPred.condIncorrect 1265 # Number of conditional branches incorrect 2305system.cpu3.branchPred.BTBLookups 47874 # Number of BTB lookups 2306system.cpu3.branchPred.BTBHits 47117 # Number of BTB hits 2307system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 2308system.cpu3.branchPred.BTBHitPct 98.418766 # BTB Hit Percentage 2309system.cpu3.branchPred.usedRAS 645 # Number of times the RAS was used to get a target. 2310system.cpu3.branchPred.RASInCorrect 232 # Number of incorrect RAS predictions. 2311system.cpu3.numCycles 176930 # number of cpu cycles simulated 2312system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started 2313system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed 2314system.cpu3.fetch.icacheStallCycles 27837 # Number of cycles fetch is stalled on an Icache miss 2315system.cpu3.fetch.Insts 302665 # Number of instructions fetch has processed 2316system.cpu3.fetch.Branches 53964 # Number of branches that fetch encountered 2317system.cpu3.fetch.predictedBranches 47762 # Number of branches that fetch has predicted taken 2318system.cpu3.fetch.Cycles 106222 # Number of cycles fetch has run and was not squashing or blocked 2319system.cpu3.fetch.SquashCycles 3643 # Number of cycles fetch has spent squashing 2320system.cpu3.fetch.BlockedCycles 30631 # Number of cycles fetch has spent blocked 2321system.cpu3.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 2322system.cpu3.fetch.NoActiveThreadStallCycles 7749 # Number of stall cycles due to no active thread to fetch from 2323system.cpu3.fetch.PendingTrapStallCycles 799 # Number of stall cycles due to pending traps 2324system.cpu3.fetch.CacheLines 19577 # Number of cache lines fetched 2325system.cpu3.fetch.IcacheSquashes 266 # Number of outstanding Icache misses that were squashed 2326system.cpu3.fetch.rateDist::samples 175543 # Number of instructions fetched each cycle (Total) 2327system.cpu3.fetch.rateDist::mean 1.724164 # Number of instructions fetched each cycle (Total) 2328system.cpu3.fetch.rateDist::stdev 2.153360 # Number of instructions fetched each cycle (Total) 2329system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 2330system.cpu3.fetch.rateDist::0 69321 39.49% 39.49% # Number of instructions fetched each cycle (Total) 2331system.cpu3.fetch.rateDist::1 53950 30.73% 70.22% # Number of instructions fetched each cycle (Total) 2332system.cpu3.fetch.rateDist::2 6031 3.44% 73.66% # Number of instructions fetched each cycle (Total) 2333system.cpu3.fetch.rateDist::3 3206 1.83% 75.48% # Number of instructions fetched each cycle (Total) 2334system.cpu3.fetch.rateDist::4 696 0.40% 75.88% # Number of instructions fetched each cycle (Total) 2335system.cpu3.fetch.rateDist::5 37091 21.13% 97.01% # Number of instructions fetched each cycle (Total) 2336system.cpu3.fetch.rateDist::6 1217 0.69% 97.70% # Number of instructions fetched each cycle (Total) 2337system.cpu3.fetch.rateDist::7 754 0.43% 98.13% # Number of instructions fetched each cycle (Total) 2338system.cpu3.fetch.rateDist::8 3277 1.87% 100.00% # Number of instructions fetched each cycle (Total) 2339system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 2340system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 2341system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 2342system.cpu3.fetch.rateDist::total 175543 # Number of instructions fetched each cycle (Total) 2343system.cpu3.fetch.branchRate 0.305002 # Number of branch fetches per cycle 2344system.cpu3.fetch.rate 1.710648 # Number of inst fetches per cycle 2345system.cpu3.decode.IdleCycles 32973 # Number of cycles decode is idle 2346system.cpu3.decode.BlockedCycles 27130 # Number of cycles decode is blocked 2347system.cpu3.decode.RunCycles 100348 # Number of cycles decode is running 2348system.cpu3.decode.UnblockCycles 5043 # Number of cycles decode is unblocking 2349system.cpu3.decode.SquashCycles 2300 # Number of cycles decode is squashing 2350system.cpu3.decode.DecodedInsts 299109 # Number of instructions handled by decode 2351system.cpu3.rename.SquashCycles 2300 # Number of cycles rename is squashing 2352system.cpu3.rename.IdleCycles 33648 # Number of cycles rename is idle 2353system.cpu3.rename.BlockCycles 14616 # Number of cycles rename is blocking 2354system.cpu3.rename.serializeStallCycles 11766 # count of cycles rename stalled for serializing inst 2355system.cpu3.rename.RunCycles 95589 # Number of cycles rename is running 2356system.cpu3.rename.UnblockCycles 9875 # Number of cycles rename is unblocking 2357system.cpu3.rename.RenamedInsts 296992 # Number of instructions processed by rename 2358system.cpu3.rename.IQFullEvents 4 # Number of times rename has blocked due to IQ full 2359system.cpu3.rename.LSQFullEvents 23 # Number of times rename has blocked due to LSQ full 2360system.cpu3.rename.RenamedOperands 207702 # Number of destination operands rename has renamed 2361system.cpu3.rename.RenameLookups 570845 # Number of register rename lookups that rename has made 2362system.cpu3.rename.int_rename_lookups 442935 # Number of integer rename lookups 2363system.cpu3.rename.CommittedMaps 195079 # Number of HB maps that are committed 2364system.cpu3.rename.UndoneMaps 12623 # Number of HB maps that are undone due to squashing 2365system.cpu3.rename.serializingInsts 1101 # count of serializing insts renamed 2366system.cpu3.rename.tempSerializingInsts 1224 # count of temporary serializing insts renamed 2367system.cpu3.rename.skidInsts 12490 # count of insts added to the skid buffer 2368system.cpu3.memDep0.insertedLoads 84722 # Number of loads inserted to the mem dependence unit. 2369system.cpu3.memDep0.insertedStores 40383 # Number of stores inserted to the mem dependence unit. 2370system.cpu3.memDep0.conflictingLoads 40455 # Number of conflicting loads. 2371system.cpu3.memDep0.conflictingStores 35338 # Number of conflicting stores. 2372system.cpu3.iq.iqInstsAdded 246413 # Number of instructions added to the IQ (excludes non-spec) 2373system.cpu3.iq.iqNonSpecInstsAdded 6255 # Number of non-speculative instructions added to the IQ 2374system.cpu3.iq.iqInstsIssued 248738 # Number of instructions issued 2375system.cpu3.iq.iqSquashedInstsIssued 58 # Number of squashed instructions issued 2376system.cpu3.iq.iqSquashedInstsExamined 10413 # Number of squashed instructions iterated over during squash; mainly for profiling 2377system.cpu3.iq.iqSquashedOperandsExamined 9948 # Number of squashed operands that are examined and possibly removed from graph 2378system.cpu3.iq.iqSquashedNonSpecRemoved 566 # Number of squashed non-spec instructions that were removed 2379system.cpu3.iq.issued_per_cycle::samples 175543 # Number of insts issued each cycle 2380system.cpu3.iq.issued_per_cycle::mean 1.416963 # Number of insts issued each cycle 2381system.cpu3.iq.issued_per_cycle::stdev 1.309147 # Number of insts issued each cycle 2382system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 2383system.cpu3.iq.issued_per_cycle::0 66501 37.88% 37.88% # Number of insts issued each cycle 2384system.cpu3.iq.issued_per_cycle::1 22275 12.69% 50.57% # Number of insts issued each cycle 2385system.cpu3.iq.issued_per_cycle::2 40683 23.18% 73.75% # Number of insts issued each cycle 2386system.cpu3.iq.issued_per_cycle::3 41300 23.53% 97.27% # Number of insts issued each cycle 2387system.cpu3.iq.issued_per_cycle::4 3253 1.85% 99.13% # Number of insts issued each cycle 2388system.cpu3.iq.issued_per_cycle::5 1166 0.66% 99.79% # Number of insts issued each cycle 2389system.cpu3.iq.issued_per_cycle::6 259 0.15% 99.94% # Number of insts issued each cycle 2390system.cpu3.iq.issued_per_cycle::7 47 0.03% 99.97% # Number of insts issued each cycle 2391system.cpu3.iq.issued_per_cycle::8 59 0.03% 100.00% # Number of insts issued each cycle 2392system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 2393system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 2394system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 2395system.cpu3.iq.issued_per_cycle::total 175543 # Number of insts issued each cycle 2396system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 2397system.cpu3.iq.fu_full::IntAlu 17 6.44% 6.44% # attempts to use FU when none available 2398system.cpu3.iq.fu_full::IntMult 0 0.00% 6.44% # attempts to use FU when none available 2399system.cpu3.iq.fu_full::IntDiv 0 0.00% 6.44% # attempts to use FU when none available 2400system.cpu3.iq.fu_full::FloatAdd 0 0.00% 6.44% # attempts to use FU when none available 2401system.cpu3.iq.fu_full::FloatCmp 0 0.00% 6.44% # attempts to use FU when none available 2402system.cpu3.iq.fu_full::FloatCvt 0 0.00% 6.44% # attempts to use FU when none available 2403system.cpu3.iq.fu_full::FloatMult 0 0.00% 6.44% # attempts to use FU when none available 2404system.cpu3.iq.fu_full::FloatDiv 0 0.00% 6.44% # attempts to use FU when none available 2405system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 6.44% # attempts to use FU when none available 2406system.cpu3.iq.fu_full::SimdAdd 0 0.00% 6.44% # attempts to use FU when none available 2407system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 6.44% # attempts to use FU when none available 2408system.cpu3.iq.fu_full::SimdAlu 0 0.00% 6.44% # attempts to use FU when none available 2409system.cpu3.iq.fu_full::SimdCmp 0 0.00% 6.44% # attempts to use FU when none available 2410system.cpu3.iq.fu_full::SimdCvt 0 0.00% 6.44% # attempts to use FU when none available 2411system.cpu3.iq.fu_full::SimdMisc 0 0.00% 6.44% # attempts to use FU when none available 2412system.cpu3.iq.fu_full::SimdMult 0 0.00% 6.44% # attempts to use FU when none available 2413system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 6.44% # attempts to use FU when none available 2414system.cpu3.iq.fu_full::SimdShift 0 0.00% 6.44% # attempts to use FU when none available 2415system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 6.44% # attempts to use FU when none available 2416system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 6.44% # attempts to use FU when none available 2417system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 6.44% # attempts to use FU when none available 2418system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 6.44% # attempts to use FU when none available 2419system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 6.44% # attempts to use FU when none available 2420system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 6.44% # attempts to use FU when none available 2421system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 6.44% # attempts to use FU when none available 2422system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 6.44% # attempts to use FU when none available 2423system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 6.44% # attempts to use FU when none available 2424system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.44% # attempts to use FU when none available 2425system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 6.44% # attempts to use FU when none available 2426system.cpu3.iq.fu_full::MemRead 37 14.02% 20.45% # attempts to use FU when none available 2427system.cpu3.iq.fu_full::MemWrite 210 79.55% 100.00% # attempts to use FU when none available 2428system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 2429system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 2430system.cpu3.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 2431system.cpu3.iq.FU_type_0::IntAlu 119912 48.21% 48.21% # Type of FU issued 2432system.cpu3.iq.FU_type_0::IntMult 0 0.00% 48.21% # Type of FU issued 2433system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 48.21% # Type of FU issued 2434system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 48.21% # Type of FU issued 2435system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 48.21% # Type of FU issued 2436system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 48.21% # Type of FU issued 2437system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 48.21% # Type of FU issued 2438system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 48.21% # Type of FU issued 2439system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 48.21% # Type of FU issued 2440system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 48.21% # Type of FU issued 2441system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 48.21% # Type of FU issued 2442system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 48.21% # Type of FU issued 2443system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 48.21% # Type of FU issued 2444system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 48.21% # Type of FU issued 2445system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 48.21% # Type of FU issued 2446system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 48.21% # Type of FU issued 2447system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 48.21% # Type of FU issued 2448system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 48.21% # Type of FU issued 2449system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.21% # Type of FU issued 2450system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 48.21% # Type of FU issued 2451system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.21% # Type of FU issued 2452system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.21% # Type of FU issued 2453system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.21% # Type of FU issued 2454system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.21% # Type of FU issued 2455system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.21% # Type of FU issued 2456system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.21% # Type of FU issued 2457system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 48.21% # Type of FU issued 2458system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.21% # Type of FU issued 2459system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.21% # Type of FU issued 2460system.cpu3.iq.FU_type_0::MemRead 89101 35.82% 84.03% # Type of FU issued 2461system.cpu3.iq.FU_type_0::MemWrite 39725 15.97% 100.00% # Type of FU issued 2462system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 2463system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 2464system.cpu3.iq.FU_type_0::total 248738 # Type of FU issued 2465system.cpu3.iq.rate 1.405855 # Inst issue rate 2466system.cpu3.iq.fu_busy_cnt 264 # FU busy when requested 2467system.cpu3.iq.fu_busy_rate 0.001061 # FU busy rate (busy events/executed inst) 2468system.cpu3.iq.int_inst_queue_reads 673341 # Number of integer instruction queue reads 2469system.cpu3.iq.int_inst_queue_writes 263119 # Number of integer instruction queue writes 2470system.cpu3.iq.int_inst_queue_wakeup_accesses 246940 # Number of integer instruction queue wakeup accesses 2471system.cpu3.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads 2472system.cpu3.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes 2473system.cpu3.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses 2474system.cpu3.iq.int_alu_accesses 249002 # Number of integer alu accesses 2475system.cpu3.iq.fp_alu_accesses 0 # Number of floating point alu accesses 2476system.cpu3.iew.lsq.thread0.forwLoads 35155 # Number of loads that had data forwarded from stores 2477system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 2478system.cpu3.iew.lsq.thread0.squashedLoads 2247 # Number of loads squashed 2479system.cpu3.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed 2480system.cpu3.iew.lsq.thread0.memOrderViolation 38 # Number of memory ordering violations 2481system.cpu3.iew.lsq.thread0.squashedStores 1385 # Number of stores squashed 2482system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 2483system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 2484system.cpu3.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 2485system.cpu3.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked 2486system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle 2487system.cpu3.iew.iewSquashCycles 2300 # Number of cycles IEW is squashing 2488system.cpu3.iew.iewBlockCycles 643 # Number of cycles IEW is blocking 2489system.cpu3.iew.iewUnblockCycles 39 # Number of cycles IEW is unblocking 2490system.cpu3.iew.iewDispatchedInsts 294126 # Number of instructions dispatched to IQ 2491system.cpu3.iew.iewDispSquashedInsts 354 # Number of squashed instructions skipped by dispatch 2492system.cpu3.iew.iewDispLoadInsts 84722 # Number of dispatched load instructions 2493system.cpu3.iew.iewDispStoreInsts 40383 # Number of dispatched store instructions 2494system.cpu3.iew.iewDispNonSpecInsts 1060 # Number of dispatched non-speculative instructions 2495system.cpu3.iew.iewIQFullEvents 38 # Number of times the IQ has become full, causing a stall 2496system.cpu3.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 2497system.cpu3.iew.memOrderViolationEvents 38 # Number of memory order violations 2498system.cpu3.iew.predictedTakenIncorrect 459 # Number of branches that were predicted taken incorrectly 2499system.cpu3.iew.predictedNotTakenIncorrect 919 # Number of branches that were predicted not taken incorrectly 2500system.cpu3.iew.branchMispredicts 1378 # Number of branch mispredicts detected at execute 2501system.cpu3.iew.iewExecutedInsts 247584 # Number of executed instructions 2502system.cpu3.iew.iewExecLoadInsts 83851 # Number of load instructions executed 2503system.cpu3.iew.iewExecSquashedInsts 1154 # Number of squashed instructions skipped in execute 2504system.cpu3.iew.exec_swp 0 # number of swp insts executed 2505system.cpu3.iew.exec_nop 41458 # number of nop insts executed 2506system.cpu3.iew.exec_refs 123507 # number of memory reference insts executed 2507system.cpu3.iew.exec_branches 50799 # Number of branches executed 2508system.cpu3.iew.exec_stores 39656 # Number of stores executed 2509system.cpu3.iew.exec_rate 1.399333 # Inst execution rate 2510system.cpu3.iew.wb_sent 247229 # cumulative count of insts sent to commit 2511system.cpu3.iew.wb_count 246940 # cumulative count of insts written-back 2512system.cpu3.iew.wb_producers 140247 # num instructions producing a value 2513system.cpu3.iew.wb_consumers 144914 # num instructions consuming a value 2514system.cpu3.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 2515system.cpu3.iew.wb_rate 1.395693 # insts written-back per cycle 2516system.cpu3.iew.wb_fanout 0.967795 # average fanout of values written-back 2517system.cpu3.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 2518system.cpu3.commit.commitSquashedInsts 11951 # The number of squashed insts skipped by commit 2519system.cpu3.commit.commitNonSpecStalls 5689 # The number of times commit has been forced to stall to communicate backwards 2520system.cpu3.commit.branchMispredicts 1265 # The number of times a branch was mispredicted 2521system.cpu3.commit.committed_per_cycle::samples 165494 # Number of insts commited each cycle 2522system.cpu3.commit.committed_per_cycle::mean 1.704926 # Number of insts commited each cycle 2523system.cpu3.commit.committed_per_cycle::stdev 2.039126 # Number of insts commited each cycle 2524system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 2525system.cpu3.commit.committed_per_cycle::0 64312 38.86% 38.86% # Number of insts commited each cycle 2526system.cpu3.commit.committed_per_cycle::1 48901 29.55% 68.41% # Number of insts commited each cycle 2527system.cpu3.commit.committed_per_cycle::2 6087 3.68% 72.09% # Number of insts commited each cycle 2528system.cpu3.commit.committed_per_cycle::3 6636 4.01% 76.10% # Number of insts commited each cycle 2529system.cpu3.commit.committed_per_cycle::4 1574 0.95% 77.05% # Number of insts commited each cycle 2530system.cpu3.commit.committed_per_cycle::5 35663 21.55% 98.60% # Number of insts commited each cycle 2531system.cpu3.commit.committed_per_cycle::6 504 0.30% 98.90% # Number of insts commited each cycle 2532system.cpu3.commit.committed_per_cycle::7 999 0.60% 99.51% # Number of insts commited each cycle 2533system.cpu3.commit.committed_per_cycle::8 818 0.49% 100.00% # Number of insts commited each cycle 2534system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 2535system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 2536system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 2537system.cpu3.commit.committed_per_cycle::total 165494 # Number of insts commited each cycle 2538system.cpu3.commit.committedInsts 282155 # Number of instructions committed 2539system.cpu3.commit.committedOps 282155 # Number of ops (including micro ops) committed 2540system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed 2541system.cpu3.commit.refs 121473 # Number of memory references committed 2542system.cpu3.commit.loads 82475 # Number of loads committed 2543system.cpu3.commit.membars 4979 # Number of memory barriers committed 2544system.cpu3.commit.branches 49942 # Number of branches committed 2545system.cpu3.commit.fp_insts 0 # Number of committed floating point instructions. 2546system.cpu3.commit.int_insts 193540 # Number of committed integer instructions. 2547system.cpu3.commit.function_calls 322 # Number of function calls committed. 2548system.cpu3.commit.op_class_0::No_OpClass 40736 14.44% 14.44% # Class of committed instruction 2549system.cpu3.commit.op_class_0::IntAlu 114967 40.75% 55.18% # Class of committed instruction 2550system.cpu3.commit.op_class_0::IntMult 0 0.00% 55.18% # Class of committed instruction 2551system.cpu3.commit.op_class_0::IntDiv 0 0.00% 55.18% # Class of committed instruction 2552system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 55.18% # Class of committed instruction 2553system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 55.18% # Class of committed instruction 2554system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 55.18% # Class of committed instruction 2555system.cpu3.commit.op_class_0::FloatMult 0 0.00% 55.18% # Class of committed instruction 2556system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 55.18% # Class of committed instruction 2557system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 55.18% # Class of committed instruction 2558system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 55.18% # Class of committed instruction 2559system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 55.18% # Class of committed instruction 2560system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 55.18% # Class of committed instruction 2561system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 55.18% # Class of committed instruction 2562system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 55.18% # Class of committed instruction 2563system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 55.18% # Class of committed instruction 2564system.cpu3.commit.op_class_0::SimdMult 0 0.00% 55.18% # Class of committed instruction 2565system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 55.18% # Class of committed instruction 2566system.cpu3.commit.op_class_0::SimdShift 0 0.00% 55.18% # Class of committed instruction 2567system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 55.18% # Class of committed instruction 2568system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 55.18% # Class of committed instruction 2569system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 55.18% # Class of committed instruction 2570system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 55.18% # Class of committed instruction 2571system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 55.18% # Class of committed instruction 2572system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 55.18% # Class of committed instruction 2573system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 55.18% # Class of committed instruction 2574system.cpu3.commit.op_class_0::SimdFloatMisc 0 0.00% 55.18% # Class of committed instruction 2575system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 55.18% # Class of committed instruction 2576system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.18% # Class of committed instruction 2577system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.18% # Class of committed instruction 2578system.cpu3.commit.op_class_0::MemRead 87454 31.00% 86.18% # Class of committed instruction 2579system.cpu3.commit.op_class_0::MemWrite 38998 13.82% 100.00% # Class of committed instruction 2580system.cpu3.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 2581system.cpu3.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 2582system.cpu3.commit.op_class_0::total 282155 # Class of committed instruction 2583system.cpu3.commit.bw_lim_events 818 # number cycles where commit BW limit reached 2584system.cpu3.commit.bw_limited 0 # number of insts not committed due to BW limits 2585system.cpu3.rob.rob_reads 458195 # The number of ROB reads 2586system.cpu3.rob.rob_writes 590518 # The number of ROB writes 2587system.cpu3.timesIdled 210 # Number of times that the entire CPU went into an idle state and unscheduled itself 2588system.cpu3.idleCycles 1387 # Total number of cycles that the CPU has spent unscheduled due to idling 2589system.cpu3.quiesceCycles 44814 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 2590system.cpu3.committedInsts 236440 # Number of Instructions Simulated 2591system.cpu3.committedOps 236440 # Number of Ops (including micro ops) Simulated 2592system.cpu3.committedInsts_total 236440 # Number of Instructions Simulated 2593system.cpu3.cpi 0.748308 # CPI: Cycles Per Instruction 2594system.cpu3.cpi_total 0.748308 # CPI: Total CPI of All Threads 2595system.cpu3.ipc 1.336348 # IPC: Instructions Per Cycle 2596system.cpu3.ipc_total 1.336348 # IPC: Total IPC of All Threads 2597system.cpu3.int_regfile_reads 429141 # number of integer regfile reads 2598system.cpu3.int_regfile_writes 199912 # number of integer regfile writes 2599system.cpu3.fp_regfile_writes 64 # number of floating regfile writes 2600system.cpu3.misc_regfile_reads 125101 # number of misc regfile reads 2601system.cpu3.misc_regfile_writes 648 # number of misc regfile writes 2602system.cpu3.icache.tags.replacements 319 # number of replacements 2603system.cpu3.icache.tags.tagsinuse 80.524551 # Cycle average of tags in use 2604system.cpu3.icache.tags.total_refs 19102 # Total number of references to valid blocks. 2605system.cpu3.icache.tags.sampled_refs 430 # Sample count of references to valid blocks. 2606system.cpu3.icache.tags.avg_refs 44.423256 # Average number of references to valid blocks. 2607system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 2608system.cpu3.icache.tags.occ_blocks::cpu3.inst 80.524551 # Average occupied blocks per requestor 2609system.cpu3.icache.tags.occ_percent::cpu3.inst 0.157275 # Average percentage of cache occupancy 2610system.cpu3.icache.tags.occ_percent::total 0.157275 # Average percentage of cache occupancy 2611system.cpu3.icache.tags.occ_task_id_blocks::1024 111 # Occupied blocks per task id 2612system.cpu3.icache.tags.age_task_id_blocks_1024::0 10 # Occupied blocks per task id 2613system.cpu3.icache.tags.age_task_id_blocks_1024::1 101 # Occupied blocks per task id 2614system.cpu3.icache.tags.occ_task_id_percent::1024 0.216797 # Percentage of cache occupancy per task id 2615system.cpu3.icache.tags.tag_accesses 20007 # Number of tag accesses 2616system.cpu3.icache.tags.data_accesses 20007 # Number of data accesses 2617system.cpu3.icache.ReadReq_hits::cpu3.inst 19102 # number of ReadReq hits 2618system.cpu3.icache.ReadReq_hits::total 19102 # number of ReadReq hits 2619system.cpu3.icache.demand_hits::cpu3.inst 19102 # number of demand (read+write) hits 2620system.cpu3.icache.demand_hits::total 19102 # number of demand (read+write) hits 2621system.cpu3.icache.overall_hits::cpu3.inst 19102 # number of overall hits 2622system.cpu3.icache.overall_hits::total 19102 # number of overall hits 2623system.cpu3.icache.ReadReq_misses::cpu3.inst 475 # number of ReadReq misses 2624system.cpu3.icache.ReadReq_misses::total 475 # number of ReadReq misses 2625system.cpu3.icache.demand_misses::cpu3.inst 475 # number of demand (read+write) misses 2626system.cpu3.icache.demand_misses::total 475 # number of demand (read+write) misses 2627system.cpu3.icache.overall_misses::cpu3.inst 475 # number of overall misses 2628system.cpu3.icache.overall_misses::total 475 # number of overall misses 2629system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 6525745 # number of ReadReq miss cycles 2630system.cpu3.icache.ReadReq_miss_latency::total 6525745 # number of ReadReq miss cycles 2631system.cpu3.icache.demand_miss_latency::cpu3.inst 6525745 # number of demand (read+write) miss cycles 2632system.cpu3.icache.demand_miss_latency::total 6525745 # number of demand (read+write) miss cycles 2633system.cpu3.icache.overall_miss_latency::cpu3.inst 6525745 # number of overall miss cycles 2634system.cpu3.icache.overall_miss_latency::total 6525745 # number of overall miss cycles 2635system.cpu3.icache.ReadReq_accesses::cpu3.inst 19577 # number of ReadReq accesses(hits+misses) 2636system.cpu3.icache.ReadReq_accesses::total 19577 # number of ReadReq accesses(hits+misses) 2637system.cpu3.icache.demand_accesses::cpu3.inst 19577 # number of demand (read+write) accesses 2638system.cpu3.icache.demand_accesses::total 19577 # number of demand (read+write) accesses 2639system.cpu3.icache.overall_accesses::cpu3.inst 19577 # number of overall (read+write) accesses 2640system.cpu3.icache.overall_accesses::total 19577 # number of overall (read+write) accesses 2641system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.024263 # miss rate for ReadReq accesses 2642system.cpu3.icache.ReadReq_miss_rate::total 0.024263 # miss rate for ReadReq accesses 2643system.cpu3.icache.demand_miss_rate::cpu3.inst 0.024263 # miss rate for demand accesses 2644system.cpu3.icache.demand_miss_rate::total 0.024263 # miss rate for demand accesses 2645system.cpu3.icache.overall_miss_rate::cpu3.inst 0.024263 # miss rate for overall accesses 2646system.cpu3.icache.overall_miss_rate::total 0.024263 # miss rate for overall accesses 2647system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13738.410526 # average ReadReq miss latency 2648system.cpu3.icache.ReadReq_avg_miss_latency::total 13738.410526 # average ReadReq miss latency 2649system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13738.410526 # average overall miss latency 2650system.cpu3.icache.demand_avg_miss_latency::total 13738.410526 # average overall miss latency 2651system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13738.410526 # average overall miss latency 2652system.cpu3.icache.overall_avg_miss_latency::total 13738.410526 # average overall miss latency 2653system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2654system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2655system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked 2656system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked 2657system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2658system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2659system.cpu3.icache.fast_writes 0 # number of fast writes performed 2660system.cpu3.icache.cache_copies 0 # number of cache copies performed 2661system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 45 # number of ReadReq MSHR hits 2662system.cpu3.icache.ReadReq_mshr_hits::total 45 # number of ReadReq MSHR hits 2663system.cpu3.icache.demand_mshr_hits::cpu3.inst 45 # number of demand (read+write) MSHR hits 2664system.cpu3.icache.demand_mshr_hits::total 45 # number of demand (read+write) MSHR hits 2665system.cpu3.icache.overall_mshr_hits::cpu3.inst 45 # number of overall MSHR hits 2666system.cpu3.icache.overall_mshr_hits::total 45 # number of overall MSHR hits 2667system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 430 # number of ReadReq MSHR misses 2668system.cpu3.icache.ReadReq_mshr_misses::total 430 # number of ReadReq MSHR misses 2669system.cpu3.icache.demand_mshr_misses::cpu3.inst 430 # number of demand (read+write) MSHR misses 2670system.cpu3.icache.demand_mshr_misses::total 430 # number of demand (read+write) MSHR misses 2671system.cpu3.icache.overall_mshr_misses::cpu3.inst 430 # number of overall MSHR misses 2672system.cpu3.icache.overall_mshr_misses::total 430 # number of overall MSHR misses 2673system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 5298255 # number of ReadReq MSHR miss cycles 2674system.cpu3.icache.ReadReq_mshr_miss_latency::total 5298255 # number of ReadReq MSHR miss cycles 2675system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 5298255 # number of demand (read+write) MSHR miss cycles 2676system.cpu3.icache.demand_mshr_miss_latency::total 5298255 # number of demand (read+write) MSHR miss cycles 2677system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 5298255 # number of overall MSHR miss cycles 2678system.cpu3.icache.overall_mshr_miss_latency::total 5298255 # number of overall MSHR miss cycles 2679system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.021965 # mshr miss rate for ReadReq accesses 2680system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.021965 # mshr miss rate for ReadReq accesses 2681system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.021965 # mshr miss rate for demand accesses 2682system.cpu3.icache.demand_mshr_miss_rate::total 0.021965 # mshr miss rate for demand accesses 2683system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.021965 # mshr miss rate for overall accesses 2684system.cpu3.icache.overall_mshr_miss_rate::total 0.021965 # mshr miss rate for overall accesses 2685system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12321.523256 # average ReadReq mshr miss latency 2686system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 12321.523256 # average ReadReq mshr miss latency 2687system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12321.523256 # average overall mshr miss latency 2688system.cpu3.icache.demand_avg_mshr_miss_latency::total 12321.523256 # average overall mshr miss latency 2689system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12321.523256 # average overall mshr miss latency 2690system.cpu3.icache.overall_avg_mshr_miss_latency::total 12321.523256 # average overall mshr miss latency 2691system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate 2692system.cpu3.dcache.tags.replacements 0 # number of replacements 2693system.cpu3.dcache.tags.tagsinuse 24.706550 # Cycle average of tags in use 2694system.cpu3.dcache.tags.total_refs 44992 # Total number of references to valid blocks. 2695system.cpu3.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks. 2696system.cpu3.dcache.tags.avg_refs 1606.857143 # Average number of references to valid blocks. 2697system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 2698system.cpu3.dcache.tags.occ_blocks::cpu3.data 24.706550 # Average occupied blocks per requestor 2699system.cpu3.dcache.tags.occ_percent::cpu3.data 0.048255 # Average percentage of cache occupancy 2700system.cpu3.dcache.tags.occ_percent::total 0.048255 # Average percentage of cache occupancy 2701system.cpu3.dcache.tags.occ_task_id_blocks::1024 28 # Occupied blocks per task id 2702system.cpu3.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id 2703system.cpu3.dcache.tags.occ_task_id_percent::1024 0.054688 # Percentage of cache occupancy per task id 2704system.cpu3.dcache.tags.tag_accesses 350946 # Number of tag accesses 2705system.cpu3.dcache.tags.data_accesses 350946 # Number of data accesses 2706system.cpu3.dcache.ReadReq_hits::cpu3.data 48327 # number of ReadReq hits 2707system.cpu3.dcache.ReadReq_hits::total 48327 # number of ReadReq hits 2708system.cpu3.dcache.WriteReq_hits::cpu3.data 38795 # number of WriteReq hits 2709system.cpu3.dcache.WriteReq_hits::total 38795 # number of WriteReq hits 2710system.cpu3.dcache.SwapReq_hits::cpu3.data 12 # number of SwapReq hits 2711system.cpu3.dcache.SwapReq_hits::total 12 # number of SwapReq hits 2712system.cpu3.dcache.demand_hits::cpu3.data 87122 # number of demand (read+write) hits 2713system.cpu3.dcache.demand_hits::total 87122 # number of demand (read+write) hits 2714system.cpu3.dcache.overall_hits::cpu3.data 87122 # number of overall hits 2715system.cpu3.dcache.overall_hits::total 87122 # number of overall hits 2716system.cpu3.dcache.ReadReq_misses::cpu3.data 351 # number of ReadReq misses 2717system.cpu3.dcache.ReadReq_misses::total 351 # number of ReadReq misses 2718system.cpu3.dcache.WriteReq_misses::cpu3.data 139 # number of WriteReq misses 2719system.cpu3.dcache.WriteReq_misses::total 139 # number of WriteReq misses 2720system.cpu3.dcache.SwapReq_misses::cpu3.data 52 # number of SwapReq misses 2721system.cpu3.dcache.SwapReq_misses::total 52 # number of SwapReq misses 2722system.cpu3.dcache.demand_misses::cpu3.data 490 # number of demand (read+write) misses 2723system.cpu3.dcache.demand_misses::total 490 # number of demand (read+write) misses 2724system.cpu3.dcache.overall_misses::cpu3.data 490 # number of overall misses 2725system.cpu3.dcache.overall_misses::total 490 # number of overall misses 2726system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 4621144 # number of ReadReq miss cycles 2727system.cpu3.dcache.ReadReq_miss_latency::total 4621144 # number of ReadReq miss cycles 2728system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 3311512 # number of WriteReq miss cycles 2729system.cpu3.dcache.WriteReq_miss_latency::total 3311512 # number of WriteReq miss cycles 2730system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 513008 # number of SwapReq miss cycles 2731system.cpu3.dcache.SwapReq_miss_latency::total 513008 # number of SwapReq miss cycles 2732system.cpu3.dcache.demand_miss_latency::cpu3.data 7932656 # number of demand (read+write) miss cycles 2733system.cpu3.dcache.demand_miss_latency::total 7932656 # number of demand (read+write) miss cycles 2734system.cpu3.dcache.overall_miss_latency::cpu3.data 7932656 # number of overall miss cycles 2735system.cpu3.dcache.overall_miss_latency::total 7932656 # number of overall miss cycles 2736system.cpu3.dcache.ReadReq_accesses::cpu3.data 48678 # number of ReadReq accesses(hits+misses) 2737system.cpu3.dcache.ReadReq_accesses::total 48678 # number of ReadReq accesses(hits+misses) 2738system.cpu3.dcache.WriteReq_accesses::cpu3.data 38934 # number of WriteReq accesses(hits+misses) 2739system.cpu3.dcache.WriteReq_accesses::total 38934 # number of WriteReq accesses(hits+misses) 2740system.cpu3.dcache.SwapReq_accesses::cpu3.data 64 # number of SwapReq accesses(hits+misses) 2741system.cpu3.dcache.SwapReq_accesses::total 64 # number of SwapReq accesses(hits+misses) 2742system.cpu3.dcache.demand_accesses::cpu3.data 87612 # number of demand (read+write) accesses 2743system.cpu3.dcache.demand_accesses::total 87612 # number of demand (read+write) accesses 2744system.cpu3.dcache.overall_accesses::cpu3.data 87612 # number of overall (read+write) accesses 2745system.cpu3.dcache.overall_accesses::total 87612 # number of overall (read+write) accesses 2746system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.007211 # miss rate for ReadReq accesses 2747system.cpu3.dcache.ReadReq_miss_rate::total 0.007211 # miss rate for ReadReq accesses 2748system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.003570 # miss rate for WriteReq accesses 2749system.cpu3.dcache.WriteReq_miss_rate::total 0.003570 # miss rate for WriteReq accesses 2750system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.812500 # miss rate for SwapReq accesses 2751system.cpu3.dcache.SwapReq_miss_rate::total 0.812500 # miss rate for SwapReq accesses 2752system.cpu3.dcache.demand_miss_rate::cpu3.data 0.005593 # miss rate for demand accesses 2753system.cpu3.dcache.demand_miss_rate::total 0.005593 # miss rate for demand accesses 2754system.cpu3.dcache.overall_miss_rate::cpu3.data 0.005593 # miss rate for overall accesses 2755system.cpu3.dcache.overall_miss_rate::total 0.005593 # miss rate for overall accesses 2756system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 13165.652422 # average ReadReq miss latency 2757system.cpu3.dcache.ReadReq_avg_miss_latency::total 13165.652422 # average ReadReq miss latency 2758system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 23823.827338 # average WriteReq miss latency 2759system.cpu3.dcache.WriteReq_avg_miss_latency::total 23823.827338 # average WriteReq miss latency 2760system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 9865.538462 # average SwapReq miss latency 2761system.cpu3.dcache.SwapReq_avg_miss_latency::total 9865.538462 # average SwapReq miss latency 2762system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 16189.093878 # average overall miss latency 2763system.cpu3.dcache.demand_avg_miss_latency::total 16189.093878 # average overall miss latency 2764system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 16189.093878 # average overall miss latency 2765system.cpu3.dcache.overall_avg_miss_latency::total 16189.093878 # average overall miss latency 2766system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2767system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2768system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 2769system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked 2770system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2771system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2772system.cpu3.dcache.fast_writes 0 # number of fast writes performed 2773system.cpu3.dcache.cache_copies 0 # number of cache copies performed 2774system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 197 # number of ReadReq MSHR hits 2775system.cpu3.dcache.ReadReq_mshr_hits::total 197 # number of ReadReq MSHR hits 2776system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 33 # number of WriteReq MSHR hits 2777system.cpu3.dcache.WriteReq_mshr_hits::total 33 # number of WriteReq MSHR hits 2778system.cpu3.dcache.demand_mshr_hits::cpu3.data 230 # number of demand (read+write) MSHR hits 2779system.cpu3.dcache.demand_mshr_hits::total 230 # number of demand (read+write) MSHR hits 2780system.cpu3.dcache.overall_mshr_hits::cpu3.data 230 # number of overall MSHR hits 2781system.cpu3.dcache.overall_mshr_hits::total 230 # number of overall MSHR hits 2782system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 154 # number of ReadReq MSHR misses 2783system.cpu3.dcache.ReadReq_mshr_misses::total 154 # number of ReadReq MSHR misses 2784system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 106 # number of WriteReq MSHR misses 2785system.cpu3.dcache.WriteReq_mshr_misses::total 106 # number of WriteReq MSHR misses 2786system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 52 # number of SwapReq MSHR misses 2787system.cpu3.dcache.SwapReq_mshr_misses::total 52 # number of SwapReq MSHR misses 2788system.cpu3.dcache.demand_mshr_misses::cpu3.data 260 # number of demand (read+write) MSHR misses 2789system.cpu3.dcache.demand_mshr_misses::total 260 # number of demand (read+write) MSHR misses 2790system.cpu3.dcache.overall_mshr_misses::cpu3.data 260 # number of overall MSHR misses 2791system.cpu3.dcache.overall_mshr_misses::total 260 # number of overall MSHR misses 2792system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1052517 # number of ReadReq MSHR miss cycles 2793system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1052517 # number of ReadReq MSHR miss cycles 2794system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1403488 # number of WriteReq MSHR miss cycles 2795system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1403488 # number of WriteReq MSHR miss cycles 2796system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 408992 # number of SwapReq MSHR miss cycles 2797system.cpu3.dcache.SwapReq_mshr_miss_latency::total 408992 # number of SwapReq MSHR miss cycles 2798system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 2456005 # number of demand (read+write) MSHR miss cycles 2799system.cpu3.dcache.demand_mshr_miss_latency::total 2456005 # number of demand (read+write) MSHR miss cycles 2800system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 2456005 # number of overall MSHR miss cycles 2801system.cpu3.dcache.overall_mshr_miss_latency::total 2456005 # number of overall MSHR miss cycles 2802system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003164 # mshr miss rate for ReadReq accesses 2803system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003164 # mshr miss rate for ReadReq accesses 2804system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.002723 # mshr miss rate for WriteReq accesses 2805system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.002723 # mshr miss rate for WriteReq accesses 2806system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.812500 # mshr miss rate for SwapReq accesses 2807system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.812500 # mshr miss rate for SwapReq accesses 2808system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.002968 # mshr miss rate for demand accesses 2809system.cpu3.dcache.demand_mshr_miss_rate::total 0.002968 # mshr miss rate for demand accesses 2810system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.002968 # mshr miss rate for overall accesses 2811system.cpu3.dcache.overall_mshr_miss_rate::total 0.002968 # mshr miss rate for overall accesses 2812system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 6834.525974 # average ReadReq mshr miss latency 2813system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 6834.525974 # average ReadReq mshr miss latency 2814system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 13240.452830 # average WriteReq mshr miss latency 2815system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 13240.452830 # average WriteReq mshr miss latency 2816system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 7865.230769 # average SwapReq mshr miss latency 2817system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 7865.230769 # average SwapReq mshr miss latency 2818system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 9446.173077 # average overall mshr miss latency 2819system.cpu3.dcache.demand_avg_mshr_miss_latency::total 9446.173077 # average overall mshr miss latency 2820system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 9446.173077 # average overall mshr miss latency 2821system.cpu3.dcache.overall_avg_mshr_miss_latency::total 9446.173077 # average overall mshr miss latency 2822system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 2823 2824---------- End Simulation Statistics ---------- 2825