stats.txt revision 10036:80e84beef3bb
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000111 # Number of seconds simulated 4sim_ticks 111025500 # Number of ticks simulated 5final_tick 111025500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 93081 # Simulator instruction rate (inst/s) 8host_op_rate 93081 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 9906240 # Simulator tick rate (ticks/s) 10host_mem_usage 253180 # Number of bytes of host memory used 11host_seconds 11.21 # Real time elapsed on the host 12sim_insts 1043212 # Number of instructions simulated 13sim_ops 1043212 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu0.inst 22784 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.data 10752 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu1.inst 640 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu1.data 832 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu2.inst 4672 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu2.data 1280 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu3.inst 384 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu3.data 832 # Number of bytes read from this memory 24system.physmem.bytes_read::total 42176 # Number of bytes read from this memory 25system.physmem.bytes_inst_read::cpu0.inst 22784 # Number of instructions bytes read from this memory 26system.physmem.bytes_inst_read::cpu1.inst 640 # Number of instructions bytes read from this memory 27system.physmem.bytes_inst_read::cpu2.inst 4672 # Number of instructions bytes read from this memory 28system.physmem.bytes_inst_read::cpu3.inst 384 # Number of instructions bytes read from this memory 29system.physmem.bytes_inst_read::total 28480 # Number of instructions bytes read from this memory 30system.physmem.num_reads::cpu0.inst 356 # Number of read requests responded to by this memory 31system.physmem.num_reads::cpu0.data 168 # Number of read requests responded to by this memory 32system.physmem.num_reads::cpu1.inst 10 # Number of read requests responded to by this memory 33system.physmem.num_reads::cpu1.data 13 # Number of read requests responded to by this memory 34system.physmem.num_reads::cpu2.inst 73 # Number of read requests responded to by this memory 35system.physmem.num_reads::cpu2.data 20 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu3.inst 6 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu3.data 13 # Number of read requests responded to by this memory 38system.physmem.num_reads::total 659 # Number of read requests responded to by this memory 39system.physmem.bw_read::cpu0.inst 205214117 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::cpu0.data 96842617 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::cpu1.inst 5764442 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_read::cpu1.data 7493774 # Total read bandwidth from this memory (bytes/s) 43system.physmem.bw_read::cpu2.inst 42080423 # Total read bandwidth from this memory (bytes/s) 44system.physmem.bw_read::cpu2.data 11528883 # Total read bandwidth from this memory (bytes/s) 45system.physmem.bw_read::cpu3.inst 3458665 # Total read bandwidth from this memory (bytes/s) 46system.physmem.bw_read::cpu3.data 7493774 # Total read bandwidth from this memory (bytes/s) 47system.physmem.bw_read::total 379876695 # Total read bandwidth from this memory (bytes/s) 48system.physmem.bw_inst_read::cpu0.inst 205214117 # Instruction read bandwidth from this memory (bytes/s) 49system.physmem.bw_inst_read::cpu1.inst 5764442 # Instruction read bandwidth from this memory (bytes/s) 50system.physmem.bw_inst_read::cpu2.inst 42080423 # Instruction read bandwidth from this memory (bytes/s) 51system.physmem.bw_inst_read::cpu3.inst 3458665 # Instruction read bandwidth from this memory (bytes/s) 52system.physmem.bw_inst_read::total 256517647 # Instruction read bandwidth from this memory (bytes/s) 53system.physmem.bw_total::cpu0.inst 205214117 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.bw_total::cpu0.data 96842617 # Total bandwidth to/from this memory (bytes/s) 55system.physmem.bw_total::cpu1.inst 5764442 # Total bandwidth to/from this memory (bytes/s) 56system.physmem.bw_total::cpu1.data 7493774 # Total bandwidth to/from this memory (bytes/s) 57system.physmem.bw_total::cpu2.inst 42080423 # Total bandwidth to/from this memory (bytes/s) 58system.physmem.bw_total::cpu2.data 11528883 # Total bandwidth to/from this memory (bytes/s) 59system.physmem.bw_total::cpu3.inst 3458665 # Total bandwidth to/from this memory (bytes/s) 60system.physmem.bw_total::cpu3.data 7493774 # Total bandwidth to/from this memory (bytes/s) 61system.physmem.bw_total::total 379876695 # Total bandwidth to/from this memory (bytes/s) 62system.physmem.readReqs 660 # Number of read requests accepted 63system.physmem.writeReqs 0 # Number of write requests accepted 64system.physmem.readBursts 660 # Number of DRAM read bursts, including those serviced by the write queue 65system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 66system.physmem.bytesReadDRAM 42240 # Total number of bytes read from DRAM 67system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 68system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 69system.physmem.bytesReadSys 42240 # Total read bytes from the system interface side 70system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 71system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 72system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 73system.physmem.neitherReadNorWriteReqs 76 # Number of requests that are neither read nor write 74system.physmem.perBankRdBursts::0 115 # Per bank write bursts 75system.physmem.perBankRdBursts::1 39 # Per bank write bursts 76system.physmem.perBankRdBursts::2 29 # Per bank write bursts 77system.physmem.perBankRdBursts::3 60 # Per bank write bursts 78system.physmem.perBankRdBursts::4 65 # Per bank write bursts 79system.physmem.perBankRdBursts::5 27 # Per bank write bursts 80system.physmem.perBankRdBursts::6 18 # Per bank write bursts 81system.physmem.perBankRdBursts::7 24 # Per bank write bursts 82system.physmem.perBankRdBursts::8 7 # Per bank write bursts 83system.physmem.perBankRdBursts::9 28 # Per bank write bursts 84system.physmem.perBankRdBursts::10 23 # Per bank write bursts 85system.physmem.perBankRdBursts::11 12 # Per bank write bursts 86system.physmem.perBankRdBursts::12 60 # Per bank write bursts 87system.physmem.perBankRdBursts::13 38 # Per bank write bursts 88system.physmem.perBankRdBursts::14 17 # Per bank write bursts 89system.physmem.perBankRdBursts::15 98 # Per bank write bursts 90system.physmem.perBankWrBursts::0 0 # Per bank write bursts 91system.physmem.perBankWrBursts::1 0 # Per bank write bursts 92system.physmem.perBankWrBursts::2 0 # Per bank write bursts 93system.physmem.perBankWrBursts::3 0 # Per bank write bursts 94system.physmem.perBankWrBursts::4 0 # Per bank write bursts 95system.physmem.perBankWrBursts::5 0 # Per bank write bursts 96system.physmem.perBankWrBursts::6 0 # Per bank write bursts 97system.physmem.perBankWrBursts::7 0 # Per bank write bursts 98system.physmem.perBankWrBursts::8 0 # Per bank write bursts 99system.physmem.perBankWrBursts::9 0 # Per bank write bursts 100system.physmem.perBankWrBursts::10 0 # Per bank write bursts 101system.physmem.perBankWrBursts::11 0 # Per bank write bursts 102system.physmem.perBankWrBursts::12 0 # Per bank write bursts 103system.physmem.perBankWrBursts::13 0 # Per bank write bursts 104system.physmem.perBankWrBursts::14 0 # Per bank write bursts 105system.physmem.perBankWrBursts::15 0 # Per bank write bursts 106system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 107system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 108system.physmem.totGap 110997500 # Total gap between requests 109system.physmem.readPktSize::0 0 # Read request sizes (log2) 110system.physmem.readPktSize::1 0 # Read request sizes (log2) 111system.physmem.readPktSize::2 0 # Read request sizes (log2) 112system.physmem.readPktSize::3 0 # Read request sizes (log2) 113system.physmem.readPktSize::4 0 # Read request sizes (log2) 114system.physmem.readPktSize::5 0 # Read request sizes (log2) 115system.physmem.readPktSize::6 660 # Read request sizes (log2) 116system.physmem.writePktSize::0 0 # Write request sizes (log2) 117system.physmem.writePktSize::1 0 # Write request sizes (log2) 118system.physmem.writePktSize::2 0 # Write request sizes (log2) 119system.physmem.writePktSize::3 0 # Write request sizes (log2) 120system.physmem.writePktSize::4 0 # Write request sizes (log2) 121system.physmem.writePktSize::5 0 # Write request sizes (log2) 122system.physmem.writePktSize::6 0 # Write request sizes (log2) 123system.physmem.rdQLenPdf::0 408 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::1 191 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::2 49 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::3 10 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 155system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 187system.physmem.bytesPerActivate::samples 151 # Bytes accessed per row activation 188system.physmem.bytesPerActivate::mean 260.662252 # Bytes accessed per row activation 189system.physmem.bytesPerActivate::gmean 168.685653 # Bytes accessed per row activation 190system.physmem.bytesPerActivate::stdev 287.368727 # Bytes accessed per row activation 191system.physmem.bytesPerActivate::64 56 37.09% 37.09% # Bytes accessed per row activation 192system.physmem.bytesPerActivate::128 15 9.93% 47.02% # Bytes accessed per row activation 193system.physmem.bytesPerActivate::192 26 17.22% 64.24% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::256 9 5.96% 70.20% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::320 10 6.62% 76.82% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::384 7 4.64% 81.46% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::448 4 2.65% 84.11% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::512 6 3.97% 88.08% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::576 3 1.99% 90.07% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::640 3 1.99% 92.05% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::704 2 1.32% 93.38% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::768 2 1.32% 94.70% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::832 3 1.99% 96.69% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::1024 2 1.32% 98.01% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::1152 1 0.66% 98.68% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::1536 1 0.66% 99.34% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::1984 1 0.66% 100.00% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::total 151 # Bytes accessed per row activation 209system.physmem.totQLat 4008250 # Total ticks spent queuing 210system.physmem.totMemAccLat 18157000 # Total ticks spent from burst creation until serviced by the DRAM 211system.physmem.totBusLat 3300000 # Total ticks spent in databus transfers 212system.physmem.totBankLat 10848750 # Total ticks spent accessing banks 213system.physmem.avgQLat 6073.11 # Average queueing delay per DRAM burst 214system.physmem.avgBankLat 16437.50 # Average bank access latency per DRAM burst 215system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 216system.physmem.avgMemAccLat 27510.61 # Average memory access latency per DRAM burst 217system.physmem.avgRdBW 380.45 # Average DRAM read bandwidth in MiByte/s 218system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 219system.physmem.avgRdBWSys 380.45 # Average system read bandwidth in MiByte/s 220system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 221system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 222system.physmem.busUtil 2.97 # Data bus utilization in percentage 223system.physmem.busUtilRead 2.97 # Data bus utilization in percentage for reads 224system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 225system.physmem.avgRdQLen 0.16 # Average read queue length when enqueuing 226system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 227system.physmem.readRowHits 509 # Number of row buffer hits during reads 228system.physmem.writeRowHits 0 # Number of row buffer hits during writes 229system.physmem.readRowHitRate 77.12 # Row buffer hit rate for reads 230system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 231system.physmem.avgGap 168178.03 # Average gap between requests 232system.physmem.pageHitRate 77.12 # Row buffer hit rate, read and write combined 233system.physmem.prechargeAllPercent 11.34 # Percentage of time for which DRAM has all the banks in precharge state 234system.membus.throughput 379876695 # Throughput (bytes/s) 235system.membus.trans_dist::ReadReq 529 # Transaction distribution 236system.membus.trans_dist::ReadResp 528 # Transaction distribution 237system.membus.trans_dist::UpgradeReq 289 # Transaction distribution 238system.membus.trans_dist::UpgradeResp 76 # Transaction distribution 239system.membus.trans_dist::ReadExReq 164 # Transaction distribution 240system.membus.trans_dist::ReadExResp 131 # Transaction distribution 241system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1717 # Packet count per connected master and slave (bytes) 242system.membus.pkt_count::total 1717 # Packet count per connected master and slave (bytes) 243system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 42176 # Cumulative packet size per connected master and slave (bytes) 244system.membus.tot_pkt_size::total 42176 # Cumulative packet size per connected master and slave (bytes) 245system.membus.data_through_bus 42176 # Total data (bytes) 246system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 247system.membus.reqLayer0.occupancy 932000 # Layer occupancy (ticks) 248system.membus.reqLayer0.utilization 0.8 # Layer utilization (%) 249system.membus.respLayer1.occupancy 6290425 # Layer occupancy (ticks) 250system.membus.respLayer1.utilization 5.7 # Layer utilization (%) 251system.cpu_clk_domain.clock 500 # Clock period in ticks 252system.l2c.tags.replacements 0 # number of replacements 253system.l2c.tags.tagsinuse 417.163639 # Cycle average of tags in use 254system.l2c.tags.total_refs 1442 # Total number of references to valid blocks. 255system.l2c.tags.sampled_refs 526 # Sample count of references to valid blocks. 256system.l2c.tags.avg_refs 2.741445 # Average number of references to valid blocks. 257system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 258system.l2c.tags.occ_blocks::writebacks 0.799798 # Average occupied blocks per requestor 259system.l2c.tags.occ_blocks::cpu0.inst 285.086488 # Average occupied blocks per requestor 260system.l2c.tags.occ_blocks::cpu0.data 58.417431 # Average occupied blocks per requestor 261system.l2c.tags.occ_blocks::cpu1.inst 7.543236 # Average occupied blocks per requestor 262system.l2c.tags.occ_blocks::cpu1.data 0.694746 # Average occupied blocks per requestor 263system.l2c.tags.occ_blocks::cpu2.inst 55.417060 # Average occupied blocks per requestor 264system.l2c.tags.occ_blocks::cpu2.data 5.409300 # Average occupied blocks per requestor 265system.l2c.tags.occ_blocks::cpu3.inst 3.063366 # Average occupied blocks per requestor 266system.l2c.tags.occ_blocks::cpu3.data 0.732215 # Average occupied blocks per requestor 267system.l2c.tags.occ_percent::writebacks 0.000012 # Average percentage of cache occupancy 268system.l2c.tags.occ_percent::cpu0.inst 0.004350 # Average percentage of cache occupancy 269system.l2c.tags.occ_percent::cpu0.data 0.000891 # Average percentage of cache occupancy 270system.l2c.tags.occ_percent::cpu1.inst 0.000115 # Average percentage of cache occupancy 271system.l2c.tags.occ_percent::cpu1.data 0.000011 # Average percentage of cache occupancy 272system.l2c.tags.occ_percent::cpu2.inst 0.000846 # Average percentage of cache occupancy 273system.l2c.tags.occ_percent::cpu2.data 0.000083 # Average percentage of cache occupancy 274system.l2c.tags.occ_percent::cpu3.inst 0.000047 # Average percentage of cache occupancy 275system.l2c.tags.occ_percent::cpu3.data 0.000011 # Average percentage of cache occupancy 276system.l2c.tags.occ_percent::total 0.006365 # Average percentage of cache occupancy 277system.l2c.tags.occ_task_id_blocks::1024 526 # Occupied blocks per task id 278system.l2c.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id 279system.l2c.tags.age_task_id_blocks_1024::1 293 # Occupied blocks per task id 280system.l2c.tags.age_task_id_blocks_1024::2 182 # Occupied blocks per task id 281system.l2c.tags.occ_task_id_percent::1024 0.008026 # Percentage of cache occupancy per task id 282system.l2c.tags.tag_accesses 18228 # Number of tag accesses 283system.l2c.tags.data_accesses 18228 # Number of data accesses 284system.l2c.ReadReq_hits::cpu0.inst 229 # number of ReadReq hits 285system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits 286system.l2c.ReadReq_hits::cpu1.inst 412 # number of ReadReq hits 287system.l2c.ReadReq_hits::cpu1.data 11 # number of ReadReq hits 288system.l2c.ReadReq_hits::cpu2.inst 349 # number of ReadReq hits 289system.l2c.ReadReq_hits::cpu2.data 5 # number of ReadReq hits 290system.l2c.ReadReq_hits::cpu3.inst 420 # number of ReadReq hits 291system.l2c.ReadReq_hits::cpu3.data 11 # number of ReadReq hits 292system.l2c.ReadReq_hits::total 1442 # number of ReadReq hits 293system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits 294system.l2c.Writeback_hits::total 1 # number of Writeback hits 295system.l2c.UpgradeReq_hits::cpu0.data 3 # number of UpgradeReq hits 296system.l2c.UpgradeReq_hits::total 3 # number of UpgradeReq hits 297system.l2c.demand_hits::cpu0.inst 229 # number of demand (read+write) hits 298system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits 299system.l2c.demand_hits::cpu1.inst 412 # number of demand (read+write) hits 300system.l2c.demand_hits::cpu1.data 11 # number of demand (read+write) hits 301system.l2c.demand_hits::cpu2.inst 349 # number of demand (read+write) hits 302system.l2c.demand_hits::cpu2.data 5 # number of demand (read+write) hits 303system.l2c.demand_hits::cpu3.inst 420 # number of demand (read+write) hits 304system.l2c.demand_hits::cpu3.data 11 # number of demand (read+write) hits 305system.l2c.demand_hits::total 1442 # number of demand (read+write) hits 306system.l2c.overall_hits::cpu0.inst 229 # number of overall hits 307system.l2c.overall_hits::cpu0.data 5 # number of overall hits 308system.l2c.overall_hits::cpu1.inst 412 # number of overall hits 309system.l2c.overall_hits::cpu1.data 11 # number of overall hits 310system.l2c.overall_hits::cpu2.inst 349 # number of overall hits 311system.l2c.overall_hits::cpu2.data 5 # number of overall hits 312system.l2c.overall_hits::cpu3.inst 420 # number of overall hits 313system.l2c.overall_hits::cpu3.data 11 # number of overall hits 314system.l2c.overall_hits::total 1442 # number of overall hits 315system.l2c.ReadReq_misses::cpu0.inst 359 # number of ReadReq misses 316system.l2c.ReadReq_misses::cpu0.data 74 # number of ReadReq misses 317system.l2c.ReadReq_misses::cpu1.inst 16 # number of ReadReq misses 318system.l2c.ReadReq_misses::cpu1.data 1 # number of ReadReq misses 319system.l2c.ReadReq_misses::cpu2.inst 76 # number of ReadReq misses 320system.l2c.ReadReq_misses::cpu2.data 7 # number of ReadReq misses 321system.l2c.ReadReq_misses::cpu3.inst 9 # number of ReadReq misses 322system.l2c.ReadReq_misses::cpu3.data 1 # number of ReadReq misses 323system.l2c.ReadReq_misses::total 543 # number of ReadReq misses 324system.l2c.UpgradeReq_misses::cpu0.data 21 # number of UpgradeReq misses 325system.l2c.UpgradeReq_misses::cpu1.data 20 # number of UpgradeReq misses 326system.l2c.UpgradeReq_misses::cpu2.data 17 # number of UpgradeReq misses 327system.l2c.UpgradeReq_misses::cpu3.data 18 # number of UpgradeReq misses 328system.l2c.UpgradeReq_misses::total 76 # number of UpgradeReq misses 329system.l2c.ReadExReq_misses::cpu0.data 94 # number of ReadExReq misses 330system.l2c.ReadExReq_misses::cpu1.data 12 # number of ReadExReq misses 331system.l2c.ReadExReq_misses::cpu2.data 13 # number of ReadExReq misses 332system.l2c.ReadExReq_misses::cpu3.data 12 # number of ReadExReq misses 333system.l2c.ReadExReq_misses::total 131 # number of ReadExReq misses 334system.l2c.demand_misses::cpu0.inst 359 # number of demand (read+write) misses 335system.l2c.demand_misses::cpu0.data 168 # number of demand (read+write) misses 336system.l2c.demand_misses::cpu1.inst 16 # number of demand (read+write) misses 337system.l2c.demand_misses::cpu1.data 13 # number of demand (read+write) misses 338system.l2c.demand_misses::cpu2.inst 76 # number of demand (read+write) misses 339system.l2c.demand_misses::cpu2.data 20 # number of demand (read+write) misses 340system.l2c.demand_misses::cpu3.inst 9 # number of demand (read+write) misses 341system.l2c.demand_misses::cpu3.data 13 # number of demand (read+write) misses 342system.l2c.demand_misses::total 674 # number of demand (read+write) misses 343system.l2c.overall_misses::cpu0.inst 359 # number of overall misses 344system.l2c.overall_misses::cpu0.data 168 # number of overall misses 345system.l2c.overall_misses::cpu1.inst 16 # number of overall misses 346system.l2c.overall_misses::cpu1.data 13 # number of overall misses 347system.l2c.overall_misses::cpu2.inst 76 # number of overall misses 348system.l2c.overall_misses::cpu2.data 20 # number of overall misses 349system.l2c.overall_misses::cpu3.inst 9 # number of overall misses 350system.l2c.overall_misses::cpu3.data 13 # number of overall misses 351system.l2c.overall_misses::total 674 # number of overall misses 352system.l2c.ReadReq_miss_latency::cpu0.inst 24802000 # number of ReadReq miss cycles 353system.l2c.ReadReq_miss_latency::cpu0.data 5612000 # number of ReadReq miss cycles 354system.l2c.ReadReq_miss_latency::cpu1.inst 1162500 # number of ReadReq miss cycles 355system.l2c.ReadReq_miss_latency::cpu1.data 74500 # number of ReadReq miss cycles 356system.l2c.ReadReq_miss_latency::cpu2.inst 5361500 # number of ReadReq miss cycles 357system.l2c.ReadReq_miss_latency::cpu2.data 495250 # number of ReadReq miss cycles 358system.l2c.ReadReq_miss_latency::cpu3.inst 583750 # number of ReadReq miss cycles 359system.l2c.ReadReq_miss_latency::cpu3.data 74500 # number of ReadReq miss cycles 360system.l2c.ReadReq_miss_latency::total 38166000 # number of ReadReq miss cycles 361system.l2c.ReadExReq_miss_latency::cpu0.data 6725000 # number of ReadExReq miss cycles 362system.l2c.ReadExReq_miss_latency::cpu1.data 852250 # number of ReadExReq miss cycles 363system.l2c.ReadExReq_miss_latency::cpu2.data 1087000 # number of ReadExReq miss cycles 364system.l2c.ReadExReq_miss_latency::cpu3.data 957750 # number of ReadExReq miss cycles 365system.l2c.ReadExReq_miss_latency::total 9622000 # number of ReadExReq miss cycles 366system.l2c.demand_miss_latency::cpu0.inst 24802000 # number of demand (read+write) miss cycles 367system.l2c.demand_miss_latency::cpu0.data 12337000 # number of demand (read+write) miss cycles 368system.l2c.demand_miss_latency::cpu1.inst 1162500 # number of demand (read+write) miss cycles 369system.l2c.demand_miss_latency::cpu1.data 926750 # number of demand (read+write) miss cycles 370system.l2c.demand_miss_latency::cpu2.inst 5361500 # number of demand (read+write) miss cycles 371system.l2c.demand_miss_latency::cpu2.data 1582250 # number of demand (read+write) miss cycles 372system.l2c.demand_miss_latency::cpu3.inst 583750 # number of demand (read+write) miss cycles 373system.l2c.demand_miss_latency::cpu3.data 1032250 # number of demand (read+write) miss cycles 374system.l2c.demand_miss_latency::total 47788000 # number of demand (read+write) miss cycles 375system.l2c.overall_miss_latency::cpu0.inst 24802000 # number of overall miss cycles 376system.l2c.overall_miss_latency::cpu0.data 12337000 # number of overall miss cycles 377system.l2c.overall_miss_latency::cpu1.inst 1162500 # number of overall miss cycles 378system.l2c.overall_miss_latency::cpu1.data 926750 # number of overall miss cycles 379system.l2c.overall_miss_latency::cpu2.inst 5361500 # number of overall miss cycles 380system.l2c.overall_miss_latency::cpu2.data 1582250 # number of overall miss cycles 381system.l2c.overall_miss_latency::cpu3.inst 583750 # number of overall miss cycles 382system.l2c.overall_miss_latency::cpu3.data 1032250 # number of overall miss cycles 383system.l2c.overall_miss_latency::total 47788000 # number of overall miss cycles 384system.l2c.ReadReq_accesses::cpu0.inst 588 # number of ReadReq accesses(hits+misses) 385system.l2c.ReadReq_accesses::cpu0.data 79 # number of ReadReq accesses(hits+misses) 386system.l2c.ReadReq_accesses::cpu1.inst 428 # number of ReadReq accesses(hits+misses) 387system.l2c.ReadReq_accesses::cpu1.data 12 # number of ReadReq accesses(hits+misses) 388system.l2c.ReadReq_accesses::cpu2.inst 425 # number of ReadReq accesses(hits+misses) 389system.l2c.ReadReq_accesses::cpu2.data 12 # number of ReadReq accesses(hits+misses) 390system.l2c.ReadReq_accesses::cpu3.inst 429 # number of ReadReq accesses(hits+misses) 391system.l2c.ReadReq_accesses::cpu3.data 12 # number of ReadReq accesses(hits+misses) 392system.l2c.ReadReq_accesses::total 1985 # number of ReadReq accesses(hits+misses) 393system.l2c.Writeback_accesses::writebacks 1 # number of Writeback accesses(hits+misses) 394system.l2c.Writeback_accesses::total 1 # number of Writeback accesses(hits+misses) 395system.l2c.UpgradeReq_accesses::cpu0.data 24 # number of UpgradeReq accesses(hits+misses) 396system.l2c.UpgradeReq_accesses::cpu1.data 20 # number of UpgradeReq accesses(hits+misses) 397system.l2c.UpgradeReq_accesses::cpu2.data 17 # number of UpgradeReq accesses(hits+misses) 398system.l2c.UpgradeReq_accesses::cpu3.data 18 # number of UpgradeReq accesses(hits+misses) 399system.l2c.UpgradeReq_accesses::total 79 # number of UpgradeReq accesses(hits+misses) 400system.l2c.ReadExReq_accesses::cpu0.data 94 # number of ReadExReq accesses(hits+misses) 401system.l2c.ReadExReq_accesses::cpu1.data 12 # number of ReadExReq accesses(hits+misses) 402system.l2c.ReadExReq_accesses::cpu2.data 13 # number of ReadExReq accesses(hits+misses) 403system.l2c.ReadExReq_accesses::cpu3.data 12 # number of ReadExReq accesses(hits+misses) 404system.l2c.ReadExReq_accesses::total 131 # number of ReadExReq accesses(hits+misses) 405system.l2c.demand_accesses::cpu0.inst 588 # number of demand (read+write) accesses 406system.l2c.demand_accesses::cpu0.data 173 # number of demand (read+write) accesses 407system.l2c.demand_accesses::cpu1.inst 428 # number of demand (read+write) accesses 408system.l2c.demand_accesses::cpu1.data 24 # number of demand (read+write) accesses 409system.l2c.demand_accesses::cpu2.inst 425 # number of demand (read+write) accesses 410system.l2c.demand_accesses::cpu2.data 25 # number of demand (read+write) accesses 411system.l2c.demand_accesses::cpu3.inst 429 # number of demand (read+write) accesses 412system.l2c.demand_accesses::cpu3.data 24 # number of demand (read+write) accesses 413system.l2c.demand_accesses::total 2116 # number of demand (read+write) accesses 414system.l2c.overall_accesses::cpu0.inst 588 # number of overall (read+write) accesses 415system.l2c.overall_accesses::cpu0.data 173 # number of overall (read+write) accesses 416system.l2c.overall_accesses::cpu1.inst 428 # number of overall (read+write) accesses 417system.l2c.overall_accesses::cpu1.data 24 # number of overall (read+write) accesses 418system.l2c.overall_accesses::cpu2.inst 425 # number of overall (read+write) accesses 419system.l2c.overall_accesses::cpu2.data 25 # number of overall (read+write) accesses 420system.l2c.overall_accesses::cpu3.inst 429 # number of overall (read+write) accesses 421system.l2c.overall_accesses::cpu3.data 24 # number of overall (read+write) accesses 422system.l2c.overall_accesses::total 2116 # number of overall (read+write) accesses 423system.l2c.ReadReq_miss_rate::cpu0.inst 0.610544 # miss rate for ReadReq accesses 424system.l2c.ReadReq_miss_rate::cpu0.data 0.936709 # miss rate for ReadReq accesses 425system.l2c.ReadReq_miss_rate::cpu1.inst 0.037383 # miss rate for ReadReq accesses 426system.l2c.ReadReq_miss_rate::cpu1.data 0.083333 # miss rate for ReadReq accesses 427system.l2c.ReadReq_miss_rate::cpu2.inst 0.178824 # miss rate for ReadReq accesses 428system.l2c.ReadReq_miss_rate::cpu2.data 0.583333 # miss rate for ReadReq accesses 429system.l2c.ReadReq_miss_rate::cpu3.inst 0.020979 # miss rate for ReadReq accesses 430system.l2c.ReadReq_miss_rate::cpu3.data 0.083333 # miss rate for ReadReq accesses 431system.l2c.ReadReq_miss_rate::total 0.273552 # miss rate for ReadReq accesses 432system.l2c.UpgradeReq_miss_rate::cpu0.data 0.875000 # miss rate for UpgradeReq accesses 433system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses 434system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses 435system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses 436system.l2c.UpgradeReq_miss_rate::total 0.962025 # miss rate for UpgradeReq accesses 437system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses 438system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses 439system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses 440system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses 441system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 442system.l2c.demand_miss_rate::cpu0.inst 0.610544 # miss rate for demand accesses 443system.l2c.demand_miss_rate::cpu0.data 0.971098 # miss rate for demand accesses 444system.l2c.demand_miss_rate::cpu1.inst 0.037383 # miss rate for demand accesses 445system.l2c.demand_miss_rate::cpu1.data 0.541667 # miss rate for demand accesses 446system.l2c.demand_miss_rate::cpu2.inst 0.178824 # miss rate for demand accesses 447system.l2c.demand_miss_rate::cpu2.data 0.800000 # miss rate for demand accesses 448system.l2c.demand_miss_rate::cpu3.inst 0.020979 # miss rate for demand accesses 449system.l2c.demand_miss_rate::cpu3.data 0.541667 # miss rate for demand accesses 450system.l2c.demand_miss_rate::total 0.318526 # miss rate for demand accesses 451system.l2c.overall_miss_rate::cpu0.inst 0.610544 # miss rate for overall accesses 452system.l2c.overall_miss_rate::cpu0.data 0.971098 # miss rate for overall accesses 453system.l2c.overall_miss_rate::cpu1.inst 0.037383 # miss rate for overall accesses 454system.l2c.overall_miss_rate::cpu1.data 0.541667 # miss rate for overall accesses 455system.l2c.overall_miss_rate::cpu2.inst 0.178824 # miss rate for overall accesses 456system.l2c.overall_miss_rate::cpu2.data 0.800000 # miss rate for overall accesses 457system.l2c.overall_miss_rate::cpu3.inst 0.020979 # miss rate for overall accesses 458system.l2c.overall_miss_rate::cpu3.data 0.541667 # miss rate for overall accesses 459system.l2c.overall_miss_rate::total 0.318526 # miss rate for overall accesses 460system.l2c.ReadReq_avg_miss_latency::cpu0.inst 69086.350975 # average ReadReq miss latency 461system.l2c.ReadReq_avg_miss_latency::cpu0.data 75837.837838 # average ReadReq miss latency 462system.l2c.ReadReq_avg_miss_latency::cpu1.inst 72656.250000 # average ReadReq miss latency 463system.l2c.ReadReq_avg_miss_latency::cpu1.data 74500 # average ReadReq miss latency 464system.l2c.ReadReq_avg_miss_latency::cpu2.inst 70546.052632 # average ReadReq miss latency 465system.l2c.ReadReq_avg_miss_latency::cpu2.data 70750 # average ReadReq miss latency 466system.l2c.ReadReq_avg_miss_latency::cpu3.inst 64861.111111 # average ReadReq miss latency 467system.l2c.ReadReq_avg_miss_latency::cpu3.data 74500 # average ReadReq miss latency 468system.l2c.ReadReq_avg_miss_latency::total 70287.292818 # average ReadReq miss latency 469system.l2c.ReadExReq_avg_miss_latency::cpu0.data 71542.553191 # average ReadExReq miss latency 470system.l2c.ReadExReq_avg_miss_latency::cpu1.data 71020.833333 # average ReadExReq miss latency 471system.l2c.ReadExReq_avg_miss_latency::cpu2.data 83615.384615 # average ReadExReq miss latency 472system.l2c.ReadExReq_avg_miss_latency::cpu3.data 79812.500000 # average ReadExReq miss latency 473system.l2c.ReadExReq_avg_miss_latency::total 73450.381679 # average ReadExReq miss latency 474system.l2c.demand_avg_miss_latency::cpu0.inst 69086.350975 # average overall miss latency 475system.l2c.demand_avg_miss_latency::cpu0.data 73434.523810 # average overall miss latency 476system.l2c.demand_avg_miss_latency::cpu1.inst 72656.250000 # average overall miss latency 477system.l2c.demand_avg_miss_latency::cpu1.data 71288.461538 # average overall miss latency 478system.l2c.demand_avg_miss_latency::cpu2.inst 70546.052632 # average overall miss latency 479system.l2c.demand_avg_miss_latency::cpu2.data 79112.500000 # average overall miss latency 480system.l2c.demand_avg_miss_latency::cpu3.inst 64861.111111 # average overall miss latency 481system.l2c.demand_avg_miss_latency::cpu3.data 79403.846154 # average overall miss latency 482system.l2c.demand_avg_miss_latency::total 70902.077151 # average overall miss latency 483system.l2c.overall_avg_miss_latency::cpu0.inst 69086.350975 # average overall miss latency 484system.l2c.overall_avg_miss_latency::cpu0.data 73434.523810 # average overall miss latency 485system.l2c.overall_avg_miss_latency::cpu1.inst 72656.250000 # average overall miss latency 486system.l2c.overall_avg_miss_latency::cpu1.data 71288.461538 # average overall miss latency 487system.l2c.overall_avg_miss_latency::cpu2.inst 70546.052632 # average overall miss latency 488system.l2c.overall_avg_miss_latency::cpu2.data 79112.500000 # average overall miss latency 489system.l2c.overall_avg_miss_latency::cpu3.inst 64861.111111 # average overall miss latency 490system.l2c.overall_avg_miss_latency::cpu3.data 79403.846154 # average overall miss latency 491system.l2c.overall_avg_miss_latency::total 70902.077151 # average overall miss latency 492system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 493system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 494system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 495system.l2c.blocked::no_targets 0 # number of cycles access was blocked 496system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 497system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 498system.l2c.fast_writes 0 # number of fast writes performed 499system.l2c.cache_copies 0 # number of cache copies performed 500system.l2c.ReadReq_mshr_hits::cpu0.inst 2 # number of ReadReq MSHR hits 501system.l2c.ReadReq_mshr_hits::cpu1.inst 6 # number of ReadReq MSHR hits 502system.l2c.ReadReq_mshr_hits::cpu2.inst 3 # number of ReadReq MSHR hits 503system.l2c.ReadReq_mshr_hits::cpu3.inst 3 # number of ReadReq MSHR hits 504system.l2c.ReadReq_mshr_hits::total 14 # number of ReadReq MSHR hits 505system.l2c.demand_mshr_hits::cpu0.inst 2 # number of demand (read+write) MSHR hits 506system.l2c.demand_mshr_hits::cpu1.inst 6 # number of demand (read+write) MSHR hits 507system.l2c.demand_mshr_hits::cpu2.inst 3 # number of demand (read+write) MSHR hits 508system.l2c.demand_mshr_hits::cpu3.inst 3 # number of demand (read+write) MSHR hits 509system.l2c.demand_mshr_hits::total 14 # number of demand (read+write) MSHR hits 510system.l2c.overall_mshr_hits::cpu0.inst 2 # number of overall MSHR hits 511system.l2c.overall_mshr_hits::cpu1.inst 6 # number of overall MSHR hits 512system.l2c.overall_mshr_hits::cpu2.inst 3 # number of overall MSHR hits 513system.l2c.overall_mshr_hits::cpu3.inst 3 # number of overall MSHR hits 514system.l2c.overall_mshr_hits::total 14 # number of overall MSHR hits 515system.l2c.ReadReq_mshr_misses::cpu0.inst 357 # number of ReadReq MSHR misses 516system.l2c.ReadReq_mshr_misses::cpu0.data 74 # number of ReadReq MSHR misses 517system.l2c.ReadReq_mshr_misses::cpu1.inst 10 # number of ReadReq MSHR misses 518system.l2c.ReadReq_mshr_misses::cpu1.data 1 # number of ReadReq MSHR misses 519system.l2c.ReadReq_mshr_misses::cpu2.inst 73 # number of ReadReq MSHR misses 520system.l2c.ReadReq_mshr_misses::cpu2.data 7 # number of ReadReq MSHR misses 521system.l2c.ReadReq_mshr_misses::cpu3.inst 6 # number of ReadReq MSHR misses 522system.l2c.ReadReq_mshr_misses::cpu3.data 1 # number of ReadReq MSHR misses 523system.l2c.ReadReq_mshr_misses::total 529 # number of ReadReq MSHR misses 524system.l2c.UpgradeReq_mshr_misses::cpu0.data 21 # number of UpgradeReq MSHR misses 525system.l2c.UpgradeReq_mshr_misses::cpu1.data 20 # number of UpgradeReq MSHR misses 526system.l2c.UpgradeReq_mshr_misses::cpu2.data 17 # number of UpgradeReq MSHR misses 527system.l2c.UpgradeReq_mshr_misses::cpu3.data 18 # number of UpgradeReq MSHR misses 528system.l2c.UpgradeReq_mshr_misses::total 76 # number of UpgradeReq MSHR misses 529system.l2c.ReadExReq_mshr_misses::cpu0.data 94 # number of ReadExReq MSHR misses 530system.l2c.ReadExReq_mshr_misses::cpu1.data 12 # number of ReadExReq MSHR misses 531system.l2c.ReadExReq_mshr_misses::cpu2.data 13 # number of ReadExReq MSHR misses 532system.l2c.ReadExReq_mshr_misses::cpu3.data 12 # number of ReadExReq MSHR misses 533system.l2c.ReadExReq_mshr_misses::total 131 # number of ReadExReq MSHR misses 534system.l2c.demand_mshr_misses::cpu0.inst 357 # number of demand (read+write) MSHR misses 535system.l2c.demand_mshr_misses::cpu0.data 168 # number of demand (read+write) MSHR misses 536system.l2c.demand_mshr_misses::cpu1.inst 10 # number of demand (read+write) MSHR misses 537system.l2c.demand_mshr_misses::cpu1.data 13 # number of demand (read+write) MSHR misses 538system.l2c.demand_mshr_misses::cpu2.inst 73 # number of demand (read+write) MSHR misses 539system.l2c.demand_mshr_misses::cpu2.data 20 # number of demand (read+write) MSHR misses 540system.l2c.demand_mshr_misses::cpu3.inst 6 # number of demand (read+write) MSHR misses 541system.l2c.demand_mshr_misses::cpu3.data 13 # number of demand (read+write) MSHR misses 542system.l2c.demand_mshr_misses::total 660 # number of demand (read+write) MSHR misses 543system.l2c.overall_mshr_misses::cpu0.inst 357 # number of overall MSHR misses 544system.l2c.overall_mshr_misses::cpu0.data 168 # number of overall MSHR misses 545system.l2c.overall_mshr_misses::cpu1.inst 10 # number of overall MSHR misses 546system.l2c.overall_mshr_misses::cpu1.data 13 # number of overall MSHR misses 547system.l2c.overall_mshr_misses::cpu2.inst 73 # number of overall MSHR misses 548system.l2c.overall_mshr_misses::cpu2.data 20 # number of overall MSHR misses 549system.l2c.overall_mshr_misses::cpu3.inst 6 # number of overall MSHR misses 550system.l2c.overall_mshr_misses::cpu3.data 13 # number of overall MSHR misses 551system.l2c.overall_mshr_misses::total 660 # number of overall MSHR misses 552system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 20238250 # number of ReadReq MSHR miss cycles 553system.l2c.ReadReq_mshr_miss_latency::cpu0.data 4701500 # number of ReadReq MSHR miss cycles 554system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 676500 # number of ReadReq MSHR miss cycles 555system.l2c.ReadReq_mshr_miss_latency::cpu1.data 62500 # number of ReadReq MSHR miss cycles 556system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 4287250 # number of ReadReq MSHR miss cycles 557system.l2c.ReadReq_mshr_miss_latency::cpu2.data 408750 # number of ReadReq MSHR miss cycles 558system.l2c.ReadReq_mshr_miss_latency::cpu3.inst 369250 # number of ReadReq MSHR miss cycles 559system.l2c.ReadReq_mshr_miss_latency::cpu3.data 62500 # number of ReadReq MSHR miss cycles 560system.l2c.ReadReq_mshr_miss_latency::total 30806500 # number of ReadReq MSHR miss cycles 561system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 210021 # number of UpgradeReq MSHR miss cycles 562system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 217519 # number of UpgradeReq MSHR miss cycles 563system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 170017 # number of UpgradeReq MSHR miss cycles 564system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 180018 # number of UpgradeReq MSHR miss cycles 565system.l2c.UpgradeReq_mshr_miss_latency::total 777575 # number of UpgradeReq MSHR miss cycles 566system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 5552000 # number of ReadExReq MSHR miss cycles 567system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 701750 # number of ReadExReq MSHR miss cycles 568system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 928000 # number of ReadExReq MSHR miss cycles 569system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 807250 # number of ReadExReq MSHR miss cycles 570system.l2c.ReadExReq_mshr_miss_latency::total 7989000 # number of ReadExReq MSHR miss cycles 571system.l2c.demand_mshr_miss_latency::cpu0.inst 20238250 # number of demand (read+write) MSHR miss cycles 572system.l2c.demand_mshr_miss_latency::cpu0.data 10253500 # number of demand (read+write) MSHR miss cycles 573system.l2c.demand_mshr_miss_latency::cpu1.inst 676500 # number of demand (read+write) MSHR miss cycles 574system.l2c.demand_mshr_miss_latency::cpu1.data 764250 # number of demand (read+write) MSHR miss cycles 575system.l2c.demand_mshr_miss_latency::cpu2.inst 4287250 # number of demand (read+write) MSHR miss cycles 576system.l2c.demand_mshr_miss_latency::cpu2.data 1336750 # number of demand (read+write) MSHR miss cycles 577system.l2c.demand_mshr_miss_latency::cpu3.inst 369250 # number of demand (read+write) MSHR miss cycles 578system.l2c.demand_mshr_miss_latency::cpu3.data 869750 # number of demand (read+write) MSHR miss cycles 579system.l2c.demand_mshr_miss_latency::total 38795500 # number of demand (read+write) MSHR miss cycles 580system.l2c.overall_mshr_miss_latency::cpu0.inst 20238250 # number of overall MSHR miss cycles 581system.l2c.overall_mshr_miss_latency::cpu0.data 10253500 # number of overall MSHR miss cycles 582system.l2c.overall_mshr_miss_latency::cpu1.inst 676500 # number of overall MSHR miss cycles 583system.l2c.overall_mshr_miss_latency::cpu1.data 764250 # number of overall MSHR miss cycles 584system.l2c.overall_mshr_miss_latency::cpu2.inst 4287250 # number of overall MSHR miss cycles 585system.l2c.overall_mshr_miss_latency::cpu2.data 1336750 # number of overall MSHR miss cycles 586system.l2c.overall_mshr_miss_latency::cpu3.inst 369250 # number of overall MSHR miss cycles 587system.l2c.overall_mshr_miss_latency::cpu3.data 869750 # number of overall MSHR miss cycles 588system.l2c.overall_mshr_miss_latency::total 38795500 # number of overall MSHR miss cycles 589system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.607143 # mshr miss rate for ReadReq accesses 590system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.936709 # mshr miss rate for ReadReq accesses 591system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.023364 # mshr miss rate for ReadReq accesses 592system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.083333 # mshr miss rate for ReadReq accesses 593system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.171765 # mshr miss rate for ReadReq accesses 594system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.583333 # mshr miss rate for ReadReq accesses 595system.l2c.ReadReq_mshr_miss_rate::cpu3.inst 0.013986 # mshr miss rate for ReadReq accesses 596system.l2c.ReadReq_mshr_miss_rate::cpu3.data 0.083333 # mshr miss rate for ReadReq accesses 597system.l2c.ReadReq_mshr_miss_rate::total 0.266499 # mshr miss rate for ReadReq accesses 598system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.875000 # mshr miss rate for UpgradeReq accesses 599system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses 600system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for UpgradeReq accesses 601system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for UpgradeReq accesses 602system.l2c.UpgradeReq_mshr_miss_rate::total 0.962025 # mshr miss rate for UpgradeReq accesses 603system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses 604system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses 605system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses 606system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for ReadExReq accesses 607system.l2c.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 608system.l2c.demand_mshr_miss_rate::cpu0.inst 0.607143 # mshr miss rate for demand accesses 609system.l2c.demand_mshr_miss_rate::cpu0.data 0.971098 # mshr miss rate for demand accesses 610system.l2c.demand_mshr_miss_rate::cpu1.inst 0.023364 # mshr miss rate for demand accesses 611system.l2c.demand_mshr_miss_rate::cpu1.data 0.541667 # mshr miss rate for demand accesses 612system.l2c.demand_mshr_miss_rate::cpu2.inst 0.171765 # mshr miss rate for demand accesses 613system.l2c.demand_mshr_miss_rate::cpu2.data 0.800000 # mshr miss rate for demand accesses 614system.l2c.demand_mshr_miss_rate::cpu3.inst 0.013986 # mshr miss rate for demand accesses 615system.l2c.demand_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for demand accesses 616system.l2c.demand_mshr_miss_rate::total 0.311909 # mshr miss rate for demand accesses 617system.l2c.overall_mshr_miss_rate::cpu0.inst 0.607143 # mshr miss rate for overall accesses 618system.l2c.overall_mshr_miss_rate::cpu0.data 0.971098 # mshr miss rate for overall accesses 619system.l2c.overall_mshr_miss_rate::cpu1.inst 0.023364 # mshr miss rate for overall accesses 620system.l2c.overall_mshr_miss_rate::cpu1.data 0.541667 # mshr miss rate for overall accesses 621system.l2c.overall_mshr_miss_rate::cpu2.inst 0.171765 # mshr miss rate for overall accesses 622system.l2c.overall_mshr_miss_rate::cpu2.data 0.800000 # mshr miss rate for overall accesses 623system.l2c.overall_mshr_miss_rate::cpu3.inst 0.013986 # mshr miss rate for overall accesses 624system.l2c.overall_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for overall accesses 625system.l2c.overall_mshr_miss_rate::total 0.311909 # mshr miss rate for overall accesses 626system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 56689.775910 # average ReadReq mshr miss latency 627system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 63533.783784 # average ReadReq mshr miss latency 628system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 67650 # average ReadReq mshr miss latency 629system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 62500 # average ReadReq mshr miss latency 630system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 58729.452055 # average ReadReq mshr miss latency 631system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 58392.857143 # average ReadReq mshr miss latency 632system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 61541.666667 # average ReadReq mshr miss latency 633system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 62500 # average ReadReq mshr miss latency 634system.l2c.ReadReq_avg_mshr_miss_latency::total 58235.349716 # average ReadReq mshr miss latency 635system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average UpgradeReq mshr miss latency 636system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10875.950000 # average UpgradeReq mshr miss latency 637system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10001 # average UpgradeReq mshr miss latency 638system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 10001 # average UpgradeReq mshr miss latency 639system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10231.250000 # average UpgradeReq mshr miss latency 640system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 59063.829787 # average ReadExReq mshr miss latency 641system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 58479.166667 # average ReadExReq mshr miss latency 642system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 71384.615385 # average ReadExReq mshr miss latency 643system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 67270.833333 # average ReadExReq mshr miss latency 644system.l2c.ReadExReq_avg_mshr_miss_latency::total 60984.732824 # average ReadExReq mshr miss latency 645system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 56689.775910 # average overall mshr miss latency 646system.l2c.demand_avg_mshr_miss_latency::cpu0.data 61032.738095 # average overall mshr miss latency 647system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 67650 # average overall mshr miss latency 648system.l2c.demand_avg_mshr_miss_latency::cpu1.data 58788.461538 # average overall mshr miss latency 649system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 58729.452055 # average overall mshr miss latency 650system.l2c.demand_avg_mshr_miss_latency::cpu2.data 66837.500000 # average overall mshr miss latency 651system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 61541.666667 # average overall mshr miss latency 652system.l2c.demand_avg_mshr_miss_latency::cpu3.data 66903.846154 # average overall mshr miss latency 653system.l2c.demand_avg_mshr_miss_latency::total 58781.060606 # average overall mshr miss latency 654system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 56689.775910 # average overall mshr miss latency 655system.l2c.overall_avg_mshr_miss_latency::cpu0.data 61032.738095 # average overall mshr miss latency 656system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 67650 # average overall mshr miss latency 657system.l2c.overall_avg_mshr_miss_latency::cpu1.data 58788.461538 # average overall mshr miss latency 658system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 58729.452055 # average overall mshr miss latency 659system.l2c.overall_avg_mshr_miss_latency::cpu2.data 66837.500000 # average overall mshr miss latency 660system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 61541.666667 # average overall mshr miss latency 661system.l2c.overall_avg_mshr_miss_latency::cpu3.data 66903.846154 # average overall mshr miss latency 662system.l2c.overall_avg_mshr_miss_latency::total 58781.060606 # average overall mshr miss latency 663system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 664system.toL2Bus.throughput 1689557804 # Throughput (bytes/s) 665system.toL2Bus.trans_dist::ReadReq 2542 # Transaction distribution 666system.toL2Bus.trans_dist::ReadResp 2541 # Transaction distribution 667system.toL2Bus.trans_dist::Writeback 1 # Transaction distribution 668system.toL2Bus.trans_dist::UpgradeReq 292 # Transaction distribution 669system.toL2Bus.trans_dist::UpgradeResp 292 # Transaction distribution 670system.toL2Bus.trans_dist::ReadExReq 389 # Transaction distribution 671system.toL2Bus.trans_dist::ReadExResp 389 # Transaction distribution 672system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1175 # Packet count per connected master and slave (bytes) 673system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 591 # Packet count per connected master and slave (bytes) 674system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 856 # Packet count per connected master and slave (bytes) 675system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 373 # Packet count per connected master and slave (bytes) 676system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 850 # Packet count per connected master and slave (bytes) 677system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 367 # Packet count per connected master and slave (bytes) 678system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 858 # Packet count per connected master and slave (bytes) 679system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 348 # Packet count per connected master and slave (bytes) 680system.toL2Bus.pkt_count::total 5418 # Packet count per connected master and slave (bytes) 681system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 37568 # Cumulative packet size per connected master and slave (bytes) 682system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 11136 # Cumulative packet size per connected master and slave (bytes) 683system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 27392 # Cumulative packet size per connected master and slave (bytes) 684system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1536 # Cumulative packet size per connected master and slave (bytes) 685system.toL2Bus.tot_pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 27200 # Cumulative packet size per connected master and slave (bytes) 686system.toL2Bus.tot_pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes) 687system.toL2Bus.tot_pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 27456 # Cumulative packet size per connected master and slave (bytes) 688system.toL2Bus.tot_pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 1536 # Cumulative packet size per connected master and slave (bytes) 689system.toL2Bus.tot_pkt_size::total 135424 # Cumulative packet size per connected master and slave (bytes) 690system.toL2Bus.data_through_bus 135424 # Total data (bytes) 691system.toL2Bus.snoop_data_through_bus 52160 # Total snoop data (bytes) 692system.toL2Bus.reqLayer0.occupancy 1628974 # Layer occupancy (ticks) 693system.toL2Bus.reqLayer0.utilization 1.5 # Layer utilization (%) 694system.toL2Bus.respLayer0.occupancy 2704748 # Layer occupancy (ticks) 695system.toL2Bus.respLayer0.utilization 2.4 # Layer utilization (%) 696system.toL2Bus.respLayer1.occupancy 1475514 # Layer occupancy (ticks) 697system.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) 698system.toL2Bus.respLayer2.occupancy 1928994 # Layer occupancy (ticks) 699system.toL2Bus.respLayer2.utilization 1.7 # Layer utilization (%) 700system.toL2Bus.respLayer3.occupancy 1199245 # Layer occupancy (ticks) 701system.toL2Bus.respLayer3.utilization 1.1 # Layer utilization (%) 702system.toL2Bus.respLayer4.occupancy 1926995 # Layer occupancy (ticks) 703system.toL2Bus.respLayer4.utilization 1.7 # Layer utilization (%) 704system.toL2Bus.respLayer5.occupancy 1183748 # Layer occupancy (ticks) 705system.toL2Bus.respLayer5.utilization 1.1 # Layer utilization (%) 706system.toL2Bus.respLayer6.occupancy 1932245 # Layer occupancy (ticks) 707system.toL2Bus.respLayer6.utilization 1.7 # Layer utilization (%) 708system.toL2Bus.respLayer7.occupancy 1115744 # Layer occupancy (ticks) 709system.toL2Bus.respLayer7.utilization 1.0 # Layer utilization (%) 710system.cpu0.branchPred.lookups 83087 # Number of BP lookups 711system.cpu0.branchPred.condPredicted 80860 # Number of conditional branches predicted 712system.cpu0.branchPred.condIncorrect 1219 # Number of conditional branches incorrect 713system.cpu0.branchPred.BTBLookups 80377 # Number of BTB lookups 714system.cpu0.branchPred.BTBHits 78332 # Number of BTB hits 715system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 716system.cpu0.branchPred.BTBHitPct 97.455740 # BTB Hit Percentage 717system.cpu0.branchPred.usedRAS 512 # Number of times the RAS was used to get a target. 718system.cpu0.branchPred.RASInCorrect 132 # Number of incorrect RAS predictions. 719system.cpu0.workload.num_syscalls 89 # Number of system calls 720system.cpu0.numCycles 222052 # number of cpu cycles simulated 721system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 722system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 723system.cpu0.fetch.icacheStallCycles 17259 # Number of cycles fetch is stalled on an Icache miss 724system.cpu0.fetch.Insts 493192 # Number of instructions fetch has processed 725system.cpu0.fetch.Branches 83087 # Number of branches that fetch encountered 726system.cpu0.fetch.predictedBranches 78844 # Number of branches that fetch has predicted taken 727system.cpu0.fetch.Cycles 161829 # Number of cycles fetch has run and was not squashing or blocked 728system.cpu0.fetch.SquashCycles 3807 # Number of cycles fetch has spent squashing 729system.cpu0.fetch.BlockedCycles 13993 # Number of cycles fetch has spent blocked 730system.cpu0.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 731system.cpu0.fetch.PendingTrapStallCycles 1512 # Number of stall cycles due to pending traps 732system.cpu0.fetch.CacheLines 5869 # Number of cache lines fetched 733system.cpu0.fetch.IcacheSquashes 488 # Number of outstanding Icache misses that were squashed 734system.cpu0.fetch.rateDist::samples 197038 # Number of instructions fetched each cycle (Total) 735system.cpu0.fetch.rateDist::mean 2.503030 # Number of instructions fetched each cycle (Total) 736system.cpu0.fetch.rateDist::stdev 2.216871 # Number of instructions fetched each cycle (Total) 737system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 738system.cpu0.fetch.rateDist::0 35209 17.87% 17.87% # Number of instructions fetched each cycle (Total) 739system.cpu0.fetch.rateDist::1 80150 40.68% 58.55% # Number of instructions fetched each cycle (Total) 740system.cpu0.fetch.rateDist::2 582 0.30% 58.84% # Number of instructions fetched each cycle (Total) 741system.cpu0.fetch.rateDist::3 988 0.50% 59.34% # Number of instructions fetched each cycle (Total) 742system.cpu0.fetch.rateDist::4 452 0.23% 59.57% # Number of instructions fetched each cycle (Total) 743system.cpu0.fetch.rateDist::5 76210 38.68% 98.25% # Number of instructions fetched each cycle (Total) 744system.cpu0.fetch.rateDist::6 578 0.29% 98.54% # Number of instructions fetched each cycle (Total) 745system.cpu0.fetch.rateDist::7 364 0.18% 98.73% # Number of instructions fetched each cycle (Total) 746system.cpu0.fetch.rateDist::8 2505 1.27% 100.00% # Number of instructions fetched each cycle (Total) 747system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 748system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 749system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 750system.cpu0.fetch.rateDist::total 197038 # Number of instructions fetched each cycle (Total) 751system.cpu0.fetch.branchRate 0.374178 # Number of branch fetches per cycle 752system.cpu0.fetch.rate 2.221065 # Number of inst fetches per cycle 753system.cpu0.decode.IdleCycles 17851 # Number of cycles decode is idle 754system.cpu0.decode.BlockedCycles 15597 # Number of cycles decode is blocked 755system.cpu0.decode.RunCycles 160862 # Number of cycles decode is running 756system.cpu0.decode.UnblockCycles 288 # Number of cycles decode is unblocking 757system.cpu0.decode.SquashCycles 2440 # Number of cycles decode is squashing 758system.cpu0.decode.DecodedInsts 490280 # Number of instructions handled by decode 759system.cpu0.rename.SquashCycles 2440 # Number of cycles rename is squashing 760system.cpu0.rename.IdleCycles 18507 # Number of cycles rename is idle 761system.cpu0.rename.BlockCycles 827 # Number of cycles rename is blocking 762system.cpu0.rename.serializeStallCycles 14176 # count of cycles rename stalled for serializing inst 763system.cpu0.rename.RunCycles 160527 # Number of cycles rename is running 764system.cpu0.rename.UnblockCycles 561 # Number of cycles rename is unblocking 765system.cpu0.rename.RenamedInsts 487444 # Number of instructions processed by rename 766system.cpu0.rename.IQFullEvents 4 # Number of times rename has blocked due to IQ full 767system.cpu0.rename.LSQFullEvents 187 # Number of times rename has blocked due to LSQ full 768system.cpu0.rename.RenamedOperands 333388 # Number of destination operands rename has renamed 769system.cpu0.rename.RenameLookups 972038 # Number of register rename lookups that rename has made 770system.cpu0.rename.int_rename_lookups 734246 # Number of integer rename lookups 771system.cpu0.rename.CommittedMaps 320411 # Number of HB maps that are committed 772system.cpu0.rename.UndoneMaps 12977 # Number of HB maps that are undone due to squashing 773system.cpu0.rename.serializingInsts 872 # count of serializing insts renamed 774system.cpu0.rename.tempSerializingInsts 895 # count of temporary serializing insts renamed 775system.cpu0.rename.skidInsts 3641 # count of insts added to the skid buffer 776system.cpu0.memDep0.insertedLoads 155927 # Number of loads inserted to the mem dependence unit. 777system.cpu0.memDep0.insertedStores 78789 # Number of stores inserted to the mem dependence unit. 778system.cpu0.memDep0.conflictingLoads 76026 # Number of conflicting loads. 779system.cpu0.memDep0.conflictingStores 75860 # Number of conflicting stores. 780system.cpu0.iq.iqInstsAdded 407640 # Number of instructions added to the IQ (excludes non-spec) 781system.cpu0.iq.iqNonSpecInstsAdded 922 # Number of non-speculative instructions added to the IQ 782system.cpu0.iq.iqInstsIssued 405044 # Number of instructions issued 783system.cpu0.iq.iqSquashedInstsIssued 133 # Number of squashed instructions issued 784system.cpu0.iq.iqSquashedInstsExamined 10720 # Number of squashed instructions iterated over during squash; mainly for profiling 785system.cpu0.iq.iqSquashedOperandsExamined 9396 # Number of squashed operands that are examined and possibly removed from graph 786system.cpu0.iq.iqSquashedNonSpecRemoved 363 # Number of squashed non-spec instructions that were removed 787system.cpu0.iq.issued_per_cycle::samples 197038 # Number of insts issued each cycle 788system.cpu0.iq.issued_per_cycle::mean 2.055664 # Number of insts issued each cycle 789system.cpu0.iq.issued_per_cycle::stdev 1.097184 # Number of insts issued each cycle 790system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 791system.cpu0.iq.issued_per_cycle::0 34076 17.29% 17.29% # Number of insts issued each cycle 792system.cpu0.iq.issued_per_cycle::1 4941 2.51% 19.80% # Number of insts issued each cycle 793system.cpu0.iq.issued_per_cycle::2 78065 39.62% 59.42% # Number of insts issued each cycle 794system.cpu0.iq.issued_per_cycle::3 77371 39.27% 98.69% # Number of insts issued each cycle 795system.cpu0.iq.issued_per_cycle::4 1552 0.79% 99.48% # Number of insts issued each cycle 796system.cpu0.iq.issued_per_cycle::5 667 0.34% 99.81% # Number of insts issued each cycle 797system.cpu0.iq.issued_per_cycle::6 262 0.13% 99.95% # Number of insts issued each cycle 798system.cpu0.iq.issued_per_cycle::7 87 0.04% 99.99% # Number of insts issued each cycle 799system.cpu0.iq.issued_per_cycle::8 17 0.01% 100.00% # Number of insts issued each cycle 800system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 801system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 802system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 803system.cpu0.iq.issued_per_cycle::total 197038 # Number of insts issued each cycle 804system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 805system.cpu0.iq.fu_full::IntAlu 57 27.01% 27.01% # attempts to use FU when none available 806system.cpu0.iq.fu_full::IntMult 0 0.00% 27.01% # attempts to use FU when none available 807system.cpu0.iq.fu_full::IntDiv 0 0.00% 27.01% # attempts to use FU when none available 808system.cpu0.iq.fu_full::FloatAdd 0 0.00% 27.01% # attempts to use FU when none available 809system.cpu0.iq.fu_full::FloatCmp 0 0.00% 27.01% # attempts to use FU when none available 810system.cpu0.iq.fu_full::FloatCvt 0 0.00% 27.01% # attempts to use FU when none available 811system.cpu0.iq.fu_full::FloatMult 0 0.00% 27.01% # attempts to use FU when none available 812system.cpu0.iq.fu_full::FloatDiv 0 0.00% 27.01% # attempts to use FU when none available 813system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 27.01% # attempts to use FU when none available 814system.cpu0.iq.fu_full::SimdAdd 0 0.00% 27.01% # attempts to use FU when none available 815system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 27.01% # attempts to use FU when none available 816system.cpu0.iq.fu_full::SimdAlu 0 0.00% 27.01% # attempts to use FU when none available 817system.cpu0.iq.fu_full::SimdCmp 0 0.00% 27.01% # attempts to use FU when none available 818system.cpu0.iq.fu_full::SimdCvt 0 0.00% 27.01% # attempts to use FU when none available 819system.cpu0.iq.fu_full::SimdMisc 0 0.00% 27.01% # attempts to use FU when none available 820system.cpu0.iq.fu_full::SimdMult 0 0.00% 27.01% # attempts to use FU when none available 821system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 27.01% # attempts to use FU when none available 822system.cpu0.iq.fu_full::SimdShift 0 0.00% 27.01% # attempts to use FU when none available 823system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 27.01% # attempts to use FU when none available 824system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 27.01% # attempts to use FU when none available 825system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 27.01% # attempts to use FU when none available 826system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 27.01% # attempts to use FU when none available 827system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 27.01% # attempts to use FU when none available 828system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 27.01% # attempts to use FU when none available 829system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 27.01% # attempts to use FU when none available 830system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 27.01% # attempts to use FU when none available 831system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 27.01% # attempts to use FU when none available 832system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 27.01% # attempts to use FU when none available 833system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 27.01% # attempts to use FU when none available 834system.cpu0.iq.fu_full::MemRead 42 19.91% 46.92% # attempts to use FU when none available 835system.cpu0.iq.fu_full::MemWrite 112 53.08% 100.00% # attempts to use FU when none available 836system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 837system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 838system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 839system.cpu0.iq.FU_type_0::IntAlu 171308 42.29% 42.29% # Type of FU issued 840system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.29% # Type of FU issued 841system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.29% # Type of FU issued 842system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.29% # Type of FU issued 843system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.29% # Type of FU issued 844system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.29% # Type of FU issued 845system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.29% # Type of FU issued 846system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.29% # Type of FU issued 847system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.29% # Type of FU issued 848system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.29% # Type of FU issued 849system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.29% # Type of FU issued 850system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.29% # Type of FU issued 851system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.29% # Type of FU issued 852system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.29% # Type of FU issued 853system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.29% # Type of FU issued 854system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.29% # Type of FU issued 855system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.29% # Type of FU issued 856system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.29% # Type of FU issued 857system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.29% # Type of FU issued 858system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.29% # Type of FU issued 859system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.29% # Type of FU issued 860system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.29% # Type of FU issued 861system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.29% # Type of FU issued 862system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.29% # Type of FU issued 863system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.29% # Type of FU issued 864system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.29% # Type of FU issued 865system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.29% # Type of FU issued 866system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.29% # Type of FU issued 867system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.29% # Type of FU issued 868system.cpu0.iq.FU_type_0::MemRead 155505 38.39% 80.69% # Type of FU issued 869system.cpu0.iq.FU_type_0::MemWrite 78231 19.31% 100.00% # Type of FU issued 870system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 871system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 872system.cpu0.iq.FU_type_0::total 405044 # Type of FU issued 873system.cpu0.iq.rate 1.824095 # Inst issue rate 874system.cpu0.iq.fu_busy_cnt 211 # FU busy when requested 875system.cpu0.iq.fu_busy_rate 0.000521 # FU busy rate (busy events/executed inst) 876system.cpu0.iq.int_inst_queue_reads 1007470 # Number of integer instruction queue reads 877system.cpu0.iq.int_inst_queue_writes 419326 # Number of integer instruction queue writes 878system.cpu0.iq.int_inst_queue_wakeup_accesses 403231 # Number of integer instruction queue wakeup accesses 879system.cpu0.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads 880system.cpu0.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes 881system.cpu0.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses 882system.cpu0.iq.int_alu_accesses 405255 # Number of integer alu accesses 883system.cpu0.iq.fp_alu_accesses 0 # Number of floating point alu accesses 884system.cpu0.iew.lsq.thread0.forwLoads 75609 # Number of loads that had data forwarded from stores 885system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 886system.cpu0.iew.lsq.thread0.squashedLoads 2132 # Number of loads squashed 887system.cpu0.iew.lsq.thread0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed 888system.cpu0.iew.lsq.thread0.memOrderViolation 44 # Number of memory ordering violations 889system.cpu0.iew.lsq.thread0.squashedStores 1385 # Number of stores squashed 890system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 891system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 892system.cpu0.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 893system.cpu0.iew.lsq.thread0.cacheBlocked 19 # Number of times an access to memory failed due to the cache being blocked 894system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle 895system.cpu0.iew.iewSquashCycles 2440 # Number of cycles IEW is squashing 896system.cpu0.iew.iewBlockCycles 371 # Number of cycles IEW is blocking 897system.cpu0.iew.iewUnblockCycles 29 # Number of cycles IEW is unblocking 898system.cpu0.iew.iewDispatchedInsts 485139 # Number of instructions dispatched to IQ 899system.cpu0.iew.iewDispSquashedInsts 313 # Number of squashed instructions skipped by dispatch 900system.cpu0.iew.iewDispLoadInsts 155927 # Number of dispatched load instructions 901system.cpu0.iew.iewDispStoreInsts 78789 # Number of dispatched store instructions 902system.cpu0.iew.iewDispNonSpecInsts 806 # Number of dispatched non-speculative instructions 903system.cpu0.iew.iewIQFullEvents 30 # Number of times the IQ has become full, causing a stall 904system.cpu0.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 905system.cpu0.iew.memOrderViolationEvents 44 # Number of memory order violations 906system.cpu0.iew.predictedTakenIncorrect 328 # Number of branches that were predicted taken incorrectly 907system.cpu0.iew.predictedNotTakenIncorrect 1114 # Number of branches that were predicted not taken incorrectly 908system.cpu0.iew.branchMispredicts 1442 # Number of branch mispredicts detected at execute 909system.cpu0.iew.iewExecutedInsts 403978 # Number of executed instructions 910system.cpu0.iew.iewExecLoadInsts 155175 # Number of load instructions executed 911system.cpu0.iew.iewExecSquashedInsts 1066 # Number of squashed instructions skipped in execute 912system.cpu0.iew.exec_swp 0 # number of swp insts executed 913system.cpu0.iew.exec_nop 76577 # number of nop insts executed 914system.cpu0.iew.exec_refs 233309 # number of memory reference insts executed 915system.cpu0.iew.exec_branches 80250 # Number of branches executed 916system.cpu0.iew.exec_stores 78134 # Number of stores executed 917system.cpu0.iew.exec_rate 1.819295 # Inst execution rate 918system.cpu0.iew.wb_sent 403557 # cumulative count of insts sent to commit 919system.cpu0.iew.wb_count 403231 # cumulative count of insts written-back 920system.cpu0.iew.wb_producers 238890 # num instructions producing a value 921system.cpu0.iew.wb_consumers 241357 # num instructions consuming a value 922system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 923system.cpu0.iew.wb_rate 1.815931 # insts written-back per cycle 924system.cpu0.iew.wb_fanout 0.989779 # average fanout of values written-back 925system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 926system.cpu0.commit.commitSquashedInsts 12132 # The number of squashed insts skipped by commit 927system.cpu0.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards 928system.cpu0.commit.branchMispredicts 1219 # The number of times a branch was mispredicted 929system.cpu0.commit.committed_per_cycle::samples 194598 # Number of insts commited each cycle 930system.cpu0.commit.committed_per_cycle::mean 2.430487 # Number of insts commited each cycle 931system.cpu0.commit.committed_per_cycle::stdev 2.136021 # Number of insts commited each cycle 932system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 933system.cpu0.commit.committed_per_cycle::0 34535 17.75% 17.75% # Number of insts commited each cycle 934system.cpu0.commit.committed_per_cycle::1 80010 41.12% 58.86% # Number of insts commited each cycle 935system.cpu0.commit.committed_per_cycle::2 2413 1.24% 60.10% # Number of insts commited each cycle 936system.cpu0.commit.committed_per_cycle::3 690 0.35% 60.46% # Number of insts commited each cycle 937system.cpu0.commit.committed_per_cycle::4 532 0.27% 60.73% # Number of insts commited each cycle 938system.cpu0.commit.committed_per_cycle::5 75417 38.76% 99.49% # Number of insts commited each cycle 939system.cpu0.commit.committed_per_cycle::6 460 0.24% 99.72% # Number of insts commited each cycle 940system.cpu0.commit.committed_per_cycle::7 239 0.12% 99.84% # Number of insts commited each cycle 941system.cpu0.commit.committed_per_cycle::8 302 0.16% 100.00% # Number of insts commited each cycle 942system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 943system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 944system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 945system.cpu0.commit.committed_per_cycle::total 194598 # Number of insts commited each cycle 946system.cpu0.commit.committedInsts 472968 # Number of instructions committed 947system.cpu0.commit.committedOps 472968 # Number of ops (including micro ops) committed 948system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed 949system.cpu0.commit.refs 231199 # Number of memory references committed 950system.cpu0.commit.loads 153795 # Number of loads committed 951system.cpu0.commit.membars 84 # Number of memory barriers committed 952system.cpu0.commit.branches 79291 # Number of branches committed 953system.cpu0.commit.fp_insts 0 # Number of committed floating point instructions. 954system.cpu0.commit.int_insts 318742 # Number of committed integer instructions. 955system.cpu0.commit.function_calls 223 # Number of function calls committed. 956system.cpu0.commit.bw_lim_events 302 # number cycles where commit BW limit reached 957system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits 958system.cpu0.rob.rob_reads 678235 # The number of ROB reads 959system.cpu0.rob.rob_writes 972657 # The number of ROB writes 960system.cpu0.timesIdled 325 # Number of times that the entire CPU went into an idle state and unscheduled itself 961system.cpu0.idleCycles 25014 # Total number of cycles that the CPU has spent unscheduled due to idling 962system.cpu0.committedInsts 396861 # Number of Instructions Simulated 963system.cpu0.committedOps 396861 # Number of Ops (including micro ops) Simulated 964system.cpu0.committedInsts_total 396861 # Number of Instructions Simulated 965system.cpu0.cpi 0.559521 # CPI: Cycles Per Instruction 966system.cpu0.cpi_total 0.559521 # CPI: Total CPI of All Threads 967system.cpu0.ipc 1.787244 # IPC: Instructions Per Cycle 968system.cpu0.ipc_total 1.787244 # IPC: Total IPC of All Threads 969system.cpu0.int_regfile_reads 722661 # number of integer regfile reads 970system.cpu0.int_regfile_writes 325753 # number of integer regfile writes 971system.cpu0.fp_regfile_reads 192 # number of floating regfile reads 972system.cpu0.misc_regfile_reads 235146 # number of misc regfile reads 973system.cpu0.misc_regfile_writes 564 # number of misc regfile writes 974system.cpu0.icache.tags.replacements 297 # number of replacements 975system.cpu0.icache.tags.tagsinuse 241.312438 # Cycle average of tags in use 976system.cpu0.icache.tags.total_refs 5113 # Total number of references to valid blocks. 977system.cpu0.icache.tags.sampled_refs 587 # Sample count of references to valid blocks. 978system.cpu0.icache.tags.avg_refs 8.710392 # Average number of references to valid blocks. 979system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 980system.cpu0.icache.tags.occ_blocks::cpu0.inst 241.312438 # Average occupied blocks per requestor 981system.cpu0.icache.tags.occ_percent::cpu0.inst 0.471313 # Average percentage of cache occupancy 982system.cpu0.icache.tags.occ_percent::total 0.471313 # Average percentage of cache occupancy 983system.cpu0.icache.tags.occ_task_id_blocks::1024 290 # Occupied blocks per task id 984system.cpu0.icache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id 985system.cpu0.icache.tags.age_task_id_blocks_1024::1 145 # Occupied blocks per task id 986system.cpu0.icache.tags.age_task_id_blocks_1024::2 85 # Occupied blocks per task id 987system.cpu0.icache.tags.occ_task_id_percent::1024 0.566406 # Percentage of cache occupancy per task id 988system.cpu0.icache.tags.tag_accesses 6456 # Number of tag accesses 989system.cpu0.icache.tags.data_accesses 6456 # Number of data accesses 990system.cpu0.icache.ReadReq_hits::cpu0.inst 5113 # number of ReadReq hits 991system.cpu0.icache.ReadReq_hits::total 5113 # number of ReadReq hits 992system.cpu0.icache.demand_hits::cpu0.inst 5113 # number of demand (read+write) hits 993system.cpu0.icache.demand_hits::total 5113 # number of demand (read+write) hits 994system.cpu0.icache.overall_hits::cpu0.inst 5113 # number of overall hits 995system.cpu0.icache.overall_hits::total 5113 # number of overall hits 996system.cpu0.icache.ReadReq_misses::cpu0.inst 756 # number of ReadReq misses 997system.cpu0.icache.ReadReq_misses::total 756 # number of ReadReq misses 998system.cpu0.icache.demand_misses::cpu0.inst 756 # number of demand (read+write) misses 999system.cpu0.icache.demand_misses::total 756 # number of demand (read+write) misses 1000system.cpu0.icache.overall_misses::cpu0.inst 756 # number of overall misses 1001system.cpu0.icache.overall_misses::total 756 # number of overall misses 1002system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 35939745 # number of ReadReq miss cycles 1003system.cpu0.icache.ReadReq_miss_latency::total 35939745 # number of ReadReq miss cycles 1004system.cpu0.icache.demand_miss_latency::cpu0.inst 35939745 # number of demand (read+write) miss cycles 1005system.cpu0.icache.demand_miss_latency::total 35939745 # number of demand (read+write) miss cycles 1006system.cpu0.icache.overall_miss_latency::cpu0.inst 35939745 # number of overall miss cycles 1007system.cpu0.icache.overall_miss_latency::total 35939745 # number of overall miss cycles 1008system.cpu0.icache.ReadReq_accesses::cpu0.inst 5869 # number of ReadReq accesses(hits+misses) 1009system.cpu0.icache.ReadReq_accesses::total 5869 # number of ReadReq accesses(hits+misses) 1010system.cpu0.icache.demand_accesses::cpu0.inst 5869 # number of demand (read+write) accesses 1011system.cpu0.icache.demand_accesses::total 5869 # number of demand (read+write) accesses 1012system.cpu0.icache.overall_accesses::cpu0.inst 5869 # number of overall (read+write) accesses 1013system.cpu0.icache.overall_accesses::total 5869 # number of overall (read+write) accesses 1014system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.128812 # miss rate for ReadReq accesses 1015system.cpu0.icache.ReadReq_miss_rate::total 0.128812 # miss rate for ReadReq accesses 1016system.cpu0.icache.demand_miss_rate::cpu0.inst 0.128812 # miss rate for demand accesses 1017system.cpu0.icache.demand_miss_rate::total 0.128812 # miss rate for demand accesses 1018system.cpu0.icache.overall_miss_rate::cpu0.inst 0.128812 # miss rate for overall accesses 1019system.cpu0.icache.overall_miss_rate::total 0.128812 # miss rate for overall accesses 1020system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 47539.345238 # average ReadReq miss latency 1021system.cpu0.icache.ReadReq_avg_miss_latency::total 47539.345238 # average ReadReq miss latency 1022system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 47539.345238 # average overall miss latency 1023system.cpu0.icache.demand_avg_miss_latency::total 47539.345238 # average overall miss latency 1024system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 47539.345238 # average overall miss latency 1025system.cpu0.icache.overall_avg_miss_latency::total 47539.345238 # average overall miss latency 1026system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1027system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1028system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1029system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 1030system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1031system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1032system.cpu0.icache.fast_writes 0 # number of fast writes performed 1033system.cpu0.icache.cache_copies 0 # number of cache copies performed 1034system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 168 # number of ReadReq MSHR hits 1035system.cpu0.icache.ReadReq_mshr_hits::total 168 # number of ReadReq MSHR hits 1036system.cpu0.icache.demand_mshr_hits::cpu0.inst 168 # number of demand (read+write) MSHR hits 1037system.cpu0.icache.demand_mshr_hits::total 168 # number of demand (read+write) MSHR hits 1038system.cpu0.icache.overall_mshr_hits::cpu0.inst 168 # number of overall MSHR hits 1039system.cpu0.icache.overall_mshr_hits::total 168 # number of overall MSHR hits 1040system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 588 # number of ReadReq MSHR misses 1041system.cpu0.icache.ReadReq_mshr_misses::total 588 # number of ReadReq MSHR misses 1042system.cpu0.icache.demand_mshr_misses::cpu0.inst 588 # number of demand (read+write) MSHR misses 1043system.cpu0.icache.demand_mshr_misses::total 588 # number of demand (read+write) MSHR misses 1044system.cpu0.icache.overall_mshr_misses::cpu0.inst 588 # number of overall MSHR misses 1045system.cpu0.icache.overall_mshr_misses::total 588 # number of overall MSHR misses 1046system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 27686752 # number of ReadReq MSHR miss cycles 1047system.cpu0.icache.ReadReq_mshr_miss_latency::total 27686752 # number of ReadReq MSHR miss cycles 1048system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 27686752 # number of demand (read+write) MSHR miss cycles 1049system.cpu0.icache.demand_mshr_miss_latency::total 27686752 # number of demand (read+write) MSHR miss cycles 1050system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 27686752 # number of overall MSHR miss cycles 1051system.cpu0.icache.overall_mshr_miss_latency::total 27686752 # number of overall MSHR miss cycles 1052system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.100187 # mshr miss rate for ReadReq accesses 1053system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.100187 # mshr miss rate for ReadReq accesses 1054system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.100187 # mshr miss rate for demand accesses 1055system.cpu0.icache.demand_mshr_miss_rate::total 0.100187 # mshr miss rate for demand accesses 1056system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.100187 # mshr miss rate for overall accesses 1057system.cpu0.icache.overall_mshr_miss_rate::total 0.100187 # mshr miss rate for overall accesses 1058system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 47086.312925 # average ReadReq mshr miss latency 1059system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 47086.312925 # average ReadReq mshr miss latency 1060system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 47086.312925 # average overall mshr miss latency 1061system.cpu0.icache.demand_avg_mshr_miss_latency::total 47086.312925 # average overall mshr miss latency 1062system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 47086.312925 # average overall mshr miss latency 1063system.cpu0.icache.overall_avg_mshr_miss_latency::total 47086.312925 # average overall mshr miss latency 1064system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1065system.cpu0.dcache.tags.replacements 2 # number of replacements 1066system.cpu0.dcache.tags.tagsinuse 142.026071 # Cycle average of tags in use 1067system.cpu0.dcache.tags.total_refs 155821 # Total number of references to valid blocks. 1068system.cpu0.dcache.tags.sampled_refs 170 # Sample count of references to valid blocks. 1069system.cpu0.dcache.tags.avg_refs 916.594118 # Average number of references to valid blocks. 1070system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1071system.cpu0.dcache.tags.occ_blocks::cpu0.data 142.026071 # Average occupied blocks per requestor 1072system.cpu0.dcache.tags.occ_percent::cpu0.data 0.277395 # Average percentage of cache occupancy 1073system.cpu0.dcache.tags.occ_percent::total 0.277395 # Average percentage of cache occupancy 1074system.cpu0.dcache.tags.occ_task_id_blocks::1024 168 # Occupied blocks per task id 1075system.cpu0.dcache.tags.age_task_id_blocks_1024::0 17 # Occupied blocks per task id 1076system.cpu0.dcache.tags.age_task_id_blocks_1024::1 51 # Occupied blocks per task id 1077system.cpu0.dcache.tags.age_task_id_blocks_1024::2 100 # Occupied blocks per task id 1078system.cpu0.dcache.tags.occ_task_id_percent::1024 0.328125 # Percentage of cache occupancy per task id 1079system.cpu0.dcache.tags.tag_accesses 627950 # Number of tag accesses 1080system.cpu0.dcache.tags.data_accesses 627950 # Number of data accesses 1081system.cpu0.dcache.ReadReq_hits::cpu0.data 79085 # number of ReadReq hits 1082system.cpu0.dcache.ReadReq_hits::total 79085 # number of ReadReq hits 1083system.cpu0.dcache.WriteReq_hits::cpu0.data 76817 # number of WriteReq hits 1084system.cpu0.dcache.WriteReq_hits::total 76817 # number of WriteReq hits 1085system.cpu0.dcache.SwapReq_hits::cpu0.data 21 # number of SwapReq hits 1086system.cpu0.dcache.SwapReq_hits::total 21 # number of SwapReq hits 1087system.cpu0.dcache.demand_hits::cpu0.data 155902 # number of demand (read+write) hits 1088system.cpu0.dcache.demand_hits::total 155902 # number of demand (read+write) hits 1089system.cpu0.dcache.overall_hits::cpu0.data 155902 # number of overall hits 1090system.cpu0.dcache.overall_hits::total 155902 # number of overall hits 1091system.cpu0.dcache.ReadReq_misses::cpu0.data 420 # number of ReadReq misses 1092system.cpu0.dcache.ReadReq_misses::total 420 # number of ReadReq misses 1093system.cpu0.dcache.WriteReq_misses::cpu0.data 545 # number of WriteReq misses 1094system.cpu0.dcache.WriteReq_misses::total 545 # number of WriteReq misses 1095system.cpu0.dcache.SwapReq_misses::cpu0.data 21 # number of SwapReq misses 1096system.cpu0.dcache.SwapReq_misses::total 21 # number of SwapReq misses 1097system.cpu0.dcache.demand_misses::cpu0.data 965 # number of demand (read+write) misses 1098system.cpu0.dcache.demand_misses::total 965 # number of demand (read+write) misses 1099system.cpu0.dcache.overall_misses::cpu0.data 965 # number of overall misses 1100system.cpu0.dcache.overall_misses::total 965 # number of overall misses 1101system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 13542707 # number of ReadReq miss cycles 1102system.cpu0.dcache.ReadReq_miss_latency::total 13542707 # number of ReadReq miss cycles 1103system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 32279504 # number of WriteReq miss cycles 1104system.cpu0.dcache.WriteReq_miss_latency::total 32279504 # number of WriteReq miss cycles 1105system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 404750 # number of SwapReq miss cycles 1106system.cpu0.dcache.SwapReq_miss_latency::total 404750 # number of SwapReq miss cycles 1107system.cpu0.dcache.demand_miss_latency::cpu0.data 45822211 # number of demand (read+write) miss cycles 1108system.cpu0.dcache.demand_miss_latency::total 45822211 # number of demand (read+write) miss cycles 1109system.cpu0.dcache.overall_miss_latency::cpu0.data 45822211 # number of overall miss cycles 1110system.cpu0.dcache.overall_miss_latency::total 45822211 # number of overall miss cycles 1111system.cpu0.dcache.ReadReq_accesses::cpu0.data 79505 # number of ReadReq accesses(hits+misses) 1112system.cpu0.dcache.ReadReq_accesses::total 79505 # number of ReadReq accesses(hits+misses) 1113system.cpu0.dcache.WriteReq_accesses::cpu0.data 77362 # number of WriteReq accesses(hits+misses) 1114system.cpu0.dcache.WriteReq_accesses::total 77362 # number of WriteReq accesses(hits+misses) 1115system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) 1116system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) 1117system.cpu0.dcache.demand_accesses::cpu0.data 156867 # number of demand (read+write) accesses 1118system.cpu0.dcache.demand_accesses::total 156867 # number of demand (read+write) accesses 1119system.cpu0.dcache.overall_accesses::cpu0.data 156867 # number of overall (read+write) accesses 1120system.cpu0.dcache.overall_accesses::total 156867 # number of overall (read+write) accesses 1121system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.005283 # miss rate for ReadReq accesses 1122system.cpu0.dcache.ReadReq_miss_rate::total 0.005283 # miss rate for ReadReq accesses 1123system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007045 # miss rate for WriteReq accesses 1124system.cpu0.dcache.WriteReq_miss_rate::total 0.007045 # miss rate for WriteReq accesses 1125system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.500000 # miss rate for SwapReq accesses 1126system.cpu0.dcache.SwapReq_miss_rate::total 0.500000 # miss rate for SwapReq accesses 1127system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006152 # miss rate for demand accesses 1128system.cpu0.dcache.demand_miss_rate::total 0.006152 # miss rate for demand accesses 1129system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006152 # miss rate for overall accesses 1130system.cpu0.dcache.overall_miss_rate::total 0.006152 # miss rate for overall accesses 1131system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 32244.540476 # average ReadReq miss latency 1132system.cpu0.dcache.ReadReq_avg_miss_latency::total 32244.540476 # average ReadReq miss latency 1133system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 59228.447706 # average WriteReq miss latency 1134system.cpu0.dcache.WriteReq_avg_miss_latency::total 59228.447706 # average WriteReq miss latency 1135system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 19273.809524 # average SwapReq miss latency 1136system.cpu0.dcache.SwapReq_avg_miss_latency::total 19273.809524 # average SwapReq miss latency 1137system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 47484.156477 # average overall miss latency 1138system.cpu0.dcache.demand_avg_miss_latency::total 47484.156477 # average overall miss latency 1139system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 47484.156477 # average overall miss latency 1140system.cpu0.dcache.overall_avg_miss_latency::total 47484.156477 # average overall miss latency 1141system.cpu0.dcache.blocked_cycles::no_mshrs 503 # number of cycles access was blocked 1142system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1143system.cpu0.dcache.blocked::no_mshrs 21 # number of cycles access was blocked 1144system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 1145system.cpu0.dcache.avg_blocked_cycles::no_mshrs 23.952381 # average number of cycles each access was blocked 1146system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1147system.cpu0.dcache.fast_writes 0 # number of fast writes performed 1148system.cpu0.dcache.cache_copies 0 # number of cache copies performed 1149system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks 1150system.cpu0.dcache.writebacks::total 1 # number of writebacks 1151system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 227 # number of ReadReq MSHR hits 1152system.cpu0.dcache.ReadReq_mshr_hits::total 227 # number of ReadReq MSHR hits 1153system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 373 # number of WriteReq MSHR hits 1154system.cpu0.dcache.WriteReq_mshr_hits::total 373 # number of WriteReq MSHR hits 1155system.cpu0.dcache.demand_mshr_hits::cpu0.data 600 # number of demand (read+write) MSHR hits 1156system.cpu0.dcache.demand_mshr_hits::total 600 # number of demand (read+write) MSHR hits 1157system.cpu0.dcache.overall_mshr_hits::cpu0.data 600 # number of overall MSHR hits 1158system.cpu0.dcache.overall_mshr_hits::total 600 # number of overall MSHR hits 1159system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 193 # number of ReadReq MSHR misses 1160system.cpu0.dcache.ReadReq_mshr_misses::total 193 # number of ReadReq MSHR misses 1161system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 172 # number of WriteReq MSHR misses 1162system.cpu0.dcache.WriteReq_mshr_misses::total 172 # number of WriteReq MSHR misses 1163system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 21 # number of SwapReq MSHR misses 1164system.cpu0.dcache.SwapReq_mshr_misses::total 21 # number of SwapReq MSHR misses 1165system.cpu0.dcache.demand_mshr_misses::cpu0.data 365 # number of demand (read+write) MSHR misses 1166system.cpu0.dcache.demand_mshr_misses::total 365 # number of demand (read+write) MSHR misses 1167system.cpu0.dcache.overall_mshr_misses::cpu0.data 365 # number of overall MSHR misses 1168system.cpu0.dcache.overall_mshr_misses::total 365 # number of overall MSHR misses 1169system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 6251507 # number of ReadReq MSHR miss cycles 1170system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6251507 # number of ReadReq MSHR miss cycles 1171system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7188729 # number of WriteReq MSHR miss cycles 1172system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7188729 # number of WriteReq MSHR miss cycles 1173system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 361250 # number of SwapReq MSHR miss cycles 1174system.cpu0.dcache.SwapReq_mshr_miss_latency::total 361250 # number of SwapReq MSHR miss cycles 1175system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 13440236 # number of demand (read+write) MSHR miss cycles 1176system.cpu0.dcache.demand_mshr_miss_latency::total 13440236 # number of demand (read+write) MSHR miss cycles 1177system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 13440236 # number of overall MSHR miss cycles 1178system.cpu0.dcache.overall_mshr_miss_latency::total 13440236 # number of overall MSHR miss cycles 1179system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002428 # mshr miss rate for ReadReq accesses 1180system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002428 # mshr miss rate for ReadReq accesses 1181system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002223 # mshr miss rate for WriteReq accesses 1182system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002223 # mshr miss rate for WriteReq accesses 1183system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.500000 # mshr miss rate for SwapReq accesses 1184system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SwapReq accesses 1185system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002327 # mshr miss rate for demand accesses 1186system.cpu0.dcache.demand_mshr_miss_rate::total 0.002327 # mshr miss rate for demand accesses 1187system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002327 # mshr miss rate for overall accesses 1188system.cpu0.dcache.overall_mshr_miss_rate::total 0.002327 # mshr miss rate for overall accesses 1189system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 32391.227979 # average ReadReq mshr miss latency 1190system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 32391.227979 # average ReadReq mshr miss latency 1191system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 41794.936047 # average WriteReq mshr miss latency 1192system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 41794.936047 # average WriteReq mshr miss latency 1193system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 17202.380952 # average SwapReq mshr miss latency 1194system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 17202.380952 # average SwapReq mshr miss latency 1195system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 36822.564384 # average overall mshr miss latency 1196system.cpu0.dcache.demand_avg_mshr_miss_latency::total 36822.564384 # average overall mshr miss latency 1197system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 36822.564384 # average overall mshr miss latency 1198system.cpu0.dcache.overall_avg_mshr_miss_latency::total 36822.564384 # average overall mshr miss latency 1199system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1200system.cpu1.branchPred.lookups 47485 # Number of BP lookups 1201system.cpu1.branchPred.condPredicted 44754 # Number of conditional branches predicted 1202system.cpu1.branchPred.condIncorrect 1270 # Number of conditional branches incorrect 1203system.cpu1.branchPred.BTBLookups 41396 # Number of BTB lookups 1204system.cpu1.branchPred.BTBHits 40599 # Number of BTB hits 1205system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 1206system.cpu1.branchPred.BTBHitPct 98.074693 # BTB Hit Percentage 1207system.cpu1.branchPred.usedRAS 654 # Number of times the RAS was used to get a target. 1208system.cpu1.branchPred.RASInCorrect 232 # Number of incorrect RAS predictions. 1209system.cpu1.numCycles 177933 # number of cpu cycles simulated 1210system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1211system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 1212system.cpu1.fetch.icacheStallCycles 31734 # Number of cycles fetch is stalled on an Icache miss 1213system.cpu1.fetch.Insts 260080 # Number of instructions fetch has processed 1214system.cpu1.fetch.Branches 47485 # Number of branches that fetch encountered 1215system.cpu1.fetch.predictedBranches 41253 # Number of branches that fetch has predicted taken 1216system.cpu1.fetch.Cycles 95164 # Number of cycles fetch has run and was not squashing or blocked 1217system.cpu1.fetch.SquashCycles 3727 # Number of cycles fetch has spent squashing 1218system.cpu1.fetch.BlockedCycles 37889 # Number of cycles fetch has spent blocked 1219system.cpu1.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 1220system.cpu1.fetch.NoActiveThreadStallCycles 7775 # Number of stall cycles due to no active thread to fetch from 1221system.cpu1.fetch.PendingTrapStallCycles 775 # Number of stall cycles due to pending traps 1222system.cpu1.fetch.CacheLines 23379 # Number of cache lines fetched 1223system.cpu1.fetch.IcacheSquashes 257 # Number of outstanding Icache misses that were squashed 1224system.cpu1.fetch.rateDist::samples 175722 # Number of instructions fetched each cycle (Total) 1225system.cpu1.fetch.rateDist::mean 1.480065 # Number of instructions fetched each cycle (Total) 1226system.cpu1.fetch.rateDist::stdev 2.059330 # Number of instructions fetched each cycle (Total) 1227system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 1228system.cpu1.fetch.rateDist::0 80558 45.84% 45.84% # Number of instructions fetched each cycle (Total) 1229system.cpu1.fetch.rateDist::1 49339 28.08% 73.92% # Number of instructions fetched each cycle (Total) 1230system.cpu1.fetch.rateDist::2 7969 4.54% 78.46% # Number of instructions fetched each cycle (Total) 1231system.cpu1.fetch.rateDist::3 3191 1.82% 80.27% # Number of instructions fetched each cycle (Total) 1232system.cpu1.fetch.rateDist::4 687 0.39% 80.66% # Number of instructions fetched each cycle (Total) 1233system.cpu1.fetch.rateDist::5 28723 16.35% 97.01% # Number of instructions fetched each cycle (Total) 1234system.cpu1.fetch.rateDist::6 1207 0.69% 97.70% # Number of instructions fetched each cycle (Total) 1235system.cpu1.fetch.rateDist::7 759 0.43% 98.13% # Number of instructions fetched each cycle (Total) 1236system.cpu1.fetch.rateDist::8 3289 1.87% 100.00% # Number of instructions fetched each cycle (Total) 1237system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 1238system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1239system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 1240system.cpu1.fetch.rateDist::total 175722 # Number of instructions fetched each cycle (Total) 1241system.cpu1.fetch.branchRate 0.266870 # Number of branch fetches per cycle 1242system.cpu1.fetch.rate 1.461674 # Number of inst fetches per cycle 1243system.cpu1.decode.IdleCycles 38713 # Number of cycles decode is idle 1244system.cpu1.decode.BlockedCycles 32553 # Number of cycles decode is blocked 1245system.cpu1.decode.RunCycles 87468 # Number of cycles decode is running 1246system.cpu1.decode.UnblockCycles 6833 # Number of cycles decode is unblocking 1247system.cpu1.decode.SquashCycles 2380 # Number of cycles decode is squashing 1248system.cpu1.decode.DecodedInsts 256418 # Number of instructions handled by decode 1249system.cpu1.rename.SquashCycles 2380 # Number of cycles rename is squashing 1250system.cpu1.rename.IdleCycles 39395 # Number of cycles rename is idle 1251system.cpu1.rename.BlockCycles 20083 # Number of cycles rename is blocking 1252system.cpu1.rename.serializeStallCycles 11723 # count of cycles rename stalled for serializing inst 1253system.cpu1.rename.RunCycles 80903 # Number of cycles rename is running 1254system.cpu1.rename.UnblockCycles 13463 # Number of cycles rename is unblocking 1255system.cpu1.rename.RenamedInsts 254199 # Number of instructions processed by rename 1256system.cpu1.rename.IQFullEvents 1 # Number of times rename has blocked due to IQ full 1257system.cpu1.rename.LSQFullEvents 22 # Number of times rename has blocked due to LSQ full 1258system.cpu1.rename.RenamedOperands 175957 # Number of destination operands rename has renamed 1259system.cpu1.rename.RenameLookups 477753 # Number of register rename lookups that rename has made 1260system.cpu1.rename.int_rename_lookups 373133 # Number of integer rename lookups 1261system.cpu1.rename.CommittedMaps 162997 # Number of HB maps that are committed 1262system.cpu1.rename.UndoneMaps 12960 # Number of HB maps that are undone due to squashing 1263system.cpu1.rename.serializingInsts 1085 # count of serializing insts renamed 1264system.cpu1.rename.tempSerializingInsts 1202 # count of temporary serializing insts renamed 1265system.cpu1.rename.skidInsts 16072 # count of insts added to the skid buffer 1266system.cpu1.memDep0.insertedLoads 69810 # Number of loads inserted to the mem dependence unit. 1267system.cpu1.memDep0.insertedStores 31966 # Number of stores inserted to the mem dependence unit. 1268system.cpu1.memDep0.conflictingLoads 34021 # Number of conflicting loads. 1269system.cpu1.memDep0.conflictingStores 26934 # Number of conflicting stores. 1270system.cpu1.iq.iqInstsAdded 208112 # Number of instructions added to the IQ (excludes non-spec) 1271system.cpu1.iq.iqNonSpecInstsAdded 8163 # Number of non-speculative instructions added to the IQ 1272system.cpu1.iq.iqInstsIssued 211912 # Number of instructions issued 1273system.cpu1.iq.iqSquashedInstsIssued 84 # Number of squashed instructions issued 1274system.cpu1.iq.iqSquashedInstsExamined 10867 # Number of squashed instructions iterated over during squash; mainly for profiling 1275system.cpu1.iq.iqSquashedOperandsExamined 10947 # Number of squashed operands that are examined and possibly removed from graph 1276system.cpu1.iq.iqSquashedNonSpecRemoved 602 # Number of squashed non-spec instructions that were removed 1277system.cpu1.iq.issued_per_cycle::samples 175722 # Number of insts issued each cycle 1278system.cpu1.iq.issued_per_cycle::mean 1.205950 # Number of insts issued each cycle 1279system.cpu1.iq.issued_per_cycle::stdev 1.291467 # Number of insts issued each cycle 1280system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 1281system.cpu1.iq.issued_per_cycle::0 78073 44.43% 44.43% # Number of insts issued each cycle 1282system.cpu1.iq.issued_per_cycle::1 27855 15.85% 60.28% # Number of insts issued each cycle 1283system.cpu1.iq.issued_per_cycle::2 32175 18.31% 78.59% # Number of insts issued each cycle 1284system.cpu1.iq.issued_per_cycle::3 32813 18.67% 97.26% # Number of insts issued each cycle 1285system.cpu1.iq.issued_per_cycle::4 3279 1.87% 99.13% # Number of insts issued each cycle 1286system.cpu1.iq.issued_per_cycle::5 1173 0.67% 99.80% # Number of insts issued each cycle 1287system.cpu1.iq.issued_per_cycle::6 248 0.14% 99.94% # Number of insts issued each cycle 1288system.cpu1.iq.issued_per_cycle::7 49 0.03% 99.97% # Number of insts issued each cycle 1289system.cpu1.iq.issued_per_cycle::8 57 0.03% 100.00% # Number of insts issued each cycle 1290system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1291system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1292system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 1293system.cpu1.iq.issued_per_cycle::total 175722 # Number of insts issued each cycle 1294system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 1295system.cpu1.iq.fu_full::IntAlu 12 4.51% 4.51% # attempts to use FU when none available 1296system.cpu1.iq.fu_full::IntMult 0 0.00% 4.51% # attempts to use FU when none available 1297system.cpu1.iq.fu_full::IntDiv 0 0.00% 4.51% # attempts to use FU when none available 1298system.cpu1.iq.fu_full::FloatAdd 0 0.00% 4.51% # attempts to use FU when none available 1299system.cpu1.iq.fu_full::FloatCmp 0 0.00% 4.51% # attempts to use FU when none available 1300system.cpu1.iq.fu_full::FloatCvt 0 0.00% 4.51% # attempts to use FU when none available 1301system.cpu1.iq.fu_full::FloatMult 0 0.00% 4.51% # attempts to use FU when none available 1302system.cpu1.iq.fu_full::FloatDiv 0 0.00% 4.51% # attempts to use FU when none available 1303system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 4.51% # attempts to use FU when none available 1304system.cpu1.iq.fu_full::SimdAdd 0 0.00% 4.51% # attempts to use FU when none available 1305system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 4.51% # attempts to use FU when none available 1306system.cpu1.iq.fu_full::SimdAlu 0 0.00% 4.51% # attempts to use FU when none available 1307system.cpu1.iq.fu_full::SimdCmp 0 0.00% 4.51% # attempts to use FU when none available 1308system.cpu1.iq.fu_full::SimdCvt 0 0.00% 4.51% # attempts to use FU when none available 1309system.cpu1.iq.fu_full::SimdMisc 0 0.00% 4.51% # attempts to use FU when none available 1310system.cpu1.iq.fu_full::SimdMult 0 0.00% 4.51% # attempts to use FU when none available 1311system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 4.51% # attempts to use FU when none available 1312system.cpu1.iq.fu_full::SimdShift 0 0.00% 4.51% # attempts to use FU when none available 1313system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 4.51% # attempts to use FU when none available 1314system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 4.51% # attempts to use FU when none available 1315system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 4.51% # attempts to use FU when none available 1316system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 4.51% # attempts to use FU when none available 1317system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 4.51% # attempts to use FU when none available 1318system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 4.51% # attempts to use FU when none available 1319system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 4.51% # attempts to use FU when none available 1320system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 4.51% # attempts to use FU when none available 1321system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 4.51% # attempts to use FU when none available 1322system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.51% # attempts to use FU when none available 1323system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 4.51% # attempts to use FU when none available 1324system.cpu1.iq.fu_full::MemRead 44 16.54% 21.05% # attempts to use FU when none available 1325system.cpu1.iq.fu_full::MemWrite 210 78.95% 100.00% # attempts to use FU when none available 1326system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 1327system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 1328system.cpu1.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 1329system.cpu1.iq.FU_type_0::IntAlu 104746 49.43% 49.43% # Type of FU issued 1330system.cpu1.iq.FU_type_0::IntMult 0 0.00% 49.43% # Type of FU issued 1331system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 49.43% # Type of FU issued 1332system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 49.43% # Type of FU issued 1333system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 49.43% # Type of FU issued 1334system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 49.43% # Type of FU issued 1335system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 49.43% # Type of FU issued 1336system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 49.43% # Type of FU issued 1337system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 49.43% # Type of FU issued 1338system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 49.43% # Type of FU issued 1339system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 49.43% # Type of FU issued 1340system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 49.43% # Type of FU issued 1341system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 49.43% # Type of FU issued 1342system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 49.43% # Type of FU issued 1343system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 49.43% # Type of FU issued 1344system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 49.43% # Type of FU issued 1345system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 49.43% # Type of FU issued 1346system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 49.43% # Type of FU issued 1347system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.43% # Type of FU issued 1348system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 49.43% # Type of FU issued 1349system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.43% # Type of FU issued 1350system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.43% # Type of FU issued 1351system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.43% # Type of FU issued 1352system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.43% # Type of FU issued 1353system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.43% # Type of FU issued 1354system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.43% # Type of FU issued 1355system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 49.43% # Type of FU issued 1356system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.43% # Type of FU issued 1357system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.43% # Type of FU issued 1358system.cpu1.iq.FU_type_0::MemRead 75888 35.81% 85.24% # Type of FU issued 1359system.cpu1.iq.FU_type_0::MemWrite 31278 14.76% 100.00% # Type of FU issued 1360system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 1361system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 1362system.cpu1.iq.FU_type_0::total 211912 # Type of FU issued 1363system.cpu1.iq.rate 1.190965 # Inst issue rate 1364system.cpu1.iq.fu_busy_cnt 266 # FU busy when requested 1365system.cpu1.iq.fu_busy_rate 0.001255 # FU busy rate (busy events/executed inst) 1366system.cpu1.iq.int_inst_queue_reads 599896 # Number of integer instruction queue reads 1367system.cpu1.iq.int_inst_queue_writes 227186 # Number of integer instruction queue writes 1368system.cpu1.iq.int_inst_queue_wakeup_accesses 210068 # Number of integer instruction queue wakeup accesses 1369system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads 1370system.cpu1.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes 1371system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses 1372system.cpu1.iq.int_alu_accesses 212178 # Number of integer alu accesses 1373system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses 1374system.cpu1.iew.lsq.thread0.forwLoads 26664 # Number of loads that had data forwarded from stores 1375system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 1376system.cpu1.iew.lsq.thread0.squashedLoads 2449 # Number of loads squashed 1377system.cpu1.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed 1378system.cpu1.iew.lsq.thread0.memOrderViolation 44 # Number of memory ordering violations 1379system.cpu1.iew.lsq.thread0.squashedStores 1447 # Number of stores squashed 1380system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 1381system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 1382system.cpu1.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 1383system.cpu1.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked 1384system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle 1385system.cpu1.iew.iewSquashCycles 2380 # Number of cycles IEW is squashing 1386system.cpu1.iew.iewBlockCycles 699 # Number of cycles IEW is blocking 1387system.cpu1.iew.iewUnblockCycles 40 # Number of cycles IEW is unblocking 1388system.cpu1.iew.iewDispatchedInsts 251202 # Number of instructions dispatched to IQ 1389system.cpu1.iew.iewDispSquashedInsts 408 # Number of squashed instructions skipped by dispatch 1390system.cpu1.iew.iewDispLoadInsts 69810 # Number of dispatched load instructions 1391system.cpu1.iew.iewDispStoreInsts 31966 # Number of dispatched store instructions 1392system.cpu1.iew.iewDispNonSpecInsts 1044 # Number of dispatched non-speculative instructions 1393system.cpu1.iew.iewIQFullEvents 40 # Number of times the IQ has become full, causing a stall 1394system.cpu1.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 1395system.cpu1.iew.memOrderViolationEvents 44 # Number of memory order violations 1396system.cpu1.iew.predictedTakenIncorrect 470 # Number of branches that were predicted taken incorrectly 1397system.cpu1.iew.predictedNotTakenIncorrect 919 # Number of branches that were predicted not taken incorrectly 1398system.cpu1.iew.branchMispredicts 1389 # Number of branch mispredicts detected at execute 1399system.cpu1.iew.iewExecutedInsts 210729 # Number of executed instructions 1400system.cpu1.iew.iewExecLoadInsts 68768 # Number of load instructions executed 1401system.cpu1.iew.iewExecSquashedInsts 1183 # Number of squashed instructions skipped in execute 1402system.cpu1.iew.exec_swp 0 # number of swp insts executed 1403system.cpu1.iew.exec_nop 34927 # number of nop insts executed 1404system.cpu1.iew.exec_refs 99964 # number of memory reference insts executed 1405system.cpu1.iew.exec_branches 44131 # Number of branches executed 1406system.cpu1.iew.exec_stores 31196 # Number of stores executed 1407system.cpu1.iew.exec_rate 1.184317 # Inst execution rate 1408system.cpu1.iew.wb_sent 210356 # cumulative count of insts sent to commit 1409system.cpu1.iew.wb_count 210068 # cumulative count of insts written-back 1410system.cpu1.iew.wb_producers 116711 # num instructions producing a value 1411system.cpu1.iew.wb_consumers 121376 # num instructions consuming a value 1412system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 1413system.cpu1.iew.wb_rate 1.180602 # insts written-back per cycle 1414system.cpu1.iew.wb_fanout 0.961566 # average fanout of values written-back 1415system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 1416system.cpu1.commit.commitSquashedInsts 12479 # The number of squashed insts skipped by commit 1417system.cpu1.commit.commitNonSpecStalls 7561 # The number of times commit has been forced to stall to communicate backwards 1418system.cpu1.commit.branchMispredicts 1270 # The number of times a branch was mispredicted 1419system.cpu1.commit.committed_per_cycle::samples 165567 # Number of insts commited each cycle 1420system.cpu1.commit.committed_per_cycle::mean 1.441743 # Number of insts commited each cycle 1421system.cpu1.commit.committed_per_cycle::stdev 1.939965 # Number of insts commited each cycle 1422system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 1423system.cpu1.commit.committed_per_cycle::0 77636 46.89% 46.89% # Number of insts commited each cycle 1424system.cpu1.commit.committed_per_cycle::1 42274 25.53% 72.42% # Number of insts commited each cycle 1425system.cpu1.commit.committed_per_cycle::2 6096 3.68% 76.11% # Number of insts commited each cycle 1426system.cpu1.commit.committed_per_cycle::3 8474 5.12% 81.22% # Number of insts commited each cycle 1427system.cpu1.commit.committed_per_cycle::4 1557 0.94% 82.16% # Number of insts commited each cycle 1428system.cpu1.commit.committed_per_cycle::5 27207 16.43% 98.60% # Number of insts commited each cycle 1429system.cpu1.commit.committed_per_cycle::6 510 0.31% 98.90% # Number of insts commited each cycle 1430system.cpu1.commit.committed_per_cycle::7 1010 0.61% 99.51% # Number of insts commited each cycle 1431system.cpu1.commit.committed_per_cycle::8 803 0.49% 100.00% # Number of insts commited each cycle 1432system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 1433system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 1434system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 1435system.cpu1.commit.committed_per_cycle::total 165567 # Number of insts commited each cycle 1436system.cpu1.commit.committedInsts 238705 # Number of instructions committed 1437system.cpu1.commit.committedOps 238705 # Number of ops (including micro ops) committed 1438system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed 1439system.cpu1.commit.refs 97880 # Number of memory references committed 1440system.cpu1.commit.loads 67361 # Number of loads committed 1441system.cpu1.commit.membars 6845 # Number of memory barriers committed 1442system.cpu1.commit.branches 43327 # Number of branches committed 1443system.cpu1.commit.fp_insts 0 # Number of committed floating point instructions. 1444system.cpu1.commit.int_insts 163326 # Number of committed integer instructions. 1445system.cpu1.commit.function_calls 322 # Number of function calls committed. 1446system.cpu1.commit.bw_lim_events 803 # number cycles where commit BW limit reached 1447system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits 1448system.cpu1.rob.rob_reads 415361 # The number of ROB reads 1449system.cpu1.rob.rob_writes 504754 # The number of ROB writes 1450system.cpu1.timesIdled 217 # Number of times that the entire CPU went into an idle state and unscheduled itself 1451system.cpu1.idleCycles 2211 # Total number of cycles that the CPU has spent unscheduled due to idling 1452system.cpu1.quiesceCycles 44117 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1453system.cpu1.committedInsts 197745 # Number of Instructions Simulated 1454system.cpu1.committedOps 197745 # Number of Ops (including micro ops) Simulated 1455system.cpu1.committedInsts_total 197745 # Number of Instructions Simulated 1456system.cpu1.cpi 0.899810 # CPI: Cycles Per Instruction 1457system.cpu1.cpi_total 0.899810 # CPI: Total CPI of All Threads 1458system.cpu1.ipc 1.111345 # IPC: Instructions Per Cycle 1459system.cpu1.ipc_total 1.111345 # IPC: Total IPC of All Threads 1460system.cpu1.int_regfile_reads 358439 # number of integer regfile reads 1461system.cpu1.int_regfile_writes 167768 # number of integer regfile writes 1462system.cpu1.fp_regfile_writes 64 # number of floating regfile writes 1463system.cpu1.misc_regfile_reads 101509 # number of misc regfile reads 1464system.cpu1.misc_regfile_writes 648 # number of misc regfile writes 1465system.cpu1.icache.tags.replacements 318 # number of replacements 1466system.cpu1.icache.tags.tagsinuse 76.730517 # Cycle average of tags in use 1467system.cpu1.icache.tags.total_refs 22903 # Total number of references to valid blocks. 1468system.cpu1.icache.tags.sampled_refs 428 # Sample count of references to valid blocks. 1469system.cpu1.icache.tags.avg_refs 53.511682 # Average number of references to valid blocks. 1470system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1471system.cpu1.icache.tags.occ_blocks::cpu1.inst 76.730517 # Average occupied blocks per requestor 1472system.cpu1.icache.tags.occ_percent::cpu1.inst 0.149864 # Average percentage of cache occupancy 1473system.cpu1.icache.tags.occ_percent::total 0.149864 # Average percentage of cache occupancy 1474system.cpu1.icache.tags.occ_task_id_blocks::1024 110 # Occupied blocks per task id 1475system.cpu1.icache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id 1476system.cpu1.icache.tags.age_task_id_blocks_1024::1 99 # Occupied blocks per task id 1477system.cpu1.icache.tags.occ_task_id_percent::1024 0.214844 # Percentage of cache occupancy per task id 1478system.cpu1.icache.tags.tag_accesses 23807 # Number of tag accesses 1479system.cpu1.icache.tags.data_accesses 23807 # Number of data accesses 1480system.cpu1.icache.ReadReq_hits::cpu1.inst 22903 # number of ReadReq hits 1481system.cpu1.icache.ReadReq_hits::total 22903 # number of ReadReq hits 1482system.cpu1.icache.demand_hits::cpu1.inst 22903 # number of demand (read+write) hits 1483system.cpu1.icache.demand_hits::total 22903 # number of demand (read+write) hits 1484system.cpu1.icache.overall_hits::cpu1.inst 22903 # number of overall hits 1485system.cpu1.icache.overall_hits::total 22903 # number of overall hits 1486system.cpu1.icache.ReadReq_misses::cpu1.inst 476 # number of ReadReq misses 1487system.cpu1.icache.ReadReq_misses::total 476 # number of ReadReq misses 1488system.cpu1.icache.demand_misses::cpu1.inst 476 # number of demand (read+write) misses 1489system.cpu1.icache.demand_misses::total 476 # number of demand (read+write) misses 1490system.cpu1.icache.overall_misses::cpu1.inst 476 # number of overall misses 1491system.cpu1.icache.overall_misses::total 476 # number of overall misses 1492system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7186493 # number of ReadReq miss cycles 1493system.cpu1.icache.ReadReq_miss_latency::total 7186493 # number of ReadReq miss cycles 1494system.cpu1.icache.demand_miss_latency::cpu1.inst 7186493 # number of demand (read+write) miss cycles 1495system.cpu1.icache.demand_miss_latency::total 7186493 # number of demand (read+write) miss cycles 1496system.cpu1.icache.overall_miss_latency::cpu1.inst 7186493 # number of overall miss cycles 1497system.cpu1.icache.overall_miss_latency::total 7186493 # number of overall miss cycles 1498system.cpu1.icache.ReadReq_accesses::cpu1.inst 23379 # number of ReadReq accesses(hits+misses) 1499system.cpu1.icache.ReadReq_accesses::total 23379 # number of ReadReq accesses(hits+misses) 1500system.cpu1.icache.demand_accesses::cpu1.inst 23379 # number of demand (read+write) accesses 1501system.cpu1.icache.demand_accesses::total 23379 # number of demand (read+write) accesses 1502system.cpu1.icache.overall_accesses::cpu1.inst 23379 # number of overall (read+write) accesses 1503system.cpu1.icache.overall_accesses::total 23379 # number of overall (read+write) accesses 1504system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.020360 # miss rate for ReadReq accesses 1505system.cpu1.icache.ReadReq_miss_rate::total 0.020360 # miss rate for ReadReq accesses 1506system.cpu1.icache.demand_miss_rate::cpu1.inst 0.020360 # miss rate for demand accesses 1507system.cpu1.icache.demand_miss_rate::total 0.020360 # miss rate for demand accesses 1508system.cpu1.icache.overall_miss_rate::cpu1.inst 0.020360 # miss rate for overall accesses 1509system.cpu1.icache.overall_miss_rate::total 0.020360 # miss rate for overall accesses 1510system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15097.674370 # average ReadReq miss latency 1511system.cpu1.icache.ReadReq_avg_miss_latency::total 15097.674370 # average ReadReq miss latency 1512system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15097.674370 # average overall miss latency 1513system.cpu1.icache.demand_avg_miss_latency::total 15097.674370 # average overall miss latency 1514system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15097.674370 # average overall miss latency 1515system.cpu1.icache.overall_avg_miss_latency::total 15097.674370 # average overall miss latency 1516system.cpu1.icache.blocked_cycles::no_mshrs 26 # number of cycles access was blocked 1517system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1518system.cpu1.icache.blocked::no_mshrs 2 # number of cycles access was blocked 1519system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1520system.cpu1.icache.avg_blocked_cycles::no_mshrs 13 # average number of cycles each access was blocked 1521system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1522system.cpu1.icache.fast_writes 0 # number of fast writes performed 1523system.cpu1.icache.cache_copies 0 # number of cache copies performed 1524system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 48 # number of ReadReq MSHR hits 1525system.cpu1.icache.ReadReq_mshr_hits::total 48 # number of ReadReq MSHR hits 1526system.cpu1.icache.demand_mshr_hits::cpu1.inst 48 # number of demand (read+write) MSHR hits 1527system.cpu1.icache.demand_mshr_hits::total 48 # number of demand (read+write) MSHR hits 1528system.cpu1.icache.overall_mshr_hits::cpu1.inst 48 # number of overall MSHR hits 1529system.cpu1.icache.overall_mshr_hits::total 48 # number of overall MSHR hits 1530system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 428 # number of ReadReq MSHR misses 1531system.cpu1.icache.ReadReq_mshr_misses::total 428 # number of ReadReq MSHR misses 1532system.cpu1.icache.demand_mshr_misses::cpu1.inst 428 # number of demand (read+write) MSHR misses 1533system.cpu1.icache.demand_mshr_misses::total 428 # number of demand (read+write) MSHR misses 1534system.cpu1.icache.overall_mshr_misses::cpu1.inst 428 # number of overall MSHR misses 1535system.cpu1.icache.overall_mshr_misses::total 428 # number of overall MSHR misses 1536system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5726506 # number of ReadReq MSHR miss cycles 1537system.cpu1.icache.ReadReq_mshr_miss_latency::total 5726506 # number of ReadReq MSHR miss cycles 1538system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5726506 # number of demand (read+write) MSHR miss cycles 1539system.cpu1.icache.demand_mshr_miss_latency::total 5726506 # number of demand (read+write) MSHR miss cycles 1540system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5726506 # number of overall MSHR miss cycles 1541system.cpu1.icache.overall_mshr_miss_latency::total 5726506 # number of overall MSHR miss cycles 1542system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.018307 # mshr miss rate for ReadReq accesses 1543system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.018307 # mshr miss rate for ReadReq accesses 1544system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.018307 # mshr miss rate for demand accesses 1545system.cpu1.icache.demand_mshr_miss_rate::total 0.018307 # mshr miss rate for demand accesses 1546system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.018307 # mshr miss rate for overall accesses 1547system.cpu1.icache.overall_mshr_miss_rate::total 0.018307 # mshr miss rate for overall accesses 1548system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13379.686916 # average ReadReq mshr miss latency 1549system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13379.686916 # average ReadReq mshr miss latency 1550system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13379.686916 # average overall mshr miss latency 1551system.cpu1.icache.demand_avg_mshr_miss_latency::total 13379.686916 # average overall mshr miss latency 1552system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13379.686916 # average overall mshr miss latency 1553system.cpu1.icache.overall_avg_mshr_miss_latency::total 13379.686916 # average overall mshr miss latency 1554system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1555system.cpu1.dcache.tags.replacements 0 # number of replacements 1556system.cpu1.dcache.tags.tagsinuse 23.664777 # Cycle average of tags in use 1557system.cpu1.dcache.tags.total_refs 36646 # Total number of references to valid blocks. 1558system.cpu1.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. 1559system.cpu1.dcache.tags.avg_refs 1263.655172 # Average number of references to valid blocks. 1560system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1561system.cpu1.dcache.tags.occ_blocks::cpu1.data 23.664777 # Average occupied blocks per requestor 1562system.cpu1.dcache.tags.occ_percent::cpu1.data 0.046220 # Average percentage of cache occupancy 1563system.cpu1.dcache.tags.occ_percent::total 0.046220 # Average percentage of cache occupancy 1564system.cpu1.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id 1565system.cpu1.dcache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id 1566system.cpu1.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id 1567system.cpu1.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id 1568system.cpu1.dcache.tags.tag_accesses 290684 # Number of tag accesses 1569system.cpu1.dcache.tags.data_accesses 290684 # Number of data accesses 1570system.cpu1.dcache.ReadReq_hits::cpu1.data 41736 # number of ReadReq hits 1571system.cpu1.dcache.ReadReq_hits::total 41736 # number of ReadReq hits 1572system.cpu1.dcache.WriteReq_hits::cpu1.data 30310 # number of WriteReq hits 1573system.cpu1.dcache.WriteReq_hits::total 30310 # number of WriteReq hits 1574system.cpu1.dcache.SwapReq_hits::cpu1.data 13 # number of SwapReq hits 1575system.cpu1.dcache.SwapReq_hits::total 13 # number of SwapReq hits 1576system.cpu1.dcache.demand_hits::cpu1.data 72046 # number of demand (read+write) hits 1577system.cpu1.dcache.demand_hits::total 72046 # number of demand (read+write) hits 1578system.cpu1.dcache.overall_hits::cpu1.data 72046 # number of overall hits 1579system.cpu1.dcache.overall_hits::total 72046 # number of overall hits 1580system.cpu1.dcache.ReadReq_misses::cpu1.data 352 # number of ReadReq misses 1581system.cpu1.dcache.ReadReq_misses::total 352 # number of ReadReq misses 1582system.cpu1.dcache.WriteReq_misses::cpu1.data 139 # number of WriteReq misses 1583system.cpu1.dcache.WriteReq_misses::total 139 # number of WriteReq misses 1584system.cpu1.dcache.SwapReq_misses::cpu1.data 57 # number of SwapReq misses 1585system.cpu1.dcache.SwapReq_misses::total 57 # number of SwapReq misses 1586system.cpu1.dcache.demand_misses::cpu1.data 491 # number of demand (read+write) misses 1587system.cpu1.dcache.demand_misses::total 491 # number of demand (read+write) misses 1588system.cpu1.dcache.overall_misses::cpu1.data 491 # number of overall misses 1589system.cpu1.dcache.overall_misses::total 491 # number of overall misses 1590system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 4404095 # number of ReadReq miss cycles 1591system.cpu1.dcache.ReadReq_miss_latency::total 4404095 # number of ReadReq miss cycles 1592system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2802760 # number of WriteReq miss cycles 1593system.cpu1.dcache.WriteReq_miss_latency::total 2802760 # number of WriteReq miss cycles 1594system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 563508 # number of SwapReq miss cycles 1595system.cpu1.dcache.SwapReq_miss_latency::total 563508 # number of SwapReq miss cycles 1596system.cpu1.dcache.demand_miss_latency::cpu1.data 7206855 # number of demand (read+write) miss cycles 1597system.cpu1.dcache.demand_miss_latency::total 7206855 # number of demand (read+write) miss cycles 1598system.cpu1.dcache.overall_miss_latency::cpu1.data 7206855 # number of overall miss cycles 1599system.cpu1.dcache.overall_miss_latency::total 7206855 # number of overall miss cycles 1600system.cpu1.dcache.ReadReq_accesses::cpu1.data 42088 # number of ReadReq accesses(hits+misses) 1601system.cpu1.dcache.ReadReq_accesses::total 42088 # number of ReadReq accesses(hits+misses) 1602system.cpu1.dcache.WriteReq_accesses::cpu1.data 30449 # number of WriteReq accesses(hits+misses) 1603system.cpu1.dcache.WriteReq_accesses::total 30449 # number of WriteReq accesses(hits+misses) 1604system.cpu1.dcache.SwapReq_accesses::cpu1.data 70 # number of SwapReq accesses(hits+misses) 1605system.cpu1.dcache.SwapReq_accesses::total 70 # number of SwapReq accesses(hits+misses) 1606system.cpu1.dcache.demand_accesses::cpu1.data 72537 # number of demand (read+write) accesses 1607system.cpu1.dcache.demand_accesses::total 72537 # number of demand (read+write) accesses 1608system.cpu1.dcache.overall_accesses::cpu1.data 72537 # number of overall (read+write) accesses 1609system.cpu1.dcache.overall_accesses::total 72537 # number of overall (read+write) accesses 1610system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.008363 # miss rate for ReadReq accesses 1611system.cpu1.dcache.ReadReq_miss_rate::total 0.008363 # miss rate for ReadReq accesses 1612system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.004565 # miss rate for WriteReq accesses 1613system.cpu1.dcache.WriteReq_miss_rate::total 0.004565 # miss rate for WriteReq accesses 1614system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.814286 # miss rate for SwapReq accesses 1615system.cpu1.dcache.SwapReq_miss_rate::total 0.814286 # miss rate for SwapReq accesses 1616system.cpu1.dcache.demand_miss_rate::cpu1.data 0.006769 # miss rate for demand accesses 1617system.cpu1.dcache.demand_miss_rate::total 0.006769 # miss rate for demand accesses 1618system.cpu1.dcache.overall_miss_rate::cpu1.data 0.006769 # miss rate for overall accesses 1619system.cpu1.dcache.overall_miss_rate::total 0.006769 # miss rate for overall accesses 1620system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12511.633523 # average ReadReq miss latency 1621system.cpu1.dcache.ReadReq_avg_miss_latency::total 12511.633523 # average ReadReq miss latency 1622system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 20163.741007 # average WriteReq miss latency 1623system.cpu1.dcache.WriteReq_avg_miss_latency::total 20163.741007 # average WriteReq miss latency 1624system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 9886.105263 # average SwapReq miss latency 1625system.cpu1.dcache.SwapReq_avg_miss_latency::total 9886.105263 # average SwapReq miss latency 1626system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14677.912424 # average overall miss latency 1627system.cpu1.dcache.demand_avg_miss_latency::total 14677.912424 # average overall miss latency 1628system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14677.912424 # average overall miss latency 1629system.cpu1.dcache.overall_avg_miss_latency::total 14677.912424 # average overall miss latency 1630system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1631system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1632system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1633system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1634system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1635system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1636system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1637system.cpu1.dcache.cache_copies 0 # number of cache copies performed 1638system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 187 # number of ReadReq MSHR hits 1639system.cpu1.dcache.ReadReq_mshr_hits::total 187 # number of ReadReq MSHR hits 1640system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 32 # number of WriteReq MSHR hits 1641system.cpu1.dcache.WriteReq_mshr_hits::total 32 # number of WriteReq MSHR hits 1642system.cpu1.dcache.demand_mshr_hits::cpu1.data 219 # number of demand (read+write) MSHR hits 1643system.cpu1.dcache.demand_mshr_hits::total 219 # number of demand (read+write) MSHR hits 1644system.cpu1.dcache.overall_mshr_hits::cpu1.data 219 # number of overall MSHR hits 1645system.cpu1.dcache.overall_mshr_hits::total 219 # number of overall MSHR hits 1646system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 165 # number of ReadReq MSHR misses 1647system.cpu1.dcache.ReadReq_mshr_misses::total 165 # number of ReadReq MSHR misses 1648system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 107 # number of WriteReq MSHR misses 1649system.cpu1.dcache.WriteReq_mshr_misses::total 107 # number of WriteReq MSHR misses 1650system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 57 # number of SwapReq MSHR misses 1651system.cpu1.dcache.SwapReq_mshr_misses::total 57 # number of SwapReq MSHR misses 1652system.cpu1.dcache.demand_mshr_misses::cpu1.data 272 # number of demand (read+write) MSHR misses 1653system.cpu1.dcache.demand_mshr_misses::total 272 # number of demand (read+write) MSHR misses 1654system.cpu1.dcache.overall_mshr_misses::cpu1.data 272 # number of overall MSHR misses 1655system.cpu1.dcache.overall_mshr_misses::total 272 # number of overall MSHR misses 1656system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1130523 # number of ReadReq MSHR miss cycles 1657system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1130523 # number of ReadReq MSHR miss cycles 1658system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1329240 # number of WriteReq MSHR miss cycles 1659system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1329240 # number of WriteReq MSHR miss cycles 1660system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 449492 # number of SwapReq MSHR miss cycles 1661system.cpu1.dcache.SwapReq_mshr_miss_latency::total 449492 # number of SwapReq MSHR miss cycles 1662system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2459763 # number of demand (read+write) MSHR miss cycles 1663system.cpu1.dcache.demand_mshr_miss_latency::total 2459763 # number of demand (read+write) MSHR miss cycles 1664system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2459763 # number of overall MSHR miss cycles 1665system.cpu1.dcache.overall_mshr_miss_latency::total 2459763 # number of overall MSHR miss cycles 1666system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003920 # mshr miss rate for ReadReq accesses 1667system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003920 # mshr miss rate for ReadReq accesses 1668system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.003514 # mshr miss rate for WriteReq accesses 1669system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.003514 # mshr miss rate for WriteReq accesses 1670system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.814286 # mshr miss rate for SwapReq accesses 1671system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.814286 # mshr miss rate for SwapReq accesses 1672system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.003750 # mshr miss rate for demand accesses 1673system.cpu1.dcache.demand_mshr_miss_rate::total 0.003750 # mshr miss rate for demand accesses 1674system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.003750 # mshr miss rate for overall accesses 1675system.cpu1.dcache.overall_mshr_miss_rate::total 0.003750 # mshr miss rate for overall accesses 1676system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 6851.654545 # average ReadReq mshr miss latency 1677system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 6851.654545 # average ReadReq mshr miss latency 1678system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 12422.803738 # average WriteReq mshr miss latency 1679system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 12422.803738 # average WriteReq mshr miss latency 1680system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 7885.824561 # average SwapReq mshr miss latency 1681system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 7885.824561 # average SwapReq mshr miss latency 1682system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 9043.246324 # average overall mshr miss latency 1683system.cpu1.dcache.demand_avg_mshr_miss_latency::total 9043.246324 # average overall mshr miss latency 1684system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 9043.246324 # average overall mshr miss latency 1685system.cpu1.dcache.overall_avg_mshr_miss_latency::total 9043.246324 # average overall mshr miss latency 1686system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1687system.cpu2.branchPred.lookups 51289 # Number of BP lookups 1688system.cpu2.branchPred.condPredicted 48575 # Number of conditional branches predicted 1689system.cpu2.branchPred.condIncorrect 1303 # Number of conditional branches incorrect 1690system.cpu2.branchPred.BTBLookups 45091 # Number of BTB lookups 1691system.cpu2.branchPred.BTBHits 44400 # Number of BTB hits 1692system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 1693system.cpu2.branchPred.BTBHitPct 98.467543 # BTB Hit Percentage 1694system.cpu2.branchPred.usedRAS 684 # Number of times the RAS was used to get a target. 1695system.cpu2.branchPred.RASInCorrect 232 # Number of incorrect RAS predictions. 1696system.cpu2.numCycles 177568 # number of cpu cycles simulated 1697system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started 1698system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed 1699system.cpu2.fetch.icacheStallCycles 28811 # Number of cycles fetch is stalled on an Icache miss 1700system.cpu2.fetch.Insts 286582 # Number of instructions fetch has processed 1701system.cpu2.fetch.Branches 51289 # Number of branches that fetch encountered 1702system.cpu2.fetch.predictedBranches 45084 # Number of branches that fetch has predicted taken 1703system.cpu2.fetch.Cycles 100994 # Number of cycles fetch has run and was not squashing or blocked 1704system.cpu2.fetch.SquashCycles 3797 # Number of cycles fetch has spent squashing 1705system.cpu2.fetch.BlockedCycles 31174 # Number of cycles fetch has spent blocked 1706system.cpu2.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 1707system.cpu2.fetch.NoActiveThreadStallCycles 7777 # Number of stall cycles due to no active thread to fetch from 1708system.cpu2.fetch.PendingTrapStallCycles 828 # Number of stall cycles due to pending traps 1709system.cpu2.fetch.CacheLines 19751 # Number of cache lines fetched 1710system.cpu2.fetch.IcacheSquashes 271 # Number of outstanding Icache misses that were squashed 1711system.cpu2.fetch.rateDist::samples 172005 # Number of instructions fetched each cycle (Total) 1712system.cpu2.fetch.rateDist::mean 1.666126 # Number of instructions fetched each cycle (Total) 1713system.cpu2.fetch.rateDist::stdev 2.139968 # Number of instructions fetched each cycle (Total) 1714system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 1715system.cpu2.fetch.rateDist::0 71011 41.28% 41.28% # Number of instructions fetched each cycle (Total) 1716system.cpu2.fetch.rateDist::1 51378 29.87% 71.15% # Number of instructions fetched each cycle (Total) 1717system.cpu2.fetch.rateDist::2 6118 3.56% 74.71% # Number of instructions fetched each cycle (Total) 1718system.cpu2.fetch.rateDist::3 3176 1.85% 76.56% # Number of instructions fetched each cycle (Total) 1719system.cpu2.fetch.rateDist::4 688 0.40% 76.96% # Number of instructions fetched each cycle (Total) 1720system.cpu2.fetch.rateDist::5 34434 20.02% 96.98% # Number of instructions fetched each cycle (Total) 1721system.cpu2.fetch.rateDist::6 1153 0.67% 97.65% # Number of instructions fetched each cycle (Total) 1722system.cpu2.fetch.rateDist::7 776 0.45% 98.10% # Number of instructions fetched each cycle (Total) 1723system.cpu2.fetch.rateDist::8 3271 1.90% 100.00% # Number of instructions fetched each cycle (Total) 1724system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 1725system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1726system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 1727system.cpu2.fetch.rateDist::total 172005 # Number of instructions fetched each cycle (Total) 1728system.cpu2.fetch.branchRate 0.288841 # Number of branch fetches per cycle 1729system.cpu2.fetch.rate 1.613928 # Number of inst fetches per cycle 1730system.cpu2.decode.IdleCycles 33784 # Number of cycles decode is idle 1731system.cpu2.decode.BlockedCycles 27886 # Number of cycles decode is blocked 1732system.cpu2.decode.RunCycles 95100 # Number of cycles decode is running 1733system.cpu2.decode.UnblockCycles 5041 # Number of cycles decode is unblocking 1734system.cpu2.decode.SquashCycles 2417 # Number of cycles decode is squashing 1735system.cpu2.decode.DecodedInsts 283075 # Number of instructions handled by decode 1736system.cpu2.rename.SquashCycles 2417 # Number of cycles rename is squashing 1737system.cpu2.rename.IdleCycles 34494 # Number of cycles rename is idle 1738system.cpu2.rename.BlockCycles 14868 # Number of cycles rename is blocking 1739system.cpu2.rename.serializeStallCycles 12252 # count of cycles rename stalled for serializing inst 1740system.cpu2.rename.RunCycles 90315 # Number of cycles rename is running 1741system.cpu2.rename.UnblockCycles 9882 # Number of cycles rename is unblocking 1742system.cpu2.rename.RenamedInsts 280839 # Number of instructions processed by rename 1743system.cpu2.rename.LSQFullEvents 23 # Number of times rename has blocked due to LSQ full 1744system.cpu2.rename.RenamedOperands 196811 # Number of destination operands rename has renamed 1745system.cpu2.rename.RenameLookups 538430 # Number of register rename lookups that rename has made 1746system.cpu2.rename.int_rename_lookups 418650 # Number of integer rename lookups 1747system.cpu2.rename.CommittedMaps 183802 # Number of HB maps that are committed 1748system.cpu2.rename.UndoneMaps 13009 # Number of HB maps that are undone due to squashing 1749system.cpu2.rename.serializingInsts 1113 # count of serializing insts renamed 1750system.cpu2.rename.tempSerializingInsts 1241 # count of temporary serializing insts renamed 1751system.cpu2.rename.skidInsts 12535 # count of insts added to the skid buffer 1752system.cpu2.memDep0.insertedLoads 79329 # Number of loads inserted to the mem dependence unit. 1753system.cpu2.memDep0.insertedStores 37643 # Number of stores inserted to the mem dependence unit. 1754system.cpu2.memDep0.conflictingLoads 37867 # Number of conflicting loads. 1755system.cpu2.memDep0.conflictingStores 32593 # Number of conflicting stores. 1756system.cpu2.iq.iqInstsAdded 232899 # Number of instructions added to the IQ (excludes non-spec) 1757system.cpu2.iq.iqNonSpecInstsAdded 6340 # Number of non-speculative instructions added to the IQ 1758system.cpu2.iq.iqInstsIssued 234900 # Number of instructions issued 1759system.cpu2.iq.iqSquashedInstsIssued 101 # Number of squashed instructions issued 1760system.cpu2.iq.iqSquashedInstsExamined 11011 # Number of squashed instructions iterated over during squash; mainly for profiling 1761system.cpu2.iq.iqSquashedOperandsExamined 10850 # Number of squashed operands that are examined and possibly removed from graph 1762system.cpu2.iq.iqSquashedNonSpecRemoved 602 # Number of squashed non-spec instructions that were removed 1763system.cpu2.iq.issued_per_cycle::samples 172005 # Number of insts issued each cycle 1764system.cpu2.iq.issued_per_cycle::mean 1.365658 # Number of insts issued each cycle 1765system.cpu2.iq.issued_per_cycle::stdev 1.313804 # Number of insts issued each cycle 1766system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 1767system.cpu2.iq.issued_per_cycle::0 68443 39.79% 39.79% # Number of insts issued each cycle 1768system.cpu2.iq.issued_per_cycle::1 22432 13.04% 52.83% # Number of insts issued each cycle 1769system.cpu2.iq.issued_per_cycle::2 37853 22.01% 74.84% # Number of insts issued each cycle 1770system.cpu2.iq.issued_per_cycle::3 38470 22.37% 97.21% # Number of insts issued each cycle 1771system.cpu2.iq.issued_per_cycle::4 3247 1.89% 99.09% # Number of insts issued each cycle 1772system.cpu2.iq.issued_per_cycle::5 1167 0.68% 99.77% # Number of insts issued each cycle 1773system.cpu2.iq.issued_per_cycle::6 279 0.16% 99.93% # Number of insts issued each cycle 1774system.cpu2.iq.issued_per_cycle::7 57 0.03% 99.97% # Number of insts issued each cycle 1775system.cpu2.iq.issued_per_cycle::8 57 0.03% 100.00% # Number of insts issued each cycle 1776system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1777system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1778system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 1779system.cpu2.iq.issued_per_cycle::total 172005 # Number of insts issued each cycle 1780system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 1781system.cpu2.iq.fu_full::IntAlu 17 6.01% 6.01% # attempts to use FU when none available 1782system.cpu2.iq.fu_full::IntMult 0 0.00% 6.01% # attempts to use FU when none available 1783system.cpu2.iq.fu_full::IntDiv 0 0.00% 6.01% # attempts to use FU when none available 1784system.cpu2.iq.fu_full::FloatAdd 0 0.00% 6.01% # attempts to use FU when none available 1785system.cpu2.iq.fu_full::FloatCmp 0 0.00% 6.01% # attempts to use FU when none available 1786system.cpu2.iq.fu_full::FloatCvt 0 0.00% 6.01% # attempts to use FU when none available 1787system.cpu2.iq.fu_full::FloatMult 0 0.00% 6.01% # attempts to use FU when none available 1788system.cpu2.iq.fu_full::FloatDiv 0 0.00% 6.01% # attempts to use FU when none available 1789system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 6.01% # attempts to use FU when none available 1790system.cpu2.iq.fu_full::SimdAdd 0 0.00% 6.01% # attempts to use FU when none available 1791system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 6.01% # attempts to use FU when none available 1792system.cpu2.iq.fu_full::SimdAlu 0 0.00% 6.01% # attempts to use FU when none available 1793system.cpu2.iq.fu_full::SimdCmp 0 0.00% 6.01% # attempts to use FU when none available 1794system.cpu2.iq.fu_full::SimdCvt 0 0.00% 6.01% # attempts to use FU when none available 1795system.cpu2.iq.fu_full::SimdMisc 0 0.00% 6.01% # attempts to use FU when none available 1796system.cpu2.iq.fu_full::SimdMult 0 0.00% 6.01% # attempts to use FU when none available 1797system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 6.01% # attempts to use FU when none available 1798system.cpu2.iq.fu_full::SimdShift 0 0.00% 6.01% # attempts to use FU when none available 1799system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 6.01% # attempts to use FU when none available 1800system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 6.01% # attempts to use FU when none available 1801system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 6.01% # attempts to use FU when none available 1802system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 6.01% # attempts to use FU when none available 1803system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 6.01% # attempts to use FU when none available 1804system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 6.01% # attempts to use FU when none available 1805system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 6.01% # attempts to use FU when none available 1806system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 6.01% # attempts to use FU when none available 1807system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 6.01% # attempts to use FU when none available 1808system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.01% # attempts to use FU when none available 1809system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 6.01% # attempts to use FU when none available 1810system.cpu2.iq.fu_full::MemRead 56 19.79% 25.80% # attempts to use FU when none available 1811system.cpu2.iq.fu_full::MemWrite 210 74.20% 100.00% # attempts to use FU when none available 1812system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 1813system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 1814system.cpu2.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 1815system.cpu2.iq.FU_type_0::IntAlu 114350 48.68% 48.68% # Type of FU issued 1816system.cpu2.iq.FU_type_0::IntMult 0 0.00% 48.68% # Type of FU issued 1817system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 48.68% # Type of FU issued 1818system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 48.68% # Type of FU issued 1819system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 48.68% # Type of FU issued 1820system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 48.68% # Type of FU issued 1821system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 48.68% # Type of FU issued 1822system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 48.68% # Type of FU issued 1823system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 48.68% # Type of FU issued 1824system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 48.68% # Type of FU issued 1825system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 48.68% # Type of FU issued 1826system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 48.68% # Type of FU issued 1827system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 48.68% # Type of FU issued 1828system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 48.68% # Type of FU issued 1829system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 48.68% # Type of FU issued 1830system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 48.68% # Type of FU issued 1831system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 48.68% # Type of FU issued 1832system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 48.68% # Type of FU issued 1833system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.68% # Type of FU issued 1834system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 48.68% # Type of FU issued 1835system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.68% # Type of FU issued 1836system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.68% # Type of FU issued 1837system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.68% # Type of FU issued 1838system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.68% # Type of FU issued 1839system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.68% # Type of FU issued 1840system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.68% # Type of FU issued 1841system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 48.68% # Type of FU issued 1842system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.68% # Type of FU issued 1843system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.68% # Type of FU issued 1844system.cpu2.iq.FU_type_0::MemRead 83592 35.59% 84.27% # Type of FU issued 1845system.cpu2.iq.FU_type_0::MemWrite 36958 15.73% 100.00% # Type of FU issued 1846system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 1847system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 1848system.cpu2.iq.FU_type_0::total 234900 # Type of FU issued 1849system.cpu2.iq.rate 1.322873 # Inst issue rate 1850system.cpu2.iq.fu_busy_cnt 283 # FU busy when requested 1851system.cpu2.iq.fu_busy_rate 0.001205 # FU busy rate (busy events/executed inst) 1852system.cpu2.iq.int_inst_queue_reads 642189 # Number of integer instruction queue reads 1853system.cpu2.iq.int_inst_queue_writes 250297 # Number of integer instruction queue writes 1854system.cpu2.iq.int_inst_queue_wakeup_accesses 233099 # Number of integer instruction queue wakeup accesses 1855system.cpu2.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads 1856system.cpu2.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes 1857system.cpu2.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses 1858system.cpu2.iq.int_alu_accesses 235183 # Number of integer alu accesses 1859system.cpu2.iq.fp_alu_accesses 0 # Number of floating point alu accesses 1860system.cpu2.iew.lsq.thread0.forwLoads 32324 # Number of loads that had data forwarded from stores 1861system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 1862system.cpu2.iew.lsq.thread0.squashedLoads 2477 # Number of loads squashed 1863system.cpu2.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed 1864system.cpu2.iew.lsq.thread0.memOrderViolation 47 # Number of memory ordering violations 1865system.cpu2.iew.lsq.thread0.squashedStores 1468 # Number of stores squashed 1866system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 1867system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 1868system.cpu2.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 1869system.cpu2.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked 1870system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle 1871system.cpu2.iew.iewSquashCycles 2417 # Number of cycles IEW is squashing 1872system.cpu2.iew.iewBlockCycles 878 # Number of cycles IEW is blocking 1873system.cpu2.iew.iewUnblockCycles 50 # Number of cycles IEW is unblocking 1874system.cpu2.iew.iewDispatchedInsts 278010 # Number of instructions dispatched to IQ 1875system.cpu2.iew.iewDispSquashedInsts 351 # Number of squashed instructions skipped by dispatch 1876system.cpu2.iew.iewDispLoadInsts 79329 # Number of dispatched load instructions 1877system.cpu2.iew.iewDispStoreInsts 37643 # Number of dispatched store instructions 1878system.cpu2.iew.iewDispNonSpecInsts 1071 # Number of dispatched non-speculative instructions 1879system.cpu2.iew.iewIQFullEvents 50 # Number of times the IQ has become full, causing a stall 1880system.cpu2.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 1881system.cpu2.iew.memOrderViolationEvents 47 # Number of memory order violations 1882system.cpu2.iew.predictedTakenIncorrect 457 # Number of branches that were predicted taken incorrectly 1883system.cpu2.iew.predictedNotTakenIncorrect 973 # Number of branches that were predicted not taken incorrectly 1884system.cpu2.iew.branchMispredicts 1430 # Number of branch mispredicts detected at execute 1885system.cpu2.iew.iewExecutedInsts 233765 # Number of executed instructions 1886system.cpu2.iew.iewExecLoadInsts 78300 # Number of load instructions executed 1887system.cpu2.iew.iewExecSquashedInsts 1135 # Number of squashed instructions skipped in execute 1888system.cpu2.iew.exec_swp 0 # number of swp insts executed 1889system.cpu2.iew.exec_nop 38771 # number of nop insts executed 1890system.cpu2.iew.exec_refs 115173 # number of memory reference insts executed 1891system.cpu2.iew.exec_branches 48001 # Number of branches executed 1892system.cpu2.iew.exec_stores 36873 # Number of stores executed 1893system.cpu2.iew.exec_rate 1.316482 # Inst execution rate 1894system.cpu2.iew.wb_sent 233385 # cumulative count of insts sent to commit 1895system.cpu2.iew.wb_count 233099 # cumulative count of insts written-back 1896system.cpu2.iew.wb_producers 131933 # num instructions producing a value 1897system.cpu2.iew.wb_consumers 136641 # num instructions consuming a value 1898system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 1899system.cpu2.iew.wb_rate 1.312731 # insts written-back per cycle 1900system.cpu2.iew.wb_fanout 0.965545 # average fanout of values written-back 1901system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 1902system.cpu2.commit.commitSquashedInsts 12656 # The number of squashed insts skipped by commit 1903system.cpu2.commit.commitNonSpecStalls 5738 # The number of times commit has been forced to stall to communicate backwards 1904system.cpu2.commit.branchMispredicts 1303 # The number of times a branch was mispredicted 1905system.cpu2.commit.committed_per_cycle::samples 161811 # Number of insts commited each cycle 1906system.cpu2.commit.committed_per_cycle::mean 1.639889 # Number of insts commited each cycle 1907system.cpu2.commit.committed_per_cycle::stdev 2.021157 # Number of insts commited each cycle 1908system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 1909system.cpu2.commit.committed_per_cycle::0 66196 40.91% 40.91% # Number of insts commited each cycle 1910system.cpu2.commit.committed_per_cycle::1 46128 28.51% 69.42% # Number of insts commited each cycle 1911system.cpu2.commit.committed_per_cycle::2 6098 3.77% 73.19% # Number of insts commited each cycle 1912system.cpu2.commit.committed_per_cycle::3 6657 4.11% 77.30% # Number of insts commited each cycle 1913system.cpu2.commit.committed_per_cycle::4 1558 0.96% 78.26% # Number of insts commited each cycle 1914system.cpu2.commit.committed_per_cycle::5 32865 20.31% 98.57% # Number of insts commited each cycle 1915system.cpu2.commit.committed_per_cycle::6 486 0.30% 98.87% # Number of insts commited each cycle 1916system.cpu2.commit.committed_per_cycle::7 1000 0.62% 99.49% # Number of insts commited each cycle 1917system.cpu2.commit.committed_per_cycle::8 823 0.51% 100.00% # Number of insts commited each cycle 1918system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 1919system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 1920system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 1921system.cpu2.commit.committed_per_cycle::total 161811 # Number of insts commited each cycle 1922system.cpu2.commit.committedInsts 265352 # Number of instructions committed 1923system.cpu2.commit.committedOps 265352 # Number of ops (including micro ops) committed 1924system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed 1925system.cpu2.commit.refs 113027 # Number of memory references committed 1926system.cpu2.commit.loads 76852 # Number of loads committed 1927system.cpu2.commit.membars 5022 # Number of memory barriers committed 1928system.cpu2.commit.branches 47160 # Number of branches committed 1929system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions. 1930system.cpu2.commit.int_insts 182307 # Number of committed integer instructions. 1931system.cpu2.commit.function_calls 322 # Number of function calls committed. 1932system.cpu2.commit.bw_lim_events 823 # number cycles where commit BW limit reached 1933system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits 1934system.cpu2.rob.rob_reads 438409 # The number of ROB reads 1935system.cpu2.rob.rob_writes 558438 # The number of ROB writes 1936system.cpu2.timesIdled 223 # Number of times that the entire CPU went into an idle state and unscheduled itself 1937system.cpu2.idleCycles 5563 # Total number of cycles that the CPU has spent unscheduled due to idling 1938system.cpu2.quiesceCycles 44482 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1939system.cpu2.committedInsts 222382 # Number of Instructions Simulated 1940system.cpu2.committedOps 222382 # Number of Ops (including micro ops) Simulated 1941system.cpu2.committedInsts_total 222382 # Number of Instructions Simulated 1942system.cpu2.cpi 0.798482 # CPI: Cycles Per Instruction 1943system.cpu2.cpi_total 0.798482 # CPI: Total CPI of All Threads 1944system.cpu2.ipc 1.252377 # IPC: Instructions Per Cycle 1945system.cpu2.ipc_total 1.252377 # IPC: Total IPC of All Threads 1946system.cpu2.int_regfile_reads 404230 # number of integer regfile reads 1947system.cpu2.int_regfile_writes 188772 # number of integer regfile writes 1948system.cpu2.fp_regfile_writes 64 # number of floating regfile writes 1949system.cpu2.misc_regfile_reads 116736 # number of misc regfile reads 1950system.cpu2.misc_regfile_writes 648 # number of misc regfile writes 1951system.cpu2.icache.tags.replacements 317 # number of replacements 1952system.cpu2.icache.tags.tagsinuse 82.236554 # Cycle average of tags in use 1953system.cpu2.icache.tags.total_refs 19258 # Total number of references to valid blocks. 1954system.cpu2.icache.tags.sampled_refs 425 # Sample count of references to valid blocks. 1955system.cpu2.icache.tags.avg_refs 45.312941 # Average number of references to valid blocks. 1956system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1957system.cpu2.icache.tags.occ_blocks::cpu2.inst 82.236554 # Average occupied blocks per requestor 1958system.cpu2.icache.tags.occ_percent::cpu2.inst 0.160618 # Average percentage of cache occupancy 1959system.cpu2.icache.tags.occ_percent::total 0.160618 # Average percentage of cache occupancy 1960system.cpu2.icache.tags.occ_task_id_blocks::1024 108 # Occupied blocks per task id 1961system.cpu2.icache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id 1962system.cpu2.icache.tags.age_task_id_blocks_1024::1 97 # Occupied blocks per task id 1963system.cpu2.icache.tags.occ_task_id_percent::1024 0.210938 # Percentage of cache occupancy per task id 1964system.cpu2.icache.tags.tag_accesses 20176 # Number of tag accesses 1965system.cpu2.icache.tags.data_accesses 20176 # Number of data accesses 1966system.cpu2.icache.ReadReq_hits::cpu2.inst 19258 # number of ReadReq hits 1967system.cpu2.icache.ReadReq_hits::total 19258 # number of ReadReq hits 1968system.cpu2.icache.demand_hits::cpu2.inst 19258 # number of demand (read+write) hits 1969system.cpu2.icache.demand_hits::total 19258 # number of demand (read+write) hits 1970system.cpu2.icache.overall_hits::cpu2.inst 19258 # number of overall hits 1971system.cpu2.icache.overall_hits::total 19258 # number of overall hits 1972system.cpu2.icache.ReadReq_misses::cpu2.inst 493 # number of ReadReq misses 1973system.cpu2.icache.ReadReq_misses::total 493 # number of ReadReq misses 1974system.cpu2.icache.demand_misses::cpu2.inst 493 # number of demand (read+write) misses 1975system.cpu2.icache.demand_misses::total 493 # number of demand (read+write) misses 1976system.cpu2.icache.overall_misses::cpu2.inst 493 # number of overall misses 1977system.cpu2.icache.overall_misses::total 493 # number of overall misses 1978system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 11621241 # number of ReadReq miss cycles 1979system.cpu2.icache.ReadReq_miss_latency::total 11621241 # number of ReadReq miss cycles 1980system.cpu2.icache.demand_miss_latency::cpu2.inst 11621241 # number of demand (read+write) miss cycles 1981system.cpu2.icache.demand_miss_latency::total 11621241 # number of demand (read+write) miss cycles 1982system.cpu2.icache.overall_miss_latency::cpu2.inst 11621241 # number of overall miss cycles 1983system.cpu2.icache.overall_miss_latency::total 11621241 # number of overall miss cycles 1984system.cpu2.icache.ReadReq_accesses::cpu2.inst 19751 # number of ReadReq accesses(hits+misses) 1985system.cpu2.icache.ReadReq_accesses::total 19751 # number of ReadReq accesses(hits+misses) 1986system.cpu2.icache.demand_accesses::cpu2.inst 19751 # number of demand (read+write) accesses 1987system.cpu2.icache.demand_accesses::total 19751 # number of demand (read+write) accesses 1988system.cpu2.icache.overall_accesses::cpu2.inst 19751 # number of overall (read+write) accesses 1989system.cpu2.icache.overall_accesses::total 19751 # number of overall (read+write) accesses 1990system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.024961 # miss rate for ReadReq accesses 1991system.cpu2.icache.ReadReq_miss_rate::total 0.024961 # miss rate for ReadReq accesses 1992system.cpu2.icache.demand_miss_rate::cpu2.inst 0.024961 # miss rate for demand accesses 1993system.cpu2.icache.demand_miss_rate::total 0.024961 # miss rate for demand accesses 1994system.cpu2.icache.overall_miss_rate::cpu2.inst 0.024961 # miss rate for overall accesses 1995system.cpu2.icache.overall_miss_rate::total 0.024961 # miss rate for overall accesses 1996system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 23572.496957 # average ReadReq miss latency 1997system.cpu2.icache.ReadReq_avg_miss_latency::total 23572.496957 # average ReadReq miss latency 1998system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 23572.496957 # average overall miss latency 1999system.cpu2.icache.demand_avg_miss_latency::total 23572.496957 # average overall miss latency 2000system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 23572.496957 # average overall miss latency 2001system.cpu2.icache.overall_avg_miss_latency::total 23572.496957 # average overall miss latency 2002system.cpu2.icache.blocked_cycles::no_mshrs 85 # number of cycles access was blocked 2003system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2004system.cpu2.icache.blocked::no_mshrs 1 # number of cycles access was blocked 2005system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked 2006system.cpu2.icache.avg_blocked_cycles::no_mshrs 85 # average number of cycles each access was blocked 2007system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2008system.cpu2.icache.fast_writes 0 # number of fast writes performed 2009system.cpu2.icache.cache_copies 0 # number of cache copies performed 2010system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 68 # number of ReadReq MSHR hits 2011system.cpu2.icache.ReadReq_mshr_hits::total 68 # number of ReadReq MSHR hits 2012system.cpu2.icache.demand_mshr_hits::cpu2.inst 68 # number of demand (read+write) MSHR hits 2013system.cpu2.icache.demand_mshr_hits::total 68 # number of demand (read+write) MSHR hits 2014system.cpu2.icache.overall_mshr_hits::cpu2.inst 68 # number of overall MSHR hits 2015system.cpu2.icache.overall_mshr_hits::total 68 # number of overall MSHR hits 2016system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 425 # number of ReadReq MSHR misses 2017system.cpu2.icache.ReadReq_mshr_misses::total 425 # number of ReadReq MSHR misses 2018system.cpu2.icache.demand_mshr_misses::cpu2.inst 425 # number of demand (read+write) MSHR misses 2019system.cpu2.icache.demand_mshr_misses::total 425 # number of demand (read+write) MSHR misses 2020system.cpu2.icache.overall_mshr_misses::cpu2.inst 425 # number of overall MSHR misses 2021system.cpu2.icache.overall_mshr_misses::total 425 # number of overall MSHR misses 2022system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 9301005 # number of ReadReq MSHR miss cycles 2023system.cpu2.icache.ReadReq_mshr_miss_latency::total 9301005 # number of ReadReq MSHR miss cycles 2024system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 9301005 # number of demand (read+write) MSHR miss cycles 2025system.cpu2.icache.demand_mshr_miss_latency::total 9301005 # number of demand (read+write) MSHR miss cycles 2026system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 9301005 # number of overall MSHR miss cycles 2027system.cpu2.icache.overall_mshr_miss_latency::total 9301005 # number of overall MSHR miss cycles 2028system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.021518 # mshr miss rate for ReadReq accesses 2029system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.021518 # mshr miss rate for ReadReq accesses 2030system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.021518 # mshr miss rate for demand accesses 2031system.cpu2.icache.demand_mshr_miss_rate::total 0.021518 # mshr miss rate for demand accesses 2032system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.021518 # mshr miss rate for overall accesses 2033system.cpu2.icache.overall_mshr_miss_rate::total 0.021518 # mshr miss rate for overall accesses 2034system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 21884.717647 # average ReadReq mshr miss latency 2035system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 21884.717647 # average ReadReq mshr miss latency 2036system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 21884.717647 # average overall mshr miss latency 2037system.cpu2.icache.demand_avg_mshr_miss_latency::total 21884.717647 # average overall mshr miss latency 2038system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 21884.717647 # average overall mshr miss latency 2039system.cpu2.icache.overall_avg_mshr_miss_latency::total 21884.717647 # average overall mshr miss latency 2040system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate 2041system.cpu2.dcache.tags.replacements 0 # number of replacements 2042system.cpu2.dcache.tags.tagsinuse 26.142591 # Cycle average of tags in use 2043system.cpu2.dcache.tags.total_refs 42207 # Total number of references to valid blocks. 2044system.cpu2.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks. 2045system.cpu2.dcache.tags.avg_refs 1507.392857 # Average number of references to valid blocks. 2046system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 2047system.cpu2.dcache.tags.occ_blocks::cpu2.data 26.142591 # Average occupied blocks per requestor 2048system.cpu2.dcache.tags.occ_percent::cpu2.data 0.051060 # Average percentage of cache occupancy 2049system.cpu2.dcache.tags.occ_percent::total 0.051060 # Average percentage of cache occupancy 2050system.cpu2.dcache.tags.occ_task_id_blocks::1024 28 # Occupied blocks per task id 2051system.cpu2.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id 2052system.cpu2.dcache.tags.occ_task_id_percent::1024 0.054688 # Percentage of cache occupancy per task id 2053system.cpu2.dcache.tags.tag_accesses 328789 # Number of tag accesses 2054system.cpu2.dcache.tags.data_accesses 328789 # Number of data accesses 2055system.cpu2.dcache.ReadReq_hits::cpu2.data 45613 # number of ReadReq hits 2056system.cpu2.dcache.ReadReq_hits::total 45613 # number of ReadReq hits 2057system.cpu2.dcache.WriteReq_hits::cpu2.data 35966 # number of WriteReq hits 2058system.cpu2.dcache.WriteReq_hits::total 35966 # number of WriteReq hits 2059system.cpu2.dcache.SwapReq_hits::cpu2.data 13 # number of SwapReq hits 2060system.cpu2.dcache.SwapReq_hits::total 13 # number of SwapReq hits 2061system.cpu2.dcache.demand_hits::cpu2.data 81579 # number of demand (read+write) hits 2062system.cpu2.dcache.demand_hits::total 81579 # number of demand (read+write) hits 2063system.cpu2.dcache.overall_hits::cpu2.data 81579 # number of overall hits 2064system.cpu2.dcache.overall_hits::total 81579 # number of overall hits 2065system.cpu2.dcache.ReadReq_misses::cpu2.data 346 # number of ReadReq misses 2066system.cpu2.dcache.ReadReq_misses::total 346 # number of ReadReq misses 2067system.cpu2.dcache.WriteReq_misses::cpu2.data 139 # number of WriteReq misses 2068system.cpu2.dcache.WriteReq_misses::total 139 # number of WriteReq misses 2069system.cpu2.dcache.SwapReq_misses::cpu2.data 57 # number of SwapReq misses 2070system.cpu2.dcache.SwapReq_misses::total 57 # number of SwapReq misses 2071system.cpu2.dcache.demand_misses::cpu2.data 485 # number of demand (read+write) misses 2072system.cpu2.dcache.demand_misses::total 485 # number of demand (read+write) misses 2073system.cpu2.dcache.overall_misses::cpu2.data 485 # number of overall misses 2074system.cpu2.dcache.overall_misses::total 485 # number of overall misses 2075system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 5532140 # number of ReadReq miss cycles 2076system.cpu2.dcache.ReadReq_miss_latency::total 5532140 # number of ReadReq miss cycles 2077system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 3131011 # number of WriteReq miss cycles 2078system.cpu2.dcache.WriteReq_miss_latency::total 3131011 # number of WriteReq miss cycles 2079system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 555006 # number of SwapReq miss cycles 2080system.cpu2.dcache.SwapReq_miss_latency::total 555006 # number of SwapReq miss cycles 2081system.cpu2.dcache.demand_miss_latency::cpu2.data 8663151 # number of demand (read+write) miss cycles 2082system.cpu2.dcache.demand_miss_latency::total 8663151 # number of demand (read+write) miss cycles 2083system.cpu2.dcache.overall_miss_latency::cpu2.data 8663151 # number of overall miss cycles 2084system.cpu2.dcache.overall_miss_latency::total 8663151 # number of overall miss cycles 2085system.cpu2.dcache.ReadReq_accesses::cpu2.data 45959 # number of ReadReq accesses(hits+misses) 2086system.cpu2.dcache.ReadReq_accesses::total 45959 # number of ReadReq accesses(hits+misses) 2087system.cpu2.dcache.WriteReq_accesses::cpu2.data 36105 # number of WriteReq accesses(hits+misses) 2088system.cpu2.dcache.WriteReq_accesses::total 36105 # number of WriteReq accesses(hits+misses) 2089system.cpu2.dcache.SwapReq_accesses::cpu2.data 70 # number of SwapReq accesses(hits+misses) 2090system.cpu2.dcache.SwapReq_accesses::total 70 # number of SwapReq accesses(hits+misses) 2091system.cpu2.dcache.demand_accesses::cpu2.data 82064 # number of demand (read+write) accesses 2092system.cpu2.dcache.demand_accesses::total 82064 # number of demand (read+write) accesses 2093system.cpu2.dcache.overall_accesses::cpu2.data 82064 # number of overall (read+write) accesses 2094system.cpu2.dcache.overall_accesses::total 82064 # number of overall (read+write) accesses 2095system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.007528 # miss rate for ReadReq accesses 2096system.cpu2.dcache.ReadReq_miss_rate::total 0.007528 # miss rate for ReadReq accesses 2097system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.003850 # miss rate for WriteReq accesses 2098system.cpu2.dcache.WriteReq_miss_rate::total 0.003850 # miss rate for WriteReq accesses 2099system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.814286 # miss rate for SwapReq accesses 2100system.cpu2.dcache.SwapReq_miss_rate::total 0.814286 # miss rate for SwapReq accesses 2101system.cpu2.dcache.demand_miss_rate::cpu2.data 0.005910 # miss rate for demand accesses 2102system.cpu2.dcache.demand_miss_rate::total 0.005910 # miss rate for demand accesses 2103system.cpu2.dcache.overall_miss_rate::cpu2.data 0.005910 # miss rate for overall accesses 2104system.cpu2.dcache.overall_miss_rate::total 0.005910 # miss rate for overall accesses 2105system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 15988.843931 # average ReadReq miss latency 2106system.cpu2.dcache.ReadReq_avg_miss_latency::total 15988.843931 # average ReadReq miss latency 2107system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 22525.258993 # average WriteReq miss latency 2108system.cpu2.dcache.WriteReq_avg_miss_latency::total 22525.258993 # average WriteReq miss latency 2109system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 9736.947368 # average SwapReq miss latency 2110system.cpu2.dcache.SwapReq_avg_miss_latency::total 9736.947368 # average SwapReq miss latency 2111system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 17862.167010 # average overall miss latency 2112system.cpu2.dcache.demand_avg_miss_latency::total 17862.167010 # average overall miss latency 2113system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 17862.167010 # average overall miss latency 2114system.cpu2.dcache.overall_avg_miss_latency::total 17862.167010 # average overall miss latency 2115system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2116system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2117system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 2118system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked 2119system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2120system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2121system.cpu2.dcache.fast_writes 0 # number of fast writes performed 2122system.cpu2.dcache.cache_copies 0 # number of cache copies performed 2123system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 184 # number of ReadReq MSHR hits 2124system.cpu2.dcache.ReadReq_mshr_hits::total 184 # number of ReadReq MSHR hits 2125system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 33 # number of WriteReq MSHR hits 2126system.cpu2.dcache.WriteReq_mshr_hits::total 33 # number of WriteReq MSHR hits 2127system.cpu2.dcache.demand_mshr_hits::cpu2.data 217 # number of demand (read+write) MSHR hits 2128system.cpu2.dcache.demand_mshr_hits::total 217 # number of demand (read+write) MSHR hits 2129system.cpu2.dcache.overall_mshr_hits::cpu2.data 217 # number of overall MSHR hits 2130system.cpu2.dcache.overall_mshr_hits::total 217 # number of overall MSHR hits 2131system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 162 # number of ReadReq MSHR misses 2132system.cpu2.dcache.ReadReq_mshr_misses::total 162 # number of ReadReq MSHR misses 2133system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 106 # number of WriteReq MSHR misses 2134system.cpu2.dcache.WriteReq_mshr_misses::total 106 # number of WriteReq MSHR misses 2135system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 57 # number of SwapReq MSHR misses 2136system.cpu2.dcache.SwapReq_mshr_misses::total 57 # number of SwapReq MSHR misses 2137system.cpu2.dcache.demand_mshr_misses::cpu2.data 268 # number of demand (read+write) MSHR misses 2138system.cpu2.dcache.demand_mshr_misses::total 268 # number of demand (read+write) MSHR misses 2139system.cpu2.dcache.overall_mshr_misses::cpu2.data 268 # number of overall MSHR misses 2140system.cpu2.dcache.overall_mshr_misses::total 268 # number of overall MSHR misses 2141system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1488769 # number of ReadReq MSHR miss cycles 2142system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1488769 # number of ReadReq MSHR miss cycles 2143system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1526989 # number of WriteReq MSHR miss cycles 2144system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1526989 # number of WriteReq MSHR miss cycles 2145system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 440994 # number of SwapReq MSHR miss cycles 2146system.cpu2.dcache.SwapReq_mshr_miss_latency::total 440994 # number of SwapReq MSHR miss cycles 2147system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3015758 # number of demand (read+write) MSHR miss cycles 2148system.cpu2.dcache.demand_mshr_miss_latency::total 3015758 # number of demand (read+write) MSHR miss cycles 2149system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3015758 # number of overall MSHR miss cycles 2150system.cpu2.dcache.overall_mshr_miss_latency::total 3015758 # number of overall MSHR miss cycles 2151system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003525 # mshr miss rate for ReadReq accesses 2152system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003525 # mshr miss rate for ReadReq accesses 2153system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.002936 # mshr miss rate for WriteReq accesses 2154system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.002936 # mshr miss rate for WriteReq accesses 2155system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.814286 # mshr miss rate for SwapReq accesses 2156system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.814286 # mshr miss rate for SwapReq accesses 2157system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.003266 # mshr miss rate for demand accesses 2158system.cpu2.dcache.demand_mshr_miss_rate::total 0.003266 # mshr miss rate for demand accesses 2159system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.003266 # mshr miss rate for overall accesses 2160system.cpu2.dcache.overall_mshr_miss_rate::total 0.003266 # mshr miss rate for overall accesses 2161system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 9189.932099 # average ReadReq mshr miss latency 2162system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 9189.932099 # average ReadReq mshr miss latency 2163system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 14405.556604 # average WriteReq mshr miss latency 2164system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 14405.556604 # average WriteReq mshr miss latency 2165system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 7736.736842 # average SwapReq mshr miss latency 2166system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 7736.736842 # average SwapReq mshr miss latency 2167system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 11252.828358 # average overall mshr miss latency 2168system.cpu2.dcache.demand_avg_mshr_miss_latency::total 11252.828358 # average overall mshr miss latency 2169system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 11252.828358 # average overall mshr miss latency 2170system.cpu2.dcache.overall_avg_mshr_miss_latency::total 11252.828358 # average overall mshr miss latency 2171system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 2172system.cpu3.branchPred.lookups 52302 # Number of BP lookups 2173system.cpu3.branchPred.condPredicted 49590 # Number of conditional branches predicted 2174system.cpu3.branchPred.condIncorrect 1266 # Number of conditional branches incorrect 2175system.cpu3.branchPred.BTBLookups 46219 # Number of BTB lookups 2176system.cpu3.branchPred.BTBHits 45467 # Number of BTB hits 2177system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 2178system.cpu3.branchPred.BTBHitPct 98.372963 # BTB Hit Percentage 2179system.cpu3.branchPred.usedRAS 659 # Number of times the RAS was used to get a target. 2180system.cpu3.branchPred.RASInCorrect 232 # Number of incorrect RAS predictions. 2181system.cpu3.numCycles 177222 # number of cpu cycles simulated 2182system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started 2183system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed 2184system.cpu3.fetch.icacheStallCycles 28851 # Number of cycles fetch is stalled on an Icache miss 2185system.cpu3.fetch.Insts 291591 # Number of instructions fetch has processed 2186system.cpu3.fetch.Branches 52302 # Number of branches that fetch encountered 2187system.cpu3.fetch.predictedBranches 46126 # Number of branches that fetch has predicted taken 2188system.cpu3.fetch.Cycles 103443 # Number of cycles fetch has run and was not squashing or blocked 2189system.cpu3.fetch.SquashCycles 3689 # Number of cycles fetch has spent squashing 2190system.cpu3.fetch.BlockedCycles 32601 # Number of cycles fetch has spent blocked 2191system.cpu3.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 2192system.cpu3.fetch.NoActiveThreadStallCycles 7775 # Number of stall cycles due to no active thread to fetch from 2193system.cpu3.fetch.PendingTrapStallCycles 799 # Number of stall cycles due to pending traps 2194system.cpu3.fetch.CacheLines 20565 # Number of cache lines fetched 2195system.cpu3.fetch.IcacheSquashes 250 # Number of outstanding Icache misses that were squashed 2196system.cpu3.fetch.rateDist::samples 175820 # Number of instructions fetched each cycle (Total) 2197system.cpu3.fetch.rateDist::mean 1.658463 # Number of instructions fetched each cycle (Total) 2198system.cpu3.fetch.rateDist::stdev 2.129406 # Number of instructions fetched each cycle (Total) 2199system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 2200system.cpu3.fetch.rateDist::0 72377 41.17% 41.17% # Number of instructions fetched each cycle (Total) 2201system.cpu3.fetch.rateDist::1 52818 30.04% 71.21% # Number of instructions fetched each cycle (Total) 2202system.cpu3.fetch.rateDist::2 6573 3.74% 74.94% # Number of instructions fetched each cycle (Total) 2203system.cpu3.fetch.rateDist::3 3193 1.82% 76.76% # Number of instructions fetched each cycle (Total) 2204system.cpu3.fetch.rateDist::4 659 0.37% 77.14% # Number of instructions fetched each cycle (Total) 2205system.cpu3.fetch.rateDist::5 35007 19.91% 97.05% # Number of instructions fetched each cycle (Total) 2206system.cpu3.fetch.rateDist::6 1204 0.68% 97.73% # Number of instructions fetched each cycle (Total) 2207system.cpu3.fetch.rateDist::7 759 0.43% 98.16% # Number of instructions fetched each cycle (Total) 2208system.cpu3.fetch.rateDist::8 3230 1.84% 100.00% # Number of instructions fetched each cycle (Total) 2209system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 2210system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 2211system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 2212system.cpu3.fetch.rateDist::total 175820 # Number of instructions fetched each cycle (Total) 2213system.cpu3.fetch.branchRate 0.295121 # Number of branch fetches per cycle 2214system.cpu3.fetch.rate 1.645343 # Number of inst fetches per cycle 2215system.cpu3.decode.IdleCycles 34477 # Number of cycles decode is idle 2216system.cpu3.decode.BlockedCycles 28631 # Number of cycles decode is blocked 2217system.cpu3.decode.RunCycles 97078 # Number of cycles decode is running 2218system.cpu3.decode.UnblockCycles 5513 # Number of cycles decode is unblocking 2219system.cpu3.decode.SquashCycles 2346 # Number of cycles decode is squashing 2220system.cpu3.decode.DecodedInsts 288057 # Number of instructions handled by decode 2221system.cpu3.rename.SquashCycles 2346 # Number of cycles rename is squashing 2222system.cpu3.rename.IdleCycles 35172 # Number of cycles rename is idle 2223system.cpu3.rename.BlockCycles 16067 # Number of cycles rename is blocking 2224system.cpu3.rename.serializeStallCycles 11804 # count of cycles rename stalled for serializing inst 2225system.cpu3.rename.RunCycles 91834 # Number of cycles rename is running 2226system.cpu3.rename.UnblockCycles 10822 # Number of cycles rename is unblocking 2227system.cpu3.rename.RenamedInsts 285905 # Number of instructions processed by rename 2228system.cpu3.rename.IQFullEvents 4 # Number of times rename has blocked due to IQ full 2229system.cpu3.rename.LSQFullEvents 21 # Number of times rename has blocked due to LSQ full 2230system.cpu3.rename.RenamedOperands 199357 # Number of destination operands rename has renamed 2231system.cpu3.rename.RenameLookups 546724 # Number of register rename lookups that rename has made 2232system.cpu3.rename.int_rename_lookups 424837 # Number of integer rename lookups 2233system.cpu3.rename.CommittedMaps 186591 # Number of HB maps that are committed 2234system.cpu3.rename.UndoneMaps 12766 # Number of HB maps that are undone due to squashing 2235system.cpu3.rename.serializingInsts 1101 # count of serializing insts renamed 2236system.cpu3.rename.tempSerializingInsts 1226 # count of temporary serializing insts renamed 2237system.cpu3.rename.skidInsts 13474 # count of insts added to the skid buffer 2238system.cpu3.memDep0.insertedLoads 80900 # Number of loads inserted to the mem dependence unit. 2239system.cpu3.memDep0.insertedStores 38213 # Number of stores inserted to the mem dependence unit. 2240system.cpu3.memDep0.conflictingLoads 38893 # Number of conflicting loads. 2241system.cpu3.memDep0.conflictingStores 33161 # Number of conflicting stores. 2242system.cpu3.iq.iqInstsAdded 236458 # Number of instructions added to the IQ (excludes non-spec) 2243system.cpu3.iq.iqNonSpecInstsAdded 6797 # Number of non-speculative instructions added to the IQ 2244system.cpu3.iq.iqInstsIssued 238990 # Number of instructions issued 2245system.cpu3.iq.iqSquashedInstsIssued 102 # Number of squashed instructions issued 2246system.cpu3.iq.iqSquashedInstsExamined 10736 # Number of squashed instructions iterated over during squash; mainly for profiling 2247system.cpu3.iq.iqSquashedOperandsExamined 10730 # Number of squashed operands that are examined and possibly removed from graph 2248system.cpu3.iq.iqSquashedNonSpecRemoved 584 # Number of squashed non-spec instructions that were removed 2249system.cpu3.iq.issued_per_cycle::samples 175820 # Number of insts issued each cycle 2250system.cpu3.iq.issued_per_cycle::mean 1.359288 # Number of insts issued each cycle 2251system.cpu3.iq.issued_per_cycle::stdev 1.308373 # Number of insts issued each cycle 2252system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 2253system.cpu3.iq.issued_per_cycle::0 69781 39.69% 39.69% # Number of insts issued each cycle 2254system.cpu3.iq.issued_per_cycle::1 23810 13.54% 53.23% # Number of insts issued each cycle 2255system.cpu3.iq.issued_per_cycle::2 38390 21.83% 75.07% # Number of insts issued each cycle 2256system.cpu3.iq.issued_per_cycle::3 39046 22.21% 97.27% # Number of insts issued each cycle 2257system.cpu3.iq.issued_per_cycle::4 3247 1.85% 99.12% # Number of insts issued each cycle 2258system.cpu3.iq.issued_per_cycle::5 1173 0.67% 99.79% # Number of insts issued each cycle 2259system.cpu3.iq.issued_per_cycle::6 261 0.15% 99.94% # Number of insts issued each cycle 2260system.cpu3.iq.issued_per_cycle::7 53 0.03% 99.97% # Number of insts issued each cycle 2261system.cpu3.iq.issued_per_cycle::8 59 0.03% 100.00% # Number of insts issued each cycle 2262system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 2263system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 2264system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 2265system.cpu3.iq.issued_per_cycle::total 175820 # Number of insts issued each cycle 2266system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 2267system.cpu3.iq.fu_full::IntAlu 17 6.20% 6.20% # attempts to use FU when none available 2268system.cpu3.iq.fu_full::IntMult 0 0.00% 6.20% # attempts to use FU when none available 2269system.cpu3.iq.fu_full::IntDiv 0 0.00% 6.20% # attempts to use FU when none available 2270system.cpu3.iq.fu_full::FloatAdd 0 0.00% 6.20% # attempts to use FU when none available 2271system.cpu3.iq.fu_full::FloatCmp 0 0.00% 6.20% # attempts to use FU when none available 2272system.cpu3.iq.fu_full::FloatCvt 0 0.00% 6.20% # attempts to use FU when none available 2273system.cpu3.iq.fu_full::FloatMult 0 0.00% 6.20% # attempts to use FU when none available 2274system.cpu3.iq.fu_full::FloatDiv 0 0.00% 6.20% # attempts to use FU when none available 2275system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 6.20% # attempts to use FU when none available 2276system.cpu3.iq.fu_full::SimdAdd 0 0.00% 6.20% # attempts to use FU when none available 2277system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 6.20% # attempts to use FU when none available 2278system.cpu3.iq.fu_full::SimdAlu 0 0.00% 6.20% # attempts to use FU when none available 2279system.cpu3.iq.fu_full::SimdCmp 0 0.00% 6.20% # attempts to use FU when none available 2280system.cpu3.iq.fu_full::SimdCvt 0 0.00% 6.20% # attempts to use FU when none available 2281system.cpu3.iq.fu_full::SimdMisc 0 0.00% 6.20% # attempts to use FU when none available 2282system.cpu3.iq.fu_full::SimdMult 0 0.00% 6.20% # attempts to use FU when none available 2283system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 6.20% # attempts to use FU when none available 2284system.cpu3.iq.fu_full::SimdShift 0 0.00% 6.20% # attempts to use FU when none available 2285system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 6.20% # attempts to use FU when none available 2286system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 6.20% # attempts to use FU when none available 2287system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 6.20% # attempts to use FU when none available 2288system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 6.20% # attempts to use FU when none available 2289system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 6.20% # attempts to use FU when none available 2290system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 6.20% # attempts to use FU when none available 2291system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 6.20% # attempts to use FU when none available 2292system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 6.20% # attempts to use FU when none available 2293system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 6.20% # attempts to use FU when none available 2294system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.20% # attempts to use FU when none available 2295system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 6.20% # attempts to use FU when none available 2296system.cpu3.iq.fu_full::MemRead 47 17.15% 23.36% # attempts to use FU when none available 2297system.cpu3.iq.fu_full::MemWrite 210 76.64% 100.00% # attempts to use FU when none available 2298system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 2299system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 2300system.cpu3.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 2301system.cpu3.iq.FU_type_0::IntAlu 115815 48.46% 48.46% # Type of FU issued 2302system.cpu3.iq.FU_type_0::IntMult 0 0.00% 48.46% # Type of FU issued 2303system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 48.46% # Type of FU issued 2304system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 48.46% # Type of FU issued 2305system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 48.46% # Type of FU issued 2306system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 48.46% # Type of FU issued 2307system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 48.46% # Type of FU issued 2308system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 48.46% # Type of FU issued 2309system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 48.46% # Type of FU issued 2310system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 48.46% # Type of FU issued 2311system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 48.46% # Type of FU issued 2312system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 48.46% # Type of FU issued 2313system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 48.46% # Type of FU issued 2314system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 48.46% # Type of FU issued 2315system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 48.46% # Type of FU issued 2316system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 48.46% # Type of FU issued 2317system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 48.46% # Type of FU issued 2318system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 48.46% # Type of FU issued 2319system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.46% # Type of FU issued 2320system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 48.46% # Type of FU issued 2321system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.46% # Type of FU issued 2322system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.46% # Type of FU issued 2323system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.46% # Type of FU issued 2324system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.46% # Type of FU issued 2325system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.46% # Type of FU issued 2326system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.46% # Type of FU issued 2327system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 48.46% # Type of FU issued 2328system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.46% # Type of FU issued 2329system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.46% # Type of FU issued 2330system.cpu3.iq.FU_type_0::MemRead 85668 35.85% 84.31% # Type of FU issued 2331system.cpu3.iq.FU_type_0::MemWrite 37507 15.69% 100.00% # Type of FU issued 2332system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 2333system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 2334system.cpu3.iq.FU_type_0::total 238990 # Type of FU issued 2335system.cpu3.iq.rate 1.348535 # Inst issue rate 2336system.cpu3.iq.fu_busy_cnt 274 # FU busy when requested 2337system.cpu3.iq.fu_busy_rate 0.001146 # FU busy rate (busy events/executed inst) 2338system.cpu3.iq.int_inst_queue_reads 654176 # Number of integer instruction queue reads 2339system.cpu3.iq.int_inst_queue_writes 254038 # Number of integer instruction queue writes 2340system.cpu3.iq.int_inst_queue_wakeup_accesses 237197 # Number of integer instruction queue wakeup accesses 2341system.cpu3.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads 2342system.cpu3.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes 2343system.cpu3.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses 2344system.cpu3.iq.int_alu_accesses 239264 # Number of integer alu accesses 2345system.cpu3.iq.fp_alu_accesses 0 # Number of floating point alu accesses 2346system.cpu3.iew.lsq.thread0.forwLoads 32896 # Number of loads that had data forwarded from stores 2347system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 2348system.cpu3.iew.lsq.thread0.squashedLoads 2413 # Number of loads squashed 2349system.cpu3.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed 2350system.cpu3.iew.lsq.thread0.memOrderViolation 47 # Number of memory ordering violations 2351system.cpu3.iew.lsq.thread0.squashedStores 1461 # Number of stores squashed 2352system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 2353system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 2354system.cpu3.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 2355system.cpu3.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked 2356system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle 2357system.cpu3.iew.iewSquashCycles 2346 # Number of cycles IEW is squashing 2358system.cpu3.iew.iewBlockCycles 674 # Number of cycles IEW is blocking 2359system.cpu3.iew.iewUnblockCycles 43 # Number of cycles IEW is unblocking 2360system.cpu3.iew.iewDispatchedInsts 283043 # Number of instructions dispatched to IQ 2361system.cpu3.iew.iewDispSquashedInsts 388 # Number of squashed instructions skipped by dispatch 2362system.cpu3.iew.iewDispLoadInsts 80900 # Number of dispatched load instructions 2363system.cpu3.iew.iewDispStoreInsts 38213 # Number of dispatched store instructions 2364system.cpu3.iew.iewDispNonSpecInsts 1061 # Number of dispatched non-speculative instructions 2365system.cpu3.iew.iewIQFullEvents 42 # Number of times the IQ has become full, causing a stall 2366system.cpu3.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 2367system.cpu3.iew.memOrderViolationEvents 47 # Number of memory order violations 2368system.cpu3.iew.predictedTakenIncorrect 456 # Number of branches that were predicted taken incorrectly 2369system.cpu3.iew.predictedNotTakenIncorrect 929 # Number of branches that were predicted not taken incorrectly 2370system.cpu3.iew.branchMispredicts 1385 # Number of branch mispredicts detected at execute 2371system.cpu3.iew.iewExecutedInsts 237848 # Number of executed instructions 2372system.cpu3.iew.iewExecLoadInsts 79902 # Number of load instructions executed 2373system.cpu3.iew.iewExecSquashedInsts 1142 # Number of squashed instructions skipped in execute 2374system.cpu3.iew.exec_swp 0 # number of swp insts executed 2375system.cpu3.iew.exec_nop 39788 # number of nop insts executed 2376system.cpu3.iew.exec_refs 117326 # number of memory reference insts executed 2377system.cpu3.iew.exec_branches 49028 # Number of branches executed 2378system.cpu3.iew.exec_stores 37424 # Number of stores executed 2379system.cpu3.iew.exec_rate 1.342091 # Inst execution rate 2380system.cpu3.iew.wb_sent 237481 # cumulative count of insts sent to commit 2381system.cpu3.iew.wb_count 237197 # cumulative count of insts written-back 2382system.cpu3.iew.wb_producers 134032 # num instructions producing a value 2383system.cpu3.iew.wb_consumers 138708 # num instructions consuming a value 2384system.cpu3.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 2385system.cpu3.iew.wb_rate 1.338417 # insts written-back per cycle 2386system.cpu3.iew.wb_fanout 0.966289 # average fanout of values written-back 2387system.cpu3.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 2388system.cpu3.commit.commitSquashedInsts 12298 # The number of squashed insts skipped by commit 2389system.cpu3.commit.commitNonSpecStalls 6213 # The number of times commit has been forced to stall to communicate backwards 2390system.cpu3.commit.branchMispredicts 1266 # The number of times a branch was mispredicted 2391system.cpu3.commit.committed_per_cycle::samples 165699 # Number of insts commited each cycle 2392system.cpu3.commit.committed_per_cycle::mean 1.633836 # Number of insts commited each cycle 2393system.cpu3.commit.committed_per_cycle::stdev 2.016583 # Number of insts commited each cycle 2394system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 2395system.cpu3.commit.committed_per_cycle::0 68017 41.05% 41.05% # Number of insts commited each cycle 2396system.cpu3.commit.committed_per_cycle::1 47143 28.45% 69.50% # Number of insts commited each cycle 2397system.cpu3.commit.committed_per_cycle::2 6068 3.66% 73.16% # Number of insts commited each cycle 2398system.cpu3.commit.committed_per_cycle::3 7148 4.31% 77.48% # Number of insts commited each cycle 2399system.cpu3.commit.committed_per_cycle::4 1577 0.95% 78.43% # Number of insts commited each cycle 2400system.cpu3.commit.committed_per_cycle::5 33420 20.17% 98.60% # Number of insts commited each cycle 2401system.cpu3.commit.committed_per_cycle::6 508 0.31% 98.90% # Number of insts commited each cycle 2402system.cpu3.commit.committed_per_cycle::7 998 0.60% 99.51% # Number of insts commited each cycle 2403system.cpu3.commit.committed_per_cycle::8 820 0.49% 100.00% # Number of insts commited each cycle 2404system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 2405system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 2406system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 2407system.cpu3.commit.committed_per_cycle::total 165699 # Number of insts commited each cycle 2408system.cpu3.commit.committedInsts 270725 # Number of instructions committed 2409system.cpu3.commit.committedOps 270725 # Number of ops (including micro ops) committed 2410system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed 2411system.cpu3.commit.refs 115239 # Number of memory references committed 2412system.cpu3.commit.loads 78487 # Number of loads committed 2413system.cpu3.commit.membars 5499 # Number of memory barriers committed 2414system.cpu3.commit.branches 48212 # Number of branches committed 2415system.cpu3.commit.fp_insts 0 # Number of committed floating point instructions. 2416system.cpu3.commit.int_insts 185574 # Number of committed integer instructions. 2417system.cpu3.commit.function_calls 322 # Number of function calls committed. 2418system.cpu3.commit.bw_lim_events 820 # number cycles where commit BW limit reached 2419system.cpu3.commit.bw_limited 0 # number of insts not committed due to BW limits 2420system.cpu3.rob.rob_reads 447315 # The number of ROB reads 2421system.cpu3.rob.rob_writes 568397 # The number of ROB writes 2422system.cpu3.timesIdled 211 # Number of times that the entire CPU went into an idle state and unscheduled itself 2423system.cpu3.idleCycles 1402 # Total number of cycles that the CPU has spent unscheduled due to idling 2424system.cpu3.quiesceCycles 44828 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 2425system.cpu3.committedInsts 226224 # Number of Instructions Simulated 2426system.cpu3.committedOps 226224 # Number of Ops (including micro ops) Simulated 2427system.cpu3.committedInsts_total 226224 # Number of Instructions Simulated 2428system.cpu3.cpi 0.783392 # CPI: Cycles Per Instruction 2429system.cpu3.cpi_total 0.783392 # CPI: Total CPI of All Threads 2430system.cpu3.ipc 1.276501 # IPC: Instructions Per Cycle 2431system.cpu3.ipc_total 1.276501 # IPC: Total IPC of All Threads 2432system.cpu3.int_regfile_reads 410473 # number of integer regfile reads 2433system.cpu3.int_regfile_writes 191353 # number of integer regfile writes 2434system.cpu3.fp_regfile_writes 64 # number of floating regfile writes 2435system.cpu3.misc_regfile_reads 118878 # number of misc regfile reads 2436system.cpu3.misc_regfile_writes 648 # number of misc regfile writes 2437system.cpu3.icache.tags.replacements 319 # number of replacements 2438system.cpu3.icache.tags.tagsinuse 79.942822 # Cycle average of tags in use 2439system.cpu3.icache.tags.total_refs 20090 # Total number of references to valid blocks. 2440system.cpu3.icache.tags.sampled_refs 429 # Sample count of references to valid blocks. 2441system.cpu3.icache.tags.avg_refs 46.829837 # Average number of references to valid blocks. 2442system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 2443system.cpu3.icache.tags.occ_blocks::cpu3.inst 79.942822 # Average occupied blocks per requestor 2444system.cpu3.icache.tags.occ_percent::cpu3.inst 0.156138 # Average percentage of cache occupancy 2445system.cpu3.icache.tags.occ_percent::total 0.156138 # Average percentage of cache occupancy 2446system.cpu3.icache.tags.occ_task_id_blocks::1024 110 # Occupied blocks per task id 2447system.cpu3.icache.tags.age_task_id_blocks_1024::0 10 # Occupied blocks per task id 2448system.cpu3.icache.tags.age_task_id_blocks_1024::1 100 # Occupied blocks per task id 2449system.cpu3.icache.tags.occ_task_id_percent::1024 0.214844 # Percentage of cache occupancy per task id 2450system.cpu3.icache.tags.tag_accesses 20994 # Number of tag accesses 2451system.cpu3.icache.tags.data_accesses 20994 # Number of data accesses 2452system.cpu3.icache.ReadReq_hits::cpu3.inst 20090 # number of ReadReq hits 2453system.cpu3.icache.ReadReq_hits::total 20090 # number of ReadReq hits 2454system.cpu3.icache.demand_hits::cpu3.inst 20090 # number of demand (read+write) hits 2455system.cpu3.icache.demand_hits::total 20090 # number of demand (read+write) hits 2456system.cpu3.icache.overall_hits::cpu3.inst 20090 # number of overall hits 2457system.cpu3.icache.overall_hits::total 20090 # number of overall hits 2458system.cpu3.icache.ReadReq_misses::cpu3.inst 475 # number of ReadReq misses 2459system.cpu3.icache.ReadReq_misses::total 475 # number of ReadReq misses 2460system.cpu3.icache.demand_misses::cpu3.inst 475 # number of demand (read+write) misses 2461system.cpu3.icache.demand_misses::total 475 # number of demand (read+write) misses 2462system.cpu3.icache.overall_misses::cpu3.inst 475 # number of overall misses 2463system.cpu3.icache.overall_misses::total 475 # number of overall misses 2464system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 6449745 # number of ReadReq miss cycles 2465system.cpu3.icache.ReadReq_miss_latency::total 6449745 # number of ReadReq miss cycles 2466system.cpu3.icache.demand_miss_latency::cpu3.inst 6449745 # number of demand (read+write) miss cycles 2467system.cpu3.icache.demand_miss_latency::total 6449745 # number of demand (read+write) miss cycles 2468system.cpu3.icache.overall_miss_latency::cpu3.inst 6449745 # number of overall miss cycles 2469system.cpu3.icache.overall_miss_latency::total 6449745 # number of overall miss cycles 2470system.cpu3.icache.ReadReq_accesses::cpu3.inst 20565 # number of ReadReq accesses(hits+misses) 2471system.cpu3.icache.ReadReq_accesses::total 20565 # number of ReadReq accesses(hits+misses) 2472system.cpu3.icache.demand_accesses::cpu3.inst 20565 # number of demand (read+write) accesses 2473system.cpu3.icache.demand_accesses::total 20565 # number of demand (read+write) accesses 2474system.cpu3.icache.overall_accesses::cpu3.inst 20565 # number of overall (read+write) accesses 2475system.cpu3.icache.overall_accesses::total 20565 # number of overall (read+write) accesses 2476system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.023097 # miss rate for ReadReq accesses 2477system.cpu3.icache.ReadReq_miss_rate::total 0.023097 # miss rate for ReadReq accesses 2478system.cpu3.icache.demand_miss_rate::cpu3.inst 0.023097 # miss rate for demand accesses 2479system.cpu3.icache.demand_miss_rate::total 0.023097 # miss rate for demand accesses 2480system.cpu3.icache.overall_miss_rate::cpu3.inst 0.023097 # miss rate for overall accesses 2481system.cpu3.icache.overall_miss_rate::total 0.023097 # miss rate for overall accesses 2482system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13578.410526 # average ReadReq miss latency 2483system.cpu3.icache.ReadReq_avg_miss_latency::total 13578.410526 # average ReadReq miss latency 2484system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13578.410526 # average overall miss latency 2485system.cpu3.icache.demand_avg_miss_latency::total 13578.410526 # average overall miss latency 2486system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13578.410526 # average overall miss latency 2487system.cpu3.icache.overall_avg_miss_latency::total 13578.410526 # average overall miss latency 2488system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2489system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2490system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked 2491system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked 2492system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2493system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2494system.cpu3.icache.fast_writes 0 # number of fast writes performed 2495system.cpu3.icache.cache_copies 0 # number of cache copies performed 2496system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 46 # number of ReadReq MSHR hits 2497system.cpu3.icache.ReadReq_mshr_hits::total 46 # number of ReadReq MSHR hits 2498system.cpu3.icache.demand_mshr_hits::cpu3.inst 46 # number of demand (read+write) MSHR hits 2499system.cpu3.icache.demand_mshr_hits::total 46 # number of demand (read+write) MSHR hits 2500system.cpu3.icache.overall_mshr_hits::cpu3.inst 46 # number of overall MSHR hits 2501system.cpu3.icache.overall_mshr_hits::total 46 # number of overall MSHR hits 2502system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 429 # number of ReadReq MSHR misses 2503system.cpu3.icache.ReadReq_mshr_misses::total 429 # number of ReadReq MSHR misses 2504system.cpu3.icache.demand_mshr_misses::cpu3.inst 429 # number of demand (read+write) MSHR misses 2505system.cpu3.icache.demand_mshr_misses::total 429 # number of demand (read+write) MSHR misses 2506system.cpu3.icache.overall_mshr_misses::cpu3.inst 429 # number of overall MSHR misses 2507system.cpu3.icache.overall_mshr_misses::total 429 # number of overall MSHR misses 2508system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 5223755 # number of ReadReq MSHR miss cycles 2509system.cpu3.icache.ReadReq_mshr_miss_latency::total 5223755 # number of ReadReq MSHR miss cycles 2510system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 5223755 # number of demand (read+write) MSHR miss cycles 2511system.cpu3.icache.demand_mshr_miss_latency::total 5223755 # number of demand (read+write) MSHR miss cycles 2512system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 5223755 # number of overall MSHR miss cycles 2513system.cpu3.icache.overall_mshr_miss_latency::total 5223755 # number of overall MSHR miss cycles 2514system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.020861 # mshr miss rate for ReadReq accesses 2515system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.020861 # mshr miss rate for ReadReq accesses 2516system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.020861 # mshr miss rate for demand accesses 2517system.cpu3.icache.demand_mshr_miss_rate::total 0.020861 # mshr miss rate for demand accesses 2518system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.020861 # mshr miss rate for overall accesses 2519system.cpu3.icache.overall_mshr_miss_rate::total 0.020861 # mshr miss rate for overall accesses 2520system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12176.585082 # average ReadReq mshr miss latency 2521system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 12176.585082 # average ReadReq mshr miss latency 2522system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12176.585082 # average overall mshr miss latency 2523system.cpu3.icache.demand_avg_mshr_miss_latency::total 12176.585082 # average overall mshr miss latency 2524system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12176.585082 # average overall mshr miss latency 2525system.cpu3.icache.overall_avg_mshr_miss_latency::total 12176.585082 # average overall mshr miss latency 2526system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate 2527system.cpu3.dcache.tags.replacements 0 # number of replacements 2528system.cpu3.dcache.tags.tagsinuse 24.692248 # Cycle average of tags in use 2529system.cpu3.dcache.tags.total_refs 42769 # Total number of references to valid blocks. 2530system.cpu3.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks. 2531system.cpu3.dcache.tags.avg_refs 1527.464286 # Average number of references to valid blocks. 2532system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 2533system.cpu3.dcache.tags.occ_blocks::cpu3.data 24.692248 # Average occupied blocks per requestor 2534system.cpu3.dcache.tags.occ_percent::cpu3.data 0.048227 # Average percentage of cache occupancy 2535system.cpu3.dcache.tags.occ_percent::total 0.048227 # Average percentage of cache occupancy 2536system.cpu3.dcache.tags.occ_task_id_blocks::1024 28 # Occupied blocks per task id 2537system.cpu3.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id 2538system.cpu3.dcache.tags.occ_task_id_percent::1024 0.054688 # Percentage of cache occupancy per task id 2539system.cpu3.dcache.tags.tag_accesses 335202 # Number of tag accesses 2540system.cpu3.dcache.tags.data_accesses 335202 # Number of data accesses 2541system.cpu3.dcache.ReadReq_hits::cpu3.data 46656 # number of ReadReq hits 2542system.cpu3.dcache.ReadReq_hits::total 46656 # number of ReadReq hits 2543system.cpu3.dcache.WriteReq_hits::cpu3.data 36553 # number of WriteReq hits 2544system.cpu3.dcache.WriteReq_hits::total 36553 # number of WriteReq hits 2545system.cpu3.dcache.SwapReq_hits::cpu3.data 14 # number of SwapReq hits 2546system.cpu3.dcache.SwapReq_hits::total 14 # number of SwapReq hits 2547system.cpu3.dcache.demand_hits::cpu3.data 83209 # number of demand (read+write) hits 2548system.cpu3.dcache.demand_hits::total 83209 # number of demand (read+write) hits 2549system.cpu3.dcache.overall_hits::cpu3.data 83209 # number of overall hits 2550system.cpu3.dcache.overall_hits::total 83209 # number of overall hits 2551system.cpu3.dcache.ReadReq_misses::cpu3.data 333 # number of ReadReq misses 2552system.cpu3.dcache.ReadReq_misses::total 333 # number of ReadReq misses 2553system.cpu3.dcache.WriteReq_misses::cpu3.data 131 # number of WriteReq misses 2554system.cpu3.dcache.WriteReq_misses::total 131 # number of WriteReq misses 2555system.cpu3.dcache.SwapReq_misses::cpu3.data 54 # number of SwapReq misses 2556system.cpu3.dcache.SwapReq_misses::total 54 # number of SwapReq misses 2557system.cpu3.dcache.demand_misses::cpu3.data 464 # number of demand (read+write) misses 2558system.cpu3.dcache.demand_misses::total 464 # number of demand (read+write) misses 2559system.cpu3.dcache.overall_misses::cpu3.data 464 # number of overall misses 2560system.cpu3.dcache.overall_misses::total 464 # number of overall misses 2561system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 4248100 # number of ReadReq miss cycles 2562system.cpu3.dcache.ReadReq_miss_latency::total 4248100 # number of ReadReq miss cycles 2563system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 3351512 # number of WriteReq miss cycles 2564system.cpu3.dcache.WriteReq_miss_latency::total 3351512 # number of WriteReq miss cycles 2565system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 492006 # number of SwapReq miss cycles 2566system.cpu3.dcache.SwapReq_miss_latency::total 492006 # number of SwapReq miss cycles 2567system.cpu3.dcache.demand_miss_latency::cpu3.data 7599612 # number of demand (read+write) miss cycles 2568system.cpu3.dcache.demand_miss_latency::total 7599612 # number of demand (read+write) miss cycles 2569system.cpu3.dcache.overall_miss_latency::cpu3.data 7599612 # number of overall miss cycles 2570system.cpu3.dcache.overall_miss_latency::total 7599612 # number of overall miss cycles 2571system.cpu3.dcache.ReadReq_accesses::cpu3.data 46989 # number of ReadReq accesses(hits+misses) 2572system.cpu3.dcache.ReadReq_accesses::total 46989 # number of ReadReq accesses(hits+misses) 2573system.cpu3.dcache.WriteReq_accesses::cpu3.data 36684 # number of WriteReq accesses(hits+misses) 2574system.cpu3.dcache.WriteReq_accesses::total 36684 # number of WriteReq accesses(hits+misses) 2575system.cpu3.dcache.SwapReq_accesses::cpu3.data 68 # number of SwapReq accesses(hits+misses) 2576system.cpu3.dcache.SwapReq_accesses::total 68 # number of SwapReq accesses(hits+misses) 2577system.cpu3.dcache.demand_accesses::cpu3.data 83673 # number of demand (read+write) accesses 2578system.cpu3.dcache.demand_accesses::total 83673 # number of demand (read+write) accesses 2579system.cpu3.dcache.overall_accesses::cpu3.data 83673 # number of overall (read+write) accesses 2580system.cpu3.dcache.overall_accesses::total 83673 # number of overall (read+write) accesses 2581system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.007087 # miss rate for ReadReq accesses 2582system.cpu3.dcache.ReadReq_miss_rate::total 0.007087 # miss rate for ReadReq accesses 2583system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.003571 # miss rate for WriteReq accesses 2584system.cpu3.dcache.WriteReq_miss_rate::total 0.003571 # miss rate for WriteReq accesses 2585system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.794118 # miss rate for SwapReq accesses 2586system.cpu3.dcache.SwapReq_miss_rate::total 0.794118 # miss rate for SwapReq accesses 2587system.cpu3.dcache.demand_miss_rate::cpu3.data 0.005545 # miss rate for demand accesses 2588system.cpu3.dcache.demand_miss_rate::total 0.005545 # miss rate for demand accesses 2589system.cpu3.dcache.overall_miss_rate::cpu3.data 0.005545 # miss rate for overall accesses 2590system.cpu3.dcache.overall_miss_rate::total 0.005545 # miss rate for overall accesses 2591system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 12757.057057 # average ReadReq miss latency 2592system.cpu3.dcache.ReadReq_avg_miss_latency::total 12757.057057 # average ReadReq miss latency 2593system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 25584.061069 # average WriteReq miss latency 2594system.cpu3.dcache.WriteReq_avg_miss_latency::total 25584.061069 # average WriteReq miss latency 2595system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 9111.222222 # average SwapReq miss latency 2596system.cpu3.dcache.SwapReq_avg_miss_latency::total 9111.222222 # average SwapReq miss latency 2597system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 16378.474138 # average overall miss latency 2598system.cpu3.dcache.demand_avg_miss_latency::total 16378.474138 # average overall miss latency 2599system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 16378.474138 # average overall miss latency 2600system.cpu3.dcache.overall_avg_miss_latency::total 16378.474138 # average overall miss latency 2601system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2602system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2603system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 2604system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked 2605system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2606system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2607system.cpu3.dcache.fast_writes 0 # number of fast writes performed 2608system.cpu3.dcache.cache_copies 0 # number of cache copies performed 2609system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 181 # number of ReadReq MSHR hits 2610system.cpu3.dcache.ReadReq_mshr_hits::total 181 # number of ReadReq MSHR hits 2611system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 31 # number of WriteReq MSHR hits 2612system.cpu3.dcache.WriteReq_mshr_hits::total 31 # number of WriteReq MSHR hits 2613system.cpu3.dcache.demand_mshr_hits::cpu3.data 212 # number of demand (read+write) MSHR hits 2614system.cpu3.dcache.demand_mshr_hits::total 212 # number of demand (read+write) MSHR hits 2615system.cpu3.dcache.overall_mshr_hits::cpu3.data 212 # number of overall MSHR hits 2616system.cpu3.dcache.overall_mshr_hits::total 212 # number of overall MSHR hits 2617system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 152 # number of ReadReq MSHR misses 2618system.cpu3.dcache.ReadReq_mshr_misses::total 152 # number of ReadReq MSHR misses 2619system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 100 # number of WriteReq MSHR misses 2620system.cpu3.dcache.WriteReq_mshr_misses::total 100 # number of WriteReq MSHR misses 2621system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 54 # number of SwapReq MSHR misses 2622system.cpu3.dcache.SwapReq_mshr_misses::total 54 # number of SwapReq MSHR misses 2623system.cpu3.dcache.demand_mshr_misses::cpu3.data 252 # number of demand (read+write) MSHR misses 2624system.cpu3.dcache.demand_mshr_misses::total 252 # number of demand (read+write) MSHR misses 2625system.cpu3.dcache.overall_mshr_misses::cpu3.data 252 # number of overall MSHR misses 2626system.cpu3.dcache.overall_mshr_misses::total 252 # number of overall MSHR misses 2627system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1002524 # number of ReadReq MSHR miss cycles 2628system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1002524 # number of ReadReq MSHR miss cycles 2629system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1408238 # number of WriteReq MSHR miss cycles 2630system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1408238 # number of WriteReq MSHR miss cycles 2631system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 383994 # number of SwapReq MSHR miss cycles 2632system.cpu3.dcache.SwapReq_mshr_miss_latency::total 383994 # number of SwapReq MSHR miss cycles 2633system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 2410762 # number of demand (read+write) MSHR miss cycles 2634system.cpu3.dcache.demand_mshr_miss_latency::total 2410762 # number of demand (read+write) MSHR miss cycles 2635system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 2410762 # number of overall MSHR miss cycles 2636system.cpu3.dcache.overall_mshr_miss_latency::total 2410762 # number of overall MSHR miss cycles 2637system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003235 # mshr miss rate for ReadReq accesses 2638system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003235 # mshr miss rate for ReadReq accesses 2639system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.002726 # mshr miss rate for WriteReq accesses 2640system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.002726 # mshr miss rate for WriteReq accesses 2641system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.794118 # mshr miss rate for SwapReq accesses 2642system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.794118 # mshr miss rate for SwapReq accesses 2643system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.003012 # mshr miss rate for demand accesses 2644system.cpu3.dcache.demand_mshr_miss_rate::total 0.003012 # mshr miss rate for demand accesses 2645system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.003012 # mshr miss rate for overall accesses 2646system.cpu3.dcache.overall_mshr_miss_rate::total 0.003012 # mshr miss rate for overall accesses 2647system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 6595.552632 # average ReadReq mshr miss latency 2648system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 6595.552632 # average ReadReq mshr miss latency 2649system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 14082.380000 # average WriteReq mshr miss latency 2650system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 14082.380000 # average WriteReq mshr miss latency 2651system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 7111 # average SwapReq mshr miss latency 2652system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 7111 # average SwapReq mshr miss latency 2653system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 9566.515873 # average overall mshr miss latency 2654system.cpu3.dcache.demand_avg_mshr_miss_latency::total 9566.515873 # average overall mshr miss latency 2655system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 9566.515873 # average overall mshr miss latency 2656system.cpu3.dcache.overall_avg_mshr_miss_latency::total 9566.515873 # average overall mshr miss latency 2657system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 2658 2659---------- End Simulation Statistics ---------- 2660