stats.txt revision 11960
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.054141 4sim_ticks 54141000500 5final_tick 54141000500 6sim_freq 1000000000000 7host_inst_rate 903691 8host_op_rate 908191 9host_tick_rate 540015581 10host_mem_usage 404604 11host_seconds 100.26 12sim_insts 90602408 13sim_ops 91053639 14system.voltage_domain.voltage 1 15system.clk_domain.clock 1000 16system.physmem.pwrStateResidencyTicks::UNDEFINED 54141000500 17system.physmem.bytes_read::cpu.inst 431323084 18system.physmem.bytes_read::cpu.data 90016598 19system.physmem.bytes_read::total 521339682 20system.physmem.bytes_inst_read::cpu.inst 431323084 21system.physmem.bytes_inst_read::total 431323084 22system.physmem.bytes_written::cpu.data 18908138 23system.physmem.bytes_written::total 18908138 24system.physmem.num_reads::cpu.inst 107830771 25system.physmem.num_reads::cpu.data 22461532 26system.physmem.num_reads::total 130292303 27system.physmem.num_writes::cpu.data 4738868 28system.physmem.num_writes::total 4738868 29system.physmem.bw_read::cpu.inst 7966662604 30system.physmem.bw_read::cpu.data 1662632703 31system.physmem.bw_read::total 9629295306 32system.physmem.bw_inst_read::cpu.inst 7966662604 33system.physmem.bw_inst_read::total 7966662604 34system.physmem.bw_write::cpu.data 349238799 35system.physmem.bw_write::total 349238799 36system.physmem.bw_total::cpu.inst 7966662604 37system.physmem.bw_total::cpu.data 2011871502 38system.physmem.bw_total::total 9978534106 39system.pwrStateResidencyTicks::UNDEFINED 54141000500 40system.cpu_clk_domain.clock 500 41system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 54141000500 42system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 43system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 44system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 45system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 46system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 47system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 48system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 49system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 50system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 51system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 52system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 53system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 54system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 55system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 56system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 57system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 58system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 59system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 60system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 61system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 62system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 63system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 64system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 65system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 66system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 67system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 68system.cpu.dstage2_mmu.stage2_tlb.hits 0 69system.cpu.dstage2_mmu.stage2_tlb.misses 0 70system.cpu.dstage2_mmu.stage2_tlb.accesses 0 71system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 54141000500 72system.cpu.dtb.walker.walks 0 73system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 74system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 75system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 76system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 77system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 78system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 79system.cpu.dtb.walker.walkRequestOrigin::total 0 80system.cpu.dtb.inst_hits 0 81system.cpu.dtb.inst_misses 0 82system.cpu.dtb.read_hits 0 83system.cpu.dtb.read_misses 0 84system.cpu.dtb.write_hits 0 85system.cpu.dtb.write_misses 0 86system.cpu.dtb.flush_tlb 0 87system.cpu.dtb.flush_tlb_mva 0 88system.cpu.dtb.flush_tlb_mva_asid 0 89system.cpu.dtb.flush_tlb_asid 0 90system.cpu.dtb.flush_entries 0 91system.cpu.dtb.align_faults 0 92system.cpu.dtb.prefetch_faults 0 93system.cpu.dtb.domain_faults 0 94system.cpu.dtb.perms_faults 0 95system.cpu.dtb.read_accesses 0 96system.cpu.dtb.write_accesses 0 97system.cpu.dtb.inst_accesses 0 98system.cpu.dtb.hits 0 99system.cpu.dtb.misses 0 100system.cpu.dtb.accesses 0 101system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 54141000500 102system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 103system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 104system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 105system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 106system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 107system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 108system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 109system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 110system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 111system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 112system.cpu.istage2_mmu.stage2_tlb.read_hits 0 113system.cpu.istage2_mmu.stage2_tlb.read_misses 0 114system.cpu.istage2_mmu.stage2_tlb.write_hits 0 115system.cpu.istage2_mmu.stage2_tlb.write_misses 0 116system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 117system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 118system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 119system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 120system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 121system.cpu.istage2_mmu.stage2_tlb.align_faults 0 122system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 123system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 124system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 125system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 126system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 127system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 128system.cpu.istage2_mmu.stage2_tlb.hits 0 129system.cpu.istage2_mmu.stage2_tlb.misses 0 130system.cpu.istage2_mmu.stage2_tlb.accesses 0 131system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 54141000500 132system.cpu.itb.walker.walks 0 133system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 134system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 135system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 136system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 137system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 138system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 139system.cpu.itb.walker.walkRequestOrigin::total 0 140system.cpu.itb.inst_hits 0 141system.cpu.itb.inst_misses 0 142system.cpu.itb.read_hits 0 143system.cpu.itb.read_misses 0 144system.cpu.itb.write_hits 0 145system.cpu.itb.write_misses 0 146system.cpu.itb.flush_tlb 0 147system.cpu.itb.flush_tlb_mva 0 148system.cpu.itb.flush_tlb_mva_asid 0 149system.cpu.itb.flush_tlb_asid 0 150system.cpu.itb.flush_entries 0 151system.cpu.itb.align_faults 0 152system.cpu.itb.prefetch_faults 0 153system.cpu.itb.domain_faults 0 154system.cpu.itb.perms_faults 0 155system.cpu.itb.read_accesses 0 156system.cpu.itb.write_accesses 0 157system.cpu.itb.inst_accesses 0 158system.cpu.itb.hits 0 159system.cpu.itb.misses 0 160system.cpu.itb.accesses 0 161system.cpu.workload.numSyscalls 442 162system.cpu.pwrStateResidencyTicks::ON 54141000500 163system.cpu.numCycles 108282002 164system.cpu.numWorkItemsStarted 0 165system.cpu.numWorkItemsCompleted 0 166system.cpu.committedInsts 90602408 167system.cpu.committedOps 91053639 168system.cpu.num_int_alu_accesses 72326352 169system.cpu.num_fp_alu_accesses 48 170system.cpu.num_func_calls 112245 171system.cpu.num_conditional_control_insts 15520157 172system.cpu.num_int_insts 72326352 173system.cpu.num_fp_insts 48 174system.cpu.num_int_register_reads 124257600 175system.cpu.num_int_register_writes 52782988 176system.cpu.num_fp_register_reads 54 177system.cpu.num_fp_register_writes 30 178system.cpu.num_cc_register_reads 271814243 179system.cpu.num_cc_register_writes 53956115 180system.cpu.num_mem_refs 27220755 181system.cpu.num_load_insts 22475911 182system.cpu.num_store_insts 4744844 183system.cpu.num_idle_cycles 0 184system.cpu.num_busy_cycles 108282002 185system.cpu.not_idle_fraction 1 186system.cpu.idle_fraction 0 187system.cpu.Branches 18732305 188system.cpu.op_class::No_OpClass 0 0.00% 0.00% 189system.cpu.op_class::IntAlu 63822829 70.09% 70.09% 190system.cpu.op_class::IntMult 10474 0.01% 70.10% 191system.cpu.op_class::IntDiv 0 0.00% 70.10% 192system.cpu.op_class::FloatAdd 0 0.00% 70.10% 193system.cpu.op_class::FloatCmp 0 0.00% 70.10% 194system.cpu.op_class::FloatCvt 0 0.00% 70.10% 195system.cpu.op_class::FloatMult 0 0.00% 70.10% 196system.cpu.op_class::FloatMultAcc 0 0.00% 70.10% 197system.cpu.op_class::FloatDiv 0 0.00% 70.10% 198system.cpu.op_class::FloatMisc 0 0.00% 70.10% 199system.cpu.op_class::FloatSqrt 0 0.00% 70.10% 200system.cpu.op_class::SimdAdd 0 0.00% 70.10% 201system.cpu.op_class::SimdAddAcc 0 0.00% 70.10% 202system.cpu.op_class::SimdAlu 0 0.00% 70.10% 203system.cpu.op_class::SimdCmp 0 0.00% 70.10% 204system.cpu.op_class::SimdCvt 0 0.00% 70.10% 205system.cpu.op_class::SimdMisc 0 0.00% 70.10% 206system.cpu.op_class::SimdMult 0 0.00% 70.10% 207system.cpu.op_class::SimdMultAcc 0 0.00% 70.10% 208system.cpu.op_class::SimdShift 0 0.00% 70.10% 209system.cpu.op_class::SimdShiftAcc 0 0.00% 70.10% 210system.cpu.op_class::SimdSqrt 0 0.00% 70.10% 211system.cpu.op_class::SimdFloatAdd 0 0.00% 70.10% 212system.cpu.op_class::SimdFloatAlu 0 0.00% 70.10% 213system.cpu.op_class::SimdFloatCmp 0 0.00% 70.10% 214system.cpu.op_class::SimdFloatCvt 6 0.00% 70.10% 215system.cpu.op_class::SimdFloatDiv 0 0.00% 70.10% 216system.cpu.op_class::SimdFloatMisc 15 0.00% 70.10% 217system.cpu.op_class::SimdFloatMult 0 0.00% 70.10% 218system.cpu.op_class::SimdFloatMultAcc 2 0.00% 70.10% 219system.cpu.op_class::SimdFloatSqrt 0 0.00% 70.10% 220system.cpu.op_class::MemRead 22475905 24.68% 94.79% 221system.cpu.op_class::MemWrite 4744822 5.21% 100.00% 222system.cpu.op_class::FloatMemRead 6 0.00% 100.00% 223system.cpu.op_class::FloatMemWrite 22 0.00% 100.00% 224system.cpu.op_class::IprAccess 0 0.00% 100.00% 225system.cpu.op_class::InstPrefetch 0 0.00% 100.00% 226system.cpu.op_class::total 91054081 227system.membus.snoop_filter.tot_requests 0 228system.membus.snoop_filter.hit_single_requests 0 229system.membus.snoop_filter.hit_multi_requests 0 230system.membus.snoop_filter.tot_snoops 0 231system.membus.snoop_filter.hit_single_snoops 0 232system.membus.snoop_filter.hit_multi_snoops 0 233system.membus.pwrStateResidencyTicks::UNDEFINED 54141000500 234system.membus.trans_dist::ReadReq 130287906 235system.membus.trans_dist::ReadResp 130291793 236system.membus.trans_dist::WriteReq 4734981 237system.membus.trans_dist::WriteResp 4734981 238system.membus.trans_dist::SoftPFReq 510 239system.membus.trans_dist::SoftPFResp 510 240system.membus.trans_dist::LoadLockedReq 3887 241system.membus.trans_dist::StoreCondReq 3887 242system.membus.trans_dist::StoreCondResp 3887 243system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 215661542 244system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 54400800 245system.membus.pkt_count::total 270062342 246system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 431323084 247system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 108924736 248system.membus.pkt_size::total 540247820 249system.membus.snoops 0 250system.membus.snoopTraffic 0 251system.membus.snoop_fanout::samples 135031171 252system.membus.snoop_fanout::mean 0 253system.membus.snoop_fanout::stdev 0 254system.membus.snoop_fanout::underflows 0 0.00% 0.00% 255system.membus.snoop_fanout::0 135031171 100.00% 100.00% 256system.membus.snoop_fanout::1 0 0.00% 100.00% 257system.membus.snoop_fanout::overflows 0 0.00% 100.00% 258system.membus.snoop_fanout::min_value 0 259system.membus.snoop_fanout::max_value 0 260system.membus.snoop_fanout::total 135031171 261 262---------- End Simulation Statistics ---------- 263