stats.txt revision 11507
111507SCurtis.Dunham@arm.com
211507SCurtis.Dunham@arm.com---------- Begin Simulation Statistics ----------
311507SCurtis.Dunham@arm.comsim_seconds                                  0.054141                       # Number of seconds simulated
411507SCurtis.Dunham@arm.comsim_ticks                                 54141000500                       # Number of ticks simulated
511507SCurtis.Dunham@arm.comfinal_tick                                54141000500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
611507SCurtis.Dunham@arm.comsim_freq                                 1000000000000                       # Frequency of simulated ticks
711507SCurtis.Dunham@arm.comhost_inst_rate                                 991860                       # Simulator instruction rate (inst/s)
811507SCurtis.Dunham@arm.comhost_op_rate                                   996799                       # Simulator op (including micro ops) rate (op/s)
911507SCurtis.Dunham@arm.comhost_tick_rate                              592702245                       # Simulator tick rate (ticks/s)
1011507SCurtis.Dunham@arm.comhost_mem_usage                                 389728                       # Number of bytes of host memory used
1111507SCurtis.Dunham@arm.comhost_seconds                                    91.35                       # Real time elapsed on the host
1211507SCurtis.Dunham@arm.comsim_insts                                    90602408                       # Number of instructions simulated
1311507SCurtis.Dunham@arm.comsim_ops                                      91053639                       # Number of ops (including micro ops) simulated
1411507SCurtis.Dunham@arm.comsystem.voltage_domain.voltage                       1                       # Voltage in Volts
1511507SCurtis.Dunham@arm.comsystem.clk_domain.clock                          1000                       # Clock period in ticks
1611507SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu.inst         431323084                       # Number of bytes read from this memory
1711507SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu.data          90016598                       # Number of bytes read from this memory
1811507SCurtis.Dunham@arm.comsystem.physmem.bytes_read::total            521339682                       # Number of bytes read from this memory
1911507SCurtis.Dunham@arm.comsystem.physmem.bytes_inst_read::cpu.inst    431323084                       # Number of instructions bytes read from this memory
2011507SCurtis.Dunham@arm.comsystem.physmem.bytes_inst_read::total       431323084                       # Number of instructions bytes read from this memory
2111507SCurtis.Dunham@arm.comsystem.physmem.bytes_written::cpu.data       18908138                       # Number of bytes written to this memory
2211507SCurtis.Dunham@arm.comsystem.physmem.bytes_written::total          18908138                       # Number of bytes written to this memory
2311507SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu.inst          107830771                       # Number of read requests responded to by this memory
2411507SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu.data           22461532                       # Number of read requests responded to by this memory
2511507SCurtis.Dunham@arm.comsystem.physmem.num_reads::total             130292303                       # Number of read requests responded to by this memory
2611507SCurtis.Dunham@arm.comsystem.physmem.num_writes::cpu.data           4738868                       # Number of write requests responded to by this memory
2711507SCurtis.Dunham@arm.comsystem.physmem.num_writes::total              4738868                       # Number of write requests responded to by this memory
2811507SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu.inst           7966662604                       # Total read bandwidth from this memory (bytes/s)
2911507SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu.data           1662632703                       # Total read bandwidth from this memory (bytes/s)
3011507SCurtis.Dunham@arm.comsystem.physmem.bw_read::total              9629295306                       # Total read bandwidth from this memory (bytes/s)
3111507SCurtis.Dunham@arm.comsystem.physmem.bw_inst_read::cpu.inst      7966662604                       # Instruction read bandwidth from this memory (bytes/s)
3211507SCurtis.Dunham@arm.comsystem.physmem.bw_inst_read::total         7966662604                       # Instruction read bandwidth from this memory (bytes/s)
3311507SCurtis.Dunham@arm.comsystem.physmem.bw_write::cpu.data           349238799                       # Write bandwidth from this memory (bytes/s)
3411507SCurtis.Dunham@arm.comsystem.physmem.bw_write::total              349238799                       # Write bandwidth from this memory (bytes/s)
3511507SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu.inst          7966662604                       # Total bandwidth to/from this memory (bytes/s)
3611507SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu.data          2011871502                       # Total bandwidth to/from this memory (bytes/s)
3711507SCurtis.Dunham@arm.comsystem.physmem.bw_total::total             9978534106                       # Total bandwidth to/from this memory (bytes/s)
3811507SCurtis.Dunham@arm.comsystem.cpu_clk_domain.clock                       500                       # Clock period in ticks
3911507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
4011507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
4111507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
4211507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
4311507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
4411507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
4511507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
4611507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
4711507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
4811507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
4911507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
5011507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
5111507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
5211507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
5311507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
5411507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
5511507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
5611507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
5711507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
5811507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
5911507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
6011507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
6111507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
6211507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
6311507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
6411507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
6511507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
6611507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
6711507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
6811507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walks                         0                       # Table walker walks requested
6911507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
7011507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
7111507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
7211507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
7311507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
7411507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
7511507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
7611507SCurtis.Dunham@arm.comsystem.cpu.dtb.inst_hits                            0                       # ITB inst hits
7711507SCurtis.Dunham@arm.comsystem.cpu.dtb.inst_misses                          0                       # ITB inst misses
7811507SCurtis.Dunham@arm.comsystem.cpu.dtb.read_hits                            0                       # DTB read hits
7911507SCurtis.Dunham@arm.comsystem.cpu.dtb.read_misses                          0                       # DTB read misses
8011507SCurtis.Dunham@arm.comsystem.cpu.dtb.write_hits                           0                       # DTB write hits
8111507SCurtis.Dunham@arm.comsystem.cpu.dtb.write_misses                         0                       # DTB write misses
8211507SCurtis.Dunham@arm.comsystem.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
8311507SCurtis.Dunham@arm.comsystem.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
8411507SCurtis.Dunham@arm.comsystem.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
8511507SCurtis.Dunham@arm.comsystem.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
8611507SCurtis.Dunham@arm.comsystem.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
8711507SCurtis.Dunham@arm.comsystem.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
8811507SCurtis.Dunham@arm.comsystem.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
8911507SCurtis.Dunham@arm.comsystem.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
9011507SCurtis.Dunham@arm.comsystem.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
9111507SCurtis.Dunham@arm.comsystem.cpu.dtb.read_accesses                        0                       # DTB read accesses
9211507SCurtis.Dunham@arm.comsystem.cpu.dtb.write_accesses                       0                       # DTB write accesses
9311507SCurtis.Dunham@arm.comsystem.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
9411507SCurtis.Dunham@arm.comsystem.cpu.dtb.hits                                 0                       # DTB hits
9511507SCurtis.Dunham@arm.comsystem.cpu.dtb.misses                               0                       # DTB misses
9611507SCurtis.Dunham@arm.comsystem.cpu.dtb.accesses                             0                       # DTB accesses
9711507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
9811507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
9911507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
10011507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
10111507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
10211507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
10311507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
10411507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
10511507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
10611507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
10711507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
10811507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
10911507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
11011507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
11111507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
11211507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
11311507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
11411507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
11511507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
11611507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
11711507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
11811507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
11911507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
12011507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
12111507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
12211507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
12311507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
12411507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
12511507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
12611507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walks                         0                       # Table walker walks requested
12711507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
12811507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
12911507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
13011507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
13111507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
13211507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
13311507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
13411507SCurtis.Dunham@arm.comsystem.cpu.itb.inst_hits                            0                       # ITB inst hits
13511507SCurtis.Dunham@arm.comsystem.cpu.itb.inst_misses                          0                       # ITB inst misses
13611507SCurtis.Dunham@arm.comsystem.cpu.itb.read_hits                            0                       # DTB read hits
13711507SCurtis.Dunham@arm.comsystem.cpu.itb.read_misses                          0                       # DTB read misses
13811507SCurtis.Dunham@arm.comsystem.cpu.itb.write_hits                           0                       # DTB write hits
13911507SCurtis.Dunham@arm.comsystem.cpu.itb.write_misses                         0                       # DTB write misses
14011507SCurtis.Dunham@arm.comsystem.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
14111507SCurtis.Dunham@arm.comsystem.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
14211507SCurtis.Dunham@arm.comsystem.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
14311507SCurtis.Dunham@arm.comsystem.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
14411507SCurtis.Dunham@arm.comsystem.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
14511507SCurtis.Dunham@arm.comsystem.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
14611507SCurtis.Dunham@arm.comsystem.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
14711507SCurtis.Dunham@arm.comsystem.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
14811507SCurtis.Dunham@arm.comsystem.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
14911507SCurtis.Dunham@arm.comsystem.cpu.itb.read_accesses                        0                       # DTB read accesses
15011507SCurtis.Dunham@arm.comsystem.cpu.itb.write_accesses                       0                       # DTB write accesses
15111507SCurtis.Dunham@arm.comsystem.cpu.itb.inst_accesses                        0                       # ITB inst accesses
15211507SCurtis.Dunham@arm.comsystem.cpu.itb.hits                                 0                       # DTB hits
15311507SCurtis.Dunham@arm.comsystem.cpu.itb.misses                               0                       # DTB misses
15411507SCurtis.Dunham@arm.comsystem.cpu.itb.accesses                             0                       # DTB accesses
15511507SCurtis.Dunham@arm.comsystem.cpu.workload.num_syscalls                  442                       # Number of system calls
15611507SCurtis.Dunham@arm.comsystem.cpu.numCycles                        108282002                       # number of cpu cycles simulated
15711507SCurtis.Dunham@arm.comsystem.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
15811507SCurtis.Dunham@arm.comsystem.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
15911507SCurtis.Dunham@arm.comsystem.cpu.committedInsts                    90602408                       # Number of instructions committed
16011507SCurtis.Dunham@arm.comsystem.cpu.committedOps                      91053639                       # Number of ops (including micro ops) committed
16111507SCurtis.Dunham@arm.comsystem.cpu.num_int_alu_accesses              72326352                       # Number of integer alu accesses
16211507SCurtis.Dunham@arm.comsystem.cpu.num_fp_alu_accesses                     48                       # Number of float alu accesses
16311507SCurtis.Dunham@arm.comsystem.cpu.num_func_calls                      112245                       # number of times a function call or return occured
16411507SCurtis.Dunham@arm.comsystem.cpu.num_conditional_control_insts     15520157                       # number of instructions that are conditional controls
16511507SCurtis.Dunham@arm.comsystem.cpu.num_int_insts                     72326352                       # number of integer instructions
16611507SCurtis.Dunham@arm.comsystem.cpu.num_fp_insts                            48                       # number of float instructions
16711507SCurtis.Dunham@arm.comsystem.cpu.num_int_register_reads           124257699                       # number of times the integer registers were read
16811507SCurtis.Dunham@arm.comsystem.cpu.num_int_register_writes           52782988                       # number of times the integer registers were written
16911507SCurtis.Dunham@arm.comsystem.cpu.num_fp_register_reads                   54                       # number of times the floating registers were read
17011507SCurtis.Dunham@arm.comsystem.cpu.num_fp_register_writes                  30                       # number of times the floating registers were written
17111507SCurtis.Dunham@arm.comsystem.cpu.num_cc_register_reads            271814243                       # number of times the CC registers were read
17211507SCurtis.Dunham@arm.comsystem.cpu.num_cc_register_writes            53956115                       # number of times the CC registers were written
17311507SCurtis.Dunham@arm.comsystem.cpu.num_mem_refs                      27220755                       # number of memory refs
17411507SCurtis.Dunham@arm.comsystem.cpu.num_load_insts                    22475911                       # Number of load instructions
17511507SCurtis.Dunham@arm.comsystem.cpu.num_store_insts                    4744844                       # Number of store instructions
17611507SCurtis.Dunham@arm.comsystem.cpu.num_idle_cycles                   0.002000                       # Number of idle cycles
17711507SCurtis.Dunham@arm.comsystem.cpu.num_busy_cycles               108282001.998000                       # Number of busy cycles
17811507SCurtis.Dunham@arm.comsystem.cpu.not_idle_fraction                 1.000000                       # Percentage of non-idle cycles
17911507SCurtis.Dunham@arm.comsystem.cpu.idle_fraction                     0.000000                       # Percentage of idle cycles
18011507SCurtis.Dunham@arm.comsystem.cpu.Branches                          18732305                       # Number of branches fetched
18111507SCurtis.Dunham@arm.comsystem.cpu.op_class::No_OpClass                     0      0.00%      0.00% # Class of executed instruction
18211507SCurtis.Dunham@arm.comsystem.cpu.op_class::IntAlu                  63822829     70.09%     70.09% # Class of executed instruction
18311507SCurtis.Dunham@arm.comsystem.cpu.op_class::IntMult                    10474      0.01%     70.10% # Class of executed instruction
18411507SCurtis.Dunham@arm.comsystem.cpu.op_class::IntDiv                         0      0.00%     70.10% # Class of executed instruction
18511507SCurtis.Dunham@arm.comsystem.cpu.op_class::FloatAdd                       0      0.00%     70.10% # Class of executed instruction
18611507SCurtis.Dunham@arm.comsystem.cpu.op_class::FloatCmp                       0      0.00%     70.10% # Class of executed instruction
18711507SCurtis.Dunham@arm.comsystem.cpu.op_class::FloatCvt                       0      0.00%     70.10% # Class of executed instruction
18811507SCurtis.Dunham@arm.comsystem.cpu.op_class::FloatMult                      0      0.00%     70.10% # Class of executed instruction
18911507SCurtis.Dunham@arm.comsystem.cpu.op_class::FloatDiv                       0      0.00%     70.10% # Class of executed instruction
19011507SCurtis.Dunham@arm.comsystem.cpu.op_class::FloatSqrt                      0      0.00%     70.10% # Class of executed instruction
19111507SCurtis.Dunham@arm.comsystem.cpu.op_class::SimdAdd                        0      0.00%     70.10% # Class of executed instruction
19211507SCurtis.Dunham@arm.comsystem.cpu.op_class::SimdAddAcc                     0      0.00%     70.10% # Class of executed instruction
19311507SCurtis.Dunham@arm.comsystem.cpu.op_class::SimdAlu                        0      0.00%     70.10% # Class of executed instruction
19411507SCurtis.Dunham@arm.comsystem.cpu.op_class::SimdCmp                        0      0.00%     70.10% # Class of executed instruction
19511507SCurtis.Dunham@arm.comsystem.cpu.op_class::SimdCvt                        0      0.00%     70.10% # Class of executed instruction
19611507SCurtis.Dunham@arm.comsystem.cpu.op_class::SimdMisc                       0      0.00%     70.10% # Class of executed instruction
19711507SCurtis.Dunham@arm.comsystem.cpu.op_class::SimdMult                       0      0.00%     70.10% # Class of executed instruction
19811507SCurtis.Dunham@arm.comsystem.cpu.op_class::SimdMultAcc                    0      0.00%     70.10% # Class of executed instruction
19911507SCurtis.Dunham@arm.comsystem.cpu.op_class::SimdShift                      0      0.00%     70.10% # Class of executed instruction
20011507SCurtis.Dunham@arm.comsystem.cpu.op_class::SimdShiftAcc                   0      0.00%     70.10% # Class of executed instruction
20111507SCurtis.Dunham@arm.comsystem.cpu.op_class::SimdSqrt                       0      0.00%     70.10% # Class of executed instruction
20211507SCurtis.Dunham@arm.comsystem.cpu.op_class::SimdFloatAdd                   0      0.00%     70.10% # Class of executed instruction
20311507SCurtis.Dunham@arm.comsystem.cpu.op_class::SimdFloatAlu                   0      0.00%     70.10% # Class of executed instruction
20411507SCurtis.Dunham@arm.comsystem.cpu.op_class::SimdFloatCmp                   0      0.00%     70.10% # Class of executed instruction
20511507SCurtis.Dunham@arm.comsystem.cpu.op_class::SimdFloatCvt                   6      0.00%     70.10% # Class of executed instruction
20611507SCurtis.Dunham@arm.comsystem.cpu.op_class::SimdFloatDiv                   0      0.00%     70.10% # Class of executed instruction
20711507SCurtis.Dunham@arm.comsystem.cpu.op_class::SimdFloatMisc                 15      0.00%     70.10% # Class of executed instruction
20811507SCurtis.Dunham@arm.comsystem.cpu.op_class::SimdFloatMult                  0      0.00%     70.10% # Class of executed instruction
20911507SCurtis.Dunham@arm.comsystem.cpu.op_class::SimdFloatMultAcc               2      0.00%     70.10% # Class of executed instruction
21011507SCurtis.Dunham@arm.comsystem.cpu.op_class::SimdFloatSqrt                  0      0.00%     70.10% # Class of executed instruction
21111507SCurtis.Dunham@arm.comsystem.cpu.op_class::MemRead                 22475911     24.68%     94.79% # Class of executed instruction
21211507SCurtis.Dunham@arm.comsystem.cpu.op_class::MemWrite                 4744844      5.21%    100.00% # Class of executed instruction
21311507SCurtis.Dunham@arm.comsystem.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
21411507SCurtis.Dunham@arm.comsystem.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
21511507SCurtis.Dunham@arm.comsystem.cpu.op_class::total                   91054081                       # Class of executed instruction
21611507SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadReq           130287906                       # Transaction distribution
21711507SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadResp          130291793                       # Transaction distribution
21811507SCurtis.Dunham@arm.comsystem.membus.trans_dist::WriteReq            4734981                       # Transaction distribution
21911507SCurtis.Dunham@arm.comsystem.membus.trans_dist::WriteResp           4734981                       # Transaction distribution
22011507SCurtis.Dunham@arm.comsystem.membus.trans_dist::SoftPFReq               510                       # Transaction distribution
22111507SCurtis.Dunham@arm.comsystem.membus.trans_dist::SoftPFResp              510                       # Transaction distribution
22211507SCurtis.Dunham@arm.comsystem.membus.trans_dist::LoadLockedReq          3887                       # Transaction distribution
22311507SCurtis.Dunham@arm.comsystem.membus.trans_dist::StoreCondReq           3887                       # Transaction distribution
22411507SCurtis.Dunham@arm.comsystem.membus.trans_dist::StoreCondResp          3887                       # Transaction distribution
22511507SCurtis.Dunham@arm.comsystem.membus.pkt_count_system.cpu.icache_port::system.physmem.port    215661542                       # Packet count per connected master and slave (bytes)
22611507SCurtis.Dunham@arm.comsystem.membus.pkt_count_system.cpu.dcache_port::system.physmem.port     54400800                       # Packet count per connected master and slave (bytes)
22711507SCurtis.Dunham@arm.comsystem.membus.pkt_count::total              270062342                       # Packet count per connected master and slave (bytes)
22811507SCurtis.Dunham@arm.comsystem.membus.pkt_size_system.cpu.icache_port::system.physmem.port    431323084                       # Cumulative packet size per connected master and slave (bytes)
22911507SCurtis.Dunham@arm.comsystem.membus.pkt_size_system.cpu.dcache_port::system.physmem.port    108924736                       # Cumulative packet size per connected master and slave (bytes)
23011507SCurtis.Dunham@arm.comsystem.membus.pkt_size::total               540247820                       # Cumulative packet size per connected master and slave (bytes)
23111507SCurtis.Dunham@arm.comsystem.membus.snoops                                0                       # Total snoops (count)
23211507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::samples         135031171                       # Request fanout histogram
23311507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::mean             0.798562                       # Request fanout histogram
23411507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::stdev            0.401074                       # Request fanout histogram
23511507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
23611507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::0                27200400     20.14%     20.14% # Request fanout histogram
23711507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::1               107830771     79.86%    100.00% # Request fanout histogram
23811507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
23911507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::min_value               0                       # Request fanout histogram
24011507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::max_value               1                       # Request fanout histogram
24111507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::total           135031171                       # Request fanout histogram
24211507SCurtis.Dunham@arm.com
24311507SCurtis.Dunham@arm.com---------- End Simulation Statistics   ----------
244