xref: /gem5/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_VIPER_Baseline/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.000548                       # Number of seconds simulated
sim_ticks                                   548459500                       # Number of ticks simulated
final_tick                                  548459500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                  76623                       # Simulator instruction rate (inst/s)
host_op_rate                                   157567                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                              627550839                       # Simulator tick rate (ticks/s)
host_mem_usage                                1298164                       # Number of bytes of host memory used
host_seconds                                     0.87                       # Real time elapsed on the host
sim_insts                                       66963                       # Number of instructions simulated
sim_ops                                        137705                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.mem_ctrls.bytes_read::dir_cntrl0         99840                       # Number of bytes read from this memory
system.mem_ctrls.bytes_read::total              99840                       # Number of bytes read from this memory
system.mem_ctrls.num_reads::dir_cntrl0           1560                       # Number of read requests responded to by this memory
system.mem_ctrls.num_reads::total                1560                       # Number of read requests responded to by this memory
system.mem_ctrls.bw_read::dir_cntrl0        182037142                       # Total read bandwidth from this memory (bytes/s)
system.mem_ctrls.bw_read::total             182037142                       # Total read bandwidth from this memory (bytes/s)
system.mem_ctrls.bw_total::dir_cntrl0       182037142                       # Total bandwidth to/from this memory (bytes/s)
system.mem_ctrls.bw_total::total            182037142                       # Total bandwidth to/from this memory (bytes/s)
system.mem_ctrls.readReqs                        1560                       # Number of read requests accepted
system.mem_ctrls.writeReqs                          0                       # Number of write requests accepted
system.mem_ctrls.readBursts                      1560                       # Number of DRAM read bursts, including those serviced by the write queue
system.mem_ctrls.writeBursts                        0                       # Number of DRAM write bursts, including those merged in the write queue
system.mem_ctrls.bytesReadDRAM                  99840                       # Total number of bytes read from DRAM
system.mem_ctrls.bytesReadWrQ                       0                       # Total number of bytes read from write queue
system.mem_ctrls.bytesWritten                       0                       # Total number of bytes written to DRAM
system.mem_ctrls.bytesReadSys                   99840                       # Total read bytes from the system interface side
system.mem_ctrls.bytesWrittenSys                    0                       # Total written bytes from the system interface side
system.mem_ctrls.servicedByWrQ                      0                       # Number of DRAM read bursts serviced by the write queue
system.mem_ctrls.mergedWrBursts                     0                       # Number of DRAM write bursts merged with an existing one
system.mem_ctrls.neitherReadNorWriteReqs            0                       # Number of requests that are neither read nor write
system.mem_ctrls.perBankRdBursts::0               122                       # Per bank write bursts
system.mem_ctrls.perBankRdBursts::1               192                       # Per bank write bursts
system.mem_ctrls.perBankRdBursts::2                93                       # Per bank write bursts
system.mem_ctrls.perBankRdBursts::3                44                       # Per bank write bursts
system.mem_ctrls.perBankRdBursts::4                61                       # Per bank write bursts
system.mem_ctrls.perBankRdBursts::5                79                       # Per bank write bursts
system.mem_ctrls.perBankRdBursts::6                52                       # Per bank write bursts
system.mem_ctrls.perBankRdBursts::7                42                       # Per bank write bursts
system.mem_ctrls.perBankRdBursts::8                54                       # Per bank write bursts
system.mem_ctrls.perBankRdBursts::9                56                       # Per bank write bursts
system.mem_ctrls.perBankRdBursts::10              182                       # Per bank write bursts
system.mem_ctrls.perBankRdBursts::11               90                       # Per bank write bursts
system.mem_ctrls.perBankRdBursts::12              223                       # Per bank write bursts
system.mem_ctrls.perBankRdBursts::13              125                       # Per bank write bursts
system.mem_ctrls.perBankRdBursts::14               51                       # Per bank write bursts
system.mem_ctrls.perBankRdBursts::15               94                       # Per bank write bursts
system.mem_ctrls.perBankWrBursts::0                 0                       # Per bank write bursts
system.mem_ctrls.perBankWrBursts::1                 0                       # Per bank write bursts
system.mem_ctrls.perBankWrBursts::2                 0                       # Per bank write bursts
system.mem_ctrls.perBankWrBursts::3                 0                       # Per bank write bursts
system.mem_ctrls.perBankWrBursts::4                 0                       # Per bank write bursts
system.mem_ctrls.perBankWrBursts::5                 0                       # Per bank write bursts
system.mem_ctrls.perBankWrBursts::6                 0                       # Per bank write bursts
system.mem_ctrls.perBankWrBursts::7                 0                       # Per bank write bursts
system.mem_ctrls.perBankWrBursts::8                 0                       # Per bank write bursts
system.mem_ctrls.perBankWrBursts::9                 0                       # Per bank write bursts
system.mem_ctrls.perBankWrBursts::10                0                       # Per bank write bursts
system.mem_ctrls.perBankWrBursts::11                0                       # Per bank write bursts
system.mem_ctrls.perBankWrBursts::12                0                       # Per bank write bursts
system.mem_ctrls.perBankWrBursts::13                0                       # Per bank write bursts
system.mem_ctrls.perBankWrBursts::14                0                       # Per bank write bursts
system.mem_ctrls.perBankWrBursts::15                0                       # Per bank write bursts
system.mem_ctrls.numRdRetry                         0                       # Number of times read queue was full causing retry
system.mem_ctrls.numWrRetry                         0                       # Number of times write queue was full causing retry
system.mem_ctrls.totGap                     548231000                       # Total gap between requests
system.mem_ctrls.readPktSize::0                     0                       # Read request sizes (log2)
system.mem_ctrls.readPktSize::1                     0                       # Read request sizes (log2)
system.mem_ctrls.readPktSize::2                     0                       # Read request sizes (log2)
system.mem_ctrls.readPktSize::3                     0                       # Read request sizes (log2)
system.mem_ctrls.readPktSize::4                     0                       # Read request sizes (log2)
system.mem_ctrls.readPktSize::5                     0                       # Read request sizes (log2)
system.mem_ctrls.readPktSize::6                  1560                       # Read request sizes (log2)
system.mem_ctrls.writePktSize::0                    0                       # Write request sizes (log2)
system.mem_ctrls.writePktSize::1                    0                       # Write request sizes (log2)
system.mem_ctrls.writePktSize::2                    0                       # Write request sizes (log2)
system.mem_ctrls.writePktSize::3                    0                       # Write request sizes (log2)
system.mem_ctrls.writePktSize::4                    0                       # Write request sizes (log2)
system.mem_ctrls.writePktSize::5                    0                       # Write request sizes (log2)
system.mem_ctrls.writePktSize::6                    0                       # Write request sizes (log2)
system.mem_ctrls.rdQLenPdf::0                    1545                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::1                       3                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::2                       2                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::3                       4                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::4                       5                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::5                       1                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::6                       0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::7                       0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::8                       0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::9                       0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::10                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::11                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::12                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::13                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::14                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::15                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::16                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::17                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::18                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::19                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::20                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::21                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::22                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::23                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::24                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::25                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::26                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::27                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::28                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::29                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::30                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::31                      0                       # What read queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::0                       0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::1                       0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::2                       0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::3                       0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::4                       0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::5                       0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::6                       0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::7                       0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::8                       0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::9                       0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::10                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::11                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::12                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::13                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::14                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::15                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::16                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::17                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::18                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::19                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::20                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::21                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::22                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::23                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::24                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::25                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::26                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::27                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::28                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::29                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::30                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::31                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::32                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::33                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::34                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::35                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::36                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::37                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::38                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::39                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::40                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::41                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::42                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::43                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::44                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::45                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::46                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::47                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::48                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::49                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::50                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::51                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::52                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::53                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::54                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::55                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::56                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::57                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::58                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::59                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::60                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::61                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::62                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::63                      0                       # What write queue length does an incoming req see
system.mem_ctrls.bytesPerActivate::samples          467                       # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::mean    212.008565                       # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::gmean   148.026325                       # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::stdev   209.604491                       # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::0-127          171     36.62%     36.62% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::128-255          154     32.98%     69.59% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::256-383           64     13.70%     83.30% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::384-511           31      6.64%     89.94% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::512-639           16      3.43%     93.36% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::640-767           12      2.57%     95.93% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::768-895            7      1.50%     97.43% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::896-1023            3      0.64%     98.07% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::1024-1151            9      1.93%    100.00% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::total          467                       # Bytes accessed per row activation
system.mem_ctrls.totQLat                     15697750                       # Total ticks spent queuing
system.mem_ctrls.totMemAccLat                44947750                       # Total ticks spent from burst creation until serviced by the DRAM
system.mem_ctrls.totBusLat                    7800000                       # Total ticks spent in databus transfers
system.mem_ctrls.avgQLat                     10062.66                       # Average queueing delay per DRAM burst
system.mem_ctrls.avgBusLat                    5000.00                       # Average bus latency per DRAM burst
system.mem_ctrls.avgMemAccLat                28812.66                       # Average memory access latency per DRAM burst
system.mem_ctrls.avgRdBW                       182.04                       # Average DRAM read bandwidth in MiByte/s
system.mem_ctrls.avgWrBW                         0.00                       # Average achieved write bandwidth in MiByte/s
system.mem_ctrls.avgRdBWSys                    182.04                       # Average system read bandwidth in MiByte/s
system.mem_ctrls.avgWrBWSys                      0.00                       # Average system write bandwidth in MiByte/s
system.mem_ctrls.peakBW                      12800.00                       # Theoretical peak bandwidth in MiByte/s
system.mem_ctrls.busUtil                         1.42                       # Data bus utilization in percentage
system.mem_ctrls.busUtilRead                     1.42                       # Data bus utilization in percentage for reads
system.mem_ctrls.busUtilWrite                    0.00                       # Data bus utilization in percentage for writes
system.mem_ctrls.avgRdQLen                       1.01                       # Average read queue length when enqueuing
system.mem_ctrls.avgWrQLen                       0.00                       # Average write queue length when enqueuing
system.mem_ctrls.readRowHits                     1088                       # Number of row buffer hits during reads
system.mem_ctrls.writeRowHits                       0                       # Number of row buffer hits during writes
system.mem_ctrls.readRowHitRate                 69.74                       # Row buffer hit rate for reads
system.mem_ctrls.writeRowHitRate                  nan                       # Row buffer hit rate for writes
system.mem_ctrls.avgGap                     351430.13                       # Average gap between requests
system.mem_ctrls.pageHitRate                    69.74                       # Row buffer hit rate, read and write combined
system.mem_ctrls_0.actEnergy                  1323000                       # Energy for activate commands per rank (pJ)
system.mem_ctrls_0.preEnergy                   721875                       # Energy for precharge commands per rank (pJ)
system.mem_ctrls_0.readEnergy                 5335200                       # Energy for read commands per rank (pJ)
system.mem_ctrls_0.writeEnergy                      0                       # Energy for write commands per rank (pJ)
system.mem_ctrls_0.refreshEnergy             35599200                       # Energy for refresh commands per rank (pJ)
system.mem_ctrls_0.actBackEnergy            300176820                       # Energy for active background per rank (pJ)
system.mem_ctrls_0.preBackEnergy             63865500                       # Energy for precharge background per rank (pJ)
system.mem_ctrls_0.totalEnergy              407021595                       # Total energy per rank (pJ)
system.mem_ctrls_0.averagePower            746.421165                       # Core power per rank (mW)
system.mem_ctrls_0.memoryStateTime::IDLE    107390750                       # Time in different power states
system.mem_ctrls_0.memoryStateTime::REF      18200000                       # Time in different power states
system.mem_ctrls_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.mem_ctrls_0.memoryStateTime::ACT     422764250                       # Time in different power states
system.mem_ctrls_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.mem_ctrls_1.actEnergy                  2207520                       # Energy for activate commands per rank (pJ)
system.mem_ctrls_1.preEnergy                  1204500                       # Energy for precharge commands per rank (pJ)
system.mem_ctrls_1.readEnergy                 6731400                       # Energy for read commands per rank (pJ)
system.mem_ctrls_1.writeEnergy                      0                       # Energy for write commands per rank (pJ)
system.mem_ctrls_1.refreshEnergy             35599200                       # Energy for refresh commands per rank (pJ)
system.mem_ctrls_1.actBackEnergy            328972365                       # Energy for active background per rank (pJ)
system.mem_ctrls_1.preBackEnergy             38606250                       # Energy for precharge background per rank (pJ)
system.mem_ctrls_1.totalEnergy              413321235                       # Total energy per rank (pJ)
system.mem_ctrls_1.averagePower            757.973831                       # Core power per rank (mW)
system.mem_ctrls_1.memoryStateTime::IDLE     62414250                       # Time in different power states
system.mem_ctrls_1.memoryStateTime::REF      18200000                       # Time in different power states
system.mem_ctrls_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.mem_ctrls_1.memoryStateTime::ACT     464697000                       # Time in different power states
system.mem_ctrls_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.ruby.clk_domain.clock                      500                       # Clock period in ticks
system.ruby.phys_mem.bytes_read::cpu0.inst       696760                       # Number of bytes read from this memory
system.ruby.phys_mem.bytes_read::cpu0.data       119832                       # Number of bytes read from this memory
system.ruby.phys_mem.bytes_read::cpu1.CUs0.ComputeUnit         3280                       # Number of bytes read from this memory
system.ruby.phys_mem.bytes_read::cpu1.CUs1.ComputeUnit         3280                       # Number of bytes read from this memory
system.ruby.phys_mem.bytes_read::total         823152                       # Number of bytes read from this memory
system.ruby.phys_mem.bytes_inst_read::cpu0.inst       696760                       # Number of instructions bytes read from this memory
system.ruby.phys_mem.bytes_inst_read::cpu1.CUs0.ComputeUnit         2000                       # Number of instructions bytes read from this memory
system.ruby.phys_mem.bytes_inst_read::cpu1.CUs1.ComputeUnit         2000                       # Number of instructions bytes read from this memory
system.ruby.phys_mem.bytes_inst_read::total       700760                       # Number of instructions bytes read from this memory
system.ruby.phys_mem.bytes_written::cpu0.data        72767                       # Number of bytes written to this memory
system.ruby.phys_mem.bytes_written::cpu1.CUs0.ComputeUnit          256                       # Number of bytes written to this memory
system.ruby.phys_mem.bytes_written::cpu1.CUs1.ComputeUnit          256                       # Number of bytes written to this memory
system.ruby.phys_mem.bytes_written::total        73279                       # Number of bytes written to this memory
system.ruby.phys_mem.num_reads::cpu0.inst        87095                       # Number of read requests responded to by this memory
system.ruby.phys_mem.num_reads::cpu0.data        16686                       # Number of read requests responded to by this memory
system.ruby.phys_mem.num_reads::cpu1.CUs0.ComputeUnit          555                       # Number of read requests responded to by this memory
system.ruby.phys_mem.num_reads::cpu1.CUs1.ComputeUnit          555                       # Number of read requests responded to by this memory
system.ruby.phys_mem.num_reads::total          104891                       # Number of read requests responded to by this memory
system.ruby.phys_mem.num_writes::cpu0.data        10422                       # Number of write requests responded to by this memory
system.ruby.phys_mem.num_writes::cpu1.CUs0.ComputeUnit          256                       # Number of write requests responded to by this memory
system.ruby.phys_mem.num_writes::cpu1.CUs1.ComputeUnit          256                       # Number of write requests responded to by this memory
system.ruby.phys_mem.num_writes::total          10934                       # Number of write requests responded to by this memory
system.ruby.phys_mem.bw_read::cpu0.inst    1270394623                       # Total read bandwidth from this memory (bytes/s)
system.ruby.phys_mem.bw_read::cpu0.data     218488330                       # Total read bandwidth from this memory (bytes/s)
system.ruby.phys_mem.bw_read::cpu1.CUs0.ComputeUnit      5980387                       # Total read bandwidth from this memory (bytes/s)
system.ruby.phys_mem.bw_read::cpu1.CUs1.ComputeUnit      5980387                       # Total read bandwidth from this memory (bytes/s)
system.ruby.phys_mem.bw_read::total        1500843727                       # Total read bandwidth from this memory (bytes/s)
system.ruby.phys_mem.bw_inst_read::cpu0.inst   1270394623                       # Instruction read bandwidth from this memory (bytes/s)
system.ruby.phys_mem.bw_inst_read::cpu1.CUs0.ComputeUnit      3646577                       # Instruction read bandwidth from this memory (bytes/s)
system.ruby.phys_mem.bw_inst_read::cpu1.CUs1.ComputeUnit      3646577                       # Instruction read bandwidth from this memory (bytes/s)
system.ruby.phys_mem.bw_inst_read::total   1277687778                       # Instruction read bandwidth from this memory (bytes/s)
system.ruby.phys_mem.bw_write::cpu0.data    132675248                       # Write bandwidth from this memory (bytes/s)
system.ruby.phys_mem.bw_write::cpu1.CUs0.ComputeUnit       466762                       # Write bandwidth from this memory (bytes/s)
system.ruby.phys_mem.bw_write::cpu1.CUs1.ComputeUnit       466762                       # Write bandwidth from this memory (bytes/s)
system.ruby.phys_mem.bw_write::total        133608771                       # Write bandwidth from this memory (bytes/s)
system.ruby.phys_mem.bw_total::cpu0.inst   1270394623                       # Total bandwidth to/from this memory (bytes/s)
system.ruby.phys_mem.bw_total::cpu0.data    351163577                       # Total bandwidth to/from this memory (bytes/s)
system.ruby.phys_mem.bw_total::cpu1.CUs0.ComputeUnit      6447149                       # Total bandwidth to/from this memory (bytes/s)
system.ruby.phys_mem.bw_total::cpu1.CUs1.ComputeUnit      6447149                       # Total bandwidth to/from this memory (bytes/s)
system.ruby.phys_mem.bw_total::total       1634452498                       # Total bandwidth to/from this memory (bytes/s)
system.ruby.outstanding_req_hist::bucket_size            1                      
system.ruby.outstanding_req_hist::max_bucket            9                      
system.ruby.outstanding_req_hist::samples       114203                      
system.ruby.outstanding_req_hist::mean       1.000035                      
system.ruby.outstanding_req_hist::gmean      1.000024                      
system.ruby.outstanding_req_hist::stdev      0.005918                      
system.ruby.outstanding_req_hist         |           0      0.00%      0.00% |      114199    100.00%    100.00% |           4      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
system.ruby.outstanding_req_hist::total        114203                      
system.ruby.latency_hist::bucket_size              64                      
system.ruby.latency_hist::max_bucket              639                      
system.ruby.latency_hist::samples              114203                      
system.ruby.latency_hist::mean               3.766924                      
system.ruby.latency_hist::gmean              1.075767                      
system.ruby.latency_hist::stdev             23.927354                      
system.ruby.latency_hist                 |      112668     98.66%     98.66% |           0      0.00%     98.66% |           0      0.00%     98.66% |        1489      1.30%     99.96% |          10      0.01%     99.97% |          13      0.01%     99.98% |          16      0.01%     99.99% |           7      0.01%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
system.ruby.latency_hist::total                114203                      
system.ruby.hit_latency_hist::bucket_size           64                      
system.ruby.hit_latency_hist::max_bucket          639                      
system.ruby.hit_latency_hist::samples            1535                      
system.ruby.hit_latency_hist::mean         206.165472                      
system.ruby.hit_latency_hist::gmean        204.491657                      
system.ruby.hit_latency_hist::stdev         32.551053                      
system.ruby.hit_latency_hist             |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |        1489     97.00%     97.00% |          10      0.65%     97.65% |          13      0.85%     98.50% |          16      1.04%     99.54% |           7      0.46%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
system.ruby.hit_latency_hist::total              1535                      
system.ruby.miss_latency_hist::bucket_size            2                      
system.ruby.miss_latency_hist::max_bucket           19                      
system.ruby.miss_latency_hist::samples         112668                      
system.ruby.miss_latency_hist::mean          1.009426                      
system.ruby.miss_latency_hist::gmean         1.001543                      
system.ruby.miss_latency_hist::stdev         0.411800                      
system.ruby.miss_latency_hist            |      112609     99.95%     99.95% |           0      0.00%     99.95% |           0      0.00%     99.95% |           0      0.00%     99.95% |           0      0.00%     99.95% |           0      0.00%     99.95% |           0      0.00%     99.95% |           0      0.00%     99.95% |           0      0.00%     99.95% |          59      0.05%    100.00%
system.ruby.miss_latency_hist::total           112668                      
system.ruby.L1Cache.incomplete_times           112609                      
system.ruby.L2Cache.incomplete_times               59                      
system.cp_cntrl0.L1D0cache.demand_hits              0                       # Number of cache demand hits
system.cp_cntrl0.L1D0cache.demand_misses          506                       # Number of cache demand misses
system.cp_cntrl0.L1D0cache.demand_accesses          506                       # Number of cache demand accesses
system.cp_cntrl0.L1D0cache.num_data_array_reads        16155                       # number of data array reads
system.cp_cntrl0.L1D0cache.num_data_array_writes        11985                       # number of data array writes
system.cp_cntrl0.L1D0cache.num_tag_array_reads        27132                       # number of tag array reads
system.cp_cntrl0.L1D0cache.num_tag_array_writes         1584                       # number of tag array writes
system.cp_cntrl0.L1D1cache.demand_hits              0                       # Number of cache demand hits
system.cp_cntrl0.L1D1cache.demand_misses            0                       # Number of cache demand misses
system.cp_cntrl0.L1D1cache.demand_accesses            0                       # Number of cache demand accesses
system.cp_cntrl0.L1Icache.demand_hits               0                       # Number of cache demand hits
system.cp_cntrl0.L1Icache.demand_misses          1088                       # Number of cache demand misses
system.cp_cntrl0.L1Icache.demand_accesses         1088                       # Number of cache demand accesses
system.cp_cntrl0.L1Icache.num_data_array_reads        86007                       # number of data array reads
system.cp_cntrl0.L1Icache.num_data_array_writes           54                       # number of data array writes
system.cp_cntrl0.L1Icache.num_tag_array_reads        87684                       # number of tag array reads
system.cp_cntrl0.L1Icache.num_tag_array_writes           54                       # number of tag array writes
system.cp_cntrl0.L2cache.demand_hits                0                       # Number of cache demand hits
system.cp_cntrl0.L2cache.demand_misses           1535                       # Number of cache demand misses
system.cp_cntrl0.L2cache.demand_accesses         1535                       # Number of cache demand accesses
system.cp_cntrl0.L2cache.num_data_array_reads          120                       # number of data array reads
system.cp_cntrl0.L2cache.num_data_array_writes        11982                       # number of data array writes
system.cp_cntrl0.L2cache.num_tag_array_reads        12046                       # number of tag array reads
system.cp_cntrl0.L2cache.num_tag_array_writes         1641                       # number of tag array writes
system.cpu0.clk_domain.clock                      500                       # Clock period in ticks
system.cpu0.apic_clk_domain.clock                8000                       # Clock period in ticks
system.cpu0.workload.numSyscalls                   21                       # Number of system calls
system.cpu0.numCycles                         1096919                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.committedInsts                      66963                       # Number of instructions committed
system.cpu0.committedOps                       137705                       # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses               136380                       # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses                  1279                       # Number of float alu accesses
system.cpu0.num_func_calls                       3196                       # number of times a function call or return occured
system.cpu0.num_conditional_control_insts        12151                       # number of instructions that are conditional controls
system.cpu0.num_int_insts                      136380                       # number of integer instructions
system.cpu0.num_fp_insts                         1279                       # number of float instructions
system.cpu0.num_int_register_reads             257490                       # number of times the integer registers were read
system.cpu0.num_int_register_writes            110039                       # number of times the integer registers were written
system.cpu0.num_fp_register_reads                1981                       # number of times the floating registers were read
system.cpu0.num_fp_register_writes                981                       # number of times the floating registers were written
system.cpu0.num_cc_register_reads               78262                       # number of times the CC registers were read
system.cpu0.num_cc_register_writes              42183                       # number of times the CC registers were written
system.cpu0.num_mem_refs                        27198                       # number of memory refs
system.cpu0.num_load_insts                      16684                       # Number of load instructions
system.cpu0.num_store_insts                     10514                       # Number of store instructions
system.cpu0.num_idle_cycles               7577.003986                       # Number of idle cycles
system.cpu0.num_busy_cycles              1089341.996014                       # Number of busy cycles
system.cpu0.not_idle_fraction                0.993092                       # Percentage of non-idle cycles
system.cpu0.idle_fraction                    0.006908                       # Percentage of idle cycles
system.cpu0.Branches                            16199                       # Number of branches fetched
system.cpu0.op_class::No_OpClass                  615      0.45%      0.45% # Class of executed instruction
system.cpu0.op_class::IntAlu                   108791     79.00%     79.45% # Class of executed instruction
system.cpu0.op_class::IntMult                      13      0.01%     79.46% # Class of executed instruction
system.cpu0.op_class::IntDiv                      138      0.10%     79.56% # Class of executed instruction
system.cpu0.op_class::FloatAdd                    950      0.69%     80.25% # Class of executed instruction
system.cpu0.op_class::FloatCmp                      0      0.00%     80.25% # Class of executed instruction
system.cpu0.op_class::FloatCvt                      0      0.00%     80.25% # Class of executed instruction
system.cpu0.op_class::FloatMult                     0      0.00%     80.25% # Class of executed instruction
system.cpu0.op_class::FloatDiv                      0      0.00%     80.25% # Class of executed instruction
system.cpu0.op_class::FloatSqrt                     0      0.00%     80.25% # Class of executed instruction
system.cpu0.op_class::SimdAdd                       0      0.00%     80.25% # Class of executed instruction
system.cpu0.op_class::SimdAddAcc                    0      0.00%     80.25% # Class of executed instruction
system.cpu0.op_class::SimdAlu                       0      0.00%     80.25% # Class of executed instruction
system.cpu0.op_class::SimdCmp                       0      0.00%     80.25% # Class of executed instruction
system.cpu0.op_class::SimdCvt                       0      0.00%     80.25% # Class of executed instruction
system.cpu0.op_class::SimdMisc                      0      0.00%     80.25% # Class of executed instruction
system.cpu0.op_class::SimdMult                      0      0.00%     80.25% # Class of executed instruction
system.cpu0.op_class::SimdMultAcc                   0      0.00%     80.25% # Class of executed instruction
system.cpu0.op_class::SimdShift                     0      0.00%     80.25% # Class of executed instruction
system.cpu0.op_class::SimdShiftAcc                  0      0.00%     80.25% # Class of executed instruction
system.cpu0.op_class::SimdSqrt                      0      0.00%     80.25% # Class of executed instruction
system.cpu0.op_class::SimdFloatAdd                  0      0.00%     80.25% # Class of executed instruction
system.cpu0.op_class::SimdFloatAlu                  0      0.00%     80.25% # Class of executed instruction
system.cpu0.op_class::SimdFloatCmp                  0      0.00%     80.25% # Class of executed instruction
system.cpu0.op_class::SimdFloatCvt                  0      0.00%     80.25% # Class of executed instruction
system.cpu0.op_class::SimdFloatDiv                  0      0.00%     80.25% # Class of executed instruction
system.cpu0.op_class::SimdFloatMisc                 0      0.00%     80.25% # Class of executed instruction
system.cpu0.op_class::SimdFloatMult                 0      0.00%     80.25% # Class of executed instruction
system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     80.25% # Class of executed instruction
system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     80.25% # Class of executed instruction
system.cpu0.op_class::MemRead                   16684     12.12%     92.36% # Class of executed instruction
system.cpu0.op_class::MemWrite                  10514      7.64%    100.00% # Class of executed instruction
system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::total                    137705                       # Class of executed instruction
system.cpu1.clk_domain.voltage_domain.voltage            1                       # Voltage in Volts
system.cpu1.clk_domain.clock                     1000                       # Clock period in ticks
system.cpu1.CUs0.wavefronts00.timesBlockedDueVrfPortAvail            0                       # number of times instructions are blocked due to VRF port availability
system.cpu1.CUs0.wavefronts00.timesBlockedDueWAXDependencies            0                       # number of times the wf's instructions are blocked due to WAW or WAR dependencies
system.cpu1.CUs0.wavefronts00.timesBlockedDueRAWDependencies          372                       # number of times the wf's instructions are blocked due to RAW dependencies
system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::samples           39                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::mean     0.794872                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::stdev     0.863880                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::underflows            0      0.00%      0.00% # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::0-1           28     71.79%     71.79% # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::2-3           11     28.21%    100.00% # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::4            0      0.00%    100.00% # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::overflows            0      0.00%    100.00% # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::min_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::max_value            2                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::total           39                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::samples           39                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::mean     0.589744                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::stdev     0.498310                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::underflows            0      0.00%      0.00% # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::0-1           39    100.00%    100.00% # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::2-3            0      0.00%    100.00% # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::overflows            0      0.00%    100.00% # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::min_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::max_value            1                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::total           39                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts01.timesBlockedDueVrfPortAvail            0                       # number of times instructions are blocked due to VRF port availability
system.cpu1.CUs0.wavefronts01.timesBlockedDueWAXDependencies            0                       # number of times the wf's instructions are blocked due to WAW or WAR dependencies
system.cpu1.CUs0.wavefronts01.timesBlockedDueRAWDependencies            0                       # number of times the wf's instructions are blocked due to RAW dependencies
system.cpu1.CUs0.wavefronts01.src_reg_operand_dist::samples            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts01.src_reg_operand_dist::mean          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts01.src_reg_operand_dist::stdev          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts01.src_reg_operand_dist::underflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts01.src_reg_operand_dist::0-1            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts01.src_reg_operand_dist::2-3            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts01.src_reg_operand_dist::4            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts01.src_reg_operand_dist::overflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts01.src_reg_operand_dist::min_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts01.src_reg_operand_dist::max_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts01.src_reg_operand_dist::total            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::samples            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::mean          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::stdev          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::underflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::0-1            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::2-3            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::overflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::min_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::max_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::total            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts02.timesBlockedDueVrfPortAvail            0                       # number of times instructions are blocked due to VRF port availability
system.cpu1.CUs0.wavefronts02.timesBlockedDueWAXDependencies            0                       # number of times the wf's instructions are blocked due to WAW or WAR dependencies
system.cpu1.CUs0.wavefronts02.timesBlockedDueRAWDependencies            0                       # number of times the wf's instructions are blocked due to RAW dependencies
system.cpu1.CUs0.wavefronts02.src_reg_operand_dist::samples            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts02.src_reg_operand_dist::mean          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts02.src_reg_operand_dist::stdev          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts02.src_reg_operand_dist::underflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts02.src_reg_operand_dist::0-1            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts02.src_reg_operand_dist::2-3            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts02.src_reg_operand_dist::4            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts02.src_reg_operand_dist::overflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts02.src_reg_operand_dist::min_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts02.src_reg_operand_dist::max_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts02.src_reg_operand_dist::total            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::samples            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::mean          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::stdev          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::underflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::0-1            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::2-3            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::overflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::min_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::max_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::total            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts03.timesBlockedDueVrfPortAvail            0                       # number of times instructions are blocked due to VRF port availability
system.cpu1.CUs0.wavefronts03.timesBlockedDueWAXDependencies            0                       # number of times the wf's instructions are blocked due to WAW or WAR dependencies
system.cpu1.CUs0.wavefronts03.timesBlockedDueRAWDependencies            0                       # number of times the wf's instructions are blocked due to RAW dependencies
system.cpu1.CUs0.wavefronts03.src_reg_operand_dist::samples            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts03.src_reg_operand_dist::mean          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts03.src_reg_operand_dist::stdev          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts03.src_reg_operand_dist::underflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts03.src_reg_operand_dist::0-1            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts03.src_reg_operand_dist::2-3            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts03.src_reg_operand_dist::4            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts03.src_reg_operand_dist::overflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts03.src_reg_operand_dist::min_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts03.src_reg_operand_dist::max_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts03.src_reg_operand_dist::total            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts03.dst_reg_operand_dist::samples            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts03.dst_reg_operand_dist::mean          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts03.dst_reg_operand_dist::stdev          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts03.dst_reg_operand_dist::underflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts03.dst_reg_operand_dist::0-1            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts03.dst_reg_operand_dist::2-3            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts03.dst_reg_operand_dist::overflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts03.dst_reg_operand_dist::min_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts03.dst_reg_operand_dist::max_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts03.dst_reg_operand_dist::total            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts04.timesBlockedDueVrfPortAvail            0                       # number of times instructions are blocked due to VRF port availability
system.cpu1.CUs0.wavefronts04.timesBlockedDueWAXDependencies            0                       # number of times the wf's instructions are blocked due to WAW or WAR dependencies
system.cpu1.CUs0.wavefronts04.timesBlockedDueRAWDependencies            0                       # number of times the wf's instructions are blocked due to RAW dependencies
system.cpu1.CUs0.wavefronts04.src_reg_operand_dist::samples            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts04.src_reg_operand_dist::mean          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts04.src_reg_operand_dist::stdev          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts04.src_reg_operand_dist::underflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts04.src_reg_operand_dist::0-1            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts04.src_reg_operand_dist::2-3            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts04.src_reg_operand_dist::4            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts04.src_reg_operand_dist::overflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts04.src_reg_operand_dist::min_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts04.src_reg_operand_dist::max_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts04.src_reg_operand_dist::total            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts04.dst_reg_operand_dist::samples            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts04.dst_reg_operand_dist::mean          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts04.dst_reg_operand_dist::stdev          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts04.dst_reg_operand_dist::underflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts04.dst_reg_operand_dist::0-1            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts04.dst_reg_operand_dist::2-3            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts04.dst_reg_operand_dist::overflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts04.dst_reg_operand_dist::min_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts04.dst_reg_operand_dist::max_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts04.dst_reg_operand_dist::total            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts05.timesBlockedDueVrfPortAvail            0                       # number of times instructions are blocked due to VRF port availability
system.cpu1.CUs0.wavefronts05.timesBlockedDueWAXDependencies            0                       # number of times the wf's instructions are blocked due to WAW or WAR dependencies
system.cpu1.CUs0.wavefronts05.timesBlockedDueRAWDependencies            0                       # number of times the wf's instructions are blocked due to RAW dependencies
system.cpu1.CUs0.wavefronts05.src_reg_operand_dist::samples            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts05.src_reg_operand_dist::mean          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts05.src_reg_operand_dist::stdev          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts05.src_reg_operand_dist::underflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts05.src_reg_operand_dist::0-1            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts05.src_reg_operand_dist::2-3            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts05.src_reg_operand_dist::4            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts05.src_reg_operand_dist::overflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts05.src_reg_operand_dist::min_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts05.src_reg_operand_dist::max_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts05.src_reg_operand_dist::total            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::samples            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::mean          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::stdev          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::underflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::0-1            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::2-3            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::overflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::min_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::max_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::total            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts06.timesBlockedDueVrfPortAvail            0                       # number of times instructions are blocked due to VRF port availability
system.cpu1.CUs0.wavefronts06.timesBlockedDueWAXDependencies            0                       # number of times the wf's instructions are blocked due to WAW or WAR dependencies
system.cpu1.CUs0.wavefronts06.timesBlockedDueRAWDependencies            0                       # number of times the wf's instructions are blocked due to RAW dependencies
system.cpu1.CUs0.wavefronts06.src_reg_operand_dist::samples            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts06.src_reg_operand_dist::mean          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts06.src_reg_operand_dist::stdev          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts06.src_reg_operand_dist::underflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts06.src_reg_operand_dist::0-1            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts06.src_reg_operand_dist::2-3            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts06.src_reg_operand_dist::4            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts06.src_reg_operand_dist::overflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts06.src_reg_operand_dist::min_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts06.src_reg_operand_dist::max_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts06.src_reg_operand_dist::total            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::samples            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::mean          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::stdev          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::underflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::0-1            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::2-3            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::overflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::min_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::max_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::total            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts07.timesBlockedDueVrfPortAvail            0                       # number of times instructions are blocked due to VRF port availability
system.cpu1.CUs0.wavefronts07.timesBlockedDueWAXDependencies            0                       # number of times the wf's instructions are blocked due to WAW or WAR dependencies
system.cpu1.CUs0.wavefronts07.timesBlockedDueRAWDependencies            0                       # number of times the wf's instructions are blocked due to RAW dependencies
system.cpu1.CUs0.wavefronts07.src_reg_operand_dist::samples            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts07.src_reg_operand_dist::mean          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts07.src_reg_operand_dist::stdev          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts07.src_reg_operand_dist::underflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts07.src_reg_operand_dist::0-1            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts07.src_reg_operand_dist::2-3            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts07.src_reg_operand_dist::4            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts07.src_reg_operand_dist::overflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts07.src_reg_operand_dist::min_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts07.src_reg_operand_dist::max_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts07.src_reg_operand_dist::total            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::samples            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::mean          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::stdev          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::underflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::0-1            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::2-3            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::overflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::min_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::max_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::total            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts08.timesBlockedDueVrfPortAvail            0                       # number of times instructions are blocked due to VRF port availability
system.cpu1.CUs0.wavefronts08.timesBlockedDueWAXDependencies            0                       # number of times the wf's instructions are blocked due to WAW or WAR dependencies
system.cpu1.CUs0.wavefronts08.timesBlockedDueRAWDependencies          353                       # number of times the wf's instructions are blocked due to RAW dependencies
system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::samples           34                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::mean     0.852941                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::stdev     0.857493                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::underflows            0      0.00%      0.00% # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::0-1           24     70.59%     70.59% # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::2-3           10     29.41%    100.00% # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::4            0      0.00%    100.00% # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::overflows            0      0.00%    100.00% # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::min_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::max_value            2                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::total           34                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::samples           34                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::mean     0.617647                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::stdev     0.493270                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::underflows            0      0.00%      0.00% # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::0-1           34    100.00%    100.00% # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::2-3            0      0.00%    100.00% # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::overflows            0      0.00%    100.00% # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::min_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::max_value            1                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::total           34                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts09.timesBlockedDueVrfPortAvail            0                       # number of times instructions are blocked due to VRF port availability
system.cpu1.CUs0.wavefronts09.timesBlockedDueWAXDependencies            0                       # number of times the wf's instructions are blocked due to WAW or WAR dependencies
system.cpu1.CUs0.wavefronts09.timesBlockedDueRAWDependencies            0                       # number of times the wf's instructions are blocked due to RAW dependencies
system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::samples            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::mean          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::stdev          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::underflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::0-1            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::2-3            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::4            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::overflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::min_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::max_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::total            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::samples            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::mean          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::stdev          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::underflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::0-1            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::2-3            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::overflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::min_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::max_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::total            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts10.timesBlockedDueVrfPortAvail            0                       # number of times instructions are blocked due to VRF port availability
system.cpu1.CUs0.wavefronts10.timesBlockedDueWAXDependencies            0                       # number of times the wf's instructions are blocked due to WAW or WAR dependencies
system.cpu1.CUs0.wavefronts10.timesBlockedDueRAWDependencies            0                       # number of times the wf's instructions are blocked due to RAW dependencies
system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::samples            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::mean          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::stdev          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::underflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::0-1            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::2-3            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::4            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::overflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::min_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::max_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::total            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::samples            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::mean          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::stdev          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::underflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::0-1            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::2-3            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::overflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::min_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::max_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::total            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts11.timesBlockedDueVrfPortAvail            0                       # number of times instructions are blocked due to VRF port availability
system.cpu1.CUs0.wavefronts11.timesBlockedDueWAXDependencies            0                       # number of times the wf's instructions are blocked due to WAW or WAR dependencies
system.cpu1.CUs0.wavefronts11.timesBlockedDueRAWDependencies            0                       # number of times the wf's instructions are blocked due to RAW dependencies
system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::samples            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::mean          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::stdev          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::underflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::0-1            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::2-3            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::4            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::overflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::min_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::max_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::total            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::samples            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::mean          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::stdev          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::underflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::0-1            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::2-3            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::overflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::min_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::max_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::total            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts12.timesBlockedDueVrfPortAvail            0                       # number of times instructions are blocked due to VRF port availability
system.cpu1.CUs0.wavefronts12.timesBlockedDueWAXDependencies            0                       # number of times the wf's instructions are blocked due to WAW or WAR dependencies
system.cpu1.CUs0.wavefronts12.timesBlockedDueRAWDependencies            0                       # number of times the wf's instructions are blocked due to RAW dependencies
system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::samples            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::mean          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::stdev          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::underflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::0-1            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::2-3            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::4            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::overflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::min_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::max_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::total            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::samples            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::mean          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::stdev          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::underflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::0-1            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::2-3            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::overflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::min_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::max_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::total            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts13.timesBlockedDueVrfPortAvail            0                       # number of times instructions are blocked due to VRF port availability
system.cpu1.CUs0.wavefronts13.timesBlockedDueWAXDependencies            0                       # number of times the wf's instructions are blocked due to WAW or WAR dependencies
system.cpu1.CUs0.wavefronts13.timesBlockedDueRAWDependencies            0                       # number of times the wf's instructions are blocked due to RAW dependencies
system.cpu1.CUs0.wavefronts13.src_reg_operand_dist::samples            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts13.src_reg_operand_dist::mean          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts13.src_reg_operand_dist::stdev          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts13.src_reg_operand_dist::underflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts13.src_reg_operand_dist::0-1            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts13.src_reg_operand_dist::2-3            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts13.src_reg_operand_dist::4            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts13.src_reg_operand_dist::overflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts13.src_reg_operand_dist::min_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts13.src_reg_operand_dist::max_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts13.src_reg_operand_dist::total            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::samples            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::mean          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::stdev          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::underflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::0-1            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::2-3            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::overflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::min_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::max_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::total            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts14.timesBlockedDueVrfPortAvail            0                       # number of times instructions are blocked due to VRF port availability
system.cpu1.CUs0.wavefronts14.timesBlockedDueWAXDependencies            0                       # number of times the wf's instructions are blocked due to WAW or WAR dependencies
system.cpu1.CUs0.wavefronts14.timesBlockedDueRAWDependencies            0                       # number of times the wf's instructions are blocked due to RAW dependencies
system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::samples            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::mean          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::stdev          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::underflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::0-1            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::2-3            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::4            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::overflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::min_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::max_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::total            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::samples            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::mean          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::stdev          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::underflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::0-1            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::2-3            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::overflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::min_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::max_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::total            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts15.timesBlockedDueVrfPortAvail            0                       # number of times instructions are blocked due to VRF port availability
system.cpu1.CUs0.wavefronts15.timesBlockedDueWAXDependencies            0                       # number of times the wf's instructions are blocked due to WAW or WAR dependencies
system.cpu1.CUs0.wavefronts15.timesBlockedDueRAWDependencies            0                       # number of times the wf's instructions are blocked due to RAW dependencies
system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::samples            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::mean          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::stdev          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::underflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::0-1            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::2-3            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::4            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::overflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::min_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::max_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::total            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::samples            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::mean          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::stdev          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::underflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::0-1            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::2-3            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::overflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::min_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::max_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::total            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts16.timesBlockedDueVrfPortAvail            0                       # number of times instructions are blocked due to VRF port availability
system.cpu1.CUs0.wavefronts16.timesBlockedDueWAXDependencies            0                       # number of times the wf's instructions are blocked due to WAW or WAR dependencies
system.cpu1.CUs0.wavefronts16.timesBlockedDueRAWDependencies          344                       # number of times the wf's instructions are blocked due to RAW dependencies
system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::samples           34                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::mean     0.852941                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::stdev     0.857493                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::underflows            0      0.00%      0.00% # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::0-1           24     70.59%     70.59% # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::2-3           10     29.41%    100.00% # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::4            0      0.00%    100.00% # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::overflows            0      0.00%    100.00% # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::min_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::max_value            2                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::total           34                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::samples           34                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::mean     0.617647                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::stdev     0.493270                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::underflows            0      0.00%      0.00% # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::0-1           34    100.00%    100.00% # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::2-3            0      0.00%    100.00% # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::overflows            0      0.00%    100.00% # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::min_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::max_value            1                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::total           34                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts17.timesBlockedDueVrfPortAvail            0                       # number of times instructions are blocked due to VRF port availability
system.cpu1.CUs0.wavefronts17.timesBlockedDueWAXDependencies            0                       # number of times the wf's instructions are blocked due to WAW or WAR dependencies
system.cpu1.CUs0.wavefronts17.timesBlockedDueRAWDependencies            0                       # number of times the wf's instructions are blocked due to RAW dependencies
system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::samples            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::mean          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::stdev          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::underflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::0-1            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::2-3            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::4            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::overflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::min_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::max_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::total            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::samples            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::mean          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::stdev          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::underflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::0-1            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::2-3            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::overflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::min_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::max_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::total            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts18.timesBlockedDueVrfPortAvail            0                       # number of times instructions are blocked due to VRF port availability
system.cpu1.CUs0.wavefronts18.timesBlockedDueWAXDependencies            0                       # number of times the wf's instructions are blocked due to WAW or WAR dependencies
system.cpu1.CUs0.wavefronts18.timesBlockedDueRAWDependencies            0                       # number of times the wf's instructions are blocked due to RAW dependencies
system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::samples            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::mean          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::stdev          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::underflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::0-1            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::2-3            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::4            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::overflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::min_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::max_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::total            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::samples            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::mean          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::stdev          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::underflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::0-1            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::2-3            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::overflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::min_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::max_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::total            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts19.timesBlockedDueVrfPortAvail            0                       # number of times instructions are blocked due to VRF port availability
system.cpu1.CUs0.wavefronts19.timesBlockedDueWAXDependencies            0                       # number of times the wf's instructions are blocked due to WAW or WAR dependencies
system.cpu1.CUs0.wavefronts19.timesBlockedDueRAWDependencies            0                       # number of times the wf's instructions are blocked due to RAW dependencies
system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::samples            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::mean          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::stdev          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::underflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::0-1            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::2-3            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::4            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::overflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::min_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::max_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::total            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::samples            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::mean          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::stdev          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::underflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::0-1            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::2-3            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::overflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::min_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::max_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::total            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts20.timesBlockedDueVrfPortAvail            0                       # number of times instructions are blocked due to VRF port availability
system.cpu1.CUs0.wavefronts20.timesBlockedDueWAXDependencies            0                       # number of times the wf's instructions are blocked due to WAW or WAR dependencies
system.cpu1.CUs0.wavefronts20.timesBlockedDueRAWDependencies            0                       # number of times the wf's instructions are blocked due to RAW dependencies
system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::samples            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::mean          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::stdev          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::underflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::0-1            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::2-3            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::4            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::overflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::min_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::max_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::total            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::samples            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::mean          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::stdev          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::underflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::0-1            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::2-3            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::overflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::min_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::max_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::total            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts21.timesBlockedDueVrfPortAvail            0                       # number of times instructions are blocked due to VRF port availability
system.cpu1.CUs0.wavefronts21.timesBlockedDueWAXDependencies            0                       # number of times the wf's instructions are blocked due to WAW or WAR dependencies
system.cpu1.CUs0.wavefronts21.timesBlockedDueRAWDependencies            0                       # number of times the wf's instructions are blocked due to RAW dependencies
system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::samples            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::mean          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::stdev          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::underflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::0-1            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::2-3            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::4            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::overflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::min_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::max_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::total            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::samples            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::mean          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::stdev          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::underflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::0-1            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::2-3            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::overflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::min_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::max_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::total            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts22.timesBlockedDueVrfPortAvail            0                       # number of times instructions are blocked due to VRF port availability
system.cpu1.CUs0.wavefronts22.timesBlockedDueWAXDependencies            0                       # number of times the wf's instructions are blocked due to WAW or WAR dependencies
system.cpu1.CUs0.wavefronts22.timesBlockedDueRAWDependencies            0                       # number of times the wf's instructions are blocked due to RAW dependencies
system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::samples            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::mean          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::stdev          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::underflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::0-1            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::2-3            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::4            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::overflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::min_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::max_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::total            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::samples            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::mean          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::stdev          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::underflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::0-1            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::2-3            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::overflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::min_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::max_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::total            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts23.timesBlockedDueVrfPortAvail            0                       # number of times instructions are blocked due to VRF port availability
system.cpu1.CUs0.wavefronts23.timesBlockedDueWAXDependencies            0                       # number of times the wf's instructions are blocked due to WAW or WAR dependencies
system.cpu1.CUs0.wavefronts23.timesBlockedDueRAWDependencies            0                       # number of times the wf's instructions are blocked due to RAW dependencies
system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::samples            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::mean          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::stdev          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::underflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::0-1            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::2-3            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::4            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::overflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::min_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::max_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::total            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::samples            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::mean          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::stdev          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::underflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::0-1            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::2-3            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::overflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::min_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::max_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::total            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts24.timesBlockedDueVrfPortAvail            0                       # number of times instructions are blocked due to VRF port availability
system.cpu1.CUs0.wavefronts24.timesBlockedDueWAXDependencies            0                       # number of times the wf's instructions are blocked due to WAW or WAR dependencies
system.cpu1.CUs0.wavefronts24.timesBlockedDueRAWDependencies          329                       # number of times the wf's instructions are blocked due to RAW dependencies
system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::samples           34                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::mean     0.852941                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::stdev     0.857493                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::underflows            0      0.00%      0.00% # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::0-1           24     70.59%     70.59% # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::2-3           10     29.41%    100.00% # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::4            0      0.00%    100.00% # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::overflows            0      0.00%    100.00% # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::min_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::max_value            2                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::total           34                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::samples           34                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::mean     0.617647                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::stdev     0.493270                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::underflows            0      0.00%      0.00% # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::0-1           34    100.00%    100.00% # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::2-3            0      0.00%    100.00% # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::overflows            0      0.00%    100.00% # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::min_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::max_value            1                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::total           34                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts25.timesBlockedDueVrfPortAvail            0                       # number of times instructions are blocked due to VRF port availability
system.cpu1.CUs0.wavefronts25.timesBlockedDueWAXDependencies            0                       # number of times the wf's instructions are blocked due to WAW or WAR dependencies
system.cpu1.CUs0.wavefronts25.timesBlockedDueRAWDependencies            0                       # number of times the wf's instructions are blocked due to RAW dependencies
system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::samples            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::mean          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::stdev          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::underflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::0-1            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::2-3            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::4            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::overflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::min_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::max_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::total            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::samples            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::mean          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::stdev          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::underflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::0-1            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::2-3            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::overflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::min_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::max_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::total            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts26.timesBlockedDueVrfPortAvail            0                       # number of times instructions are blocked due to VRF port availability
system.cpu1.CUs0.wavefronts26.timesBlockedDueWAXDependencies            0                       # number of times the wf's instructions are blocked due to WAW or WAR dependencies
system.cpu1.CUs0.wavefronts26.timesBlockedDueRAWDependencies            0                       # number of times the wf's instructions are blocked due to RAW dependencies
system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::samples            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::mean          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::stdev          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::underflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::0-1            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::2-3            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::4            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::overflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::min_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::max_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::total            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::samples            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::mean          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::stdev          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::underflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::0-1            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::2-3            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::overflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::min_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::max_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::total            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts27.timesBlockedDueVrfPortAvail            0                       # number of times instructions are blocked due to VRF port availability
system.cpu1.CUs0.wavefronts27.timesBlockedDueWAXDependencies            0                       # number of times the wf's instructions are blocked due to WAW or WAR dependencies
system.cpu1.CUs0.wavefronts27.timesBlockedDueRAWDependencies            0                       # number of times the wf's instructions are blocked due to RAW dependencies
system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::samples            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::mean          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::stdev          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::underflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::0-1            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::2-3            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::4            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::overflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::min_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::max_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::total            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::samples            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::mean          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::stdev          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::underflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::0-1            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::2-3            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::overflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::min_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::max_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::total            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts28.timesBlockedDueVrfPortAvail            0                       # number of times instructions are blocked due to VRF port availability
system.cpu1.CUs0.wavefronts28.timesBlockedDueWAXDependencies            0                       # number of times the wf's instructions are blocked due to WAW or WAR dependencies
system.cpu1.CUs0.wavefronts28.timesBlockedDueRAWDependencies            0                       # number of times the wf's instructions are blocked due to RAW dependencies
system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::samples            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::mean          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::stdev          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::underflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::0-1            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::2-3            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::4            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::overflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::min_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::max_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::total            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::samples            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::mean          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::stdev          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::underflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::0-1            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::2-3            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::overflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::min_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::max_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::total            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts29.timesBlockedDueVrfPortAvail            0                       # number of times instructions are blocked due to VRF port availability
system.cpu1.CUs0.wavefronts29.timesBlockedDueWAXDependencies            0                       # number of times the wf's instructions are blocked due to WAW or WAR dependencies
system.cpu1.CUs0.wavefronts29.timesBlockedDueRAWDependencies            0                       # number of times the wf's instructions are blocked due to RAW dependencies
system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::samples            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::mean          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::stdev          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::underflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::0-1            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::2-3            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::4            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::overflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::min_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::max_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::total            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::samples            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::mean          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::stdev          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::underflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::0-1            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::2-3            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::overflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::min_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::max_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::total            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts30.timesBlockedDueVrfPortAvail            0                       # number of times instructions are blocked due to VRF port availability
system.cpu1.CUs0.wavefronts30.timesBlockedDueWAXDependencies            0                       # number of times the wf's instructions are blocked due to WAW or WAR dependencies
system.cpu1.CUs0.wavefronts30.timesBlockedDueRAWDependencies            0                       # number of times the wf's instructions are blocked due to RAW dependencies
system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::samples            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::mean          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::stdev          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::underflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::0-1            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::2-3            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::4            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::overflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::min_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::max_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::total            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::samples            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::mean          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::stdev          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::underflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::0-1            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::2-3            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::overflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::min_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::max_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::total            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts31.timesBlockedDueVrfPortAvail            0                       # number of times instructions are blocked due to VRF port availability
system.cpu1.CUs0.wavefronts31.timesBlockedDueWAXDependencies            0                       # number of times the wf's instructions are blocked due to WAW or WAR dependencies
system.cpu1.CUs0.wavefronts31.timesBlockedDueRAWDependencies            0                       # number of times the wf's instructions are blocked due to RAW dependencies
system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::samples            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::mean          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::stdev          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::underflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::0-1            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::2-3            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::4            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::overflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::min_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::max_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::total            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::samples            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::mean          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::stdev          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::underflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::0-1            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::2-3            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::overflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::min_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::max_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::total            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::samples           43                       # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::mean     5.813953                       # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::stdev     2.683777                       # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::underflows            0      0.00%      0.00% # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::1            0      0.00%      0.00% # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::2            8     18.60%     18.60% # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::3            8     18.60%     37.21% # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::4            1      2.33%     39.53% # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::5            0      0.00%     39.53% # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::6            1      2.33%     41.86% # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::7            0      0.00%     41.86% # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::8           25     58.14%    100.00% # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::9            0      0.00%    100.00% # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::10            0      0.00%    100.00% # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::11            0      0.00%    100.00% # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::12            0      0.00%    100.00% # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::13            0      0.00%    100.00% # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::14            0      0.00%    100.00% # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::15            0      0.00%    100.00% # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::16            0      0.00%    100.00% # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::17            0      0.00%    100.00% # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::18            0      0.00%    100.00% # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::19            0      0.00%    100.00% # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::20            0      0.00%    100.00% # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::21            0      0.00%    100.00% # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::22            0      0.00%    100.00% # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::23            0      0.00%    100.00% # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::24            0      0.00%    100.00% # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::25            0      0.00%    100.00% # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::26            0      0.00%    100.00% # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::27            0      0.00%    100.00% # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::28            0      0.00%    100.00% # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::29            0      0.00%    100.00% # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::30            0      0.00%    100.00% # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::31            0      0.00%    100.00% # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::32            0      0.00%    100.00% # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::overflows            0      0.00%    100.00% # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::min_value            2                       # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::max_value            8                       # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::total           43                       # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs0.ExecStage.num_cycles_with_no_issue         4357                       # number of cycles the CU issues nothing
system.cpu1.CUs0.ExecStage.num_cycles_with_instr_issued          133                       # number of cycles the CU issued at least one instruction
system.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::ALU0           30                       # Number of cycles at least one instruction of specific type issued
system.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::ALU1           29                       # Number of cycles at least one instruction of specific type issued
system.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::ALU2           29                       # Number of cycles at least one instruction of specific type issued
system.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::ALU3           29                       # Number of cycles at least one instruction of specific type issued
system.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::GM           18                       # Number of cycles at least one instruction of specific type issued
system.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::LM            6                       # Number of cycles at least one instruction of specific type issued
system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU0         1547                       # Number of cycles no instruction of specific type issued
system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU1          483                       # Number of cycles no instruction of specific type issued
system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU2          439                       # Number of cycles no instruction of specific type issued
system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU3          403                       # Number of cycles no instruction of specific type issued
system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::GM          436                       # Number of cycles no instruction of specific type issued
system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::LM           26                       # Number of cycles no instruction of specific type issued
system.cpu1.CUs0.ExecStage.spc::samples          4490                       # Execution units active per cycle (Exec unit=SIMD,MemPipe)
system.cpu1.CUs0.ExecStage.spc::mean         0.031403                       # Execution units active per cycle (Exec unit=SIMD,MemPipe)
system.cpu1.CUs0.ExecStage.spc::stdev        0.185563                       # Execution units active per cycle (Exec unit=SIMD,MemPipe)
system.cpu1.CUs0.ExecStage.spc::underflows            0      0.00%      0.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
system.cpu1.CUs0.ExecStage.spc::0                4357     97.04%     97.04% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
system.cpu1.CUs0.ExecStage.spc::1                 126      2.81%     99.84% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
system.cpu1.CUs0.ExecStage.spc::2                   6      0.13%     99.98% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
system.cpu1.CUs0.ExecStage.spc::3                   1      0.02%    100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
system.cpu1.CUs0.ExecStage.spc::4                   0      0.00%    100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
system.cpu1.CUs0.ExecStage.spc::5                   0      0.00%    100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
system.cpu1.CUs0.ExecStage.spc::6                   0      0.00%    100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
system.cpu1.CUs0.ExecStage.spc::overflows            0      0.00%    100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
system.cpu1.CUs0.ExecStage.spc::min_value            0                       # Execution units active per cycle (Exec unit=SIMD,MemPipe)
system.cpu1.CUs0.ExecStage.spc::max_value            3                       # Execution units active per cycle (Exec unit=SIMD,MemPipe)
system.cpu1.CUs0.ExecStage.spc::total            4490                       # Execution units active per cycle (Exec unit=SIMD,MemPipe)
system.cpu1.CUs0.ExecStage.num_transitions_active_to_idle           68                       # number of CU transitions from active to idle
system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::samples           68                       # duration of idle periods in cycles
system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::mean    59.558824                       # duration of idle periods in cycles
system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::stdev   213.072854                       # duration of idle periods in cycles
system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::underflows            0      0.00%      0.00% # duration of idle periods in cycles
system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::0-4           48     70.59%     70.59% # duration of idle periods in cycles
system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::5-9            8     11.76%     82.35% # duration of idle periods in cycles
system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::10-14            1      1.47%     83.82% # duration of idle periods in cycles
system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::15-19            1      1.47%     85.29% # duration of idle periods in cycles
system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::20-24            2      2.94%     88.24% # duration of idle periods in cycles
system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::25-29            1      1.47%     89.71% # duration of idle periods in cycles
system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::30-34            0      0.00%     89.71% # duration of idle periods in cycles
system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::35-39            0      0.00%     89.71% # duration of idle periods in cycles
system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::40-44            0      0.00%     89.71% # duration of idle periods in cycles
system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::45-49            0      0.00%     89.71% # duration of idle periods in cycles
system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::50-54            0      0.00%     89.71% # duration of idle periods in cycles
system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::55-59            0      0.00%     89.71% # duration of idle periods in cycles
system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::60-64            0      0.00%     89.71% # duration of idle periods in cycles
system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::65-69            0      0.00%     89.71% # duration of idle periods in cycles
system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::70-74            0      0.00%     89.71% # duration of idle periods in cycles
system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::75            0      0.00%     89.71% # duration of idle periods in cycles
system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::overflows            7     10.29%    100.00% # duration of idle periods in cycles
system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::min_value            1                       # duration of idle periods in cycles
system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::max_value         1300                       # duration of idle periods in cycles
system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::total           68                       # duration of idle periods in cycles
system.cpu1.CUs0.GlobalMemPipeline.load_vrf_bank_conflict_cycles            0                       # total number of cycles GM data are delayed before updating the VRF
system.cpu1.CUs0.LocalMemPipeline.load_vrf_bank_conflict_cycles            0                       # total number of cycles LDS data are delayed before updating the VRF
system.cpu1.CUs0.tlb_requests                     769                       # number of uncoalesced requests
system.cpu1.CUs0.tlb_cycles              -373675448000                       # total number of cycles for all uncoalesced requests
system.cpu1.CUs0.avg_translation_latency -485923859.557867                       # Avg. translation latency for data translations
system.cpu1.CUs0.TLB_hits_distribution::page_table          769                       # TLB hits distribution (0 for page table, x for Lx-TLB
system.cpu1.CUs0.TLB_hits_distribution::L1_TLB            0                       # TLB hits distribution (0 for page table, x for Lx-TLB
system.cpu1.CUs0.TLB_hits_distribution::L2_TLB            0                       # TLB hits distribution (0 for page table, x for Lx-TLB
system.cpu1.CUs0.TLB_hits_distribution::L3_TLB            0                       # TLB hits distribution (0 for page table, x for Lx-TLB
system.cpu1.CUs0.lds_bank_access_cnt               54                       # Total number of LDS bank accesses
system.cpu1.CUs0.lds_bank_conflicts::samples            6                       # Number of bank conflicts per LDS memory packet
system.cpu1.CUs0.lds_bank_conflicts::mean            8                       # Number of bank conflicts per LDS memory packet
system.cpu1.CUs0.lds_bank_conflicts::stdev     6.196773                       # Number of bank conflicts per LDS memory packet
system.cpu1.CUs0.lds_bank_conflicts::underflows            0      0.00%      0.00% # Number of bank conflicts per LDS memory packet
system.cpu1.CUs0.lds_bank_conflicts::0-1            2     33.33%     33.33% # Number of bank conflicts per LDS memory packet
system.cpu1.CUs0.lds_bank_conflicts::2-3            0      0.00%     33.33% # Number of bank conflicts per LDS memory packet
system.cpu1.CUs0.lds_bank_conflicts::4-5            0      0.00%     33.33% # Number of bank conflicts per LDS memory packet
system.cpu1.CUs0.lds_bank_conflicts::6-7            0      0.00%     33.33% # Number of bank conflicts per LDS memory packet
system.cpu1.CUs0.lds_bank_conflicts::8-9            0      0.00%     33.33% # Number of bank conflicts per LDS memory packet
system.cpu1.CUs0.lds_bank_conflicts::10-11            0      0.00%     33.33% # Number of bank conflicts per LDS memory packet
system.cpu1.CUs0.lds_bank_conflicts::12-13            4     66.67%    100.00% # Number of bank conflicts per LDS memory packet
system.cpu1.CUs0.lds_bank_conflicts::14-15            0      0.00%    100.00% # Number of bank conflicts per LDS memory packet
system.cpu1.CUs0.lds_bank_conflicts::16-17            0      0.00%    100.00% # Number of bank conflicts per LDS memory packet
system.cpu1.CUs0.lds_bank_conflicts::18-19            0      0.00%    100.00% # Number of bank conflicts per LDS memory packet
system.cpu1.CUs0.lds_bank_conflicts::20-21            0      0.00%    100.00% # Number of bank conflicts per LDS memory packet
system.cpu1.CUs0.lds_bank_conflicts::22-23            0      0.00%    100.00% # Number of bank conflicts per LDS memory packet
system.cpu1.CUs0.lds_bank_conflicts::24-25            0      0.00%    100.00% # Number of bank conflicts per LDS memory packet
system.cpu1.CUs0.lds_bank_conflicts::26-27            0      0.00%    100.00% # Number of bank conflicts per LDS memory packet
system.cpu1.CUs0.lds_bank_conflicts::28-29            0      0.00%    100.00% # Number of bank conflicts per LDS memory packet
system.cpu1.CUs0.lds_bank_conflicts::30-31            0      0.00%    100.00% # Number of bank conflicts per LDS memory packet
system.cpu1.CUs0.lds_bank_conflicts::32-33            0      0.00%    100.00% # Number of bank conflicts per LDS memory packet
system.cpu1.CUs0.lds_bank_conflicts::34-35            0      0.00%    100.00% # Number of bank conflicts per LDS memory packet
system.cpu1.CUs0.lds_bank_conflicts::36-37            0      0.00%    100.00% # Number of bank conflicts per LDS memory packet
system.cpu1.CUs0.lds_bank_conflicts::38-39            0      0.00%    100.00% # Number of bank conflicts per LDS memory packet
system.cpu1.CUs0.lds_bank_conflicts::40-41            0      0.00%    100.00% # Number of bank conflicts per LDS memory packet
system.cpu1.CUs0.lds_bank_conflicts::42-43            0      0.00%    100.00% # Number of bank conflicts per LDS memory packet
system.cpu1.CUs0.lds_bank_conflicts::44-45            0      0.00%    100.00% # Number of bank conflicts per LDS memory packet
system.cpu1.CUs0.lds_bank_conflicts::46-47            0      0.00%    100.00% # Number of bank conflicts per LDS memory packet
system.cpu1.CUs0.lds_bank_conflicts::48-49            0      0.00%    100.00% # Number of bank conflicts per LDS memory packet
system.cpu1.CUs0.lds_bank_conflicts::50-51            0      0.00%    100.00% # Number of bank conflicts per LDS memory packet
system.cpu1.CUs0.lds_bank_conflicts::52-53            0      0.00%    100.00% # Number of bank conflicts per LDS memory packet
system.cpu1.CUs0.lds_bank_conflicts::54-55            0      0.00%    100.00% # Number of bank conflicts per LDS memory packet
system.cpu1.CUs0.lds_bank_conflicts::56-57            0      0.00%    100.00% # Number of bank conflicts per LDS memory packet
system.cpu1.CUs0.lds_bank_conflicts::58-59            0      0.00%    100.00% # Number of bank conflicts per LDS memory packet
system.cpu1.CUs0.lds_bank_conflicts::60-61            0      0.00%    100.00% # Number of bank conflicts per LDS memory packet
system.cpu1.CUs0.lds_bank_conflicts::62-63            0      0.00%    100.00% # Number of bank conflicts per LDS memory packet
system.cpu1.CUs0.lds_bank_conflicts::64             0      0.00%    100.00% # Number of bank conflicts per LDS memory packet
system.cpu1.CUs0.lds_bank_conflicts::overflows            0      0.00%    100.00% # Number of bank conflicts per LDS memory packet
system.cpu1.CUs0.lds_bank_conflicts::min_value            0                       # Number of bank conflicts per LDS memory packet
system.cpu1.CUs0.lds_bank_conflicts::max_value           12                       # Number of bank conflicts per LDS memory packet
system.cpu1.CUs0.lds_bank_conflicts::total            6                       # Number of bank conflicts per LDS memory packet
system.cpu1.CUs0.page_divergence_dist::samples           17                       # pages touched per wf (over all mem. instr.)
system.cpu1.CUs0.page_divergence_dist::mean            1                       # pages touched per wf (over all mem. instr.)
system.cpu1.CUs0.page_divergence_dist::stdev            0                       # pages touched per wf (over all mem. instr.)
system.cpu1.CUs0.page_divergence_dist::underflows            0      0.00%      0.00% # pages touched per wf (over all mem. instr.)
system.cpu1.CUs0.page_divergence_dist::1-4           17    100.00%    100.00% # pages touched per wf (over all mem. instr.)
system.cpu1.CUs0.page_divergence_dist::5-8            0      0.00%    100.00% # pages touched per wf (over all mem. instr.)
system.cpu1.CUs0.page_divergence_dist::9-12            0      0.00%    100.00% # pages touched per wf (over all mem. instr.)
system.cpu1.CUs0.page_divergence_dist::13-16            0      0.00%    100.00% # pages touched per wf (over all mem. instr.)
system.cpu1.CUs0.page_divergence_dist::17-20            0      0.00%    100.00% # pages touched per wf (over all mem. instr.)
system.cpu1.CUs0.page_divergence_dist::21-24            0      0.00%    100.00% # pages touched per wf (over all mem. instr.)
system.cpu1.CUs0.page_divergence_dist::25-28            0      0.00%    100.00% # pages touched per wf (over all mem. instr.)
system.cpu1.CUs0.page_divergence_dist::29-32            0      0.00%    100.00% # pages touched per wf (over all mem. instr.)
system.cpu1.CUs0.page_divergence_dist::33-36            0      0.00%    100.00% # pages touched per wf (over all mem. instr.)
system.cpu1.CUs0.page_divergence_dist::37-40            0      0.00%    100.00% # pages touched per wf (over all mem. instr.)
system.cpu1.CUs0.page_divergence_dist::41-44            0      0.00%    100.00% # pages touched per wf (over all mem. instr.)
system.cpu1.CUs0.page_divergence_dist::45-48            0      0.00%    100.00% # pages touched per wf (over all mem. instr.)
system.cpu1.CUs0.page_divergence_dist::49-52            0      0.00%    100.00% # pages touched per wf (over all mem. instr.)
system.cpu1.CUs0.page_divergence_dist::53-56            0      0.00%    100.00% # pages touched per wf (over all mem. instr.)
system.cpu1.CUs0.page_divergence_dist::57-60            0      0.00%    100.00% # pages touched per wf (over all mem. instr.)
system.cpu1.CUs0.page_divergence_dist::61-64            0      0.00%    100.00% # pages touched per wf (over all mem. instr.)
system.cpu1.CUs0.page_divergence_dist::overflows            0      0.00%    100.00% # pages touched per wf (over all mem. instr.)
system.cpu1.CUs0.page_divergence_dist::min_value            1                       # pages touched per wf (over all mem. instr.)
system.cpu1.CUs0.page_divergence_dist::max_value            1                       # pages touched per wf (over all mem. instr.)
system.cpu1.CUs0.page_divergence_dist::total           17                       # pages touched per wf (over all mem. instr.)
system.cpu1.CUs0.global_mem_instr_cnt              17                       # dynamic global memory instructions count
system.cpu1.CUs0.local_mem_instr_cnt                6                       # dynamic local memory intruction count
system.cpu1.CUs0.wg_blocked_due_lds_alloc            0                       # Workgroup blocked due to LDS capacity
system.cpu1.CUs0.num_instr_executed               141                       # number of instructions executed
system.cpu1.CUs0.inst_exec_rate::samples          141                       # Instruction Execution Rate: Number of executed vector instructions per cycle
system.cpu1.CUs0.inst_exec_rate::mean       94.900709                       # Instruction Execution Rate: Number of executed vector instructions per cycle
system.cpu1.CUs0.inst_exec_rate::stdev     247.493154                       # Instruction Execution Rate: Number of executed vector instructions per cycle
system.cpu1.CUs0.inst_exec_rate::underflows            0      0.00%      0.00% # Instruction Execution Rate: Number of executed vector instructions per cycle
system.cpu1.CUs0.inst_exec_rate::0-1                1      0.71%      0.71% # Instruction Execution Rate: Number of executed vector instructions per cycle
system.cpu1.CUs0.inst_exec_rate::2-3               12      8.51%      9.22% # Instruction Execution Rate: Number of executed vector instructions per cycle
system.cpu1.CUs0.inst_exec_rate::4-5               53     37.59%     46.81% # Instruction Execution Rate: Number of executed vector instructions per cycle
system.cpu1.CUs0.inst_exec_rate::6-7               31     21.99%     68.79% # Instruction Execution Rate: Number of executed vector instructions per cycle
system.cpu1.CUs0.inst_exec_rate::8-9                3      2.13%     70.92% # Instruction Execution Rate: Number of executed vector instructions per cycle
system.cpu1.CUs0.inst_exec_rate::10                 1      0.71%     71.63% # Instruction Execution Rate: Number of executed vector instructions per cycle
system.cpu1.CUs0.inst_exec_rate::overflows           40     28.37%    100.00% # Instruction Execution Rate: Number of executed vector instructions per cycle
system.cpu1.CUs0.inst_exec_rate::min_value            1                       # Instruction Execution Rate: Number of executed vector instructions per cycle
system.cpu1.CUs0.inst_exec_rate::max_value         1303                       # Instruction Execution Rate: Number of executed vector instructions per cycle
system.cpu1.CUs0.inst_exec_rate::total            141                       # Instruction Execution Rate: Number of executed vector instructions per cycle
system.cpu1.CUs0.num_vec_ops_executed            6769                       # number of vec ops executed (e.g. VSZ/inst)
system.cpu1.CUs0.num_total_cycles                4490                       # number of cycles the CU ran for
system.cpu1.CUs0.vpc                         1.507572                       # Vector Operations per cycle (this CU only)
system.cpu1.CUs0.ipc                         0.031403                       # Instructions per cycle (this CU only)
system.cpu1.CUs0.warp_execution_dist::samples          141                       # number of lanes active per instruction (oval all instructions)
system.cpu1.CUs0.warp_execution_dist::mean    48.007092                       # number of lanes active per instruction (oval all instructions)
system.cpu1.CUs0.warp_execution_dist::stdev    23.719942                       # number of lanes active per instruction (oval all instructions)
system.cpu1.CUs0.warp_execution_dist::underflows            0      0.00%      0.00% # number of lanes active per instruction (oval all instructions)
system.cpu1.CUs0.warp_execution_dist::1-4            5      3.55%      3.55% # number of lanes active per instruction (oval all instructions)
system.cpu1.CUs0.warp_execution_dist::5-8            0      0.00%      3.55% # number of lanes active per instruction (oval all instructions)
system.cpu1.CUs0.warp_execution_dist::9-12            0      0.00%      3.55% # number of lanes active per instruction (oval all instructions)
system.cpu1.CUs0.warp_execution_dist::13-16           36     25.53%     29.08% # number of lanes active per instruction (oval all instructions)
system.cpu1.CUs0.warp_execution_dist::17-20            0      0.00%     29.08% # number of lanes active per instruction (oval all instructions)
system.cpu1.CUs0.warp_execution_dist::21-24            0      0.00%     29.08% # number of lanes active per instruction (oval all instructions)
system.cpu1.CUs0.warp_execution_dist::25-28            0      0.00%     29.08% # number of lanes active per instruction (oval all instructions)
system.cpu1.CUs0.warp_execution_dist::29-32            0      0.00%     29.08% # number of lanes active per instruction (oval all instructions)
system.cpu1.CUs0.warp_execution_dist::33-36            0      0.00%     29.08% # number of lanes active per instruction (oval all instructions)
system.cpu1.CUs0.warp_execution_dist::37-40            0      0.00%     29.08% # number of lanes active per instruction (oval all instructions)
system.cpu1.CUs0.warp_execution_dist::41-44            0      0.00%     29.08% # number of lanes active per instruction (oval all instructions)
system.cpu1.CUs0.warp_execution_dist::45-48            0      0.00%     29.08% # number of lanes active per instruction (oval all instructions)
system.cpu1.CUs0.warp_execution_dist::49-52            8      5.67%     34.75% # number of lanes active per instruction (oval all instructions)
system.cpu1.CUs0.warp_execution_dist::53-56            0      0.00%     34.75% # number of lanes active per instruction (oval all instructions)
system.cpu1.CUs0.warp_execution_dist::57-60            0      0.00%     34.75% # number of lanes active per instruction (oval all instructions)
system.cpu1.CUs0.warp_execution_dist::61-64           92     65.25%    100.00% # number of lanes active per instruction (oval all instructions)
system.cpu1.CUs0.warp_execution_dist::overflows            0      0.00%    100.00% # number of lanes active per instruction (oval all instructions)
system.cpu1.CUs0.warp_execution_dist::min_value            1                       # number of lanes active per instruction (oval all instructions)
system.cpu1.CUs0.warp_execution_dist::max_value           64                       # number of lanes active per instruction (oval all instructions)
system.cpu1.CUs0.warp_execution_dist::total          141                       # number of lanes active per instruction (oval all instructions)
system.cpu1.CUs0.gmem_lanes_execution_dist::samples           18                       # number of active lanes per global memory instruction
system.cpu1.CUs0.gmem_lanes_execution_dist::mean    37.833333                       # number of active lanes per global memory instruction
system.cpu1.CUs0.gmem_lanes_execution_dist::stdev    27.064737                       # number of active lanes per global memory instruction
system.cpu1.CUs0.gmem_lanes_execution_dist::underflows            0      0.00%      0.00% # number of active lanes per global memory instruction
system.cpu1.CUs0.gmem_lanes_execution_dist::1-4            1      5.56%      5.56% # number of active lanes per global memory instruction
system.cpu1.CUs0.gmem_lanes_execution_dist::5-8            0      0.00%      5.56% # number of active lanes per global memory instruction
system.cpu1.CUs0.gmem_lanes_execution_dist::9-12            0      0.00%      5.56% # number of active lanes per global memory instruction
system.cpu1.CUs0.gmem_lanes_execution_dist::13-16            8     44.44%     50.00% # number of active lanes per global memory instruction
system.cpu1.CUs0.gmem_lanes_execution_dist::17-20            0      0.00%     50.00% # number of active lanes per global memory instruction
system.cpu1.CUs0.gmem_lanes_execution_dist::21-24            0      0.00%     50.00% # number of active lanes per global memory instruction
system.cpu1.CUs0.gmem_lanes_execution_dist::25-28            0      0.00%     50.00% # number of active lanes per global memory instruction
system.cpu1.CUs0.gmem_lanes_execution_dist::29-32            0      0.00%     50.00% # number of active lanes per global memory instruction
system.cpu1.CUs0.gmem_lanes_execution_dist::33-36            0      0.00%     50.00% # number of active lanes per global memory instruction
system.cpu1.CUs0.gmem_lanes_execution_dist::37-40            0      0.00%     50.00% # number of active lanes per global memory instruction
system.cpu1.CUs0.gmem_lanes_execution_dist::41-44            0      0.00%     50.00% # number of active lanes per global memory instruction
system.cpu1.CUs0.gmem_lanes_execution_dist::45-48            0      0.00%     50.00% # number of active lanes per global memory instruction
system.cpu1.CUs0.gmem_lanes_execution_dist::49-52            0      0.00%     50.00% # number of active lanes per global memory instruction
system.cpu1.CUs0.gmem_lanes_execution_dist::53-56            0      0.00%     50.00% # number of active lanes per global memory instruction
system.cpu1.CUs0.gmem_lanes_execution_dist::57-60            0      0.00%     50.00% # number of active lanes per global memory instruction
system.cpu1.CUs0.gmem_lanes_execution_dist::61-64            9     50.00%    100.00% # number of active lanes per global memory instruction
system.cpu1.CUs0.gmem_lanes_execution_dist::overflows            0      0.00%    100.00% # number of active lanes per global memory instruction
system.cpu1.CUs0.gmem_lanes_execution_dist::min_value            1                       # number of active lanes per global memory instruction
system.cpu1.CUs0.gmem_lanes_execution_dist::max_value           64                       # number of active lanes per global memory instruction
system.cpu1.CUs0.gmem_lanes_execution_dist::total           18                       # number of active lanes per global memory instruction
system.cpu1.CUs0.lmem_lanes_execution_dist::samples            6                       # number of active lanes per local memory instruction
system.cpu1.CUs0.lmem_lanes_execution_dist::mean    19.500000                       # number of active lanes per local memory instruction
system.cpu1.CUs0.lmem_lanes_execution_dist::stdev    22.322634                       # number of active lanes per local memory instruction
system.cpu1.CUs0.lmem_lanes_execution_dist::underflows            0      0.00%      0.00% # number of active lanes per local memory instruction
system.cpu1.CUs0.lmem_lanes_execution_dist::1-4            1     16.67%     16.67% # number of active lanes per local memory instruction
system.cpu1.CUs0.lmem_lanes_execution_dist::5-8            0      0.00%     16.67% # number of active lanes per local memory instruction
system.cpu1.CUs0.lmem_lanes_execution_dist::9-12            0      0.00%     16.67% # number of active lanes per local memory instruction
system.cpu1.CUs0.lmem_lanes_execution_dist::13-16            4     66.67%     83.33% # number of active lanes per local memory instruction
system.cpu1.CUs0.lmem_lanes_execution_dist::17-20            0      0.00%     83.33% # number of active lanes per local memory instruction
system.cpu1.CUs0.lmem_lanes_execution_dist::21-24            0      0.00%     83.33% # number of active lanes per local memory instruction
system.cpu1.CUs0.lmem_lanes_execution_dist::25-28            0      0.00%     83.33% # number of active lanes per local memory instruction
system.cpu1.CUs0.lmem_lanes_execution_dist::29-32            0      0.00%     83.33% # number of active lanes per local memory instruction
system.cpu1.CUs0.lmem_lanes_execution_dist::33-36            0      0.00%     83.33% # number of active lanes per local memory instruction
system.cpu1.CUs0.lmem_lanes_execution_dist::37-40            0      0.00%     83.33% # number of active lanes per local memory instruction
system.cpu1.CUs0.lmem_lanes_execution_dist::41-44            0      0.00%     83.33% # number of active lanes per local memory instruction
system.cpu1.CUs0.lmem_lanes_execution_dist::45-48            0      0.00%     83.33% # number of active lanes per local memory instruction
system.cpu1.CUs0.lmem_lanes_execution_dist::49-52            0      0.00%     83.33% # number of active lanes per local memory instruction
system.cpu1.CUs0.lmem_lanes_execution_dist::53-56            0      0.00%     83.33% # number of active lanes per local memory instruction
system.cpu1.CUs0.lmem_lanes_execution_dist::57-60            0      0.00%     83.33% # number of active lanes per local memory instruction
system.cpu1.CUs0.lmem_lanes_execution_dist::61-64            1     16.67%    100.00% # number of active lanes per local memory instruction
system.cpu1.CUs0.lmem_lanes_execution_dist::overflows            0      0.00%    100.00% # number of active lanes per local memory instruction
system.cpu1.CUs0.lmem_lanes_execution_dist::min_value            1                       # number of active lanes per local memory instruction
system.cpu1.CUs0.lmem_lanes_execution_dist::max_value           64                       # number of active lanes per local memory instruction
system.cpu1.CUs0.lmem_lanes_execution_dist::total            6                       # number of active lanes per local memory instruction
system.cpu1.CUs0.num_alu_insts_executed           118                       # Number of dynamic non-GM memory insts executed
system.cpu1.CUs0.times_wg_blocked_due_vgpr_alloc            0                       # Number of times WGs are blocked due to VGPR allocation per SIMD
system.cpu1.CUs0.num_CAS_ops                        0                       # number of compare and swap operations
system.cpu1.CUs0.num_failed_CAS_ops                 0                       # number of compare and swap operations that failed
system.cpu1.CUs0.num_completed_wfs                  4                       # number of completed wavefronts
system.cpu1.CUs1.wavefronts00.timesBlockedDueVrfPortAvail            0                       # number of times instructions are blocked due to VRF port availability
system.cpu1.CUs1.wavefronts00.timesBlockedDueWAXDependencies            0                       # number of times the wf's instructions are blocked due to WAW or WAR dependencies
system.cpu1.CUs1.wavefronts00.timesBlockedDueRAWDependencies          377                       # number of times the wf's instructions are blocked due to RAW dependencies
system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::samples           39                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::mean     0.794872                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::stdev     0.863880                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::underflows            0      0.00%      0.00% # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::0-1           28     71.79%     71.79% # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::2-3           11     28.21%    100.00% # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::4            0      0.00%    100.00% # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::overflows            0      0.00%    100.00% # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::min_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::max_value            2                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::total           39                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::samples           39                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::mean     0.589744                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::stdev     0.498310                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::underflows            0      0.00%      0.00% # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::0-1           39    100.00%    100.00% # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::2-3            0      0.00%    100.00% # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::overflows            0      0.00%    100.00% # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::min_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::max_value            1                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::total           39                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts01.timesBlockedDueVrfPortAvail            0                       # number of times instructions are blocked due to VRF port availability
system.cpu1.CUs1.wavefronts01.timesBlockedDueWAXDependencies            0                       # number of times the wf's instructions are blocked due to WAW or WAR dependencies
system.cpu1.CUs1.wavefronts01.timesBlockedDueRAWDependencies            0                       # number of times the wf's instructions are blocked due to RAW dependencies
system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::samples            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::mean          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::stdev          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::underflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::0-1            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::2-3            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::4            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::overflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::min_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::max_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::total            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::samples            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::mean          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::stdev          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::underflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::0-1            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::2-3            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::overflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::min_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::max_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::total            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts02.timesBlockedDueVrfPortAvail            0                       # number of times instructions are blocked due to VRF port availability
system.cpu1.CUs1.wavefronts02.timesBlockedDueWAXDependencies            0                       # number of times the wf's instructions are blocked due to WAW or WAR dependencies
system.cpu1.CUs1.wavefronts02.timesBlockedDueRAWDependencies            0                       # number of times the wf's instructions are blocked due to RAW dependencies
system.cpu1.CUs1.wavefronts02.src_reg_operand_dist::samples            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts02.src_reg_operand_dist::mean          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts02.src_reg_operand_dist::stdev          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts02.src_reg_operand_dist::underflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts02.src_reg_operand_dist::0-1            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts02.src_reg_operand_dist::2-3            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts02.src_reg_operand_dist::4            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts02.src_reg_operand_dist::overflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts02.src_reg_operand_dist::min_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts02.src_reg_operand_dist::max_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts02.src_reg_operand_dist::total            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::samples            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::mean          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::stdev          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::underflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::0-1            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::2-3            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::overflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::min_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::max_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::total            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts03.timesBlockedDueVrfPortAvail            0                       # number of times instructions are blocked due to VRF port availability
system.cpu1.CUs1.wavefronts03.timesBlockedDueWAXDependencies            0                       # number of times the wf's instructions are blocked due to WAW or WAR dependencies
system.cpu1.CUs1.wavefronts03.timesBlockedDueRAWDependencies            0                       # number of times the wf's instructions are blocked due to RAW dependencies
system.cpu1.CUs1.wavefronts03.src_reg_operand_dist::samples            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts03.src_reg_operand_dist::mean          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts03.src_reg_operand_dist::stdev          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts03.src_reg_operand_dist::underflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts03.src_reg_operand_dist::0-1            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts03.src_reg_operand_dist::2-3            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts03.src_reg_operand_dist::4            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts03.src_reg_operand_dist::overflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts03.src_reg_operand_dist::min_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts03.src_reg_operand_dist::max_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts03.src_reg_operand_dist::total            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::samples            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::mean          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::stdev          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::underflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::0-1            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::2-3            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::overflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::min_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::max_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::total            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts04.timesBlockedDueVrfPortAvail            0                       # number of times instructions are blocked due to VRF port availability
system.cpu1.CUs1.wavefronts04.timesBlockedDueWAXDependencies            0                       # number of times the wf's instructions are blocked due to WAW or WAR dependencies
system.cpu1.CUs1.wavefronts04.timesBlockedDueRAWDependencies            0                       # number of times the wf's instructions are blocked due to RAW dependencies
system.cpu1.CUs1.wavefronts04.src_reg_operand_dist::samples            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts04.src_reg_operand_dist::mean          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts04.src_reg_operand_dist::stdev          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts04.src_reg_operand_dist::underflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts04.src_reg_operand_dist::0-1            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts04.src_reg_operand_dist::2-3            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts04.src_reg_operand_dist::4            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts04.src_reg_operand_dist::overflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts04.src_reg_operand_dist::min_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts04.src_reg_operand_dist::max_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts04.src_reg_operand_dist::total            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::samples            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::mean          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::stdev          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::underflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::0-1            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::2-3            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::overflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::min_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::max_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::total            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts05.timesBlockedDueVrfPortAvail            0                       # number of times instructions are blocked due to VRF port availability
system.cpu1.CUs1.wavefronts05.timesBlockedDueWAXDependencies            0                       # number of times the wf's instructions are blocked due to WAW or WAR dependencies
system.cpu1.CUs1.wavefronts05.timesBlockedDueRAWDependencies            0                       # number of times the wf's instructions are blocked due to RAW dependencies
system.cpu1.CUs1.wavefronts05.src_reg_operand_dist::samples            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts05.src_reg_operand_dist::mean          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts05.src_reg_operand_dist::stdev          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts05.src_reg_operand_dist::underflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts05.src_reg_operand_dist::0-1            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts05.src_reg_operand_dist::2-3            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts05.src_reg_operand_dist::4            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts05.src_reg_operand_dist::overflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts05.src_reg_operand_dist::min_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts05.src_reg_operand_dist::max_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts05.src_reg_operand_dist::total            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::samples            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::mean          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::stdev          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::underflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::0-1            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::2-3            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::overflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::min_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::max_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::total            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts06.timesBlockedDueVrfPortAvail            0                       # number of times instructions are blocked due to VRF port availability
system.cpu1.CUs1.wavefronts06.timesBlockedDueWAXDependencies            0                       # number of times the wf's instructions are blocked due to WAW or WAR dependencies
system.cpu1.CUs1.wavefronts06.timesBlockedDueRAWDependencies            0                       # number of times the wf's instructions are blocked due to RAW dependencies
system.cpu1.CUs1.wavefronts06.src_reg_operand_dist::samples            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts06.src_reg_operand_dist::mean          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts06.src_reg_operand_dist::stdev          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts06.src_reg_operand_dist::underflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts06.src_reg_operand_dist::0-1            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts06.src_reg_operand_dist::2-3            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts06.src_reg_operand_dist::4            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts06.src_reg_operand_dist::overflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts06.src_reg_operand_dist::min_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts06.src_reg_operand_dist::max_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts06.src_reg_operand_dist::total            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::samples            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::mean          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::stdev          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::underflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::0-1            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::2-3            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::overflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::min_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::max_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::total            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts07.timesBlockedDueVrfPortAvail            0                       # number of times instructions are blocked due to VRF port availability
system.cpu1.CUs1.wavefronts07.timesBlockedDueWAXDependencies            0                       # number of times the wf's instructions are blocked due to WAW or WAR dependencies
system.cpu1.CUs1.wavefronts07.timesBlockedDueRAWDependencies            0                       # number of times the wf's instructions are blocked due to RAW dependencies
system.cpu1.CUs1.wavefronts07.src_reg_operand_dist::samples            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts07.src_reg_operand_dist::mean          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts07.src_reg_operand_dist::stdev          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts07.src_reg_operand_dist::underflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts07.src_reg_operand_dist::0-1            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts07.src_reg_operand_dist::2-3            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts07.src_reg_operand_dist::4            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts07.src_reg_operand_dist::overflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts07.src_reg_operand_dist::min_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts07.src_reg_operand_dist::max_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts07.src_reg_operand_dist::total            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::samples            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::mean          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::stdev          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::underflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::0-1            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::2-3            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::overflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::min_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::max_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::total            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts08.timesBlockedDueVrfPortAvail            0                       # number of times instructions are blocked due to VRF port availability
system.cpu1.CUs1.wavefronts08.timesBlockedDueWAXDependencies            0                       # number of times the wf's instructions are blocked due to WAW or WAR dependencies
system.cpu1.CUs1.wavefronts08.timesBlockedDueRAWDependencies          355                       # number of times the wf's instructions are blocked due to RAW dependencies
system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::samples           34                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::mean     0.852941                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::stdev     0.857493                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::underflows            0      0.00%      0.00% # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::0-1           24     70.59%     70.59% # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::2-3           10     29.41%    100.00% # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::4            0      0.00%    100.00% # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::overflows            0      0.00%    100.00% # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::min_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::max_value            2                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::total           34                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::samples           34                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::mean     0.617647                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::stdev     0.493270                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::underflows            0      0.00%      0.00% # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::0-1           34    100.00%    100.00% # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::2-3            0      0.00%    100.00% # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::overflows            0      0.00%    100.00% # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::min_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::max_value            1                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::total           34                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts09.timesBlockedDueVrfPortAvail            0                       # number of times instructions are blocked due to VRF port availability
system.cpu1.CUs1.wavefronts09.timesBlockedDueWAXDependencies            0                       # number of times the wf's instructions are blocked due to WAW or WAR dependencies
system.cpu1.CUs1.wavefronts09.timesBlockedDueRAWDependencies            0                       # number of times the wf's instructions are blocked due to RAW dependencies
system.cpu1.CUs1.wavefronts09.src_reg_operand_dist::samples            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts09.src_reg_operand_dist::mean          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts09.src_reg_operand_dist::stdev          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts09.src_reg_operand_dist::underflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts09.src_reg_operand_dist::0-1            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts09.src_reg_operand_dist::2-3            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts09.src_reg_operand_dist::4            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts09.src_reg_operand_dist::overflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts09.src_reg_operand_dist::min_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts09.src_reg_operand_dist::max_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts09.src_reg_operand_dist::total            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::samples            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::mean          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::stdev          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::underflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::0-1            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::2-3            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::overflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::min_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::max_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::total            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts10.timesBlockedDueVrfPortAvail            0                       # number of times instructions are blocked due to VRF port availability
system.cpu1.CUs1.wavefronts10.timesBlockedDueWAXDependencies            0                       # number of times the wf's instructions are blocked due to WAW or WAR dependencies
system.cpu1.CUs1.wavefronts10.timesBlockedDueRAWDependencies            0                       # number of times the wf's instructions are blocked due to RAW dependencies
system.cpu1.CUs1.wavefronts10.src_reg_operand_dist::samples            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts10.src_reg_operand_dist::mean          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts10.src_reg_operand_dist::stdev          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts10.src_reg_operand_dist::underflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts10.src_reg_operand_dist::0-1            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts10.src_reg_operand_dist::2-3            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts10.src_reg_operand_dist::4            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts10.src_reg_operand_dist::overflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts10.src_reg_operand_dist::min_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts10.src_reg_operand_dist::max_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts10.src_reg_operand_dist::total            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::samples            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::mean          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::stdev          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::underflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::0-1            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::2-3            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::overflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::min_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::max_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::total            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts11.timesBlockedDueVrfPortAvail            0                       # number of times instructions are blocked due to VRF port availability
system.cpu1.CUs1.wavefronts11.timesBlockedDueWAXDependencies            0                       # number of times the wf's instructions are blocked due to WAW or WAR dependencies
system.cpu1.CUs1.wavefronts11.timesBlockedDueRAWDependencies            0                       # number of times the wf's instructions are blocked due to RAW dependencies
system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::samples            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::mean          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::stdev          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::underflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::0-1            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::2-3            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::4            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::overflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::min_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::max_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::total            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::samples            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::mean          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::stdev          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::underflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::0-1            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::2-3            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::overflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::min_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::max_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::total            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts12.timesBlockedDueVrfPortAvail            0                       # number of times instructions are blocked due to VRF port availability
system.cpu1.CUs1.wavefronts12.timesBlockedDueWAXDependencies            0                       # number of times the wf's instructions are blocked due to WAW or WAR dependencies
system.cpu1.CUs1.wavefronts12.timesBlockedDueRAWDependencies            0                       # number of times the wf's instructions are blocked due to RAW dependencies
system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::samples            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::mean          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::stdev          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::underflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::0-1            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::2-3            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::4            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::overflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::min_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::max_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::total            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::samples            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::mean          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::stdev          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::underflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::0-1            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::2-3            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::overflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::min_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::max_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::total            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts13.timesBlockedDueVrfPortAvail            0                       # number of times instructions are blocked due to VRF port availability
system.cpu1.CUs1.wavefronts13.timesBlockedDueWAXDependencies            0                       # number of times the wf's instructions are blocked due to WAW or WAR dependencies
system.cpu1.CUs1.wavefronts13.timesBlockedDueRAWDependencies            0                       # number of times the wf's instructions are blocked due to RAW dependencies
system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::samples            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::mean          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::stdev          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::underflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::0-1            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::2-3            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::4            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::overflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::min_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::max_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::total            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::samples            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::mean          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::stdev          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::underflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::0-1            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::2-3            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::overflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::min_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::max_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::total            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts14.timesBlockedDueVrfPortAvail            0                       # number of times instructions are blocked due to VRF port availability
system.cpu1.CUs1.wavefronts14.timesBlockedDueWAXDependencies            0                       # number of times the wf's instructions are blocked due to WAW or WAR dependencies
system.cpu1.CUs1.wavefronts14.timesBlockedDueRAWDependencies            0                       # number of times the wf's instructions are blocked due to RAW dependencies
system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::samples            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::mean          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::stdev          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::underflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::0-1            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::2-3            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::4            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::overflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::min_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::max_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::total            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::samples            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::mean          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::stdev          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::underflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::0-1            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::2-3            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::overflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::min_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::max_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::total            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts15.timesBlockedDueVrfPortAvail            0                       # number of times instructions are blocked due to VRF port availability
system.cpu1.CUs1.wavefronts15.timesBlockedDueWAXDependencies            0                       # number of times the wf's instructions are blocked due to WAW or WAR dependencies
system.cpu1.CUs1.wavefronts15.timesBlockedDueRAWDependencies            0                       # number of times the wf's instructions are blocked due to RAW dependencies
system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::samples            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::mean          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::stdev          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::underflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::0-1            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::2-3            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::4            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::overflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::min_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::max_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::total            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::samples            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::mean          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::stdev          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::underflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::0-1            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::2-3            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::overflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::min_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::max_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::total            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts16.timesBlockedDueVrfPortAvail            0                       # number of times instructions are blocked due to VRF port availability
system.cpu1.CUs1.wavefronts16.timesBlockedDueWAXDependencies            0                       # number of times the wf's instructions are blocked due to WAW or WAR dependencies
system.cpu1.CUs1.wavefronts16.timesBlockedDueRAWDependencies          352                       # number of times the wf's instructions are blocked due to RAW dependencies
system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::samples           34                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::mean     0.852941                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::stdev     0.857493                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::underflows            0      0.00%      0.00% # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::0-1           24     70.59%     70.59% # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::2-3           10     29.41%    100.00% # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::4            0      0.00%    100.00% # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::overflows            0      0.00%    100.00% # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::min_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::max_value            2                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::total           34                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::samples           34                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::mean     0.617647                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::stdev     0.493270                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::underflows            0      0.00%      0.00% # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::0-1           34    100.00%    100.00% # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::2-3            0      0.00%    100.00% # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::overflows            0      0.00%    100.00% # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::min_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::max_value            1                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::total           34                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts17.timesBlockedDueVrfPortAvail            0                       # number of times instructions are blocked due to VRF port availability
system.cpu1.CUs1.wavefronts17.timesBlockedDueWAXDependencies            0                       # number of times the wf's instructions are blocked due to WAW or WAR dependencies
system.cpu1.CUs1.wavefronts17.timesBlockedDueRAWDependencies            0                       # number of times the wf's instructions are blocked due to RAW dependencies
system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::samples            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::mean          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::stdev          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::underflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::0-1            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::2-3            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::4            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::overflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::min_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::max_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::total            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::samples            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::mean          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::stdev          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::underflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::0-1            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::2-3            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::overflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::min_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::max_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::total            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts18.timesBlockedDueVrfPortAvail            0                       # number of times instructions are blocked due to VRF port availability
system.cpu1.CUs1.wavefronts18.timesBlockedDueWAXDependencies            0                       # number of times the wf's instructions are blocked due to WAW or WAR dependencies
system.cpu1.CUs1.wavefronts18.timesBlockedDueRAWDependencies            0                       # number of times the wf's instructions are blocked due to RAW dependencies
system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::samples            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::mean          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::stdev          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::underflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::0-1            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::2-3            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::4            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::overflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::min_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::max_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::total            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::samples            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::mean          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::stdev          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::underflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::0-1            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::2-3            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::overflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::min_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::max_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::total            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts19.timesBlockedDueVrfPortAvail            0                       # number of times instructions are blocked due to VRF port availability
system.cpu1.CUs1.wavefronts19.timesBlockedDueWAXDependencies            0                       # number of times the wf's instructions are blocked due to WAW or WAR dependencies
system.cpu1.CUs1.wavefronts19.timesBlockedDueRAWDependencies            0                       # number of times the wf's instructions are blocked due to RAW dependencies
system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::samples            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::mean          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::stdev          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::underflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::0-1            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::2-3            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::4            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::overflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::min_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::max_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::total            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::samples            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::mean          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::stdev          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::underflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::0-1            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::2-3            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::overflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::min_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::max_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::total            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts20.timesBlockedDueVrfPortAvail            0                       # number of times instructions are blocked due to VRF port availability
system.cpu1.CUs1.wavefronts20.timesBlockedDueWAXDependencies            0                       # number of times the wf's instructions are blocked due to WAW or WAR dependencies
system.cpu1.CUs1.wavefronts20.timesBlockedDueRAWDependencies            0                       # number of times the wf's instructions are blocked due to RAW dependencies
system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::samples            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::mean          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::stdev          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::underflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::0-1            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::2-3            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::4            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::overflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::min_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::max_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::total            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::samples            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::mean          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::stdev          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::underflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::0-1            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::2-3            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::overflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::min_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::max_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::total            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts21.timesBlockedDueVrfPortAvail            0                       # number of times instructions are blocked due to VRF port availability
system.cpu1.CUs1.wavefronts21.timesBlockedDueWAXDependencies            0                       # number of times the wf's instructions are blocked due to WAW or WAR dependencies
system.cpu1.CUs1.wavefronts21.timesBlockedDueRAWDependencies            0                       # number of times the wf's instructions are blocked due to RAW dependencies
system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::samples            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::mean          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::stdev          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::underflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::0-1            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::2-3            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::4            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::overflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::min_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::max_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::total            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::samples            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::mean          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::stdev          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::underflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::0-1            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::2-3            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::overflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::min_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::max_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::total            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts22.timesBlockedDueVrfPortAvail            0                       # number of times instructions are blocked due to VRF port availability
system.cpu1.CUs1.wavefronts22.timesBlockedDueWAXDependencies            0                       # number of times the wf's instructions are blocked due to WAW or WAR dependencies
system.cpu1.CUs1.wavefronts22.timesBlockedDueRAWDependencies            0                       # number of times the wf's instructions are blocked due to RAW dependencies
system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::samples            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::mean          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::stdev          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::underflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::0-1            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::2-3            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::4            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::overflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::min_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::max_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::total            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::samples            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::mean          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::stdev          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::underflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::0-1            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::2-3            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::overflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::min_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::max_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::total            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts23.timesBlockedDueVrfPortAvail            0                       # number of times instructions are blocked due to VRF port availability
system.cpu1.CUs1.wavefronts23.timesBlockedDueWAXDependencies            0                       # number of times the wf's instructions are blocked due to WAW or WAR dependencies
system.cpu1.CUs1.wavefronts23.timesBlockedDueRAWDependencies            0                       # number of times the wf's instructions are blocked due to RAW dependencies
system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::samples            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::mean          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::stdev          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::underflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::0-1            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::2-3            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::4            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::overflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::min_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::max_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::total            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::samples            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::mean          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::stdev          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::underflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::0-1            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::2-3            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::overflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::min_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::max_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::total            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts24.timesBlockedDueVrfPortAvail            0                       # number of times instructions are blocked due to VRF port availability
system.cpu1.CUs1.wavefronts24.timesBlockedDueWAXDependencies            0                       # number of times the wf's instructions are blocked due to WAW or WAR dependencies
system.cpu1.CUs1.wavefronts24.timesBlockedDueRAWDependencies          337                       # number of times the wf's instructions are blocked due to RAW dependencies
system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::samples           34                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::mean     0.852941                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::stdev     0.857493                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::underflows            0      0.00%      0.00% # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::0-1           24     70.59%     70.59% # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::2-3           10     29.41%    100.00% # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::4            0      0.00%    100.00% # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::overflows            0      0.00%    100.00% # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::min_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::max_value            2                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::total           34                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::samples           34                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::mean     0.617647                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::stdev     0.493270                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::underflows            0      0.00%      0.00% # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::0-1           34    100.00%    100.00% # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::2-3            0      0.00%    100.00% # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::overflows            0      0.00%    100.00% # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::min_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::max_value            1                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::total           34                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts25.timesBlockedDueVrfPortAvail            0                       # number of times instructions are blocked due to VRF port availability
system.cpu1.CUs1.wavefronts25.timesBlockedDueWAXDependencies            0                       # number of times the wf's instructions are blocked due to WAW or WAR dependencies
system.cpu1.CUs1.wavefronts25.timesBlockedDueRAWDependencies            0                       # number of times the wf's instructions are blocked due to RAW dependencies
system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::samples            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::mean          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::stdev          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::underflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::0-1            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::2-3            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::4            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::overflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::min_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::max_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::total            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::samples            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::mean          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::stdev          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::underflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::0-1            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::2-3            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::overflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::min_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::max_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::total            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts26.timesBlockedDueVrfPortAvail            0                       # number of times instructions are blocked due to VRF port availability
system.cpu1.CUs1.wavefronts26.timesBlockedDueWAXDependencies            0                       # number of times the wf's instructions are blocked due to WAW or WAR dependencies
system.cpu1.CUs1.wavefronts26.timesBlockedDueRAWDependencies            0                       # number of times the wf's instructions are blocked due to RAW dependencies
system.cpu1.CUs1.wavefronts26.src_reg_operand_dist::samples            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts26.src_reg_operand_dist::mean          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts26.src_reg_operand_dist::stdev          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts26.src_reg_operand_dist::underflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts26.src_reg_operand_dist::0-1            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts26.src_reg_operand_dist::2-3            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts26.src_reg_operand_dist::4            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts26.src_reg_operand_dist::overflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts26.src_reg_operand_dist::min_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts26.src_reg_operand_dist::max_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts26.src_reg_operand_dist::total            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::samples            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::mean          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::stdev          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::underflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::0-1            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::2-3            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::overflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::min_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::max_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::total            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts27.timesBlockedDueVrfPortAvail            0                       # number of times instructions are blocked due to VRF port availability
system.cpu1.CUs1.wavefronts27.timesBlockedDueWAXDependencies            0                       # number of times the wf's instructions are blocked due to WAW or WAR dependencies
system.cpu1.CUs1.wavefronts27.timesBlockedDueRAWDependencies            0                       # number of times the wf's instructions are blocked due to RAW dependencies
system.cpu1.CUs1.wavefronts27.src_reg_operand_dist::samples            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts27.src_reg_operand_dist::mean          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts27.src_reg_operand_dist::stdev          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts27.src_reg_operand_dist::underflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts27.src_reg_operand_dist::0-1            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts27.src_reg_operand_dist::2-3            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts27.src_reg_operand_dist::4            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts27.src_reg_operand_dist::overflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts27.src_reg_operand_dist::min_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts27.src_reg_operand_dist::max_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts27.src_reg_operand_dist::total            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::samples            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::mean          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::stdev          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::underflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::0-1            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::2-3            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::overflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::min_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::max_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::total            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts28.timesBlockedDueVrfPortAvail            0                       # number of times instructions are blocked due to VRF port availability
system.cpu1.CUs1.wavefronts28.timesBlockedDueWAXDependencies            0                       # number of times the wf's instructions are blocked due to WAW or WAR dependencies
system.cpu1.CUs1.wavefronts28.timesBlockedDueRAWDependencies            0                       # number of times the wf's instructions are blocked due to RAW dependencies
system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::samples            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::mean          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::stdev          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::underflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::0-1            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::2-3            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::4            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::overflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::min_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::max_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::total            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::samples            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::mean          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::stdev          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::underflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::0-1            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::2-3            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::overflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::min_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::max_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::total            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts29.timesBlockedDueVrfPortAvail            0                       # number of times instructions are blocked due to VRF port availability
system.cpu1.CUs1.wavefronts29.timesBlockedDueWAXDependencies            0                       # number of times the wf's instructions are blocked due to WAW or WAR dependencies
system.cpu1.CUs1.wavefronts29.timesBlockedDueRAWDependencies            0                       # number of times the wf's instructions are blocked due to RAW dependencies
system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::samples            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::mean          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::stdev          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::underflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::0-1            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::2-3            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::4            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::overflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::min_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::max_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::total            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::samples            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::mean          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::stdev          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::underflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::0-1            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::2-3            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::overflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::min_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::max_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::total            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts30.timesBlockedDueVrfPortAvail            0                       # number of times instructions are blocked due to VRF port availability
system.cpu1.CUs1.wavefronts30.timesBlockedDueWAXDependencies            0                       # number of times the wf's instructions are blocked due to WAW or WAR dependencies
system.cpu1.CUs1.wavefronts30.timesBlockedDueRAWDependencies            0                       # number of times the wf's instructions are blocked due to RAW dependencies
system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::samples            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::mean          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::stdev          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::underflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::0-1            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::2-3            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::4            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::overflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::min_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::max_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::total            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::samples            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::mean          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::stdev          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::underflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::0-1            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::2-3            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::overflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::min_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::max_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::total            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts31.timesBlockedDueVrfPortAvail            0                       # number of times instructions are blocked due to VRF port availability
system.cpu1.CUs1.wavefronts31.timesBlockedDueWAXDependencies            0                       # number of times the wf's instructions are blocked due to WAW or WAR dependencies
system.cpu1.CUs1.wavefronts31.timesBlockedDueRAWDependencies            0                       # number of times the wf's instructions are blocked due to RAW dependencies
system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::samples            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::mean          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::stdev          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::underflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::0-1            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::2-3            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::4            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::overflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::min_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::max_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::total            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::samples            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::mean          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::stdev          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::underflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::0-1            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::2-3            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::overflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::min_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::max_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::total            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::samples           43                       # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::mean     5.813953                       # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::stdev     2.683777                       # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::underflows            0      0.00%      0.00% # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::1            0      0.00%      0.00% # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::2            8     18.60%     18.60% # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::3            8     18.60%     37.21% # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::4            1      2.33%     39.53% # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::5            0      0.00%     39.53% # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::6            1      2.33%     41.86% # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::7            0      0.00%     41.86% # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::8           25     58.14%    100.00% # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::9            0      0.00%    100.00% # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::10            0      0.00%    100.00% # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::11            0      0.00%    100.00% # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::12            0      0.00%    100.00% # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::13            0      0.00%    100.00% # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::14            0      0.00%    100.00% # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::15            0      0.00%    100.00% # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::16            0      0.00%    100.00% # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::17            0      0.00%    100.00% # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::18            0      0.00%    100.00% # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::19            0      0.00%    100.00% # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::20            0      0.00%    100.00% # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::21            0      0.00%    100.00% # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::22            0      0.00%    100.00% # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::23            0      0.00%    100.00% # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::24            0      0.00%    100.00% # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::25            0      0.00%    100.00% # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::26            0      0.00%    100.00% # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::27            0      0.00%    100.00% # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::28            0      0.00%    100.00% # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::29            0      0.00%    100.00% # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::30            0      0.00%    100.00% # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::31            0      0.00%    100.00% # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::32            0      0.00%    100.00% # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::overflows            0      0.00%    100.00% # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::min_value            2                       # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::max_value            8                       # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::total           43                       # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs1.ExecStage.num_cycles_with_no_issue         4359                       # number of cycles the CU issues nothing
system.cpu1.CUs1.ExecStage.num_cycles_with_instr_issued          131                       # number of cycles the CU issued at least one instruction
system.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::ALU0           30                       # Number of cycles at least one instruction of specific type issued
system.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::ALU1           29                       # Number of cycles at least one instruction of specific type issued
system.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::ALU2           29                       # Number of cycles at least one instruction of specific type issued
system.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::ALU3           29                       # Number of cycles at least one instruction of specific type issued
system.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::GM           18                       # Number of cycles at least one instruction of specific type issued
system.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::LM            6                       # Number of cycles at least one instruction of specific type issued
system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::ALU0         1552                       # Number of cycles no instruction of specific type issued
system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::ALU1          447                       # Number of cycles no instruction of specific type issued
system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::ALU2          464                       # Number of cycles no instruction of specific type issued
system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::ALU3          464                       # Number of cycles no instruction of specific type issued
system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::GM          426                       # Number of cycles no instruction of specific type issued
system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::LM           33                       # Number of cycles no instruction of specific type issued
system.cpu1.CUs1.ExecStage.spc::samples          4490                       # Execution units active per cycle (Exec unit=SIMD,MemPipe)
system.cpu1.CUs1.ExecStage.spc::mean         0.031403                       # Execution units active per cycle (Exec unit=SIMD,MemPipe)
system.cpu1.CUs1.ExecStage.spc::stdev        0.189130                       # Execution units active per cycle (Exec unit=SIMD,MemPipe)
system.cpu1.CUs1.ExecStage.spc::underflows            0      0.00%      0.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
system.cpu1.CUs1.ExecStage.spc::0                4359     97.08%     97.08% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
system.cpu1.CUs1.ExecStage.spc::1                 123      2.74%     99.82% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
system.cpu1.CUs1.ExecStage.spc::2                   6      0.13%     99.96% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
system.cpu1.CUs1.ExecStage.spc::3                   2      0.04%    100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
system.cpu1.CUs1.ExecStage.spc::4                   0      0.00%    100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
system.cpu1.CUs1.ExecStage.spc::5                   0      0.00%    100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
system.cpu1.CUs1.ExecStage.spc::6                   0      0.00%    100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
system.cpu1.CUs1.ExecStage.spc::overflows            0      0.00%    100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
system.cpu1.CUs1.ExecStage.spc::min_value            0                       # Execution units active per cycle (Exec unit=SIMD,MemPipe)
system.cpu1.CUs1.ExecStage.spc::max_value            3                       # Execution units active per cycle (Exec unit=SIMD,MemPipe)
system.cpu1.CUs1.ExecStage.spc::total            4490                       # Execution units active per cycle (Exec unit=SIMD,MemPipe)
system.cpu1.CUs1.ExecStage.num_transitions_active_to_idle           74                       # number of CU transitions from active to idle
system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::samples           74                       # duration of idle periods in cycles
system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::mean    55.324324                       # duration of idle periods in cycles
system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::stdev   207.911408                       # duration of idle periods in cycles
system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::underflows            0      0.00%      0.00% # duration of idle periods in cycles
system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::0-4           56     75.68%     75.68% # duration of idle periods in cycles
system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::5-9            7      9.46%     85.14% # duration of idle periods in cycles
system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::10-14            0      0.00%     85.14% # duration of idle periods in cycles
system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::15-19            2      2.70%     87.84% # duration of idle periods in cycles
system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::20-24            1      1.35%     89.19% # duration of idle periods in cycles
system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::25-29            1      1.35%     90.54% # duration of idle periods in cycles
system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::30-34            0      0.00%     90.54% # duration of idle periods in cycles
system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::35-39            0      0.00%     90.54% # duration of idle periods in cycles
system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::40-44            0      0.00%     90.54% # duration of idle periods in cycles
system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::45-49            0      0.00%     90.54% # duration of idle periods in cycles
system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::50-54            0      0.00%     90.54% # duration of idle periods in cycles
system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::55-59            0      0.00%     90.54% # duration of idle periods in cycles
system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::60-64            0      0.00%     90.54% # duration of idle periods in cycles
system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::65-69            0      0.00%     90.54% # duration of idle periods in cycles
system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::70-74            0      0.00%     90.54% # duration of idle periods in cycles
system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::75            0      0.00%     90.54% # duration of idle periods in cycles
system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::overflows            7      9.46%    100.00% # duration of idle periods in cycles
system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::min_value            1                       # duration of idle periods in cycles
system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::max_value         1304                       # duration of idle periods in cycles
system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::total           74                       # duration of idle periods in cycles
system.cpu1.CUs1.GlobalMemPipeline.load_vrf_bank_conflict_cycles            0                       # total number of cycles GM data are delayed before updating the VRF
system.cpu1.CUs1.LocalMemPipeline.load_vrf_bank_conflict_cycles            0                       # total number of cycles LDS data are delayed before updating the VRF
system.cpu1.CUs1.tlb_requests                     769                       # number of uncoalesced requests
system.cpu1.CUs1.tlb_cycles              -373672588000                       # total number of cycles for all uncoalesced requests
system.cpu1.CUs1.avg_translation_latency -485920140.442133                       # Avg. translation latency for data translations
system.cpu1.CUs1.TLB_hits_distribution::page_table          769                       # TLB hits distribution (0 for page table, x for Lx-TLB
system.cpu1.CUs1.TLB_hits_distribution::L1_TLB            0                       # TLB hits distribution (0 for page table, x for Lx-TLB
system.cpu1.CUs1.TLB_hits_distribution::L2_TLB            0                       # TLB hits distribution (0 for page table, x for Lx-TLB
system.cpu1.CUs1.TLB_hits_distribution::L3_TLB            0                       # TLB hits distribution (0 for page table, x for Lx-TLB
system.cpu1.CUs1.lds_bank_access_cnt               53                       # Total number of LDS bank accesses
system.cpu1.CUs1.lds_bank_conflicts::samples            6                       # Number of bank conflicts per LDS memory packet
system.cpu1.CUs1.lds_bank_conflicts::mean     7.833333                       # Number of bank conflicts per LDS memory packet
system.cpu1.CUs1.lds_bank_conflicts::stdev     6.080022                       # Number of bank conflicts per LDS memory packet
system.cpu1.CUs1.lds_bank_conflicts::underflows            0      0.00%      0.00% # Number of bank conflicts per LDS memory packet
system.cpu1.CUs1.lds_bank_conflicts::0-1            2     33.33%     33.33% # Number of bank conflicts per LDS memory packet
system.cpu1.CUs1.lds_bank_conflicts::2-3            0      0.00%     33.33% # Number of bank conflicts per LDS memory packet
system.cpu1.CUs1.lds_bank_conflicts::4-5            0      0.00%     33.33% # Number of bank conflicts per LDS memory packet
system.cpu1.CUs1.lds_bank_conflicts::6-7            0      0.00%     33.33% # Number of bank conflicts per LDS memory packet
system.cpu1.CUs1.lds_bank_conflicts::8-9            0      0.00%     33.33% # Number of bank conflicts per LDS memory packet
system.cpu1.CUs1.lds_bank_conflicts::10-11            1     16.67%     50.00% # Number of bank conflicts per LDS memory packet
system.cpu1.CUs1.lds_bank_conflicts::12-13            3     50.00%    100.00% # Number of bank conflicts per LDS memory packet
system.cpu1.CUs1.lds_bank_conflicts::14-15            0      0.00%    100.00% # Number of bank conflicts per LDS memory packet
system.cpu1.CUs1.lds_bank_conflicts::16-17            0      0.00%    100.00% # Number of bank conflicts per LDS memory packet
system.cpu1.CUs1.lds_bank_conflicts::18-19            0      0.00%    100.00% # Number of bank conflicts per LDS memory packet
system.cpu1.CUs1.lds_bank_conflicts::20-21            0      0.00%    100.00% # Number of bank conflicts per LDS memory packet
system.cpu1.CUs1.lds_bank_conflicts::22-23            0      0.00%    100.00% # Number of bank conflicts per LDS memory packet
system.cpu1.CUs1.lds_bank_conflicts::24-25            0      0.00%    100.00% # Number of bank conflicts per LDS memory packet
system.cpu1.CUs1.lds_bank_conflicts::26-27            0      0.00%    100.00% # Number of bank conflicts per LDS memory packet
system.cpu1.CUs1.lds_bank_conflicts::28-29            0      0.00%    100.00% # Number of bank conflicts per LDS memory packet
system.cpu1.CUs1.lds_bank_conflicts::30-31            0      0.00%    100.00% # Number of bank conflicts per LDS memory packet
system.cpu1.CUs1.lds_bank_conflicts::32-33            0      0.00%    100.00% # Number of bank conflicts per LDS memory packet
system.cpu1.CUs1.lds_bank_conflicts::34-35            0      0.00%    100.00% # Number of bank conflicts per LDS memory packet
system.cpu1.CUs1.lds_bank_conflicts::36-37            0      0.00%    100.00% # Number of bank conflicts per LDS memory packet
system.cpu1.CUs1.lds_bank_conflicts::38-39            0      0.00%    100.00% # Number of bank conflicts per LDS memory packet
system.cpu1.CUs1.lds_bank_conflicts::40-41            0      0.00%    100.00% # Number of bank conflicts per LDS memory packet
system.cpu1.CUs1.lds_bank_conflicts::42-43            0      0.00%    100.00% # Number of bank conflicts per LDS memory packet
system.cpu1.CUs1.lds_bank_conflicts::44-45            0      0.00%    100.00% # Number of bank conflicts per LDS memory packet
system.cpu1.CUs1.lds_bank_conflicts::46-47            0      0.00%    100.00% # Number of bank conflicts per LDS memory packet
system.cpu1.CUs1.lds_bank_conflicts::48-49            0      0.00%    100.00% # Number of bank conflicts per LDS memory packet
system.cpu1.CUs1.lds_bank_conflicts::50-51            0      0.00%    100.00% # Number of bank conflicts per LDS memory packet
system.cpu1.CUs1.lds_bank_conflicts::52-53            0      0.00%    100.00% # Number of bank conflicts per LDS memory packet
system.cpu1.CUs1.lds_bank_conflicts::54-55            0      0.00%    100.00% # Number of bank conflicts per LDS memory packet
system.cpu1.CUs1.lds_bank_conflicts::56-57            0      0.00%    100.00% # Number of bank conflicts per LDS memory packet
system.cpu1.CUs1.lds_bank_conflicts::58-59            0      0.00%    100.00% # Number of bank conflicts per LDS memory packet
system.cpu1.CUs1.lds_bank_conflicts::60-61            0      0.00%    100.00% # Number of bank conflicts per LDS memory packet
system.cpu1.CUs1.lds_bank_conflicts::62-63            0      0.00%    100.00% # Number of bank conflicts per LDS memory packet
system.cpu1.CUs1.lds_bank_conflicts::64             0      0.00%    100.00% # Number of bank conflicts per LDS memory packet
system.cpu1.CUs1.lds_bank_conflicts::overflows            0      0.00%    100.00% # Number of bank conflicts per LDS memory packet
system.cpu1.CUs1.lds_bank_conflicts::min_value            0                       # Number of bank conflicts per LDS memory packet
system.cpu1.CUs1.lds_bank_conflicts::max_value           12                       # Number of bank conflicts per LDS memory packet
system.cpu1.CUs1.lds_bank_conflicts::total            6                       # Number of bank conflicts per LDS memory packet
system.cpu1.CUs1.page_divergence_dist::samples           17                       # pages touched per wf (over all mem. instr.)
system.cpu1.CUs1.page_divergence_dist::mean            1                       # pages touched per wf (over all mem. instr.)
system.cpu1.CUs1.page_divergence_dist::stdev            0                       # pages touched per wf (over all mem. instr.)
system.cpu1.CUs1.page_divergence_dist::underflows            0      0.00%      0.00% # pages touched per wf (over all mem. instr.)
system.cpu1.CUs1.page_divergence_dist::1-4           17    100.00%    100.00% # pages touched per wf (over all mem. instr.)
system.cpu1.CUs1.page_divergence_dist::5-8            0      0.00%    100.00% # pages touched per wf (over all mem. instr.)
system.cpu1.CUs1.page_divergence_dist::9-12            0      0.00%    100.00% # pages touched per wf (over all mem. instr.)
system.cpu1.CUs1.page_divergence_dist::13-16            0      0.00%    100.00% # pages touched per wf (over all mem. instr.)
system.cpu1.CUs1.page_divergence_dist::17-20            0      0.00%    100.00% # pages touched per wf (over all mem. instr.)
system.cpu1.CUs1.page_divergence_dist::21-24            0      0.00%    100.00% # pages touched per wf (over all mem. instr.)
system.cpu1.CUs1.page_divergence_dist::25-28            0      0.00%    100.00% # pages touched per wf (over all mem. instr.)
system.cpu1.CUs1.page_divergence_dist::29-32            0      0.00%    100.00% # pages touched per wf (over all mem. instr.)
system.cpu1.CUs1.page_divergence_dist::33-36            0      0.00%    100.00% # pages touched per wf (over all mem. instr.)
system.cpu1.CUs1.page_divergence_dist::37-40            0      0.00%    100.00% # pages touched per wf (over all mem. instr.)
system.cpu1.CUs1.page_divergence_dist::41-44            0      0.00%    100.00% # pages touched per wf (over all mem. instr.)
system.cpu1.CUs1.page_divergence_dist::45-48            0      0.00%    100.00% # pages touched per wf (over all mem. instr.)
system.cpu1.CUs1.page_divergence_dist::49-52            0      0.00%    100.00% # pages touched per wf (over all mem. instr.)
system.cpu1.CUs1.page_divergence_dist::53-56            0      0.00%    100.00% # pages touched per wf (over all mem. instr.)
system.cpu1.CUs1.page_divergence_dist::57-60            0      0.00%    100.00% # pages touched per wf (over all mem. instr.)
system.cpu1.CUs1.page_divergence_dist::61-64            0      0.00%    100.00% # pages touched per wf (over all mem. instr.)
system.cpu1.CUs1.page_divergence_dist::overflows            0      0.00%    100.00% # pages touched per wf (over all mem. instr.)
system.cpu1.CUs1.page_divergence_dist::min_value            1                       # pages touched per wf (over all mem. instr.)
system.cpu1.CUs1.page_divergence_dist::max_value            1                       # pages touched per wf (over all mem. instr.)
system.cpu1.CUs1.page_divergence_dist::total           17                       # pages touched per wf (over all mem. instr.)
system.cpu1.CUs1.global_mem_instr_cnt              17                       # dynamic global memory instructions count
system.cpu1.CUs1.local_mem_instr_cnt                6                       # dynamic local memory intruction count
system.cpu1.CUs1.wg_blocked_due_lds_alloc            0                       # Workgroup blocked due to LDS capacity
system.cpu1.CUs1.num_instr_executed               141                       # number of instructions executed
system.cpu1.CUs1.inst_exec_rate::samples          141                       # Instruction Execution Rate: Number of executed vector instructions per cycle
system.cpu1.CUs1.inst_exec_rate::mean       95.106383                       # Instruction Execution Rate: Number of executed vector instructions per cycle
system.cpu1.CUs1.inst_exec_rate::stdev     249.293307                       # Instruction Execution Rate: Number of executed vector instructions per cycle
system.cpu1.CUs1.inst_exec_rate::underflows            0      0.00%      0.00% # Instruction Execution Rate: Number of executed vector instructions per cycle
system.cpu1.CUs1.inst_exec_rate::0-1                1      0.71%      0.71% # Instruction Execution Rate: Number of executed vector instructions per cycle
system.cpu1.CUs1.inst_exec_rate::2-3               12      8.51%      9.22% # Instruction Execution Rate: Number of executed vector instructions per cycle
system.cpu1.CUs1.inst_exec_rate::4-5               53     37.59%     46.81% # Instruction Execution Rate: Number of executed vector instructions per cycle
system.cpu1.CUs1.inst_exec_rate::6-7               29     20.57%     67.38% # Instruction Execution Rate: Number of executed vector instructions per cycle
system.cpu1.CUs1.inst_exec_rate::8-9                5      3.55%     70.92% # Instruction Execution Rate: Number of executed vector instructions per cycle
system.cpu1.CUs1.inst_exec_rate::10                 1      0.71%     71.63% # Instruction Execution Rate: Number of executed vector instructions per cycle
system.cpu1.CUs1.inst_exec_rate::overflows           40     28.37%    100.00% # Instruction Execution Rate: Number of executed vector instructions per cycle
system.cpu1.CUs1.inst_exec_rate::min_value            1                       # Instruction Execution Rate: Number of executed vector instructions per cycle
system.cpu1.CUs1.inst_exec_rate::max_value         1307                       # Instruction Execution Rate: Number of executed vector instructions per cycle
system.cpu1.CUs1.inst_exec_rate::total            141                       # Instruction Execution Rate: Number of executed vector instructions per cycle
system.cpu1.CUs1.num_vec_ops_executed            6762                       # number of vec ops executed (e.g. VSZ/inst)
system.cpu1.CUs1.num_total_cycles                4490                       # number of cycles the CU ran for
system.cpu1.CUs1.vpc                         1.506013                       # Vector Operations per cycle (this CU only)
system.cpu1.CUs1.ipc                         0.031403                       # Instructions per cycle (this CU only)
system.cpu1.CUs1.warp_execution_dist::samples          141                       # number of lanes active per instruction (oval all instructions)
system.cpu1.CUs1.warp_execution_dist::mean    47.957447                       # number of lanes active per instruction (oval all instructions)
system.cpu1.CUs1.warp_execution_dist::stdev    23.818022                       # number of lanes active per instruction (oval all instructions)
system.cpu1.CUs1.warp_execution_dist::underflows            0      0.00%      0.00% # number of lanes active per instruction (oval all instructions)
system.cpu1.CUs1.warp_execution_dist::1-4            5      3.55%      3.55% # number of lanes active per instruction (oval all instructions)
system.cpu1.CUs1.warp_execution_dist::5-8            0      0.00%      3.55% # number of lanes active per instruction (oval all instructions)
system.cpu1.CUs1.warp_execution_dist::9-12            9      6.38%      9.93% # number of lanes active per instruction (oval all instructions)
system.cpu1.CUs1.warp_execution_dist::13-16           27     19.15%     29.08% # number of lanes active per instruction (oval all instructions)
system.cpu1.CUs1.warp_execution_dist::17-20            0      0.00%     29.08% # number of lanes active per instruction (oval all instructions)
system.cpu1.CUs1.warp_execution_dist::21-24            0      0.00%     29.08% # number of lanes active per instruction (oval all instructions)
system.cpu1.CUs1.warp_execution_dist::25-28            0      0.00%     29.08% # number of lanes active per instruction (oval all instructions)
system.cpu1.CUs1.warp_execution_dist::29-32            0      0.00%     29.08% # number of lanes active per instruction (oval all instructions)
system.cpu1.CUs1.warp_execution_dist::33-36            0      0.00%     29.08% # number of lanes active per instruction (oval all instructions)
system.cpu1.CUs1.warp_execution_dist::37-40            0      0.00%     29.08% # number of lanes active per instruction (oval all instructions)
system.cpu1.CUs1.warp_execution_dist::41-44            0      0.00%     29.08% # number of lanes active per instruction (oval all instructions)
system.cpu1.CUs1.warp_execution_dist::45-48            0      0.00%     29.08% # number of lanes active per instruction (oval all instructions)
system.cpu1.CUs1.warp_execution_dist::49-52            8      5.67%     34.75% # number of lanes active per instruction (oval all instructions)
system.cpu1.CUs1.warp_execution_dist::53-56            0      0.00%     34.75% # number of lanes active per instruction (oval all instructions)
system.cpu1.CUs1.warp_execution_dist::57-60            0      0.00%     34.75% # number of lanes active per instruction (oval all instructions)
system.cpu1.CUs1.warp_execution_dist::61-64           92     65.25%    100.00% # number of lanes active per instruction (oval all instructions)
system.cpu1.CUs1.warp_execution_dist::overflows            0      0.00%    100.00% # number of lanes active per instruction (oval all instructions)
system.cpu1.CUs1.warp_execution_dist::min_value            1                       # number of lanes active per instruction (oval all instructions)
system.cpu1.CUs1.warp_execution_dist::max_value           64                       # number of lanes active per instruction (oval all instructions)
system.cpu1.CUs1.warp_execution_dist::total          141                       # number of lanes active per instruction (oval all instructions)
system.cpu1.CUs1.gmem_lanes_execution_dist::samples           18                       # number of active lanes per global memory instruction
system.cpu1.CUs1.gmem_lanes_execution_dist::mean    37.722222                       # number of active lanes per global memory instruction
system.cpu1.CUs1.gmem_lanes_execution_dist::stdev    27.174394                       # number of active lanes per global memory instruction
system.cpu1.CUs1.gmem_lanes_execution_dist::underflows            0      0.00%      0.00% # number of active lanes per global memory instruction
system.cpu1.CUs1.gmem_lanes_execution_dist::1-4            1      5.56%      5.56% # number of active lanes per global memory instruction
system.cpu1.CUs1.gmem_lanes_execution_dist::5-8            0      0.00%      5.56% # number of active lanes per global memory instruction
system.cpu1.CUs1.gmem_lanes_execution_dist::9-12            2     11.11%     16.67% # number of active lanes per global memory instruction
system.cpu1.CUs1.gmem_lanes_execution_dist::13-16            6     33.33%     50.00% # number of active lanes per global memory instruction
system.cpu1.CUs1.gmem_lanes_execution_dist::17-20            0      0.00%     50.00% # number of active lanes per global memory instruction
system.cpu1.CUs1.gmem_lanes_execution_dist::21-24            0      0.00%     50.00% # number of active lanes per global memory instruction
system.cpu1.CUs1.gmem_lanes_execution_dist::25-28            0      0.00%     50.00% # number of active lanes per global memory instruction
system.cpu1.CUs1.gmem_lanes_execution_dist::29-32            0      0.00%     50.00% # number of active lanes per global memory instruction
system.cpu1.CUs1.gmem_lanes_execution_dist::33-36            0      0.00%     50.00% # number of active lanes per global memory instruction
system.cpu1.CUs1.gmem_lanes_execution_dist::37-40            0      0.00%     50.00% # number of active lanes per global memory instruction
system.cpu1.CUs1.gmem_lanes_execution_dist::41-44            0      0.00%     50.00% # number of active lanes per global memory instruction
system.cpu1.CUs1.gmem_lanes_execution_dist::45-48            0      0.00%     50.00% # number of active lanes per global memory instruction
system.cpu1.CUs1.gmem_lanes_execution_dist::49-52            0      0.00%     50.00% # number of active lanes per global memory instruction
system.cpu1.CUs1.gmem_lanes_execution_dist::53-56            0      0.00%     50.00% # number of active lanes per global memory instruction
system.cpu1.CUs1.gmem_lanes_execution_dist::57-60            0      0.00%     50.00% # number of active lanes per global memory instruction
system.cpu1.CUs1.gmem_lanes_execution_dist::61-64            9     50.00%    100.00% # number of active lanes per global memory instruction
system.cpu1.CUs1.gmem_lanes_execution_dist::overflows            0      0.00%    100.00% # number of active lanes per global memory instruction
system.cpu1.CUs1.gmem_lanes_execution_dist::min_value            1                       # number of active lanes per global memory instruction
system.cpu1.CUs1.gmem_lanes_execution_dist::max_value           64                       # number of active lanes per global memory instruction
system.cpu1.CUs1.gmem_lanes_execution_dist::total           18                       # number of active lanes per global memory instruction
system.cpu1.CUs1.lmem_lanes_execution_dist::samples            6                       # number of active lanes per local memory instruction
system.cpu1.CUs1.lmem_lanes_execution_dist::mean    19.333333                       # number of active lanes per local memory instruction
system.cpu1.CUs1.lmem_lanes_execution_dist::stdev    22.384518                       # number of active lanes per local memory instruction
system.cpu1.CUs1.lmem_lanes_execution_dist::underflows            0      0.00%      0.00% # number of active lanes per local memory instruction
system.cpu1.CUs1.lmem_lanes_execution_dist::1-4            1     16.67%     16.67% # number of active lanes per local memory instruction
system.cpu1.CUs1.lmem_lanes_execution_dist::5-8            0      0.00%     16.67% # number of active lanes per local memory instruction
system.cpu1.CUs1.lmem_lanes_execution_dist::9-12            1     16.67%     33.33% # number of active lanes per local memory instruction
system.cpu1.CUs1.lmem_lanes_execution_dist::13-16            3     50.00%     83.33% # number of active lanes per local memory instruction
system.cpu1.CUs1.lmem_lanes_execution_dist::17-20            0      0.00%     83.33% # number of active lanes per local memory instruction
system.cpu1.CUs1.lmem_lanes_execution_dist::21-24            0      0.00%     83.33% # number of active lanes per local memory instruction
system.cpu1.CUs1.lmem_lanes_execution_dist::25-28            0      0.00%     83.33% # number of active lanes per local memory instruction
system.cpu1.CUs1.lmem_lanes_execution_dist::29-32            0      0.00%     83.33% # number of active lanes per local memory instruction
system.cpu1.CUs1.lmem_lanes_execution_dist::33-36            0      0.00%     83.33% # number of active lanes per local memory instruction
system.cpu1.CUs1.lmem_lanes_execution_dist::37-40            0      0.00%     83.33% # number of active lanes per local memory instruction
system.cpu1.CUs1.lmem_lanes_execution_dist::41-44            0      0.00%     83.33% # number of active lanes per local memory instruction
system.cpu1.CUs1.lmem_lanes_execution_dist::45-48            0      0.00%     83.33% # number of active lanes per local memory instruction
system.cpu1.CUs1.lmem_lanes_execution_dist::49-52            0      0.00%     83.33% # number of active lanes per local memory instruction
system.cpu1.CUs1.lmem_lanes_execution_dist::53-56            0      0.00%     83.33% # number of active lanes per local memory instruction
system.cpu1.CUs1.lmem_lanes_execution_dist::57-60            0      0.00%     83.33% # number of active lanes per local memory instruction
system.cpu1.CUs1.lmem_lanes_execution_dist::61-64            1     16.67%    100.00% # number of active lanes per local memory instruction
system.cpu1.CUs1.lmem_lanes_execution_dist::overflows            0      0.00%    100.00% # number of active lanes per local memory instruction
system.cpu1.CUs1.lmem_lanes_execution_dist::min_value            1                       # number of active lanes per local memory instruction
system.cpu1.CUs1.lmem_lanes_execution_dist::max_value           64                       # number of active lanes per local memory instruction
system.cpu1.CUs1.lmem_lanes_execution_dist::total            6                       # number of active lanes per local memory instruction
system.cpu1.CUs1.num_alu_insts_executed           118                       # Number of dynamic non-GM memory insts executed
system.cpu1.CUs1.times_wg_blocked_due_vgpr_alloc            0                       # Number of times WGs are blocked due to VGPR allocation per SIMD
system.cpu1.CUs1.num_CAS_ops                        0                       # number of compare and swap operations
system.cpu1.CUs1.num_failed_CAS_ops                 0                       # number of compare and swap operations that failed
system.cpu1.CUs1.num_completed_wfs                  4                       # number of completed wavefronts
system.cpu2.num_kernel_launched                     1                       # number of kernel launched
system.dir_cntrl0.L3CacheMemory.demand_hits            0                       # Number of cache demand hits
system.dir_cntrl0.L3CacheMemory.demand_misses            0                       # Number of cache demand misses
system.dir_cntrl0.L3CacheMemory.demand_accesses            0                       # Number of cache demand accesses
system.dir_cntrl0.L3CacheMemory.num_data_array_writes         1560                       # number of data array writes
system.dir_cntrl0.L3CacheMemory.num_tag_array_reads         1560                       # number of tag array reads
system.dir_cntrl0.L3CacheMemory.num_tag_array_writes         1578                       # number of tag array writes
system.dir_cntrl0.ProbeFilterMemory.demand_hits            0                       # Number of cache demand hits
system.dir_cntrl0.ProbeFilterMemory.demand_misses            0                       # Number of cache demand misses
system.dir_cntrl0.ProbeFilterMemory.demand_accesses            0                       # Number of cache demand accesses
system.dir_cntrl0.ProbeFilterMemory.num_tag_array_reads         1560                       # number of tag array reads
system.dir_cntrl0.ProbeFilterMemory.num_tag_array_writes         1560                       # number of tag array writes
system.dispatcher_coalescer.clk_domain.voltage_domain.voltage            1                       # Voltage in Volts
system.dispatcher_coalescer.clk_domain.clock         1000                       # Clock period in ticks
system.dispatcher_coalescer.uncoalesced_accesses            0                       # Number of uncoalesced TLB accesses
system.dispatcher_coalescer.coalesced_accesses            0                       # Number of coalesced TLB accesses
system.dispatcher_coalescer.queuing_cycles            0                       # Number of cycles spent in queue
system.dispatcher_coalescer.local_queuing_cycles            0                       # Number of cycles spent in queue for all incoming reqs
system.dispatcher_coalescer.local_latency          nan                       # Avg. latency over all incoming pkts
system.dispatcher_tlb.clk_domain.voltage_domain.voltage            1                       # Voltage in Volts
system.dispatcher_tlb.clk_domain.clock           1000                       # Clock period in ticks
system.dispatcher_tlb.local_TLB_accesses            0                       # Number of TLB accesses
system.dispatcher_tlb.local_TLB_hits                0                       # Number of TLB hits
system.dispatcher_tlb.local_TLB_misses              0                       # Number of TLB misses
system.dispatcher_tlb.local_TLB_miss_rate          nan                       # TLB miss rate
system.dispatcher_tlb.global_TLB_accesses            0                       # Number of TLB accesses
system.dispatcher_tlb.global_TLB_hits               0                       # Number of TLB hits
system.dispatcher_tlb.global_TLB_misses             0                       # Number of TLB misses
system.dispatcher_tlb.global_TLB_miss_rate          nan                       # TLB miss rate
system.dispatcher_tlb.access_cycles                 0                       # Cycles spent accessing this TLB level
system.dispatcher_tlb.page_table_cycles             0                       # Cycles spent accessing the page table
system.dispatcher_tlb.unique_pages                  0                       # Number of unique pages touched
system.dispatcher_tlb.local_cycles                  0                       # Number of cycles spent in queue for all incoming reqs
system.dispatcher_tlb.local_latency               nan                       # Avg. latency over incoming coalesced reqs
system.dispatcher_tlb.avg_reuse_distance            0                       # avg. reuse distance over all pages (in ticks)
system.l1_coalescer0.clk_domain.voltage_domain.voltage            1                       # Voltage in Volts
system.l1_coalescer0.clk_domain.clock            1000                       # Clock period in ticks
system.l1_coalescer0.uncoalesced_accesses          778                       # Number of uncoalesced TLB accesses
system.l1_coalescer0.coalesced_accesses             0                       # Number of coalesced TLB accesses
system.l1_coalescer0.queuing_cycles                 0                       # Number of cycles spent in queue
system.l1_coalescer0.local_queuing_cycles            0                       # Number of cycles spent in queue for all incoming reqs
system.l1_coalescer0.local_latency                  0                       # Avg. latency over all incoming pkts
system.l1_coalescer1.clk_domain.voltage_domain.voltage            1                       # Voltage in Volts
system.l1_coalescer1.clk_domain.clock            1000                       # Clock period in ticks
system.l1_coalescer1.uncoalesced_accesses          769                       # Number of uncoalesced TLB accesses
system.l1_coalescer1.coalesced_accesses             0                       # Number of coalesced TLB accesses
system.l1_coalescer1.queuing_cycles                 0                       # Number of cycles spent in queue
system.l1_coalescer1.local_queuing_cycles            0                       # Number of cycles spent in queue for all incoming reqs
system.l1_coalescer1.local_latency                  0                       # Avg. latency over all incoming pkts
system.l1_tlb0.clk_domain.voltage_domain.voltage            1                       # Voltage in Volts
system.l1_tlb0.clk_domain.clock                  1000                       # Clock period in ticks
system.l1_tlb0.local_TLB_accesses                 778                       # Number of TLB accesses
system.l1_tlb0.local_TLB_hits                     774                       # Number of TLB hits
system.l1_tlb0.local_TLB_misses                     4                       # Number of TLB misses
system.l1_tlb0.local_TLB_miss_rate           0.514139                       # TLB miss rate
system.l1_tlb0.global_TLB_accesses                778                       # Number of TLB accesses
system.l1_tlb0.global_TLB_hits                    774                       # Number of TLB hits
system.l1_tlb0.global_TLB_misses                    4                       # Number of TLB misses
system.l1_tlb0.global_TLB_miss_rate          0.514139                       # TLB miss rate
system.l1_tlb0.access_cycles                        0                       # Cycles spent accessing this TLB level
system.l1_tlb0.page_table_cycles                    0                       # Cycles spent accessing the page table
system.l1_tlb0.unique_pages                         4                       # Number of unique pages touched
system.l1_tlb0.local_cycles                         0                       # Number of cycles spent in queue for all incoming reqs
system.l1_tlb0.local_latency                        0                       # Avg. latency over incoming coalesced reqs
system.l1_tlb0.avg_reuse_distance                   0                       # avg. reuse distance over all pages (in ticks)
system.l1_tlb1.clk_domain.voltage_domain.voltage            1                       # Voltage in Volts
system.l1_tlb1.clk_domain.clock                  1000                       # Clock period in ticks
system.l1_tlb1.local_TLB_accesses                 769                       # Number of TLB accesses
system.l1_tlb1.local_TLB_hits                     766                       # Number of TLB hits
system.l1_tlb1.local_TLB_misses                     3                       # Number of TLB misses
system.l1_tlb1.local_TLB_miss_rate           0.390117                       # TLB miss rate
system.l1_tlb1.global_TLB_accesses                769                       # Number of TLB accesses
system.l1_tlb1.global_TLB_hits                    766                       # Number of TLB hits
system.l1_tlb1.global_TLB_misses                    3                       # Number of TLB misses
system.l1_tlb1.global_TLB_miss_rate          0.390117                       # TLB miss rate
system.l1_tlb1.access_cycles                        0                       # Cycles spent accessing this TLB level
system.l1_tlb1.page_table_cycles                    0                       # Cycles spent accessing the page table
system.l1_tlb1.unique_pages                         3                       # Number of unique pages touched
system.l1_tlb1.local_cycles                         0                       # Number of cycles spent in queue for all incoming reqs
system.l1_tlb1.local_latency                        0                       # Avg. latency over incoming coalesced reqs
system.l1_tlb1.avg_reuse_distance                   0                       # avg. reuse distance over all pages (in ticks)
system.l2_coalescer.clk_domain.voltage_domain.voltage            1                       # Voltage in Volts
system.l2_coalescer.clk_domain.clock             1000                       # Clock period in ticks
system.l2_coalescer.uncoalesced_accesses            8                       # Number of uncoalesced TLB accesses
system.l2_coalescer.coalesced_accesses              1                       # Number of coalesced TLB accesses
system.l2_coalescer.queuing_cycles               8000                       # Number of cycles spent in queue
system.l2_coalescer.local_queuing_cycles         1000                       # Number of cycles spent in queue for all incoming reqs
system.l2_coalescer.local_latency                 125                       # Avg. latency over all incoming pkts
system.l2_tlb.clk_domain.voltage_domain.voltage            1                       # Voltage in Volts
system.l2_tlb.clk_domain.clock                   1000                       # Clock period in ticks
system.l2_tlb.local_TLB_accesses                    8                       # Number of TLB accesses
system.l2_tlb.local_TLB_hits                        3                       # Number of TLB hits
system.l2_tlb.local_TLB_misses                      5                       # Number of TLB misses
system.l2_tlb.local_TLB_miss_rate           62.500000                       # TLB miss rate
system.l2_tlb.global_TLB_accesses                  15                       # Number of TLB accesses
system.l2_tlb.global_TLB_hits                       3                       # Number of TLB hits
system.l2_tlb.global_TLB_misses                    12                       # Number of TLB misses
system.l2_tlb.global_TLB_miss_rate                 80                       # TLB miss rate
system.l2_tlb.access_cycles                    552008                       # Cycles spent accessing this TLB level
system.l2_tlb.page_table_cycles                     0                       # Cycles spent accessing the page table
system.l2_tlb.unique_pages                          5                       # Number of unique pages touched
system.l2_tlb.local_cycles                      69001                       # Number of cycles spent in queue for all incoming reqs
system.l2_tlb.local_latency               8625.125000                       # Avg. latency over incoming coalesced reqs
system.l2_tlb.avg_reuse_distance                    0                       # avg. reuse distance over all pages (in ticks)
system.l3_coalescer.clk_domain.voltage_domain.voltage            1                       # Voltage in Volts
system.l3_coalescer.clk_domain.clock             1000                       # Clock period in ticks
system.l3_coalescer.uncoalesced_accesses            5                       # Number of uncoalesced TLB accesses
system.l3_coalescer.coalesced_accesses              1                       # Number of coalesced TLB accesses
system.l3_coalescer.queuing_cycles               8000                       # Number of cycles spent in queue
system.l3_coalescer.local_queuing_cycles         1000                       # Number of cycles spent in queue for all incoming reqs
system.l3_coalescer.local_latency                 200                       # Avg. latency over all incoming pkts
system.l3_tlb.clk_domain.voltage_domain.voltage            1                       # Voltage in Volts
system.l3_tlb.clk_domain.clock                   1000                       # Clock period in ticks
system.l3_tlb.local_TLB_accesses                    5                       # Number of TLB accesses
system.l3_tlb.local_TLB_hits                        0                       # Number of TLB hits
system.l3_tlb.local_TLB_misses                      5                       # Number of TLB misses
system.l3_tlb.local_TLB_miss_rate                 100                       # TLB miss rate
system.l3_tlb.global_TLB_accesses                  12                       # Number of TLB accesses
system.l3_tlb.global_TLB_hits                       0                       # Number of TLB hits
system.l3_tlb.global_TLB_misses                    12                       # Number of TLB misses
system.l3_tlb.global_TLB_miss_rate                100                       # TLB miss rate
system.l3_tlb.access_cycles                   1200000                       # Cycles spent accessing this TLB level
system.l3_tlb.page_table_cycles               6000000                       # Cycles spent accessing the page table
system.l3_tlb.unique_pages                          5                       # Number of unique pages touched
system.l3_tlb.local_cycles                     150000                       # Number of cycles spent in queue for all incoming reqs
system.l3_tlb.local_latency                     30000                       # Avg. latency over incoming coalesced reqs
system.l3_tlb.avg_reuse_distance                    0                       # avg. reuse distance over all pages (in ticks)
system.piobus.trans_dist::WriteReq                 94                       # Transaction distribution
system.piobus.trans_dist::WriteResp                94                       # Transaction distribution
system.piobus.pkt_count_system.cp_cntrl0.sequencer.mem-master-port::system.cpu2.pio          188                       # Packet count per connected master and slave (bytes)
system.piobus.pkt_count::total                    188                       # Packet count per connected master and slave (bytes)
system.piobus.pkt_size_system.cp_cntrl0.sequencer.mem-master-port::system.cpu2.pio          748                       # Cumulative packet size per connected master and slave (bytes)
system.piobus.pkt_size::total                     748                       # Cumulative packet size per connected master and slave (bytes)
system.piobus.reqLayer0.occupancy              188000                       # Layer occupancy (ticks)
system.piobus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.piobus.respLayer0.occupancy              94000                       # Layer occupancy (ticks)
system.piobus.respLayer0.utilization              0.0                       # Layer utilization (%)
system.ruby.network.ext_links0.int_node.percent_links_utilized     0.130525                      
system.ruby.network.ext_links0.int_node.msg_count.Control::0            4                      
system.ruby.network.ext_links0.int_node.msg_count.Data::0           18                      
system.ruby.network.ext_links0.int_node.msg_count.Request_Control::0         1542                      
system.ruby.network.ext_links0.int_node.msg_count.Response_Data::2         1546                      
system.ruby.network.ext_links0.int_node.msg_count.Response_Control::2            2                      
system.ruby.network.ext_links0.int_node.msg_count.Writeback_Control::2           16                      
system.ruby.network.ext_links0.int_node.msg_count.Unblock_Control::4         1541                      
system.ruby.network.ext_links0.int_node.msg_bytes.Control::0           32                      
system.ruby.network.ext_links0.int_node.msg_bytes.Data::0         1296                      
system.ruby.network.ext_links0.int_node.msg_bytes.Request_Control::0        12336                      
system.ruby.network.ext_links0.int_node.msg_bytes.Response_Data::2       111312                      
system.ruby.network.ext_links0.int_node.msg_bytes.Response_Control::2           16                      
system.ruby.network.ext_links0.int_node.msg_bytes.Writeback_Control::2          128                      
system.ruby.network.ext_links0.int_node.msg_bytes.Unblock_Control::4        12328                      
system.ruby.network.ext_links1.int_node.percent_links_utilized     0.192653                      
system.ruby.network.ext_links1.int_node.msg_count.Control::0            3                      
system.ruby.network.ext_links1.int_node.msg_count.Request_Control::0         1535                      
system.ruby.network.ext_links1.int_node.msg_count.Response_Data::2         1537                      
system.ruby.network.ext_links1.int_node.msg_count.Response_Control::2            1                      
system.ruby.network.ext_links1.int_node.msg_count.Unblock_Control::4         1534                      
system.ruby.network.ext_links1.int_node.msg_bytes.Control::0           24                      
system.ruby.network.ext_links1.int_node.msg_bytes.Request_Control::0        12280                      
system.ruby.network.ext_links1.int_node.msg_bytes.Response_Data::2       110664                      
system.ruby.network.ext_links1.int_node.msg_bytes.Response_Control::2            8                      
system.ruby.network.ext_links1.int_node.msg_bytes.Unblock_Control::4        12272                      
system.tcp_cntrl0.L1cache.demand_hits               0                       # Number of cache demand hits
system.tcp_cntrl0.L1cache.demand_misses             0                       # Number of cache demand misses
system.tcp_cntrl0.L1cache.demand_accesses            0                       # Number of cache demand accesses
system.tcp_cntrl0.L1cache.num_data_array_reads            6                       # number of data array reads
system.tcp_cntrl0.L1cache.num_data_array_writes           11                       # number of data array writes
system.tcp_cntrl0.L1cache.num_tag_array_reads         1297                       # number of tag array reads
system.tcp_cntrl0.L1cache.num_tag_array_writes           11                       # number of tag array writes
system.tcp_cntrl0.L1cache.num_tag_array_stalls         1271                       # number of stalls caused by tag array
system.tcp_cntrl0.L1cache.num_data_array_stalls            2                       # number of stalls caused by data array
system.tcp_cntrl0.coalescer.gpu_tcp_ld_hits            0                       # loads that hit in the TCP
system.tcp_cntrl0.coalescer.gpu_tcp_ld_transfers            0                       # TCP to TCP load transfers
system.tcp_cntrl0.coalescer.gpu_tcc_ld_hits            0                       # loads that hit in the TCC
system.tcp_cntrl0.coalescer.gpu_ld_misses            5                       # loads that miss in the GPU
system.tcp_cntrl0.coalescer.gpu_tcp_st_hits            0                       # stores that hit in the TCP
system.tcp_cntrl0.coalescer.gpu_tcp_st_transfers            0                       # TCP to TCP store transfers
system.tcp_cntrl0.coalescer.gpu_tcc_st_hits            0                       # stores that hit in the TCC
system.tcp_cntrl0.coalescer.gpu_st_misses            9                       # stores that miss in the GPU
system.tcp_cntrl0.coalescer.cp_tcp_ld_hits            0                       # loads that hit in the TCP
system.tcp_cntrl0.coalescer.cp_tcp_ld_transfers            0                       # TCP to TCP load transfers
system.tcp_cntrl0.coalescer.cp_tcc_ld_hits            0                       # loads that hit in the TCC
system.tcp_cntrl0.coalescer.cp_ld_misses            0                       # loads that miss in the GPU
system.tcp_cntrl0.coalescer.cp_tcp_st_hits            0                       # stores that hit in the TCP
system.tcp_cntrl0.coalescer.cp_tcp_st_transfers            0                       # TCP to TCP store transfers
system.tcp_cntrl0.coalescer.cp_tcc_st_hits            0                       # stores that hit in the TCC
system.tcp_cntrl0.coalescer.cp_st_misses            0                       # stores that miss in the GPU
system.ruby.network.ext_links2.int_node.percent_links_utilized     0.002557                      
system.ruby.network.ext_links2.int_node.msg_count.Control::0            1                      
system.ruby.network.ext_links2.int_node.msg_count.Data::0           18                      
system.ruby.network.ext_links2.int_node.msg_count.Data::1           18                      
system.ruby.network.ext_links2.int_node.msg_count.Request_Control::0            7                      
system.ruby.network.ext_links2.int_node.msg_count.Request_Control::1            9                      
system.ruby.network.ext_links2.int_node.msg_count.Response_Data::2            9                      
system.ruby.network.ext_links2.int_node.msg_count.Response_Data::3           11                      
system.ruby.network.ext_links2.int_node.msg_count.Response_Control::2            1                      
system.ruby.network.ext_links2.int_node.msg_count.Writeback_Control::2           16                      
system.ruby.network.ext_links2.int_node.msg_count.Writeback_Control::3           16                      
system.ruby.network.ext_links2.int_node.msg_count.Unblock_Control::4            7                      
system.ruby.network.ext_links2.int_node.msg_bytes.Control::0            8                      
system.ruby.network.ext_links2.int_node.msg_bytes.Data::0         1296                      
system.ruby.network.ext_links2.int_node.msg_bytes.Data::1         1296                      
system.ruby.network.ext_links2.int_node.msg_bytes.Request_Control::0           56                      
system.ruby.network.ext_links2.int_node.msg_bytes.Request_Control::1           72                      
system.ruby.network.ext_links2.int_node.msg_bytes.Response_Data::2          648                      
system.ruby.network.ext_links2.int_node.msg_bytes.Response_Data::3          792                      
system.ruby.network.ext_links2.int_node.msg_bytes.Response_Control::2            8                      
system.ruby.network.ext_links2.int_node.msg_bytes.Writeback_Control::2          128                      
system.ruby.network.ext_links2.int_node.msg_bytes.Writeback_Control::3          128                      
system.ruby.network.ext_links2.int_node.msg_bytes.Unblock_Control::4           56                      
system.tcp_cntrl1.L1cache.demand_hits               0                       # Number of cache demand hits
system.tcp_cntrl1.L1cache.demand_misses             0                       # Number of cache demand misses
system.tcp_cntrl1.L1cache.demand_accesses            0                       # Number of cache demand accesses
system.tcp_cntrl1.L1cache.num_data_array_reads            6                       # number of data array reads
system.tcp_cntrl1.L1cache.num_data_array_writes           11                       # number of data array writes
system.tcp_cntrl1.L1cache.num_tag_array_reads         1297                       # number of tag array reads
system.tcp_cntrl1.L1cache.num_tag_array_writes           11                       # number of tag array writes
system.tcp_cntrl1.L1cache.num_tag_array_stalls         1271                       # number of stalls caused by tag array
system.tcp_cntrl1.L1cache.num_data_array_stalls            2                       # number of stalls caused by data array
system.tcp_cntrl1.coalescer.gpu_tcp_ld_hits            0                       # loads that hit in the TCP
system.tcp_cntrl1.coalescer.gpu_tcp_ld_transfers            0                       # TCP to TCP load transfers
system.tcp_cntrl1.coalescer.gpu_tcc_ld_hits            0                       # loads that hit in the TCC
system.tcp_cntrl1.coalescer.gpu_ld_misses            5                       # loads that miss in the GPU
system.tcp_cntrl1.coalescer.gpu_tcp_st_hits            0                       # stores that hit in the TCP
system.tcp_cntrl1.coalescer.gpu_tcp_st_transfers            0                       # TCP to TCP store transfers
system.tcp_cntrl1.coalescer.gpu_tcc_st_hits            0                       # stores that hit in the TCC
system.tcp_cntrl1.coalescer.gpu_st_misses            9                       # stores that miss in the GPU
system.tcp_cntrl1.coalescer.cp_tcp_ld_hits            0                       # loads that hit in the TCP
system.tcp_cntrl1.coalescer.cp_tcp_ld_transfers            0                       # TCP to TCP load transfers
system.tcp_cntrl1.coalescer.cp_tcc_ld_hits            0                       # loads that hit in the TCC
system.tcp_cntrl1.coalescer.cp_ld_misses            0                       # loads that miss in the GPU
system.tcp_cntrl1.coalescer.cp_tcp_st_hits            0                       # stores that hit in the TCP
system.tcp_cntrl1.coalescer.cp_tcp_st_transfers            0                       # TCP to TCP store transfers
system.tcp_cntrl1.coalescer.cp_tcc_st_hits            0                       # stores that hit in the TCC
system.tcp_cntrl1.coalescer.cp_st_misses            0                       # stores that miss in the GPU
system.sqc_cntrl0.L1cache.demand_hits               0                       # Number of cache demand hits
system.sqc_cntrl0.L1cache.demand_misses             0                       # Number of cache demand misses
system.sqc_cntrl0.L1cache.demand_accesses            0                       # Number of cache demand accesses
system.sqc_cntrl0.L1cache.num_data_array_reads           86                       # number of data array reads
system.sqc_cntrl0.L1cache.num_tag_array_reads           91                       # number of tag array reads
system.sqc_cntrl0.L1cache.num_tag_array_writes           10                       # number of tag array writes
system.sqc_cntrl0.sequencer.load_waiting_on_load           98                       # Number of times a load aliased with a pending load
system.tcc_cntrl0.L2cache.demand_hits               0                       # Number of cache demand hits
system.tcc_cntrl0.L2cache.demand_misses             0                       # Number of cache demand misses
system.tcc_cntrl0.L2cache.demand_accesses            0                       # Number of cache demand accesses
system.tcc_cntrl0.L2cache.num_data_array_writes            9                       # number of data array writes
system.tcc_cntrl0.L2cache.num_tag_array_reads           35                       # number of tag array reads
system.tcc_cntrl0.L2cache.num_tag_array_writes           11                       # number of tag array writes
system.ruby.network.msg_count.Control               8                      
system.ruby.network.msg_count.Data                 54                      
system.ruby.network.msg_count.Request_Control         3093                      
system.ruby.network.msg_count.Response_Data         3103                      
system.ruby.network.msg_count.Response_Control            4                      
system.ruby.network.msg_count.Writeback_Control           48                      
system.ruby.network.msg_count.Unblock_Control         3082                      
system.ruby.network.msg_byte.Control               64                      
system.ruby.network.msg_byte.Data                3888                      
system.ruby.network.msg_byte.Request_Control        24744                      
system.ruby.network.msg_byte.Response_Data       223416                      
system.ruby.network.msg_byte.Response_Control           32                      
system.ruby.network.msg_byte.Writeback_Control          384                      
system.ruby.network.msg_byte.Unblock_Control        24656                      
system.sqc_coalescer.clk_domain.voltage_domain.voltage            1                       # Voltage in Volts
system.sqc_coalescer.clk_domain.clock            1000                       # Clock period in ticks
system.sqc_coalescer.uncoalesced_accesses           86                       # Number of uncoalesced TLB accesses
system.sqc_coalescer.coalesced_accesses            66                       # Number of coalesced TLB accesses
system.sqc_coalescer.queuing_cycles            288000                       # Number of cycles spent in queue
system.sqc_coalescer.local_queuing_cycles       288000                       # Number of cycles spent in queue for all incoming reqs
system.sqc_coalescer.local_latency        3348.837209                       # Avg. latency over all incoming pkts
system.sqc_tlb.clk_domain.voltage_domain.voltage            1                       # Voltage in Volts
system.sqc_tlb.clk_domain.clock                  1000                       # Clock period in ticks
system.sqc_tlb.local_TLB_accesses                  66                       # Number of TLB accesses
system.sqc_tlb.local_TLB_hits                      65                       # Number of TLB hits
system.sqc_tlb.local_TLB_misses                     1                       # Number of TLB misses
system.sqc_tlb.local_TLB_miss_rate           1.515152                       # TLB miss rate
system.sqc_tlb.global_TLB_accesses                 86                       # Number of TLB accesses
system.sqc_tlb.global_TLB_hits                     78                       # Number of TLB hits
system.sqc_tlb.global_TLB_misses                    8                       # Number of TLB misses
system.sqc_tlb.global_TLB_miss_rate          9.302326                       # TLB miss rate
system.sqc_tlb.access_cycles                    86008                       # Cycles spent accessing this TLB level
system.sqc_tlb.page_table_cycles                    0                       # Cycles spent accessing the page table
system.sqc_tlb.unique_pages                         1                       # Number of unique pages touched
system.sqc_tlb.local_cycles                     66001                       # Number of cycles spent in queue for all incoming reqs
system.sqc_tlb.local_latency              1000.015152                       # Avg. latency over incoming coalesced reqs
system.sqc_tlb.avg_reuse_distance                   0                       # avg. reuse distance over all pages (in ticks)
system.ruby.network.ext_links0.int_node.throttle0.link_utilization     0.074413                      
system.ruby.network.ext_links0.int_node.throttle0.msg_count.Data::0           18                      
system.ruby.network.ext_links0.int_node.throttle0.msg_count.Request_Control::0         1542                      
system.ruby.network.ext_links0.int_node.throttle0.msg_count.Response_Data::2            2                      
system.ruby.network.ext_links0.int_node.throttle0.msg_count.Response_Control::2            2                      
system.ruby.network.ext_links0.int_node.throttle0.msg_count.Unblock_Control::4         1541                      
system.ruby.network.ext_links0.int_node.throttle0.msg_bytes.Data::0         1296                      
system.ruby.network.ext_links0.int_node.throttle0.msg_bytes.Request_Control::0        12336                      
system.ruby.network.ext_links0.int_node.throttle0.msg_bytes.Response_Data::2          144                      
system.ruby.network.ext_links0.int_node.throttle0.msg_bytes.Response_Control::2           16                      
system.ruby.network.ext_links0.int_node.throttle0.msg_bytes.Unblock_Control::4        12328                      
system.ruby.network.ext_links0.int_node.throttle1.link_utilization     0.314928                      
system.ruby.network.ext_links0.int_node.throttle1.msg_count.Control::0            3                      
system.ruby.network.ext_links0.int_node.throttle1.msg_count.Response_Data::2         1535                      
system.ruby.network.ext_links0.int_node.throttle1.msg_bytes.Control::0           24                      
system.ruby.network.ext_links0.int_node.throttle1.msg_bytes.Response_Data::2       110520                      
system.ruby.network.ext_links0.int_node.throttle2.link_utilization     0.002234                      
system.ruby.network.ext_links0.int_node.throttle2.msg_count.Control::0            1                      
system.ruby.network.ext_links0.int_node.throttle2.msg_count.Response_Data::2            9                      
system.ruby.network.ext_links0.int_node.throttle2.msg_count.Writeback_Control::2           16                      
system.ruby.network.ext_links0.int_node.throttle2.msg_bytes.Control::0            8                      
system.ruby.network.ext_links0.int_node.throttle2.msg_bytes.Response_Data::2          648                      
system.ruby.network.ext_links0.int_node.throttle2.msg_bytes.Writeback_Control::2          128                      
system.ruby.network.ext_links1.int_node.throttle0.link_utilization     0.314928                      
system.ruby.network.ext_links1.int_node.throttle0.msg_count.Control::0            3                      
system.ruby.network.ext_links1.int_node.throttle0.msg_count.Response_Data::2         1535                      
system.ruby.network.ext_links1.int_node.throttle0.msg_bytes.Control::0           24                      
system.ruby.network.ext_links1.int_node.throttle0.msg_bytes.Response_Data::2       110520                      
system.ruby.network.ext_links1.int_node.throttle1.link_utilization     0.070379                      
system.ruby.network.ext_links1.int_node.throttle1.msg_count.Request_Control::0         1535                      
system.ruby.network.ext_links1.int_node.throttle1.msg_count.Response_Data::2            2                      
system.ruby.network.ext_links1.int_node.throttle1.msg_count.Response_Control::2            1                      
system.ruby.network.ext_links1.int_node.throttle1.msg_count.Unblock_Control::4         1534                      
system.ruby.network.ext_links1.int_node.throttle1.msg_bytes.Request_Control::0        12280                      
system.ruby.network.ext_links1.int_node.throttle1.msg_bytes.Response_Data::2          144                      
system.ruby.network.ext_links1.int_node.throttle1.msg_bytes.Response_Control::2            8                      
system.ruby.network.ext_links1.int_node.throttle1.msg_bytes.Unblock_Control::4        12272                      
system.ruby.network.ext_links2.int_node.throttle0.link_utilization     0.000798                      
system.ruby.network.ext_links2.int_node.throttle0.msg_count.Response_Data::3            3                      
system.ruby.network.ext_links2.int_node.throttle0.msg_count.Writeback_Control::3            8                      
system.ruby.network.ext_links2.int_node.throttle0.msg_bytes.Response_Data::3          216                      
system.ruby.network.ext_links2.int_node.throttle0.msg_bytes.Writeback_Control::3           64                      
system.ruby.network.ext_links2.int_node.throttle1.link_utilization     0.000798                      
system.ruby.network.ext_links2.int_node.throttle1.msg_count.Response_Data::3            3                      
system.ruby.network.ext_links2.int_node.throttle1.msg_count.Writeback_Control::3            8                      
system.ruby.network.ext_links2.int_node.throttle1.msg_bytes.Response_Data::3          216                      
system.ruby.network.ext_links2.int_node.throttle1.msg_bytes.Writeback_Control::3           64                      
system.ruby.network.ext_links2.int_node.throttle2.link_utilization     0.006131                      
system.ruby.network.ext_links2.int_node.throttle2.msg_count.Control::0            1                      
system.ruby.network.ext_links2.int_node.throttle2.msg_count.Data::1           18                      
system.ruby.network.ext_links2.int_node.throttle2.msg_count.Request_Control::1            9                      
system.ruby.network.ext_links2.int_node.throttle2.msg_count.Response_Data::2            9                      
system.ruby.network.ext_links2.int_node.throttle2.msg_count.Writeback_Control::2           16                      
system.ruby.network.ext_links2.int_node.throttle2.msg_bytes.Control::0            8                      
system.ruby.network.ext_links2.int_node.throttle2.msg_bytes.Data::1         1296                      
system.ruby.network.ext_links2.int_node.throttle2.msg_bytes.Request_Control::1           72                      
system.ruby.network.ext_links2.int_node.throttle2.msg_bytes.Response_Data::2          648                      
system.ruby.network.ext_links2.int_node.throttle2.msg_bytes.Writeback_Control::2          128                      
system.ruby.network.ext_links2.int_node.throttle3.link_utilization     0.001026                      
system.ruby.network.ext_links2.int_node.throttle3.msg_count.Response_Data::3            5                      
system.ruby.network.ext_links2.int_node.throttle3.msg_bytes.Response_Data::3          360                      
system.ruby.network.ext_links2.int_node.throttle4.link_utilization     0.004034                      
system.ruby.network.ext_links2.int_node.throttle4.msg_count.Data::0           18                      
system.ruby.network.ext_links2.int_node.throttle4.msg_count.Request_Control::0            7                      
system.ruby.network.ext_links2.int_node.throttle4.msg_count.Response_Control::2            1                      
system.ruby.network.ext_links2.int_node.throttle4.msg_count.Unblock_Control::4            7                      
system.ruby.network.ext_links2.int_node.throttle4.msg_bytes.Data::0         1296                      
system.ruby.network.ext_links2.int_node.throttle4.msg_bytes.Request_Control::0           56                      
system.ruby.network.ext_links2.int_node.throttle4.msg_bytes.Response_Control::2            8                      
system.ruby.network.ext_links2.int_node.throttle4.msg_bytes.Unblock_Control::4           56                      
system.ruby.CorePair_Controller.C0_Load_L1miss          180      0.00%      0.00%
system.ruby.CorePair_Controller.C0_Load_L1hit        16155      0.00%      0.00%
system.ruby.CorePair_Controller.Ifetch0_L1hit        86007      0.00%      0.00%
system.ruby.CorePair_Controller.Ifetch0_L1miss         1088      0.00%      0.00%
system.ruby.CorePair_Controller.C0_Store_L1miss          325      0.00%      0.00%
system.ruby.CorePair_Controller.C0_Store_L1hit        10448      0.00%      0.00%
system.ruby.CorePair_Controller.NB_AckS          1034      0.00%      0.00%
system.ruby.CorePair_Controller.NB_AckM           326      0.00%      0.00%
system.ruby.CorePair_Controller.NB_AckE           175      0.00%      0.00%
system.ruby.CorePair_Controller.L1I_Repl          589      0.00%      0.00%
system.ruby.CorePair_Controller.L1D0_Repl           24      0.00%      0.00%
system.ruby.CorePair_Controller.L2_to_L1D0            5      0.00%      0.00%
system.ruby.CorePair_Controller.L2_to_L1I           54      0.00%      0.00%
system.ruby.CorePair_Controller.PrbInvData            1      0.00%      0.00%
system.ruby.CorePair_Controller.PrbShrData            2      0.00%      0.00%
system.ruby.CorePair_Controller.I.C0_Load_L1miss          175      0.00%      0.00%
system.ruby.CorePair_Controller.I.Ifetch0_L1miss         1034      0.00%      0.00%
system.ruby.CorePair_Controller.I.C0_Store_L1miss          325      0.00%      0.00%
system.ruby.CorePair_Controller.S.Ifetch0_L1hit        86007      0.00%      0.00%
system.ruby.CorePair_Controller.S.Ifetch0_L1miss           54      0.00%      0.00%
system.ruby.CorePair_Controller.S.L1I_Repl          589      0.00%      0.00%
system.ruby.CorePair_Controller.E0.C0_Load_L1miss            2      0.00%      0.00%
system.ruby.CorePair_Controller.E0.C0_Load_L1hit         3356      0.00%      0.00%
system.ruby.CorePair_Controller.E0.C0_Store_L1hit           46      0.00%      0.00%
system.ruby.CorePair_Controller.E0.L1D0_Repl           16      0.00%      0.00%
system.ruby.CorePair_Controller.E0.PrbShrData            1      0.00%      0.00%
system.ruby.CorePair_Controller.O.C0_Load_L1hit            3      0.00%      0.00%
system.ruby.CorePair_Controller.O.C0_Store_L1hit            1      0.00%      0.00%
system.ruby.CorePair_Controller.M0.C0_Load_L1miss            3      0.00%      0.00%
system.ruby.CorePair_Controller.M0.C0_Load_L1hit        12796      0.00%      0.00%
system.ruby.CorePair_Controller.M0.C0_Store_L1hit        10401      0.00%      0.00%
system.ruby.CorePair_Controller.M0.L1D0_Repl            8      0.00%      0.00%
system.ruby.CorePair_Controller.M0.PrbInvData            1      0.00%      0.00%
system.ruby.CorePair_Controller.M0.PrbShrData            1      0.00%      0.00%
system.ruby.CorePair_Controller.I_M0.NB_AckM          325      0.00%      0.00%
system.ruby.CorePair_Controller.I_E0S.NB_AckE          175      0.00%      0.00%
system.ruby.CorePair_Controller.Si_F0.L2_to_L1I           54      0.00%      0.00%
system.ruby.CorePair_Controller.O_M0.NB_AckM            1      0.00%      0.00%
system.ruby.CorePair_Controller.S0.NB_AckS         1034      0.00%      0.00%
system.ruby.CorePair_Controller.E0_F.L2_to_L1D0            2      0.00%      0.00%
system.ruby.CorePair_Controller.M0_F.L2_to_L1D0            3      0.00%      0.00%
system.ruby.Directory_Controller.RdBlkS          1034      0.00%      0.00%
system.ruby.Directory_Controller.RdBlkM           326      0.00%      0.00%
system.ruby.Directory_Controller.RdBlk            182      0.00%      0.00%
system.ruby.Directory_Controller.WriteThrough           16      0.00%      0.00%
system.ruby.Directory_Controller.Atomic             3      0.00%      0.00%
system.ruby.Directory_Controller.CPUPrbResp            4      0.00%      0.00%
system.ruby.Directory_Controller.ProbeAcksComplete         1560      0.00%      0.00%
system.ruby.Directory_Controller.MemData         1560      0.00%      0.00%
system.ruby.Directory_Controller.CoreUnblock         1541      0.00%      0.00%
system.ruby.Directory_Controller.UnblockWriteThrough           18      0.00%      0.00%
system.ruby.Directory_Controller.U.RdBlkS         1034      0.00%      0.00%
system.ruby.Directory_Controller.U.RdBlkM          326      0.00%      0.00%
system.ruby.Directory_Controller.U.RdBlk          182      0.00%      0.00%
system.ruby.Directory_Controller.U.WriteThrough           16      0.00%      0.00%
system.ruby.Directory_Controller.U.Atomic            2      0.00%      0.00%
system.ruby.Directory_Controller.BS_M.MemData         1034      0.00%      0.00%
system.ruby.Directory_Controller.BM_M.MemData          343      0.00%      0.00%
system.ruby.Directory_Controller.B_M.MemData          180      0.00%      0.00%
system.ruby.Directory_Controller.BS_PM.ProbeAcksComplete         1034      0.00%      0.00%
system.ruby.Directory_Controller.BM_PM.Atomic            1      0.00%      0.00%
system.ruby.Directory_Controller.BM_PM.CPUPrbResp            1      0.00%      0.00%
system.ruby.Directory_Controller.BM_PM.ProbeAcksComplete          343      0.00%      0.00%
system.ruby.Directory_Controller.BM_PM.MemData            1      0.00%      0.00%
system.ruby.Directory_Controller.B_PM.ProbeAcksComplete          180      0.00%      0.00%
system.ruby.Directory_Controller.B_PM.MemData            2      0.00%      0.00%
system.ruby.Directory_Controller.BM_Pm.CPUPrbResp            1      0.00%      0.00%
system.ruby.Directory_Controller.BM_Pm.ProbeAcksComplete            1      0.00%      0.00%
system.ruby.Directory_Controller.B_Pm.CPUPrbResp            2      0.00%      0.00%
system.ruby.Directory_Controller.B_Pm.ProbeAcksComplete            2      0.00%      0.00%
system.ruby.Directory_Controller.B.CoreUnblock         1541      0.00%      0.00%
system.ruby.Directory_Controller.B.UnblockWriteThrough           18      0.00%      0.00%
system.ruby.LD.latency_hist::bucket_size           64                      
system.ruby.LD.latency_hist::max_bucket           639                      
system.ruby.LD.latency_hist::samples            16335                      
system.ruby.LD.latency_hist::mean            3.253444                      
system.ruby.LD.latency_hist::gmean           1.059859                      
system.ruby.LD.latency_hist::stdev          21.887471                      
system.ruby.LD.latency_hist              |       16160     98.93%     98.93% |           0      0.00%     98.93% |           0      0.00%     98.93% |         170      1.04%     99.97% |           1      0.01%     99.98% |           1      0.01%     99.98% |           2      0.01%     99.99% |           1      0.01%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
system.ruby.LD.latency_hist::total              16335                      
system.ruby.LD.hit_latency_hist::bucket_size           64                      
system.ruby.LD.hit_latency_hist::max_bucket          639                      
system.ruby.LD.hit_latency_hist::samples          175                      
system.ruby.LD.hit_latency_hist::mean      210.828571                      
system.ruby.LD.hit_latency_hist::gmean     209.031405                      
system.ruby.LD.hit_latency_hist::stdev      34.022715                      
system.ruby.LD.hit_latency_hist          |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |         170     97.14%     97.14% |           1      0.57%     97.71% |           1      0.57%     98.29% |           2      1.14%     99.43% |           1      0.57%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
system.ruby.LD.hit_latency_hist::total            175                      
system.ruby.LD.miss_latency_hist::bucket_size            2                      
system.ruby.LD.miss_latency_hist::max_bucket           19                      
system.ruby.LD.miss_latency_hist::samples        16160                      
system.ruby.LD.miss_latency_hist::mean       1.005569                      
system.ruby.LD.miss_latency_hist::gmean      1.000911                      
system.ruby.LD.miss_latency_hist::stdev      0.316580                      
system.ruby.LD.miss_latency_hist         |       16155     99.97%     99.97% |           0      0.00%     99.97% |           0      0.00%     99.97% |           0      0.00%     99.97% |           0      0.00%     99.97% |           0      0.00%     99.97% |           0      0.00%     99.97% |           0      0.00%     99.97% |           0      0.00%     99.97% |           5      0.03%    100.00%
system.ruby.LD.miss_latency_hist::total         16160                      
system.ruby.ST.latency_hist::bucket_size           64                      
system.ruby.ST.latency_hist::max_bucket           639                      
system.ruby.ST.latency_hist::samples            10412                      
system.ruby.ST.latency_hist::mean            7.384076                      
system.ruby.ST.latency_hist::gmean           1.178989                      
system.ruby.ST.latency_hist::stdev          36.341010                      
system.ruby.ST.latency_hist              |       10090     96.91%     96.91% |           0      0.00%     96.91% |           0      0.00%     96.91% |         309      2.97%     99.88% |           4      0.04%     99.91% |           2      0.02%     99.93% |           3      0.03%     99.96% |           4      0.04%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
system.ruby.ST.latency_hist::total              10412                      
system.ruby.ST.hit_latency_hist::bucket_size           64                      
system.ruby.ST.hit_latency_hist::max_bucket          639                      
system.ruby.ST.hit_latency_hist::samples          322                      
system.ruby.ST.hit_latency_hist::mean      207.431677                      
system.ruby.ST.hit_latency_hist::gmean     205.258691                      
system.ruby.ST.hit_latency_hist::stdev      37.529677                      
system.ruby.ST.hit_latency_hist          |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |         309     95.96%     95.96% |           4      1.24%     97.20% |           2      0.62%     97.83% |           3      0.93%     98.76% |           4      1.24%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
system.ruby.ST.hit_latency_hist::total            322                      
system.ruby.ST.miss_latency_hist::bucket_size            1                      
system.ruby.ST.miss_latency_hist::max_bucket            9                      
system.ruby.ST.miss_latency_hist::samples        10090                      
system.ruby.ST.miss_latency_hist::mean              1                      
system.ruby.ST.miss_latency_hist::gmean             1                      
system.ruby.ST.miss_latency_hist         |           0      0.00%      0.00% |       10090    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
system.ruby.ST.miss_latency_hist::total         10090                      
system.ruby.IFETCH.latency_hist::bucket_size           64                      
system.ruby.IFETCH.latency_hist::max_bucket          639                      
system.ruby.IFETCH.latency_hist::samples        87095                      
system.ruby.IFETCH.latency_hist::mean        3.432677                      
system.ruby.IFETCH.latency_hist::gmean       1.067087                      
system.ruby.IFETCH.latency_hist::stdev      22.344689                      
system.ruby.IFETCH.latency_hist          |       86061     98.81%     98.81% |           0      0.00%     98.81% |           0      0.00%     98.81% |        1006      1.16%     99.97% |           5      0.01%     99.97% |          10      0.01%     99.99% |          11      0.01%    100.00% |           2      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
system.ruby.IFETCH.latency_hist::total          87095                      
system.ruby.IFETCH.hit_latency_hist::bucket_size           64                      
system.ruby.IFETCH.hit_latency_hist::max_bucket          639                      
system.ruby.IFETCH.hit_latency_hist::samples         1034                      
system.ruby.IFETCH.hit_latency_hist::mean   204.967118                      
system.ruby.IFETCH.hit_latency_hist::gmean   203.475698                      
system.ruby.IFETCH.hit_latency_hist::stdev    30.573589                      
system.ruby.IFETCH.hit_latency_hist      |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |        1006     97.29%     97.29% |           5      0.48%     97.78% |          10      0.97%     98.74% |          11      1.06%     99.81% |           2      0.19%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
system.ruby.IFETCH.hit_latency_hist::total         1034                      
system.ruby.IFETCH.miss_latency_hist::bucket_size            2                      
system.ruby.IFETCH.miss_latency_hist::max_bucket           19                      
system.ruby.IFETCH.miss_latency_hist::samples        86061                      
system.ruby.IFETCH.miss_latency_hist::mean     1.011294                      
system.ruby.IFETCH.miss_latency_hist::gmean     1.001849                      
system.ruby.IFETCH.miss_latency_hist::stdev     0.450747                      
system.ruby.IFETCH.miss_latency_hist     |       86007     99.94%     99.94% |           0      0.00%     99.94% |           0      0.00%     99.94% |           0      0.00%     99.94% |           0      0.00%     99.94% |           0      0.00%     99.94% |           0      0.00%     99.94% |           0      0.00%     99.94% |           0      0.00%     99.94% |          54      0.06%    100.00%
system.ruby.IFETCH.miss_latency_hist::total        86061                      
system.ruby.RMW_Read.latency_hist::bucket_size           32                      
system.ruby.RMW_Read.latency_hist::max_bucket          319                      
system.ruby.RMW_Read.latency_hist::samples          341                      
system.ruby.RMW_Read.latency_hist::mean      3.451613                      
system.ruby.RMW_Read.latency_hist::gmean     1.064718                      
system.ruby.RMW_Read.latency_hist::stdev    22.561449                      
system.ruby.RMW_Read.latency_hist        |         337     98.83%     98.83% |           0      0.00%     98.83% |           0      0.00%     98.83% |           0      0.00%     98.83% |           0      0.00%     98.83% |           0      0.00%     98.83% |           3      0.88%     99.71% |           1      0.29%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
system.ruby.RMW_Read.latency_hist::total          341                      
system.ruby.RMW_Read.hit_latency_hist::bucket_size           32                      
system.ruby.RMW_Read.hit_latency_hist::max_bucket          319                      
system.ruby.RMW_Read.hit_latency_hist::samples            4                      
system.ruby.RMW_Read.hit_latency_hist::mean          210                      
system.ruby.RMW_Read.hit_latency_hist::gmean   209.766277                      
system.ruby.RMW_Read.hit_latency_hist::stdev    11.430952                      
system.ruby.RMW_Read.hit_latency_hist    |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           3     75.00%     75.00% |           1     25.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
system.ruby.RMW_Read.hit_latency_hist::total            4                      
system.ruby.RMW_Read.miss_latency_hist::bucket_size            1                      
system.ruby.RMW_Read.miss_latency_hist::max_bucket            9                      
system.ruby.RMW_Read.miss_latency_hist::samples          337                      
system.ruby.RMW_Read.miss_latency_hist::mean            1                      
system.ruby.RMW_Read.miss_latency_hist::gmean            1                      
system.ruby.RMW_Read.miss_latency_hist   |           0      0.00%      0.00% |         337    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
system.ruby.RMW_Read.miss_latency_hist::total          337                      
system.ruby.Locked_RMW_Read.latency_hist::bucket_size            1                      
system.ruby.Locked_RMW_Read.latency_hist::max_bucket            9                      
system.ruby.Locked_RMW_Read.latency_hist::samples           10                      
system.ruby.Locked_RMW_Read.latency_hist::mean            1                      
system.ruby.Locked_RMW_Read.latency_hist::gmean            1                      
system.ruby.Locked_RMW_Read.latency_hist |           0      0.00%      0.00% |          10    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
system.ruby.Locked_RMW_Read.latency_hist::total           10                      
system.ruby.Locked_RMW_Read.miss_latency_hist::bucket_size            1                      
system.ruby.Locked_RMW_Read.miss_latency_hist::max_bucket            9                      
system.ruby.Locked_RMW_Read.miss_latency_hist::samples           10                      
system.ruby.Locked_RMW_Read.miss_latency_hist::mean            1                      
system.ruby.Locked_RMW_Read.miss_latency_hist::gmean            1                      
system.ruby.Locked_RMW_Read.miss_latency_hist |           0      0.00%      0.00% |          10    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
system.ruby.Locked_RMW_Read.miss_latency_hist::total           10                      
system.ruby.Locked_RMW_Write.latency_hist::bucket_size            1                      
system.ruby.Locked_RMW_Write.latency_hist::max_bucket            9                      
system.ruby.Locked_RMW_Write.latency_hist::samples           10                      
system.ruby.Locked_RMW_Write.latency_hist::mean            1                      
system.ruby.Locked_RMW_Write.latency_hist::gmean            1                      
system.ruby.Locked_RMW_Write.latency_hist |           0      0.00%      0.00% |          10    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
system.ruby.Locked_RMW_Write.latency_hist::total           10                      
system.ruby.Locked_RMW_Write.miss_latency_hist::bucket_size            1                      
system.ruby.Locked_RMW_Write.miss_latency_hist::max_bucket            9                      
system.ruby.Locked_RMW_Write.miss_latency_hist::samples           10                      
system.ruby.Locked_RMW_Write.miss_latency_hist::mean            1                      
system.ruby.Locked_RMW_Write.miss_latency_hist::gmean            1                      
system.ruby.Locked_RMW_Write.miss_latency_hist |           0      0.00%      0.00% |          10    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
system.ruby.Locked_RMW_Write.miss_latency_hist::total           10                      
system.ruby.L1Cache.miss_mach_latency_hist::bucket_size            1                      
system.ruby.L1Cache.miss_mach_latency_hist::max_bucket            9                      
system.ruby.L1Cache.miss_mach_latency_hist::samples       112609                      
system.ruby.L1Cache.miss_mach_latency_hist::mean            1                      
system.ruby.L1Cache.miss_mach_latency_hist::gmean            1                      
system.ruby.L1Cache.miss_mach_latency_hist |           0      0.00%      0.00% |      112609    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
system.ruby.L1Cache.miss_mach_latency_hist::total       112609                      
system.ruby.L2Cache.miss_mach_latency_hist::bucket_size            2                      
system.ruby.L2Cache.miss_mach_latency_hist::max_bucket           19                      
system.ruby.L2Cache.miss_mach_latency_hist::samples           59                      
system.ruby.L2Cache.miss_mach_latency_hist::mean           19                      
system.ruby.L2Cache.miss_mach_latency_hist::gmean    19.000000                      
system.ruby.L2Cache.miss_mach_latency_hist |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |          59    100.00%    100.00%
system.ruby.L2Cache.miss_mach_latency_hist::total           59                      
system.ruby.Directory.hit_mach_latency_hist::bucket_size           64                      
system.ruby.Directory.hit_mach_latency_hist::max_bucket          639                      
system.ruby.Directory.hit_mach_latency_hist::samples         1535                      
system.ruby.Directory.hit_mach_latency_hist::mean   206.165472                      
system.ruby.Directory.hit_mach_latency_hist::gmean   204.491657                      
system.ruby.Directory.hit_mach_latency_hist::stdev    32.551053                      
system.ruby.Directory.hit_mach_latency_hist |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |        1489     97.00%     97.00% |          10      0.65%     97.65% |          13      0.85%     98.50% |          16      1.04%     99.54% |           7      0.46%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
system.ruby.Directory.hit_mach_latency_hist::total         1535                      
system.ruby.LD.L1Cache.miss_type_mach_latency_hist::bucket_size            1                      
system.ruby.LD.L1Cache.miss_type_mach_latency_hist::max_bucket            9                      
system.ruby.LD.L1Cache.miss_type_mach_latency_hist::samples        16155                      
system.ruby.LD.L1Cache.miss_type_mach_latency_hist::mean            1                      
system.ruby.LD.L1Cache.miss_type_mach_latency_hist::gmean            1                      
system.ruby.LD.L1Cache.miss_type_mach_latency_hist |           0      0.00%      0.00% |       16155    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
system.ruby.LD.L1Cache.miss_type_mach_latency_hist::total        16155                      
system.ruby.LD.L2Cache.miss_type_mach_latency_hist::bucket_size            2                      
system.ruby.LD.L2Cache.miss_type_mach_latency_hist::max_bucket           19                      
system.ruby.LD.L2Cache.miss_type_mach_latency_hist::samples            5                      
system.ruby.LD.L2Cache.miss_type_mach_latency_hist::mean           19                      
system.ruby.LD.L2Cache.miss_type_mach_latency_hist::gmean    19.000000                      
system.ruby.LD.L2Cache.miss_type_mach_latency_hist |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           5    100.00%    100.00%
system.ruby.LD.L2Cache.miss_type_mach_latency_hist::total            5                      
system.ruby.LD.Directory.hit_type_mach_latency_hist::bucket_size           64                      
system.ruby.LD.Directory.hit_type_mach_latency_hist::max_bucket          639                      
system.ruby.LD.Directory.hit_type_mach_latency_hist::samples          175                      
system.ruby.LD.Directory.hit_type_mach_latency_hist::mean   210.828571                      
system.ruby.LD.Directory.hit_type_mach_latency_hist::gmean   209.031405                      
system.ruby.LD.Directory.hit_type_mach_latency_hist::stdev    34.022715                      
system.ruby.LD.Directory.hit_type_mach_latency_hist |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |         170     97.14%     97.14% |           1      0.57%     97.71% |           1      0.57%     98.29% |           2      1.14%     99.43% |           1      0.57%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
system.ruby.LD.Directory.hit_type_mach_latency_hist::total          175                      
system.ruby.ST.L1Cache.miss_type_mach_latency_hist::bucket_size            1                      
system.ruby.ST.L1Cache.miss_type_mach_latency_hist::max_bucket            9                      
system.ruby.ST.L1Cache.miss_type_mach_latency_hist::samples        10090                      
system.ruby.ST.L1Cache.miss_type_mach_latency_hist::mean            1                      
system.ruby.ST.L1Cache.miss_type_mach_latency_hist::gmean            1                      
system.ruby.ST.L1Cache.miss_type_mach_latency_hist |           0      0.00%      0.00% |       10090    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
system.ruby.ST.L1Cache.miss_type_mach_latency_hist::total        10090                      
system.ruby.ST.Directory.hit_type_mach_latency_hist::bucket_size           64                      
system.ruby.ST.Directory.hit_type_mach_latency_hist::max_bucket          639                      
system.ruby.ST.Directory.hit_type_mach_latency_hist::samples          322                      
system.ruby.ST.Directory.hit_type_mach_latency_hist::mean   207.431677                      
system.ruby.ST.Directory.hit_type_mach_latency_hist::gmean   205.258691                      
system.ruby.ST.Directory.hit_type_mach_latency_hist::stdev    37.529677                      
system.ruby.ST.Directory.hit_type_mach_latency_hist |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |         309     95.96%     95.96% |           4      1.24%     97.20% |           2      0.62%     97.83% |           3      0.93%     98.76% |           4      1.24%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
system.ruby.ST.Directory.hit_type_mach_latency_hist::total          322                      
system.ruby.IFETCH.L1Cache.miss_type_mach_latency_hist::bucket_size            1                      
system.ruby.IFETCH.L1Cache.miss_type_mach_latency_hist::max_bucket            9                      
system.ruby.IFETCH.L1Cache.miss_type_mach_latency_hist::samples        86007                      
system.ruby.IFETCH.L1Cache.miss_type_mach_latency_hist::mean            1                      
system.ruby.IFETCH.L1Cache.miss_type_mach_latency_hist::gmean            1                      
system.ruby.IFETCH.L1Cache.miss_type_mach_latency_hist |           0      0.00%      0.00% |       86007    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
system.ruby.IFETCH.L1Cache.miss_type_mach_latency_hist::total        86007                      
system.ruby.IFETCH.L2Cache.miss_type_mach_latency_hist::bucket_size            2                      
system.ruby.IFETCH.L2Cache.miss_type_mach_latency_hist::max_bucket           19                      
system.ruby.IFETCH.L2Cache.miss_type_mach_latency_hist::samples           54                      
system.ruby.IFETCH.L2Cache.miss_type_mach_latency_hist::mean           19                      
system.ruby.IFETCH.L2Cache.miss_type_mach_latency_hist::gmean    19.000000                      
system.ruby.IFETCH.L2Cache.miss_type_mach_latency_hist |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |          54    100.00%    100.00%
system.ruby.IFETCH.L2Cache.miss_type_mach_latency_hist::total           54                      
system.ruby.IFETCH.Directory.hit_type_mach_latency_hist::bucket_size           64                      
system.ruby.IFETCH.Directory.hit_type_mach_latency_hist::max_bucket          639                      
system.ruby.IFETCH.Directory.hit_type_mach_latency_hist::samples         1034                      
system.ruby.IFETCH.Directory.hit_type_mach_latency_hist::mean   204.967118                      
system.ruby.IFETCH.Directory.hit_type_mach_latency_hist::gmean   203.475698                      
system.ruby.IFETCH.Directory.hit_type_mach_latency_hist::stdev    30.573589                      
system.ruby.IFETCH.Directory.hit_type_mach_latency_hist |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |        1006     97.29%     97.29% |           5      0.48%     97.78% |          10      0.97%     98.74% |          11      1.06%     99.81% |           2      0.19%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
system.ruby.IFETCH.Directory.hit_type_mach_latency_hist::total         1034                      
system.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist::bucket_size            1                      
system.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist::max_bucket            9                      
system.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist::samples          337                      
system.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist::mean            1                      
system.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist::gmean            1                      
system.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist |           0      0.00%      0.00% |         337    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
system.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist::total          337                      
system.ruby.RMW_Read.Directory.hit_type_mach_latency_hist::bucket_size           32                      
system.ruby.RMW_Read.Directory.hit_type_mach_latency_hist::max_bucket          319                      
system.ruby.RMW_Read.Directory.hit_type_mach_latency_hist::samples            4                      
system.ruby.RMW_Read.Directory.hit_type_mach_latency_hist::mean          210                      
system.ruby.RMW_Read.Directory.hit_type_mach_latency_hist::gmean   209.766277                      
system.ruby.RMW_Read.Directory.hit_type_mach_latency_hist::stdev    11.430952                      
system.ruby.RMW_Read.Directory.hit_type_mach_latency_hist |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           3     75.00%     75.00% |           1     25.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
system.ruby.RMW_Read.Directory.hit_type_mach_latency_hist::total            4                      
system.ruby.Locked_RMW_Read.L1Cache.miss_type_mach_latency_hist::bucket_size            1                      
system.ruby.Locked_RMW_Read.L1Cache.miss_type_mach_latency_hist::max_bucket            9                      
system.ruby.Locked_RMW_Read.L1Cache.miss_type_mach_latency_hist::samples           10                      
system.ruby.Locked_RMW_Read.L1Cache.miss_type_mach_latency_hist::mean            1                      
system.ruby.Locked_RMW_Read.L1Cache.miss_type_mach_latency_hist::gmean            1                      
system.ruby.Locked_RMW_Read.L1Cache.miss_type_mach_latency_hist |           0      0.00%      0.00% |          10    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
system.ruby.Locked_RMW_Read.L1Cache.miss_type_mach_latency_hist::total           10                      
system.ruby.Locked_RMW_Write.L1Cache.miss_type_mach_latency_hist::bucket_size            1                      
system.ruby.Locked_RMW_Write.L1Cache.miss_type_mach_latency_hist::max_bucket            9                      
system.ruby.Locked_RMW_Write.L1Cache.miss_type_mach_latency_hist::samples           10                      
system.ruby.Locked_RMW_Write.L1Cache.miss_type_mach_latency_hist::mean            1                      
system.ruby.Locked_RMW_Write.L1Cache.miss_type_mach_latency_hist::gmean            1                      
system.ruby.Locked_RMW_Write.L1Cache.miss_type_mach_latency_hist |           0      0.00%      0.00% |          10    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
system.ruby.Locked_RMW_Write.L1Cache.miss_type_mach_latency_hist::total           10                      
system.ruby.SQC_Controller.Fetch                   86      0.00%      0.00%
system.ruby.SQC_Controller.Data                     5      0.00%      0.00%
system.ruby.SQC_Controller.I.Fetch                  5      0.00%      0.00%
system.ruby.SQC_Controller.I.Data                   5      0.00%      0.00%
system.ruby.SQC_Controller.V.Fetch                 81      0.00%      0.00%
system.ruby.TCC_Controller.RdBlk                    9      0.00%      0.00%
system.ruby.TCC_Controller.WrVicBlk                16      0.00%      0.00%
system.ruby.TCC_Controller.Atomic                   2      0.00%      0.00%
system.ruby.TCC_Controller.AtomicDone               1      0.00%      0.00%
system.ruby.TCC_Controller.Data                     9      0.00%      0.00%
system.ruby.TCC_Controller.PrbInv                   1      0.00%      0.00%
system.ruby.TCC_Controller.WBAck                   16      0.00%      0.00%
system.ruby.TCC_Controller.V.PrbInv                 1      0.00%      0.00%
system.ruby.TCC_Controller.I.RdBlk                  7      0.00%      0.00%
system.ruby.TCC_Controller.I.WrVicBlk              16      0.00%      0.00%
system.ruby.TCC_Controller.I.Atomic                 1      0.00%      0.00%
system.ruby.TCC_Controller.I.WBAck                 16      0.00%      0.00%
system.ruby.TCC_Controller.IV.RdBlk                 2      0.00%      0.00%
system.ruby.TCC_Controller.IV.Data                  7      0.00%      0.00%
system.ruby.TCC_Controller.A.Atomic                 1      0.00%      0.00%
system.ruby.TCC_Controller.A.AtomicDone             1      0.00%      0.00%
system.ruby.TCC_Controller.A.Data                   2      0.00%      0.00%
system.ruby.TCP_Controller.Load          |           5     50.00%     50.00% |           5     50.00%    100.00%
system.ruby.TCP_Controller.Load::total             10                      
system.ruby.TCP_Controller.StoreThrough  |           8     50.00%     50.00% |           8     50.00%    100.00%
system.ruby.TCP_Controller.StoreThrough::total           16                      
system.ruby.TCP_Controller.Atomic        |           1     50.00%     50.00% |           1     50.00%    100.00%
system.ruby.TCP_Controller.Atomic::total            2                      
system.ruby.TCP_Controller.Flush         |         768     50.00%     50.00% |         768     50.00%    100.00%
system.ruby.TCP_Controller.Flush::total          1536                      
system.ruby.TCP_Controller.Evict         |         512     50.00%     50.00% |         512     50.00%    100.00%
system.ruby.TCP_Controller.Evict::total          1024                      
system.ruby.TCP_Controller.TCC_Ack       |           3     50.00%     50.00% |           3     50.00%    100.00%
system.ruby.TCP_Controller.TCC_Ack::total            6                      
system.ruby.TCP_Controller.TCC_AckWB     |           8     50.00%     50.00% |           8     50.00%    100.00%
system.ruby.TCP_Controller.TCC_AckWB::total           16                      
system.ruby.TCP_Controller.I.Load        |           2     50.00%     50.00% |           2     50.00%    100.00%
system.ruby.TCP_Controller.I.Load::total            4                      
system.ruby.TCP_Controller.I.StoreThrough |           8     50.00%     50.00% |           8     50.00%    100.00%
system.ruby.TCP_Controller.I.StoreThrough::total           16                      
system.ruby.TCP_Controller.I.Atomic      |           1     50.00%     50.00% |           1     50.00%    100.00%
system.ruby.TCP_Controller.I.Atomic::total            2                      
system.ruby.TCP_Controller.I.Flush       |         766     50.00%     50.00% |         766     50.00%    100.00%
system.ruby.TCP_Controller.I.Flush::total         1532                      
system.ruby.TCP_Controller.I.Evict       |         510     50.00%     50.00% |         510     50.00%    100.00%
system.ruby.TCP_Controller.I.Evict::total         1020                      
system.ruby.TCP_Controller.I.TCC_Ack     |           2     50.00%     50.00% |           2     50.00%    100.00%
system.ruby.TCP_Controller.I.TCC_Ack::total            4                      
system.ruby.TCP_Controller.I.TCC_AckWB   |           8     50.00%     50.00% |           8     50.00%    100.00%
system.ruby.TCP_Controller.I.TCC_AckWB::total           16                      
system.ruby.TCP_Controller.V.Load        |           3     50.00%     50.00% |           3     50.00%    100.00%
system.ruby.TCP_Controller.V.Load::total            6                      
system.ruby.TCP_Controller.V.Flush       |           2     50.00%     50.00% |           2     50.00%    100.00%
system.ruby.TCP_Controller.V.Flush::total            4                      
system.ruby.TCP_Controller.V.Evict       |           2     50.00%     50.00% |           2     50.00%    100.00%
system.ruby.TCP_Controller.V.Evict::total            4                      
system.ruby.TCP_Controller.A.TCC_Ack     |           1     50.00%     50.00% |           1     50.00%    100.00%
system.ruby.TCP_Controller.A.TCC_Ack::total            2                      

---------- End Simulation Statistics   ----------