111308Santhony.gutierrez@amd.com 211308Santhony.gutierrez@amd.com---------- Begin Simulation Statistics ---------- 311308Santhony.gutierrez@amd.comsim_seconds 0.000314 # Number of seconds simulated 411308Santhony.gutierrez@amd.comsim_ticks 314399500 # Number of ticks simulated 511308Santhony.gutierrez@amd.comfinal_tick 314399500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 611308Santhony.gutierrez@amd.comsim_freq 1000000000000 # Frequency of simulated ticks 711308Santhony.gutierrez@amd.comhost_inst_rate 59851 # Simulator instruction rate (inst/s) 811308Santhony.gutierrez@amd.comhost_op_rate 123077 # Simulator op (including micro ops) rate (op/s) 911308Santhony.gutierrez@amd.comhost_tick_rate 280996968 # Simulator tick rate (ticks/s) 1011308Santhony.gutierrez@amd.comhost_mem_usage 1296852 # Number of bytes of host memory used 1111308Santhony.gutierrez@amd.comhost_seconds 1.12 # Real time elapsed on the host 1211308Santhony.gutierrez@amd.comsim_insts 66963 # Number of instructions simulated 1311308Santhony.gutierrez@amd.comsim_ops 137705 # Number of ops (including micro ops) simulated 1411308Santhony.gutierrez@amd.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1511308Santhony.gutierrez@amd.comsystem.clk_domain.clock 1000 # Clock period in ticks 1611308Santhony.gutierrez@amd.comsystem.mem_ctrls.bytes_read::ruby.dir_cntrl0 99840 # Number of bytes read from this memory 1711308Santhony.gutierrez@amd.comsystem.mem_ctrls.bytes_read::total 99840 # Number of bytes read from this memory 1811308Santhony.gutierrez@amd.comsystem.mem_ctrls.num_reads::ruby.dir_cntrl0 1560 # Number of read requests responded to by this memory 1911308Santhony.gutierrez@amd.comsystem.mem_ctrls.num_reads::total 1560 # Number of read requests responded to by this memory 2011308Santhony.gutierrez@amd.comsystem.mem_ctrls.bw_read::ruby.dir_cntrl0 317557757 # Total read bandwidth from this memory (bytes/s) 2111308Santhony.gutierrez@amd.comsystem.mem_ctrls.bw_read::total 317557757 # Total read bandwidth from this memory (bytes/s) 2211308Santhony.gutierrez@amd.comsystem.mem_ctrls.bw_total::ruby.dir_cntrl0 317557757 # Total bandwidth to/from this memory (bytes/s) 2311308Santhony.gutierrez@amd.comsystem.mem_ctrls.bw_total::total 317557757 # Total bandwidth to/from this memory (bytes/s) 2411308Santhony.gutierrez@amd.comsystem.mem_ctrls.readReqs 1560 # Number of read requests accepted 2511308Santhony.gutierrez@amd.comsystem.mem_ctrls.writeReqs 0 # Number of write requests accepted 2611308Santhony.gutierrez@amd.comsystem.mem_ctrls.readBursts 1560 # Number of DRAM read bursts, including those serviced by the write queue 2711308Santhony.gutierrez@amd.comsystem.mem_ctrls.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 2811308Santhony.gutierrez@amd.comsystem.mem_ctrls.bytesReadDRAM 99840 # Total number of bytes read from DRAM 2911308Santhony.gutierrez@amd.comsystem.mem_ctrls.bytesReadWrQ 0 # Total number of bytes read from write queue 3011308Santhony.gutierrez@amd.comsystem.mem_ctrls.bytesWritten 0 # Total number of bytes written to DRAM 3111308Santhony.gutierrez@amd.comsystem.mem_ctrls.bytesReadSys 99840 # Total read bytes from the system interface side 3211308Santhony.gutierrez@amd.comsystem.mem_ctrls.bytesWrittenSys 0 # Total written bytes from the system interface side 3311308Santhony.gutierrez@amd.comsystem.mem_ctrls.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 3411308Santhony.gutierrez@amd.comsystem.mem_ctrls.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 3511308Santhony.gutierrez@amd.comsystem.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 3611308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankRdBursts::0 122 # Per bank write bursts 3711308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankRdBursts::1 192 # Per bank write bursts 3811308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankRdBursts::2 93 # Per bank write bursts 3911308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankRdBursts::3 44 # Per bank write bursts 4011308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankRdBursts::4 61 # Per bank write bursts 4111308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankRdBursts::5 79 # Per bank write bursts 4211308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankRdBursts::6 52 # Per bank write bursts 4311308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankRdBursts::7 42 # Per bank write bursts 4411308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankRdBursts::8 54 # Per bank write bursts 4511308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankRdBursts::9 56 # Per bank write bursts 4611308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankRdBursts::10 182 # Per bank write bursts 4711308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankRdBursts::11 90 # Per bank write bursts 4811308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankRdBursts::12 223 # Per bank write bursts 4911308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankRdBursts::13 125 # Per bank write bursts 5011308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankRdBursts::14 51 # Per bank write bursts 5111308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankRdBursts::15 94 # Per bank write bursts 5211308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts 5311308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts 5411308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts 5511308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts 5611308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts 5711308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts 5811308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts 5911308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts 6011308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts 6111308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts 6211308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankWrBursts::10 0 # Per bank write bursts 6311308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts 6411308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts 6511308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankWrBursts::13 0 # Per bank write bursts 6611308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankWrBursts::14 0 # Per bank write bursts 6711308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts 6811308Santhony.gutierrez@amd.comsystem.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry 6911308Santhony.gutierrez@amd.comsystem.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry 7011308Santhony.gutierrez@amd.comsystem.mem_ctrls.totGap 314257000 # Total gap between requests 7111308Santhony.gutierrez@amd.comsystem.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) 7211308Santhony.gutierrez@amd.comsystem.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) 7311308Santhony.gutierrez@amd.comsystem.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) 7411308Santhony.gutierrez@amd.comsystem.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) 7511308Santhony.gutierrez@amd.comsystem.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) 7611308Santhony.gutierrez@amd.comsystem.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) 7711308Santhony.gutierrez@amd.comsystem.mem_ctrls.readPktSize::6 1560 # Read request sizes (log2) 7811308Santhony.gutierrez@amd.comsystem.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) 7911308Santhony.gutierrez@amd.comsystem.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) 8011308Santhony.gutierrez@amd.comsystem.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) 8111308Santhony.gutierrez@amd.comsystem.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) 8211308Santhony.gutierrez@amd.comsystem.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) 8311308Santhony.gutierrez@amd.comsystem.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) 8411308Santhony.gutierrez@amd.comsystem.mem_ctrls.writePktSize::6 0 # Write request sizes (log2) 8511308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::0 1544 # What read queue length does an incoming req see 8611308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::1 3 # What read queue length does an incoming req see 8711308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::2 2 # What read queue length does an incoming req see 8811308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::3 2 # What read queue length does an incoming req see 8911308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::4 4 # What read queue length does an incoming req see 9011308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::5 3 # What read queue length does an incoming req see 9111308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::6 1 # What read queue length does an incoming req see 9211308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::7 1 # What read queue length does an incoming req see 9311308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see 9411308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see 9511308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see 9611308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see 9711308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see 9811308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see 9911308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see 10011308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see 10111308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see 10211308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see 10311308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see 10411308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see 10511308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see 10611308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see 10711308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see 10811308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see 10911308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see 11011308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see 11111308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see 11211308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see 11311308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see 11411308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see 11511308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see 11611308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see 11711308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::0 0 # What write queue length does an incoming req see 11811308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::1 0 # What write queue length does an incoming req see 11911308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::2 0 # What write queue length does an incoming req see 12011308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::3 0 # What write queue length does an incoming req see 12111308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::4 0 # What write queue length does an incoming req see 12211308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::5 0 # What write queue length does an incoming req see 12311308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::6 0 # What write queue length does an incoming req see 12411308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::7 0 # What write queue length does an incoming req see 12511308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::8 0 # What write queue length does an incoming req see 12611308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::9 0 # What write queue length does an incoming req see 12711308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::10 0 # What write queue length does an incoming req see 12811308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::11 0 # What write queue length does an incoming req see 12911308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::12 0 # What write queue length does an incoming req see 13011308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::13 0 # What write queue length does an incoming req see 13111308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::14 0 # What write queue length does an incoming req see 13211308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::15 0 # What write queue length does an incoming req see 13311308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::16 0 # What write queue length does an incoming req see 13411308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::17 0 # What write queue length does an incoming req see 13511308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::18 0 # What write queue length does an incoming req see 13611308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::19 0 # What write queue length does an incoming req see 13711308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::20 0 # What write queue length does an incoming req see 13811308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::21 0 # What write queue length does an incoming req see 13911308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::22 0 # What write queue length does an incoming req see 14011308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::23 0 # What write queue length does an incoming req see 14111308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::24 0 # What write queue length does an incoming req see 14211308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::25 0 # What write queue length does an incoming req see 14311308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::26 0 # What write queue length does an incoming req see 14411308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::27 0 # What write queue length does an incoming req see 14511308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::28 0 # What write queue length does an incoming req see 14611308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::29 0 # What write queue length does an incoming req see 14711308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::30 0 # What write queue length does an incoming req see 14811308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::31 0 # What write queue length does an incoming req see 14911308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::32 0 # What write queue length does an incoming req see 15011308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see 15111308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see 15211308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see 15311308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see 15411308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see 15511308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see 15611308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see 15711308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see 15811308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see 15911308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see 16011308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see 16111308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see 16211308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see 16311308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see 16411308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see 16511308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see 16611308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see 16711308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see 16811308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see 16911308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see 17011308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see 17111308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see 17211308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see 17311308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see 17411308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see 17511308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see 17611308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see 17711308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see 17811308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see 17911308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see 18011308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see 18111308Santhony.gutierrez@amd.comsystem.mem_ctrls.bytesPerActivate::samples 398 # Bytes accessed per row activation 18211308Santhony.gutierrez@amd.comsystem.mem_ctrls.bytesPerActivate::mean 247.798995 # Bytes accessed per row activation 18311308Santhony.gutierrez@amd.comsystem.mem_ctrls.bytesPerActivate::gmean 164.777646 # Bytes accessed per row activation 18411308Santhony.gutierrez@amd.comsystem.mem_ctrls.bytesPerActivate::stdev 248.151006 # Bytes accessed per row activation 18511308Santhony.gutierrez@amd.comsystem.mem_ctrls.bytesPerActivate::0-127 138 34.67% 34.67% # Bytes accessed per row activation 18611308Santhony.gutierrez@amd.comsystem.mem_ctrls.bytesPerActivate::128-255 115 28.89% 63.57% # Bytes accessed per row activation 18711308Santhony.gutierrez@amd.comsystem.mem_ctrls.bytesPerActivate::256-383 55 13.82% 77.39% # Bytes accessed per row activation 18811308Santhony.gutierrez@amd.comsystem.mem_ctrls.bytesPerActivate::384-511 30 7.54% 84.92% # Bytes accessed per row activation 18911308Santhony.gutierrez@amd.comsystem.mem_ctrls.bytesPerActivate::512-639 19 4.77% 89.70% # Bytes accessed per row activation 19011308Santhony.gutierrez@amd.comsystem.mem_ctrls.bytesPerActivate::640-767 13 3.27% 92.96% # Bytes accessed per row activation 19111308Santhony.gutierrez@amd.comsystem.mem_ctrls.bytesPerActivate::768-895 7 1.76% 94.72% # Bytes accessed per row activation 19211308Santhony.gutierrez@amd.comsystem.mem_ctrls.bytesPerActivate::896-1023 7 1.76% 96.48% # Bytes accessed per row activation 19311308Santhony.gutierrez@amd.comsystem.mem_ctrls.bytesPerActivate::1024-1151 14 3.52% 100.00% # Bytes accessed per row activation 19411308Santhony.gutierrez@amd.comsystem.mem_ctrls.bytesPerActivate::total 398 # Bytes accessed per row activation 19511308Santhony.gutierrez@amd.comsystem.mem_ctrls.totQLat 12586250 # Total ticks spent queuing 19611308Santhony.gutierrez@amd.comsystem.mem_ctrls.totMemAccLat 41836250 # Total ticks spent from burst creation until serviced by the DRAM 19711308Santhony.gutierrez@amd.comsystem.mem_ctrls.totBusLat 7800000 # Total ticks spent in databus transfers 19811308Santhony.gutierrez@amd.comsystem.mem_ctrls.avgQLat 8068.11 # Average queueing delay per DRAM burst 19911308Santhony.gutierrez@amd.comsystem.mem_ctrls.avgBusLat 5000.00 # Average bus latency per DRAM burst 20011308Santhony.gutierrez@amd.comsystem.mem_ctrls.avgMemAccLat 26818.11 # Average memory access latency per DRAM burst 20111308Santhony.gutierrez@amd.comsystem.mem_ctrls.avgRdBW 317.56 # Average DRAM read bandwidth in MiByte/s 20211308Santhony.gutierrez@amd.comsystem.mem_ctrls.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 20311308Santhony.gutierrez@amd.comsystem.mem_ctrls.avgRdBWSys 317.56 # Average system read bandwidth in MiByte/s 20411308Santhony.gutierrez@amd.comsystem.mem_ctrls.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 20511308Santhony.gutierrez@amd.comsystem.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 20611308Santhony.gutierrez@amd.comsystem.mem_ctrls.busUtil 2.48 # Data bus utilization in percentage 20711308Santhony.gutierrez@amd.comsystem.mem_ctrls.busUtilRead 2.48 # Data bus utilization in percentage for reads 20811308Santhony.gutierrez@amd.comsystem.mem_ctrls.busUtilWrite 0.00 # Data bus utilization in percentage for writes 20911308Santhony.gutierrez@amd.comsystem.mem_ctrls.avgRdQLen 1.04 # Average read queue length when enqueuing 21011308Santhony.gutierrez@amd.comsystem.mem_ctrls.avgWrQLen 0.00 # Average write queue length when enqueuing 21111308Santhony.gutierrez@amd.comsystem.mem_ctrls.readRowHits 1157 # Number of row buffer hits during reads 21211308Santhony.gutierrez@amd.comsystem.mem_ctrls.writeRowHits 0 # Number of row buffer hits during writes 21311308Santhony.gutierrez@amd.comsystem.mem_ctrls.readRowHitRate 74.17 # Row buffer hit rate for reads 21411308Santhony.gutierrez@amd.comsystem.mem_ctrls.writeRowHitRate nan # Row buffer hit rate for writes 21511308Santhony.gutierrez@amd.comsystem.mem_ctrls.avgGap 201446.79 # Average gap between requests 21611308Santhony.gutierrez@amd.comsystem.mem_ctrls.pageHitRate 74.17 # Row buffer hit rate, read and write combined 21711308Santhony.gutierrez@amd.comsystem.mem_ctrls_0.actEnergy 1141560 # Energy for activate commands per rank (pJ) 21811308Santhony.gutierrez@amd.comsystem.mem_ctrls_0.preEnergy 622875 # Energy for precharge commands per rank (pJ) 21911308Santhony.gutierrez@amd.comsystem.mem_ctrls_0.readEnergy 5335200 # Energy for read commands per rank (pJ) 22011308Santhony.gutierrez@amd.comsystem.mem_ctrls_0.writeEnergy 0 # Energy for write commands per rank (pJ) 22111308Santhony.gutierrez@amd.comsystem.mem_ctrls_0.refreshEnergy 20342400 # Energy for refresh commands per rank (pJ) 22211308Santhony.gutierrez@amd.comsystem.mem_ctrls_0.actBackEnergy 179243055 # Energy for active background per rank (pJ) 22311308Santhony.gutierrez@amd.comsystem.mem_ctrls_0.preBackEnergy 29795250 # Energy for precharge background per rank (pJ) 22411308Santhony.gutierrez@amd.comsystem.mem_ctrls_0.totalEnergy 236480340 # Total energy per rank (pJ) 22511308Santhony.gutierrez@amd.comsystem.mem_ctrls_0.averagePower 758.654968 # Core power per rank (mW) 22611308Santhony.gutierrez@amd.comsystem.mem_ctrls_0.memoryStateTime::IDLE 51073000 # Time in different power states 22711308Santhony.gutierrez@amd.comsystem.mem_ctrls_0.memoryStateTime::REF 10400000 # Time in different power states 22811308Santhony.gutierrez@amd.comsystem.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states 22911308Santhony.gutierrez@amd.comsystem.mem_ctrls_0.memoryStateTime::ACT 252847000 # Time in different power states 23011308Santhony.gutierrez@amd.comsystem.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states 23111308Santhony.gutierrez@amd.comsystem.mem_ctrls_1.actEnergy 1867320 # Energy for activate commands per rank (pJ) 23211308Santhony.gutierrez@amd.comsystem.mem_ctrls_1.preEnergy 1018875 # Energy for precharge commands per rank (pJ) 23311308Santhony.gutierrez@amd.comsystem.mem_ctrls_1.readEnergy 6684600 # Energy for read commands per rank (pJ) 23411308Santhony.gutierrez@amd.comsystem.mem_ctrls_1.writeEnergy 0 # Energy for write commands per rank (pJ) 23511308Santhony.gutierrez@amd.comsystem.mem_ctrls_1.refreshEnergy 20342400 # Energy for refresh commands per rank (pJ) 23611308Santhony.gutierrez@amd.comsystem.mem_ctrls_1.actBackEnergy 198048780 # Energy for active background per rank (pJ) 23711308Santhony.gutierrez@amd.comsystem.mem_ctrls_1.preBackEnergy 13299000 # Energy for precharge background per rank (pJ) 23811308Santhony.gutierrez@amd.comsystem.mem_ctrls_1.totalEnergy 241260975 # Total energy per rank (pJ) 23911308Santhony.gutierrez@amd.comsystem.mem_ctrls_1.averagePower 773.991771 # Core power per rank (mW) 24011308Santhony.gutierrez@amd.comsystem.mem_ctrls_1.memoryStateTime::IDLE 20941500 # Time in different power states 24111308Santhony.gutierrez@amd.comsystem.mem_ctrls_1.memoryStateTime::REF 10400000 # Time in different power states 24211308Santhony.gutierrez@amd.comsystem.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states 24311308Santhony.gutierrez@amd.comsystem.mem_ctrls_1.memoryStateTime::ACT 280382250 # Time in different power states 24411308Santhony.gutierrez@amd.comsystem.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states 24511308Santhony.gutierrez@amd.comsystem.ruby.clk_domain.clock 500 # Clock period in ticks 24611308Santhony.gutierrez@amd.comsystem.ruby.phys_mem.bytes_read::cpu0.inst 696760 # Number of bytes read from this memory 24711308Santhony.gutierrez@amd.comsystem.ruby.phys_mem.bytes_read::cpu0.data 119832 # Number of bytes read from this memory 24811308Santhony.gutierrez@amd.comsystem.ruby.phys_mem.bytes_read::cpu1.CUs0.ComputeUnit 3280 # Number of bytes read from this memory 24911308Santhony.gutierrez@amd.comsystem.ruby.phys_mem.bytes_read::cpu1.CUs1.ComputeUnit 3280 # Number of bytes read from this memory 25011308Santhony.gutierrez@amd.comsystem.ruby.phys_mem.bytes_read::total 823152 # Number of bytes read from this memory 25111308Santhony.gutierrez@amd.comsystem.ruby.phys_mem.bytes_inst_read::cpu0.inst 696760 # Number of instructions bytes read from this memory 25211308Santhony.gutierrez@amd.comsystem.ruby.phys_mem.bytes_inst_read::cpu1.CUs0.ComputeUnit 2000 # Number of instructions bytes read from this memory 25311308Santhony.gutierrez@amd.comsystem.ruby.phys_mem.bytes_inst_read::cpu1.CUs1.ComputeUnit 2000 # Number of instructions bytes read from this memory 25411308Santhony.gutierrez@amd.comsystem.ruby.phys_mem.bytes_inst_read::total 700760 # Number of instructions bytes read from this memory 25511308Santhony.gutierrez@amd.comsystem.ruby.phys_mem.bytes_written::cpu0.data 72767 # Number of bytes written to this memory 25611308Santhony.gutierrez@amd.comsystem.ruby.phys_mem.bytes_written::cpu1.CUs0.ComputeUnit 256 # Number of bytes written to this memory 25711308Santhony.gutierrez@amd.comsystem.ruby.phys_mem.bytes_written::cpu1.CUs1.ComputeUnit 256 # Number of bytes written to this memory 25811308Santhony.gutierrez@amd.comsystem.ruby.phys_mem.bytes_written::total 73279 # Number of bytes written to this memory 25911308Santhony.gutierrez@amd.comsystem.ruby.phys_mem.num_reads::cpu0.inst 87095 # Number of read requests responded to by this memory 26011308Santhony.gutierrez@amd.comsystem.ruby.phys_mem.num_reads::cpu0.data 16686 # Number of read requests responded to by this memory 26111308Santhony.gutierrez@amd.comsystem.ruby.phys_mem.num_reads::cpu1.CUs0.ComputeUnit 555 # Number of read requests responded to by this memory 26211308Santhony.gutierrez@amd.comsystem.ruby.phys_mem.num_reads::cpu1.CUs1.ComputeUnit 555 # Number of read requests responded to by this memory 26311308Santhony.gutierrez@amd.comsystem.ruby.phys_mem.num_reads::total 104891 # Number of read requests responded to by this memory 26411308Santhony.gutierrez@amd.comsystem.ruby.phys_mem.num_writes::cpu0.data 10422 # Number of write requests responded to by this memory 26511308Santhony.gutierrez@amd.comsystem.ruby.phys_mem.num_writes::cpu1.CUs0.ComputeUnit 256 # Number of write requests responded to by this memory 26611308Santhony.gutierrez@amd.comsystem.ruby.phys_mem.num_writes::cpu1.CUs1.ComputeUnit 256 # Number of write requests responded to by this memory 26711308Santhony.gutierrez@amd.comsystem.ruby.phys_mem.num_writes::total 10934 # Number of write requests responded to by this memory 26811308Santhony.gutierrez@amd.comsystem.ruby.phys_mem.bw_read::cpu0.inst 2216161285 # Total read bandwidth from this memory (bytes/s) 26911308Santhony.gutierrez@amd.comsystem.ruby.phys_mem.bw_read::cpu0.data 381145644 # Total read bandwidth from this memory (bytes/s) 27011308Santhony.gutierrez@amd.comsystem.ruby.phys_mem.bw_read::cpu1.CUs0.ComputeUnit 10432587 # Total read bandwidth from this memory (bytes/s) 27111308Santhony.gutierrez@amd.comsystem.ruby.phys_mem.bw_read::cpu1.CUs1.ComputeUnit 10432587 # Total read bandwidth from this memory (bytes/s) 27211308Santhony.gutierrez@amd.comsystem.ruby.phys_mem.bw_read::total 2618172103 # Total read bandwidth from this memory (bytes/s) 27311308Santhony.gutierrez@amd.comsystem.ruby.phys_mem.bw_inst_read::cpu0.inst 2216161285 # Instruction read bandwidth from this memory (bytes/s) 27411308Santhony.gutierrez@amd.comsystem.ruby.phys_mem.bw_inst_read::cpu1.CUs0.ComputeUnit 6361333 # Instruction read bandwidth from this memory (bytes/s) 27511308Santhony.gutierrez@amd.comsystem.ruby.phys_mem.bw_inst_read::cpu1.CUs1.ComputeUnit 6361333 # Instruction read bandwidth from this memory (bytes/s) 27611308Santhony.gutierrez@amd.comsystem.ruby.phys_mem.bw_inst_read::total 2228883952 # Instruction read bandwidth from this memory (bytes/s) 27711308Santhony.gutierrez@amd.comsystem.ruby.phys_mem.bw_write::cpu0.data 231447569 # Write bandwidth from this memory (bytes/s) 27811308Santhony.gutierrez@amd.comsystem.ruby.phys_mem.bw_write::cpu1.CUs0.ComputeUnit 814251 # Write bandwidth from this memory (bytes/s) 27911308Santhony.gutierrez@amd.comsystem.ruby.phys_mem.bw_write::cpu1.CUs1.ComputeUnit 814251 # Write bandwidth from this memory (bytes/s) 28011308Santhony.gutierrez@amd.comsystem.ruby.phys_mem.bw_write::total 233076070 # Write bandwidth from this memory (bytes/s) 28111308Santhony.gutierrez@amd.comsystem.ruby.phys_mem.bw_total::cpu0.inst 2216161285 # Total bandwidth to/from this memory (bytes/s) 28211308Santhony.gutierrez@amd.comsystem.ruby.phys_mem.bw_total::cpu0.data 612593213 # Total bandwidth to/from this memory (bytes/s) 28311308Santhony.gutierrez@amd.comsystem.ruby.phys_mem.bw_total::cpu1.CUs0.ComputeUnit 11246837 # Total bandwidth to/from this memory (bytes/s) 28411308Santhony.gutierrez@amd.comsystem.ruby.phys_mem.bw_total::cpu1.CUs1.ComputeUnit 11246837 # Total bandwidth to/from this memory (bytes/s) 28511308Santhony.gutierrez@amd.comsystem.ruby.phys_mem.bw_total::total 2851248173 # Total bandwidth to/from this memory (bytes/s) 28611308Santhony.gutierrez@amd.comsystem.cpu0.clk_domain.clock 500 # Clock period in ticks 28711308Santhony.gutierrez@amd.comsystem.cpu0.apic_clk_domain.clock 8000 # Clock period in ticks 28811955Sgabeblack@google.comsystem.cpu0.workload.numSyscalls 21 # Number of system calls 28911308Santhony.gutierrez@amd.comsystem.cpu0.numCycles 628799 # number of cpu cycles simulated 29011308Santhony.gutierrez@amd.comsystem.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 29111308Santhony.gutierrez@amd.comsystem.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 29211308Santhony.gutierrez@amd.comsystem.cpu0.committedInsts 66963 # Number of instructions committed 29311308Santhony.gutierrez@amd.comsystem.cpu0.committedOps 137705 # Number of ops (including micro ops) committed 29411308Santhony.gutierrez@amd.comsystem.cpu0.num_int_alu_accesses 136380 # Number of integer alu accesses 29511308Santhony.gutierrez@amd.comsystem.cpu0.num_fp_alu_accesses 1279 # Number of float alu accesses 29611308Santhony.gutierrez@amd.comsystem.cpu0.num_func_calls 3196 # number of times a function call or return occured 29711308Santhony.gutierrez@amd.comsystem.cpu0.num_conditional_control_insts 12151 # number of instructions that are conditional controls 29811308Santhony.gutierrez@amd.comsystem.cpu0.num_int_insts 136380 # number of integer instructions 29911308Santhony.gutierrez@amd.comsystem.cpu0.num_fp_insts 1279 # number of float instructions 30011308Santhony.gutierrez@amd.comsystem.cpu0.num_int_register_reads 257490 # number of times the integer registers were read 30111308Santhony.gutierrez@amd.comsystem.cpu0.num_int_register_writes 110039 # number of times the integer registers were written 30211308Santhony.gutierrez@amd.comsystem.cpu0.num_fp_register_reads 1981 # number of times the floating registers were read 30311308Santhony.gutierrez@amd.comsystem.cpu0.num_fp_register_writes 981 # number of times the floating registers were written 30411308Santhony.gutierrez@amd.comsystem.cpu0.num_cc_register_reads 78262 # number of times the CC registers were read 30511308Santhony.gutierrez@amd.comsystem.cpu0.num_cc_register_writes 42183 # number of times the CC registers were written 30611308Santhony.gutierrez@amd.comsystem.cpu0.num_mem_refs 27198 # number of memory refs 30711308Santhony.gutierrez@amd.comsystem.cpu0.num_load_insts 16684 # Number of load instructions 30811308Santhony.gutierrez@amd.comsystem.cpu0.num_store_insts 10514 # Number of store instructions 30911308Santhony.gutierrez@amd.comsystem.cpu0.num_idle_cycles 8671.003972 # Number of idle cycles 31011308Santhony.gutierrez@amd.comsystem.cpu0.num_busy_cycles 620127.996028 # Number of busy cycles 31111308Santhony.gutierrez@amd.comsystem.cpu0.not_idle_fraction 0.986210 # Percentage of non-idle cycles 31211308Santhony.gutierrez@amd.comsystem.cpu0.idle_fraction 0.013790 # Percentage of idle cycles 31311308Santhony.gutierrez@amd.comsystem.cpu0.Branches 16199 # Number of branches fetched 31411308Santhony.gutierrez@amd.comsystem.cpu0.op_class::No_OpClass 615 0.45% 0.45% # Class of executed instruction 31511308Santhony.gutierrez@amd.comsystem.cpu0.op_class::IntAlu 108791 79.00% 79.45% # Class of executed instruction 31611308Santhony.gutierrez@amd.comsystem.cpu0.op_class::IntMult 13 0.01% 79.46% # Class of executed instruction 31711308Santhony.gutierrez@amd.comsystem.cpu0.op_class::IntDiv 138 0.10% 79.56% # Class of executed instruction 31811308Santhony.gutierrez@amd.comsystem.cpu0.op_class::FloatAdd 950 0.69% 80.25% # Class of executed instruction 31911308Santhony.gutierrez@amd.comsystem.cpu0.op_class::FloatCmp 0 0.00% 80.25% # Class of executed instruction 32011308Santhony.gutierrez@amd.comsystem.cpu0.op_class::FloatCvt 0 0.00% 80.25% # Class of executed instruction 32111308Santhony.gutierrez@amd.comsystem.cpu0.op_class::FloatMult 0 0.00% 80.25% # Class of executed instruction 32211308Santhony.gutierrez@amd.comsystem.cpu0.op_class::FloatDiv 0 0.00% 80.25% # Class of executed instruction 32311308Santhony.gutierrez@amd.comsystem.cpu0.op_class::FloatSqrt 0 0.00% 80.25% # Class of executed instruction 32411308Santhony.gutierrez@amd.comsystem.cpu0.op_class::SimdAdd 0 0.00% 80.25% # Class of executed instruction 32511308Santhony.gutierrez@amd.comsystem.cpu0.op_class::SimdAddAcc 0 0.00% 80.25% # Class of executed instruction 32611308Santhony.gutierrez@amd.comsystem.cpu0.op_class::SimdAlu 0 0.00% 80.25% # Class of executed instruction 32711308Santhony.gutierrez@amd.comsystem.cpu0.op_class::SimdCmp 0 0.00% 80.25% # Class of executed instruction 32811308Santhony.gutierrez@amd.comsystem.cpu0.op_class::SimdCvt 0 0.00% 80.25% # Class of executed instruction 32911308Santhony.gutierrez@amd.comsystem.cpu0.op_class::SimdMisc 0 0.00% 80.25% # Class of executed instruction 33011308Santhony.gutierrez@amd.comsystem.cpu0.op_class::SimdMult 0 0.00% 80.25% # Class of executed instruction 33111308Santhony.gutierrez@amd.comsystem.cpu0.op_class::SimdMultAcc 0 0.00% 80.25% # Class of executed instruction 33211308Santhony.gutierrez@amd.comsystem.cpu0.op_class::SimdShift 0 0.00% 80.25% # Class of executed instruction 33311308Santhony.gutierrez@amd.comsystem.cpu0.op_class::SimdShiftAcc 0 0.00% 80.25% # Class of executed instruction 33411308Santhony.gutierrez@amd.comsystem.cpu0.op_class::SimdSqrt 0 0.00% 80.25% # Class of executed instruction 33511308Santhony.gutierrez@amd.comsystem.cpu0.op_class::SimdFloatAdd 0 0.00% 80.25% # Class of executed instruction 33611308Santhony.gutierrez@amd.comsystem.cpu0.op_class::SimdFloatAlu 0 0.00% 80.25% # Class of executed instruction 33711308Santhony.gutierrez@amd.comsystem.cpu0.op_class::SimdFloatCmp 0 0.00% 80.25% # Class of executed instruction 33811308Santhony.gutierrez@amd.comsystem.cpu0.op_class::SimdFloatCvt 0 0.00% 80.25% # Class of executed instruction 33911308Santhony.gutierrez@amd.comsystem.cpu0.op_class::SimdFloatDiv 0 0.00% 80.25% # Class of executed instruction 34011308Santhony.gutierrez@amd.comsystem.cpu0.op_class::SimdFloatMisc 0 0.00% 80.25% # Class of executed instruction 34111308Santhony.gutierrez@amd.comsystem.cpu0.op_class::SimdFloatMult 0 0.00% 80.25% # Class of executed instruction 34211308Santhony.gutierrez@amd.comsystem.cpu0.op_class::SimdFloatMultAcc 0 0.00% 80.25% # Class of executed instruction 34311308Santhony.gutierrez@amd.comsystem.cpu0.op_class::SimdFloatSqrt 0 0.00% 80.25% # Class of executed instruction 34411308Santhony.gutierrez@amd.comsystem.cpu0.op_class::MemRead 16684 12.12% 92.36% # Class of executed instruction 34511308Santhony.gutierrez@amd.comsystem.cpu0.op_class::MemWrite 10514 7.64% 100.00% # Class of executed instruction 34611308Santhony.gutierrez@amd.comsystem.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 34711308Santhony.gutierrez@amd.comsystem.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 34811308Santhony.gutierrez@amd.comsystem.cpu0.op_class::total 137705 # Class of executed instruction 34911308Santhony.gutierrez@amd.comsystem.cpu1.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 35011308Santhony.gutierrez@amd.comsystem.cpu1.clk_domain.clock 1000 # Clock period in ticks 35111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts00.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 35211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts00.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 35311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts00.timesBlockedDueRAWDependencies 216 # number of times the wf's instructions are blocked due to RAW dependencies 35411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts00.src_reg_operand_dist::samples 39 # number of executed instructions with N source register operands 35511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts00.src_reg_operand_dist::mean 0.794872 # number of executed instructions with N source register operands 35611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts00.src_reg_operand_dist::stdev 0.863880 # number of executed instructions with N source register operands 35711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts00.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands 35811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts00.src_reg_operand_dist::0-1 28 71.79% 71.79% # number of executed instructions with N source register operands 35911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts00.src_reg_operand_dist::2-3 11 28.21% 100.00% # number of executed instructions with N source register operands 36011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts00.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands 36111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts00.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands 36211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts00.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 36311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts00.src_reg_operand_dist::max_value 2 # number of executed instructions with N source register operands 36411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts00.src_reg_operand_dist::total 39 # number of executed instructions with N source register operands 36511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::samples 39 # number of executed instructions with N destination register operands 36611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::mean 0.589744 # number of executed instructions with N destination register operands 36711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::stdev 0.498310 # number of executed instructions with N destination register operands 36811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N destination register operands 36911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::0-1 39 100.00% 100.00% # number of executed instructions with N destination register operands 37011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::2-3 0 0.00% 100.00% # number of executed instructions with N destination register operands 37111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N destination register operands 37211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 37311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::max_value 1 # number of executed instructions with N destination register operands 37411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::total 39 # number of executed instructions with N destination register operands 37511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts01.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 37611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts01.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 37711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts01.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 37811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts01.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 37911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts01.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 38011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts01.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 38111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts01.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 38211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts01.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 38311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts01.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 38411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts01.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 38511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts01.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 38611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts01.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 38711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts01.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 38811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts01.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 38911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 39011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 39111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 39211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 39311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 39411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 39511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 39611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 39711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 39811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 39911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts02.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 40011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts02.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 40111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts02.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 40211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts02.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 40311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts02.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 40411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts02.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 40511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts02.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 40611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts02.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 40711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts02.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 40811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts02.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 40911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts02.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 41011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts02.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 41111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts02.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 41211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts02.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 41311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 41411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 41511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 41611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 41711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 41811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 41911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 42011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 42111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 42211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 42311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts03.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 42411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts03.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 42511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts03.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 42611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts03.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 42711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts03.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 42811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts03.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 42911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts03.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 43011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts03.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 43111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts03.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 43211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts03.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 43311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts03.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 43411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts03.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 43511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts03.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 43611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts03.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 43711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts03.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 43811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts03.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 43911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts03.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 44011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts03.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 44111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts03.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 44211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts03.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 44311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts03.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 44411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts03.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 44511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts03.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 44611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts03.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 44711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts04.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 44811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts04.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 44911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts04.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 45011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts04.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 45111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts04.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 45211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts04.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 45311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts04.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 45411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts04.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 45511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts04.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 45611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts04.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 45711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts04.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 45811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts04.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 45911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts04.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 46011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts04.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 46111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts04.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 46211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts04.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 46311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts04.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 46411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts04.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 46511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts04.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 46611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts04.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 46711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts04.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 46811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts04.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 46911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts04.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 47011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts04.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 47111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts05.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 47211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts05.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 47311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts05.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 47411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts05.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 47511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts05.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 47611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts05.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 47711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts05.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 47811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts05.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 47911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts05.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 48011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts05.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 48111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts05.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 48211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts05.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 48311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts05.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 48411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts05.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 48511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 48611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 48711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 48811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 48911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 49011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 49111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 49211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 49311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 49411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 49511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts06.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 49611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts06.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 49711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts06.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 49811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts06.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 49911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts06.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 50011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts06.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 50111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts06.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 50211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts06.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 50311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts06.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 50411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts06.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 50511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts06.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 50611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts06.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 50711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts06.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 50811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts06.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 50911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 51011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 51111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 51211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 51311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 51411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 51511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 51611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 51711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 51811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 51911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts07.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 52011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts07.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 52111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts07.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 52211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts07.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 52311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts07.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 52411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts07.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 52511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts07.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 52611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts07.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 52711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts07.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 52811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts07.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 52911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts07.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 53011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts07.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 53111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts07.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 53211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts07.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 53311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 53411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 53511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 53611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 53711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 53811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 53911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 54011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 54111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 54211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 54311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts08.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 54411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts08.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 54511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts08.timesBlockedDueRAWDependencies 195 # number of times the wf's instructions are blocked due to RAW dependencies 54611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts08.src_reg_operand_dist::samples 34 # number of executed instructions with N source register operands 54711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts08.src_reg_operand_dist::mean 0.852941 # number of executed instructions with N source register operands 54811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts08.src_reg_operand_dist::stdev 0.857493 # number of executed instructions with N source register operands 54911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts08.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands 55011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts08.src_reg_operand_dist::0-1 24 70.59% 70.59% # number of executed instructions with N source register operands 55111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts08.src_reg_operand_dist::2-3 10 29.41% 100.00% # number of executed instructions with N source register operands 55211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts08.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands 55311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts08.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands 55411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts08.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 55511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts08.src_reg_operand_dist::max_value 2 # number of executed instructions with N source register operands 55611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts08.src_reg_operand_dist::total 34 # number of executed instructions with N source register operands 55711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::samples 34 # number of executed instructions with N destination register operands 55811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::mean 0.617647 # number of executed instructions with N destination register operands 55911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::stdev 0.493270 # number of executed instructions with N destination register operands 56011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N destination register operands 56111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::0-1 34 100.00% 100.00% # number of executed instructions with N destination register operands 56211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::2-3 0 0.00% 100.00% # number of executed instructions with N destination register operands 56311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N destination register operands 56411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 56511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::max_value 1 # number of executed instructions with N destination register operands 56611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::total 34 # number of executed instructions with N destination register operands 56711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts09.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 56811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts09.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 56911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts09.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 57011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts09.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 57111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts09.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 57211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts09.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 57311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts09.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 57411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts09.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 57511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts09.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 57611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts09.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 57711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts09.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 57811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts09.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 57911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts09.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 58011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts09.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 58111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 58211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 58311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 58411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 58511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 58611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 58711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 58811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 58911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 59011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 59111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts10.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 59211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts10.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 59311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts10.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 59411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts10.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 59511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts10.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 59611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts10.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 59711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts10.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 59811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts10.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 59911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts10.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 60011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts10.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 60111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts10.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 60211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts10.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 60311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts10.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 60411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts10.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 60511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 60611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 60711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 60811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 60911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 61011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 61111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 61211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 61311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 61411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 61511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts11.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 61611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts11.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 61711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts11.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 61811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts11.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 61911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts11.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 62011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts11.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 62111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts11.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 62211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts11.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 62311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts11.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 62411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts11.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 62511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts11.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 62611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts11.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 62711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts11.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 62811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts11.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 62911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 63011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 63111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 63211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 63311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 63411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 63511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 63611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 63711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 63811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 63911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts12.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 64011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts12.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 64111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts12.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 64211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts12.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 64311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts12.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 64411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts12.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 64511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts12.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 64611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts12.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 64711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts12.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 64811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts12.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 64911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts12.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 65011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts12.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 65111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts12.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 65211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts12.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 65311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 65411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 65511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 65611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 65711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 65811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 65911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 66011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 66111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 66211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 66311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts13.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 66411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts13.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 66511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts13.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 66611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts13.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 66711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts13.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 66811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts13.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 66911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts13.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 67011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts13.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 67111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts13.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 67211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts13.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 67311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts13.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 67411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts13.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 67511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts13.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 67611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts13.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 67711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 67811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 67911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 68011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 68111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 68211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 68311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 68411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 68511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 68611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 68711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts14.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 68811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts14.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 68911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts14.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 69011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts14.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 69111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts14.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 69211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts14.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 69311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts14.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 69411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts14.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 69511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts14.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 69611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts14.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 69711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts14.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 69811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts14.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 69911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts14.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 70011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts14.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 70111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 70211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 70311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 70411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 70511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 70611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 70711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 70811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 70911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 71011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 71111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts15.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 71211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts15.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 71311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts15.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 71411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts15.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 71511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts15.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 71611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts15.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 71711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts15.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 71811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts15.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 71911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts15.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 72011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts15.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 72111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts15.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 72211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts15.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 72311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts15.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 72411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts15.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 72511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 72611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 72711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 72811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 72911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 73011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 73111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 73211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 73311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 73411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 73511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts16.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 73611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts16.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 73711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts16.timesBlockedDueRAWDependencies 194 # number of times the wf's instructions are blocked due to RAW dependencies 73811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts16.src_reg_operand_dist::samples 34 # number of executed instructions with N source register operands 73911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts16.src_reg_operand_dist::mean 0.852941 # number of executed instructions with N source register operands 74011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts16.src_reg_operand_dist::stdev 0.857493 # number of executed instructions with N source register operands 74111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts16.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands 74211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts16.src_reg_operand_dist::0-1 24 70.59% 70.59% # number of executed instructions with N source register operands 74311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts16.src_reg_operand_dist::2-3 10 29.41% 100.00% # number of executed instructions with N source register operands 74411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts16.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands 74511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts16.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands 74611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts16.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 74711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts16.src_reg_operand_dist::max_value 2 # number of executed instructions with N source register operands 74811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts16.src_reg_operand_dist::total 34 # number of executed instructions with N source register operands 74911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::samples 34 # number of executed instructions with N destination register operands 75011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::mean 0.617647 # number of executed instructions with N destination register operands 75111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::stdev 0.493270 # number of executed instructions with N destination register operands 75211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N destination register operands 75311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::0-1 34 100.00% 100.00% # number of executed instructions with N destination register operands 75411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::2-3 0 0.00% 100.00% # number of executed instructions with N destination register operands 75511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N destination register operands 75611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 75711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::max_value 1 # number of executed instructions with N destination register operands 75811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::total 34 # number of executed instructions with N destination register operands 75911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts17.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 76011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts17.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 76111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts17.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 76211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts17.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 76311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts17.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 76411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts17.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 76511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts17.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 76611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts17.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 76711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts17.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 76811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts17.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 76911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts17.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 77011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts17.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 77111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts17.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 77211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts17.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 77311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 77411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 77511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 77611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 77711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 77811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 77911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 78011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 78111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 78211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 78311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts18.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 78411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts18.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 78511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts18.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 78611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts18.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 78711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts18.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 78811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts18.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 78911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts18.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 79011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts18.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 79111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts18.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 79211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts18.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 79311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts18.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 79411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts18.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 79511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts18.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 79611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts18.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 79711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 79811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 79911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 80011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 80111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 80211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 80311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 80411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 80511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 80611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 80711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts19.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 80811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts19.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 80911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts19.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 81011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts19.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 81111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts19.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 81211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts19.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 81311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts19.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 81411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts19.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 81511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts19.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 81611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts19.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 81711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts19.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 81811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts19.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 81911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts19.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 82011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts19.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 82111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 82211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 82311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 82411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 82511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 82611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 82711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 82811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 82911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 83011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 83111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts20.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 83211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts20.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 83311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts20.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 83411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts20.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 83511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts20.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 83611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts20.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 83711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts20.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 83811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts20.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 83911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts20.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 84011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts20.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 84111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts20.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 84211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts20.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 84311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts20.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 84411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts20.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 84511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 84611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 84711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 84811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 84911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 85011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 85111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 85211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 85311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 85411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 85511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts21.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 85611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts21.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 85711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts21.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 85811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts21.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 85911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts21.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 86011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts21.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 86111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts21.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 86211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts21.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 86311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts21.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 86411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts21.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 86511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts21.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 86611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts21.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 86711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts21.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 86811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts21.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 86911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 87011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 87111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 87211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 87311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 87411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 87511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 87611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 87711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 87811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 87911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts22.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 88011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts22.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 88111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts22.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 88211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts22.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 88311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts22.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 88411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts22.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 88511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts22.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 88611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts22.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 88711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts22.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 88811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts22.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 88911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts22.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 89011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts22.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 89111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts22.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 89211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts22.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 89311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 89411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 89511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 89611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 89711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 89811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 89911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 90011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 90111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 90211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 90311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts23.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 90411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts23.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 90511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts23.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 90611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts23.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 90711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts23.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 90811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts23.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 90911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts23.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 91011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts23.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 91111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts23.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 91211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts23.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 91311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts23.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 91411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts23.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 91511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts23.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 91611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts23.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 91711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 91811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 91911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 92011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 92111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 92211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 92311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 92411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 92511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 92611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 92711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts24.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 92811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts24.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 92911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts24.timesBlockedDueRAWDependencies 177 # number of times the wf's instructions are blocked due to RAW dependencies 93011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts24.src_reg_operand_dist::samples 34 # number of executed instructions with N source register operands 93111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts24.src_reg_operand_dist::mean 0.852941 # number of executed instructions with N source register operands 93211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts24.src_reg_operand_dist::stdev 0.857493 # number of executed instructions with N source register operands 93311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts24.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands 93411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts24.src_reg_operand_dist::0-1 24 70.59% 70.59% # number of executed instructions with N source register operands 93511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts24.src_reg_operand_dist::2-3 10 29.41% 100.00% # number of executed instructions with N source register operands 93611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts24.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands 93711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts24.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands 93811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts24.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 93911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts24.src_reg_operand_dist::max_value 2 # number of executed instructions with N source register operands 94011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts24.src_reg_operand_dist::total 34 # number of executed instructions with N source register operands 94111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::samples 34 # number of executed instructions with N destination register operands 94211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::mean 0.617647 # number of executed instructions with N destination register operands 94311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::stdev 0.493270 # number of executed instructions with N destination register operands 94411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N destination register operands 94511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::0-1 34 100.00% 100.00% # number of executed instructions with N destination register operands 94611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::2-3 0 0.00% 100.00% # number of executed instructions with N destination register operands 94711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N destination register operands 94811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 94911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::max_value 1 # number of executed instructions with N destination register operands 95011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::total 34 # number of executed instructions with N destination register operands 95111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts25.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 95211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts25.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 95311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts25.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 95411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts25.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 95511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts25.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 95611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts25.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 95711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts25.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 95811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts25.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 95911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts25.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 96011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts25.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 96111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts25.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 96211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts25.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 96311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts25.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 96411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts25.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 96511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 96611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 96711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 96811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 96911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 97011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 97111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 97211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 97311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 97411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 97511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts26.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 97611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts26.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 97711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts26.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 97811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts26.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 97911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts26.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 98011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts26.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 98111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts26.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 98211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts26.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 98311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts26.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 98411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts26.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 98511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts26.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 98611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts26.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 98711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts26.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 98811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts26.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 98911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 99011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 99111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 99211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 99311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 99411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 99511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 99611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 99711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 99811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 99911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts27.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 100011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts27.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 100111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts27.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 100211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts27.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 100311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts27.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 100411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts27.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 100511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts27.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 100611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts27.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 100711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts27.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 100811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts27.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 100911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts27.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 101011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts27.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 101111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts27.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 101211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts27.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 101311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 101411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 101511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 101611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 101711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 101811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 101911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 102011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 102111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 102211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 102311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts28.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 102411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts28.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 102511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts28.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 102611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts28.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 102711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts28.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 102811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts28.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 102911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts28.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 103011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts28.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 103111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts28.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 103211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts28.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 103311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts28.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 103411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts28.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 103511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts28.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 103611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts28.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 103711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 103811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 103911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 104011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 104111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 104211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 104311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 104411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 104511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 104611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 104711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts29.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 104811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts29.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 104911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts29.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 105011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts29.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 105111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts29.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 105211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts29.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 105311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts29.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 105411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts29.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 105511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts29.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 105611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts29.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 105711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts29.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 105811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts29.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 105911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts29.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 106011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts29.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 106111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 106211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 106311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 106411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 106511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 106611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 106711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 106811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 106911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 107011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 107111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts30.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 107211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts30.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 107311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts30.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 107411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts30.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 107511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts30.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 107611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts30.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 107711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts30.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 107811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts30.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 107911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts30.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 108011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts30.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 108111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts30.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 108211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts30.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 108311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts30.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 108411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts30.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 108511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 108611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 108711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 108811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 108911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 109011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 109111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 109211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 109311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 109411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 109511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts31.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 109611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts31.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 109711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts31.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 109811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts31.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 109911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts31.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 110011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts31.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 110111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts31.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 110211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts31.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 110311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts31.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 110411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts31.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 110511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts31.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 110611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts31.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 110711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts31.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 110811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts31.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 110911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 111011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 111111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 111211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 111311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 111411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 111511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 111611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 111711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 111811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 111911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::samples 43 # For each instruction fetch request recieved record how many instructions you got from it 112011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::mean 5.813953 # For each instruction fetch request recieved record how many instructions you got from it 112111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::stdev 2.683777 # For each instruction fetch request recieved record how many instructions you got from it 112211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::underflows 0 0.00% 0.00% # For each instruction fetch request recieved record how many instructions you got from it 112311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::1 0 0.00% 0.00% # For each instruction fetch request recieved record how many instructions you got from it 112411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::2 8 18.60% 18.60% # For each instruction fetch request recieved record how many instructions you got from it 112511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::3 8 18.60% 37.21% # For each instruction fetch request recieved record how many instructions you got from it 112611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::4 1 2.33% 39.53% # For each instruction fetch request recieved record how many instructions you got from it 112711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::5 0 0.00% 39.53% # For each instruction fetch request recieved record how many instructions you got from it 112811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::6 1 2.33% 41.86% # For each instruction fetch request recieved record how many instructions you got from it 112911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::7 0 0.00% 41.86% # For each instruction fetch request recieved record how many instructions you got from it 113011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::8 25 58.14% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 113111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::9 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 113211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::10 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 113311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::11 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 113411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::12 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 113511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::13 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 113611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::14 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 113711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::15 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 113811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::16 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 113911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::17 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 114011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::18 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 114111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::19 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 114211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::20 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 114311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::21 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 114411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::22 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 114511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::23 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 114611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::24 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 114711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::25 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 114811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::26 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 114911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::27 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 115011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::28 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 115111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::29 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 115211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::30 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 115311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::31 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 115411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::32 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 115511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::overflows 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 115611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::min_value 2 # For each instruction fetch request recieved record how many instructions you got from it 115711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::max_value 8 # For each instruction fetch request recieved record how many instructions you got from it 115811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::total 43 # For each instruction fetch request recieved record how many instructions you got from it 115911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.num_cycles_with_no_issue 4663 # number of cycles the CU issues nothing 116011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.num_cycles_with_instr_issued 102 # number of cycles the CU issued at least one instruction 116111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::ALU0 30 # Number of cycles at least one instruction of specific type issued 116211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::ALU1 29 # Number of cycles at least one instruction of specific type issued 116311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::ALU2 29 # Number of cycles at least one instruction of specific type issued 116411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::ALU3 29 # Number of cycles at least one instruction of specific type issued 116511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::GM 18 # Number of cycles at least one instruction of specific type issued 116611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::LM 6 # Number of cycles at least one instruction of specific type issued 116711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU0 1993 # Number of cycles no instruction of specific type issued 116811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU1 288 # Number of cycles no instruction of specific type issued 116911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU2 325 # Number of cycles no instruction of specific type issued 117011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU3 248 # Number of cycles no instruction of specific type issued 117111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::GM 341 # Number of cycles no instruction of specific type issued 117211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::LM 27 # Number of cycles no instruction of specific type issued 117311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.spc::samples 4765 # Execution units active per cycle (Exec unit=SIMD,MemPipe) 117411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.spc::mean 0.029591 # Execution units active per cycle (Exec unit=SIMD,MemPipe) 117511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.spc::stdev 0.214321 # Execution units active per cycle (Exec unit=SIMD,MemPipe) 117611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.spc::underflows 0 0.00% 0.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) 117711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.spc::0 4663 97.86% 97.86% # Execution units active per cycle (Exec unit=SIMD,MemPipe) 117811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.spc::1 65 1.36% 99.22% # Execution units active per cycle (Exec unit=SIMD,MemPipe) 117911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.spc::2 35 0.73% 99.96% # Execution units active per cycle (Exec unit=SIMD,MemPipe) 118011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.spc::3 2 0.04% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) 118111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.spc::4 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) 118211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.spc::5 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) 118311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.spc::6 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) 118411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.spc::overflows 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) 118511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.spc::min_value 0 # Execution units active per cycle (Exec unit=SIMD,MemPipe) 118611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.spc::max_value 3 # Execution units active per cycle (Exec unit=SIMD,MemPipe) 118711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.spc::total 4765 # Execution units active per cycle (Exec unit=SIMD,MemPipe) 118811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.num_transitions_active_to_idle 66 # number of CU transitions from active to idle 118911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.idle_duration_in_cycles::samples 66 # duration of idle periods in cycles 119011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.idle_duration_in_cycles::mean 61.575758 # duration of idle periods in cycles 119111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.idle_duration_in_cycles::stdev 253.572448 # duration of idle periods in cycles 119211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.idle_duration_in_cycles::underflows 0 0.00% 0.00% # duration of idle periods in cycles 119311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.idle_duration_in_cycles::0-4 45 68.18% 68.18% # duration of idle periods in cycles 119411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.idle_duration_in_cycles::5-9 10 15.15% 83.33% # duration of idle periods in cycles 119511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.idle_duration_in_cycles::10-14 0 0.00% 83.33% # duration of idle periods in cycles 119611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.idle_duration_in_cycles::15-19 1 1.52% 84.85% # duration of idle periods in cycles 119711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.idle_duration_in_cycles::20-24 2 3.03% 87.88% # duration of idle periods in cycles 119811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.idle_duration_in_cycles::25-29 1 1.52% 89.39% # duration of idle periods in cycles 119911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.idle_duration_in_cycles::30-34 0 0.00% 89.39% # duration of idle periods in cycles 120011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.idle_duration_in_cycles::35-39 0 0.00% 89.39% # duration of idle periods in cycles 120111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.idle_duration_in_cycles::40-44 0 0.00% 89.39% # duration of idle periods in cycles 120211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.idle_duration_in_cycles::45-49 0 0.00% 89.39% # duration of idle periods in cycles 120311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.idle_duration_in_cycles::50-54 0 0.00% 89.39% # duration of idle periods in cycles 120411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.idle_duration_in_cycles::55-59 0 0.00% 89.39% # duration of idle periods in cycles 120511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.idle_duration_in_cycles::60-64 0 0.00% 89.39% # duration of idle periods in cycles 120611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.idle_duration_in_cycles::65-69 0 0.00% 89.39% # duration of idle periods in cycles 120711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.idle_duration_in_cycles::70-74 0 0.00% 89.39% # duration of idle periods in cycles 120811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.idle_duration_in_cycles::75 0 0.00% 89.39% # duration of idle periods in cycles 120911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.idle_duration_in_cycles::overflows 7 10.61% 100.00% # duration of idle periods in cycles 121011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.idle_duration_in_cycles::min_value 1 # duration of idle periods in cycles 121111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.idle_duration_in_cycles::max_value 1685 # duration of idle periods in cycles 121211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ExecStage.idle_duration_in_cycles::total 66 # duration of idle periods in cycles 121311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.GlobalMemPipeline.load_vrf_bank_conflict_cycles 0 # total number of cycles GM data are delayed before updating the VRF 121411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.LocalMemPipeline.load_vrf_bank_conflict_cycles 0 # total number of cycles LDS data are delayed before updating the VRF 121511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.tlb_requests 769 # number of uncoalesced requests 121611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.tlb_cycles -212991640500 # total number of cycles for all uncoalesced requests 121711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.avg_translation_latency -276972224.317295 # Avg. translation latency for data translations 121811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.TLB_hits_distribution::page_table 769 # TLB hits distribution (0 for page table, x for Lx-TLB 121911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.TLB_hits_distribution::L1_TLB 0 # TLB hits distribution (0 for page table, x for Lx-TLB 122011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.TLB_hits_distribution::L2_TLB 0 # TLB hits distribution (0 for page table, x for Lx-TLB 122111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.TLB_hits_distribution::L3_TLB 0 # TLB hits distribution (0 for page table, x for Lx-TLB 122211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_access_cnt 54 # Total number of LDS bank accesses 122311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::samples 6 # Number of bank conflicts per LDS memory packet 122411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::mean 8 # Number of bank conflicts per LDS memory packet 122511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::stdev 6.196773 # Number of bank conflicts per LDS memory packet 122611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::underflows 0 0.00% 0.00% # Number of bank conflicts per LDS memory packet 122711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::0-1 2 33.33% 33.33% # Number of bank conflicts per LDS memory packet 122811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::2-3 0 0.00% 33.33% # Number of bank conflicts per LDS memory packet 122911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::4-5 0 0.00% 33.33% # Number of bank conflicts per LDS memory packet 123011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::6-7 0 0.00% 33.33% # Number of bank conflicts per LDS memory packet 123111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::8-9 0 0.00% 33.33% # Number of bank conflicts per LDS memory packet 123211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::10-11 0 0.00% 33.33% # Number of bank conflicts per LDS memory packet 123311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::12-13 4 66.67% 100.00% # Number of bank conflicts per LDS memory packet 123411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::14-15 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 123511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::16-17 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 123611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::18-19 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 123711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::20-21 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 123811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::22-23 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 123911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::24-25 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 124011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::26-27 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 124111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::28-29 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 124211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::30-31 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 124311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::32-33 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 124411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::34-35 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 124511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::36-37 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 124611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::38-39 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 124711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::40-41 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 124811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::42-43 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 124911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::44-45 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 125011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::46-47 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 125111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::48-49 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 125211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::50-51 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 125311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::52-53 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 125411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::54-55 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 125511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::56-57 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 125611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::58-59 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 125711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::60-61 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 125811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::62-63 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 125911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::64 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 126011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::overflows 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 126111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::min_value 0 # Number of bank conflicts per LDS memory packet 126211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::max_value 12 # Number of bank conflicts per LDS memory packet 126311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lds_bank_conflicts::total 6 # Number of bank conflicts per LDS memory packet 126411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.page_divergence_dist::samples 17 # pages touched per wf (over all mem. instr.) 126511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.page_divergence_dist::mean 1 # pages touched per wf (over all mem. instr.) 126611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.page_divergence_dist::stdev 0 # pages touched per wf (over all mem. instr.) 126711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.page_divergence_dist::underflows 0 0.00% 0.00% # pages touched per wf (over all mem. instr.) 126811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.page_divergence_dist::1-4 17 100.00% 100.00% # pages touched per wf (over all mem. instr.) 126911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.page_divergence_dist::5-8 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 127011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.page_divergence_dist::9-12 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 127111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.page_divergence_dist::13-16 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 127211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.page_divergence_dist::17-20 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 127311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.page_divergence_dist::21-24 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 127411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.page_divergence_dist::25-28 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 127511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.page_divergence_dist::29-32 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 127611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.page_divergence_dist::33-36 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 127711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.page_divergence_dist::37-40 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 127811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.page_divergence_dist::41-44 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 127911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.page_divergence_dist::45-48 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 128011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.page_divergence_dist::49-52 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 128111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.page_divergence_dist::53-56 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 128211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.page_divergence_dist::57-60 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 128311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.page_divergence_dist::61-64 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 128411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.page_divergence_dist::overflows 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 128511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.page_divergence_dist::min_value 1 # pages touched per wf (over all mem. instr.) 128611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.page_divergence_dist::max_value 1 # pages touched per wf (over all mem. instr.) 128711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.page_divergence_dist::total 17 # pages touched per wf (over all mem. instr.) 128811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.global_mem_instr_cnt 17 # dynamic global memory instructions count 128911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.local_mem_instr_cnt 6 # dynamic local memory intruction count 129011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.wg_blocked_due_lds_alloc 0 # Workgroup blocked due to LDS capacity 129111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.num_instr_executed 141 # number of instructions executed 129211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.inst_exec_rate::samples 141 # Instruction Execution Rate: Number of executed vector instructions per cycle 129311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.inst_exec_rate::mean 81.602837 # Instruction Execution Rate: Number of executed vector instructions per cycle 129411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.inst_exec_rate::stdev 244.924445 # Instruction Execution Rate: Number of executed vector instructions per cycle 129511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.inst_exec_rate::underflows 0 0.00% 0.00% # Instruction Execution Rate: Number of executed vector instructions per cycle 129611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.inst_exec_rate::0-1 1 0.71% 0.71% # Instruction Execution Rate: Number of executed vector instructions per cycle 129711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.inst_exec_rate::2-3 12 8.51% 9.22% # Instruction Execution Rate: Number of executed vector instructions per cycle 129811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.inst_exec_rate::4-5 57 40.43% 49.65% # Instruction Execution Rate: Number of executed vector instructions per cycle 129911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.inst_exec_rate::6-7 28 19.86% 69.50% # Instruction Execution Rate: Number of executed vector instructions per cycle 130011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.inst_exec_rate::8-9 2 1.42% 70.92% # Instruction Execution Rate: Number of executed vector instructions per cycle 130111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.inst_exec_rate::10 1 0.71% 71.63% # Instruction Execution Rate: Number of executed vector instructions per cycle 130211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.inst_exec_rate::overflows 40 28.37% 100.00% # Instruction Execution Rate: Number of executed vector instructions per cycle 130311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.inst_exec_rate::min_value 1 # Instruction Execution Rate: Number of executed vector instructions per cycle 130411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.inst_exec_rate::max_value 1686 # Instruction Execution Rate: Number of executed vector instructions per cycle 130511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.inst_exec_rate::total 141 # Instruction Execution Rate: Number of executed vector instructions per cycle 130611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.num_vec_ops_executed 6769 # number of vec ops executed (e.g. VSZ/inst) 130711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.num_total_cycles 4765 # number of cycles the CU ran for 130811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.vpc 1.420567 # Vector Operations per cycle (this CU only) 130911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.ipc 0.029591 # Instructions per cycle (this CU only) 131011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.warp_execution_dist::samples 141 # number of lanes active per instruction (oval all instructions) 131111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.warp_execution_dist::mean 48.007092 # number of lanes active per instruction (oval all instructions) 131211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.warp_execution_dist::stdev 23.719942 # number of lanes active per instruction (oval all instructions) 131311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.warp_execution_dist::underflows 0 0.00% 0.00% # number of lanes active per instruction (oval all instructions) 131411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.warp_execution_dist::1-4 5 3.55% 3.55% # number of lanes active per instruction (oval all instructions) 131511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.warp_execution_dist::5-8 0 0.00% 3.55% # number of lanes active per instruction (oval all instructions) 131611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.warp_execution_dist::9-12 0 0.00% 3.55% # number of lanes active per instruction (oval all instructions) 131711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.warp_execution_dist::13-16 36 25.53% 29.08% # number of lanes active per instruction (oval all instructions) 131811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.warp_execution_dist::17-20 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) 131911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.warp_execution_dist::21-24 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) 132011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.warp_execution_dist::25-28 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) 132111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.warp_execution_dist::29-32 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) 132211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.warp_execution_dist::33-36 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) 132311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.warp_execution_dist::37-40 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) 132411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.warp_execution_dist::41-44 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) 132511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.warp_execution_dist::45-48 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) 132611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.warp_execution_dist::49-52 8 5.67% 34.75% # number of lanes active per instruction (oval all instructions) 132711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.warp_execution_dist::53-56 0 0.00% 34.75% # number of lanes active per instruction (oval all instructions) 132811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.warp_execution_dist::57-60 0 0.00% 34.75% # number of lanes active per instruction (oval all instructions) 132911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.warp_execution_dist::61-64 92 65.25% 100.00% # number of lanes active per instruction (oval all instructions) 133011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.warp_execution_dist::overflows 0 0.00% 100.00% # number of lanes active per instruction (oval all instructions) 133111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.warp_execution_dist::min_value 1 # number of lanes active per instruction (oval all instructions) 133211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.warp_execution_dist::max_value 64 # number of lanes active per instruction (oval all instructions) 133311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.warp_execution_dist::total 141 # number of lanes active per instruction (oval all instructions) 133411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.gmem_lanes_execution_dist::samples 18 # number of active lanes per global memory instruction 133511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.gmem_lanes_execution_dist::mean 37.833333 # number of active lanes per global memory instruction 133611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.gmem_lanes_execution_dist::stdev 27.064737 # number of active lanes per global memory instruction 133711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.gmem_lanes_execution_dist::underflows 0 0.00% 0.00% # number of active lanes per global memory instruction 133811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.gmem_lanes_execution_dist::1-4 1 5.56% 5.56% # number of active lanes per global memory instruction 133911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.gmem_lanes_execution_dist::5-8 0 0.00% 5.56% # number of active lanes per global memory instruction 134011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.gmem_lanes_execution_dist::9-12 0 0.00% 5.56% # number of active lanes per global memory instruction 134111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.gmem_lanes_execution_dist::13-16 8 44.44% 50.00% # number of active lanes per global memory instruction 134211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.gmem_lanes_execution_dist::17-20 0 0.00% 50.00% # number of active lanes per global memory instruction 134311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.gmem_lanes_execution_dist::21-24 0 0.00% 50.00% # number of active lanes per global memory instruction 134411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.gmem_lanes_execution_dist::25-28 0 0.00% 50.00% # number of active lanes per global memory instruction 134511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.gmem_lanes_execution_dist::29-32 0 0.00% 50.00% # number of active lanes per global memory instruction 134611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.gmem_lanes_execution_dist::33-36 0 0.00% 50.00% # number of active lanes per global memory instruction 134711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.gmem_lanes_execution_dist::37-40 0 0.00% 50.00% # number of active lanes per global memory instruction 134811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.gmem_lanes_execution_dist::41-44 0 0.00% 50.00% # number of active lanes per global memory instruction 134911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.gmem_lanes_execution_dist::45-48 0 0.00% 50.00% # number of active lanes per global memory instruction 135011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.gmem_lanes_execution_dist::49-52 0 0.00% 50.00% # number of active lanes per global memory instruction 135111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.gmem_lanes_execution_dist::53-56 0 0.00% 50.00% # number of active lanes per global memory instruction 135211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.gmem_lanes_execution_dist::57-60 0 0.00% 50.00% # number of active lanes per global memory instruction 135311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.gmem_lanes_execution_dist::61-64 9 50.00% 100.00% # number of active lanes per global memory instruction 135411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.gmem_lanes_execution_dist::overflows 0 0.00% 100.00% # number of active lanes per global memory instruction 135511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.gmem_lanes_execution_dist::min_value 1 # number of active lanes per global memory instruction 135611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.gmem_lanes_execution_dist::max_value 64 # number of active lanes per global memory instruction 135711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.gmem_lanes_execution_dist::total 18 # number of active lanes per global memory instruction 135811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lmem_lanes_execution_dist::samples 6 # number of active lanes per local memory instruction 135911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lmem_lanes_execution_dist::mean 19.500000 # number of active lanes per local memory instruction 136011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lmem_lanes_execution_dist::stdev 22.322634 # number of active lanes per local memory instruction 136111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lmem_lanes_execution_dist::underflows 0 0.00% 0.00% # number of active lanes per local memory instruction 136211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lmem_lanes_execution_dist::1-4 1 16.67% 16.67% # number of active lanes per local memory instruction 136311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lmem_lanes_execution_dist::5-8 0 0.00% 16.67% # number of active lanes per local memory instruction 136411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lmem_lanes_execution_dist::9-12 0 0.00% 16.67% # number of active lanes per local memory instruction 136511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lmem_lanes_execution_dist::13-16 4 66.67% 83.33% # number of active lanes per local memory instruction 136611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lmem_lanes_execution_dist::17-20 0 0.00% 83.33% # number of active lanes per local memory instruction 136711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lmem_lanes_execution_dist::21-24 0 0.00% 83.33% # number of active lanes per local memory instruction 136811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lmem_lanes_execution_dist::25-28 0 0.00% 83.33% # number of active lanes per local memory instruction 136911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lmem_lanes_execution_dist::29-32 0 0.00% 83.33% # number of active lanes per local memory instruction 137011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lmem_lanes_execution_dist::33-36 0 0.00% 83.33% # number of active lanes per local memory instruction 137111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lmem_lanes_execution_dist::37-40 0 0.00% 83.33% # number of active lanes per local memory instruction 137211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lmem_lanes_execution_dist::41-44 0 0.00% 83.33% # number of active lanes per local memory instruction 137311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lmem_lanes_execution_dist::45-48 0 0.00% 83.33% # number of active lanes per local memory instruction 137411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lmem_lanes_execution_dist::49-52 0 0.00% 83.33% # number of active lanes per local memory instruction 137511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lmem_lanes_execution_dist::53-56 0 0.00% 83.33% # number of active lanes per local memory instruction 137611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lmem_lanes_execution_dist::57-60 0 0.00% 83.33% # number of active lanes per local memory instruction 137711308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lmem_lanes_execution_dist::61-64 1 16.67% 100.00% # number of active lanes per local memory instruction 137811308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lmem_lanes_execution_dist::overflows 0 0.00% 100.00% # number of active lanes per local memory instruction 137911308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lmem_lanes_execution_dist::min_value 1 # number of active lanes per local memory instruction 138011308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lmem_lanes_execution_dist::max_value 64 # number of active lanes per local memory instruction 138111308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.lmem_lanes_execution_dist::total 6 # number of active lanes per local memory instruction 138211308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.num_alu_insts_executed 118 # Number of dynamic non-GM memory insts executed 138311308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.times_wg_blocked_due_vgpr_alloc 0 # Number of times WGs are blocked due to VGPR allocation per SIMD 138411308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.num_CAS_ops 0 # number of compare and swap operations 138511308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.num_failed_CAS_ops 0 # number of compare and swap operations that failed 138611308Santhony.gutierrez@amd.comsystem.cpu1.CUs0.num_completed_wfs 4 # number of completed wavefronts 138711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts00.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 138811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts00.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 138911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts00.timesBlockedDueRAWDependencies 216 # number of times the wf's instructions are blocked due to RAW dependencies 139011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts00.src_reg_operand_dist::samples 39 # number of executed instructions with N source register operands 139111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts00.src_reg_operand_dist::mean 0.794872 # number of executed instructions with N source register operands 139211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts00.src_reg_operand_dist::stdev 0.863880 # number of executed instructions with N source register operands 139311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts00.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands 139411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts00.src_reg_operand_dist::0-1 28 71.79% 71.79% # number of executed instructions with N source register operands 139511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts00.src_reg_operand_dist::2-3 11 28.21% 100.00% # number of executed instructions with N source register operands 139611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts00.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands 139711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts00.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands 139811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts00.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 139911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts00.src_reg_operand_dist::max_value 2 # number of executed instructions with N source register operands 140011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts00.src_reg_operand_dist::total 39 # number of executed instructions with N source register operands 140111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::samples 39 # number of executed instructions with N destination register operands 140211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::mean 0.589744 # number of executed instructions with N destination register operands 140311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::stdev 0.498310 # number of executed instructions with N destination register operands 140411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N destination register operands 140511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::0-1 39 100.00% 100.00% # number of executed instructions with N destination register operands 140611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::2-3 0 0.00% 100.00% # number of executed instructions with N destination register operands 140711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N destination register operands 140811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 140911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::max_value 1 # number of executed instructions with N destination register operands 141011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::total 39 # number of executed instructions with N destination register operands 141111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts01.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 141211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts01.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 141311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts01.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 141411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts01.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 141511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts01.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 141611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts01.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 141711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts01.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 141811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts01.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 141911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts01.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 142011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts01.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 142111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts01.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 142211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts01.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 142311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts01.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 142411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts01.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 142511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 142611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 142711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 142811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 142911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 143011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 143111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 143211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 143311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 143411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 143511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts02.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 143611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts02.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 143711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts02.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 143811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts02.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 143911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts02.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 144011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts02.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 144111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts02.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 144211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts02.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 144311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts02.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 144411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts02.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 144511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts02.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 144611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts02.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 144711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts02.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 144811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts02.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 144911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 145011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 145111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 145211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 145311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 145411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 145511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 145611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 145711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 145811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 145911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts03.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 146011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts03.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 146111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts03.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 146211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts03.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 146311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts03.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 146411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts03.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 146511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts03.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 146611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts03.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 146711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts03.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 146811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts03.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 146911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts03.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 147011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts03.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 147111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts03.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 147211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts03.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 147311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 147411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 147511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 147611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 147711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 147811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 147911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 148011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 148111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 148211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 148311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts04.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 148411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts04.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 148511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts04.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 148611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts04.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 148711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts04.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 148811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts04.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 148911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts04.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 149011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts04.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 149111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts04.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 149211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts04.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 149311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts04.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 149411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts04.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 149511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts04.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 149611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts04.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 149711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 149811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 149911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 150011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 150111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 150211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 150311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 150411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 150511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 150611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 150711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts05.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 150811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts05.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 150911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts05.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 151011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts05.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 151111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts05.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 151211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts05.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 151311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts05.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 151411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts05.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 151511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts05.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 151611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts05.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 151711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts05.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 151811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts05.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 151911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts05.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 152011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts05.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 152111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 152211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 152311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 152411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 152511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 152611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 152711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 152811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 152911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 153011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 153111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts06.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 153211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts06.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 153311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts06.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 153411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts06.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 153511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts06.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 153611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts06.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 153711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts06.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 153811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts06.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 153911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts06.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 154011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts06.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 154111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts06.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 154211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts06.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 154311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts06.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 154411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts06.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 154511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 154611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 154711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 154811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 154911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 155011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 155111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 155211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 155311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 155411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 155511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts07.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 155611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts07.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 155711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts07.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 155811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts07.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 155911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts07.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 156011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts07.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 156111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts07.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 156211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts07.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 156311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts07.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 156411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts07.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 156511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts07.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 156611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts07.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 156711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts07.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 156811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts07.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 156911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 157011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 157111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 157211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 157311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 157411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 157511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 157611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 157711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 157811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 157911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts08.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 158011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts08.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 158111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts08.timesBlockedDueRAWDependencies 195 # number of times the wf's instructions are blocked due to RAW dependencies 158211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts08.src_reg_operand_dist::samples 34 # number of executed instructions with N source register operands 158311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts08.src_reg_operand_dist::mean 0.852941 # number of executed instructions with N source register operands 158411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts08.src_reg_operand_dist::stdev 0.857493 # number of executed instructions with N source register operands 158511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts08.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands 158611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts08.src_reg_operand_dist::0-1 24 70.59% 70.59% # number of executed instructions with N source register operands 158711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts08.src_reg_operand_dist::2-3 10 29.41% 100.00% # number of executed instructions with N source register operands 158811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts08.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands 158911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts08.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands 159011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts08.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 159111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts08.src_reg_operand_dist::max_value 2 # number of executed instructions with N source register operands 159211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts08.src_reg_operand_dist::total 34 # number of executed instructions with N source register operands 159311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::samples 34 # number of executed instructions with N destination register operands 159411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::mean 0.617647 # number of executed instructions with N destination register operands 159511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::stdev 0.493270 # number of executed instructions with N destination register operands 159611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N destination register operands 159711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::0-1 34 100.00% 100.00% # number of executed instructions with N destination register operands 159811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::2-3 0 0.00% 100.00% # number of executed instructions with N destination register operands 159911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N destination register operands 160011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 160111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::max_value 1 # number of executed instructions with N destination register operands 160211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::total 34 # number of executed instructions with N destination register operands 160311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts09.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 160411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts09.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 160511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts09.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 160611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts09.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 160711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts09.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 160811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts09.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 160911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts09.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 161011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts09.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 161111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts09.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 161211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts09.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 161311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts09.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 161411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts09.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 161511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts09.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 161611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts09.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 161711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 161811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 161911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 162011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 162111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 162211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 162311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 162411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 162511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 162611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 162711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts10.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 162811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts10.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 162911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts10.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 163011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts10.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 163111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts10.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 163211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts10.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 163311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts10.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 163411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts10.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 163511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts10.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 163611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts10.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 163711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts10.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 163811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts10.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 163911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts10.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 164011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts10.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 164111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 164211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 164311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 164411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 164511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 164611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 164711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 164811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 164911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 165011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 165111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts11.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 165211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts11.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 165311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts11.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 165411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts11.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 165511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts11.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 165611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts11.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 165711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts11.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 165811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts11.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 165911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts11.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 166011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts11.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 166111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts11.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 166211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts11.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 166311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts11.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 166411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts11.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 166511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 166611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 166711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 166811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 166911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 167011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 167111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 167211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 167311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 167411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 167511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts12.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 167611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts12.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 167711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts12.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 167811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts12.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 167911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts12.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 168011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts12.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 168111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts12.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 168211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts12.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 168311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts12.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 168411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts12.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 168511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts12.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 168611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts12.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 168711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts12.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 168811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts12.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 168911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 169011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 169111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 169211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 169311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 169411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 169511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 169611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 169711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 169811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 169911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts13.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 170011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts13.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 170111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts13.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 170211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts13.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 170311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts13.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 170411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts13.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 170511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts13.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 170611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts13.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 170711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts13.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 170811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts13.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 170911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts13.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 171011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts13.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 171111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts13.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 171211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts13.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 171311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 171411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 171511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 171611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 171711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 171811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 171911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 172011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 172111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 172211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 172311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts14.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 172411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts14.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 172511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts14.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 172611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts14.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 172711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts14.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 172811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts14.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 172911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts14.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 173011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts14.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 173111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts14.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 173211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts14.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 173311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts14.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 173411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts14.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 173511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts14.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 173611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts14.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 173711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 173811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 173911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 174011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 174111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 174211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 174311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 174411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 174511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 174611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 174711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts15.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 174811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts15.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 174911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts15.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 175011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts15.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 175111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts15.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 175211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts15.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 175311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts15.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 175411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts15.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 175511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts15.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 175611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts15.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 175711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts15.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 175811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts15.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 175911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts15.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 176011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts15.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 176111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 176211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 176311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 176411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 176511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 176611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 176711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 176811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 176911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 177011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 177111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts16.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 177211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts16.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 177311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts16.timesBlockedDueRAWDependencies 190 # number of times the wf's instructions are blocked due to RAW dependencies 177411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts16.src_reg_operand_dist::samples 34 # number of executed instructions with N source register operands 177511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts16.src_reg_operand_dist::mean 0.852941 # number of executed instructions with N source register operands 177611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts16.src_reg_operand_dist::stdev 0.857493 # number of executed instructions with N source register operands 177711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts16.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands 177811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts16.src_reg_operand_dist::0-1 24 70.59% 70.59% # number of executed instructions with N source register operands 177911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts16.src_reg_operand_dist::2-3 10 29.41% 100.00% # number of executed instructions with N source register operands 178011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts16.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands 178111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts16.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands 178211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts16.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 178311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts16.src_reg_operand_dist::max_value 2 # number of executed instructions with N source register operands 178411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts16.src_reg_operand_dist::total 34 # number of executed instructions with N source register operands 178511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::samples 34 # number of executed instructions with N destination register operands 178611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::mean 0.617647 # number of executed instructions with N destination register operands 178711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::stdev 0.493270 # number of executed instructions with N destination register operands 178811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N destination register operands 178911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::0-1 34 100.00% 100.00% # number of executed instructions with N destination register operands 179011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::2-3 0 0.00% 100.00% # number of executed instructions with N destination register operands 179111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N destination register operands 179211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 179311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::max_value 1 # number of executed instructions with N destination register operands 179411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::total 34 # number of executed instructions with N destination register operands 179511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts17.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 179611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts17.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 179711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts17.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 179811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts17.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 179911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts17.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 180011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts17.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 180111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts17.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 180211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts17.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 180311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts17.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 180411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts17.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 180511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts17.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 180611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts17.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 180711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts17.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 180811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts17.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 180911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 181011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 181111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 181211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 181311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 181411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 181511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 181611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 181711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 181811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 181911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts18.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 182011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts18.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 182111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts18.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 182211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts18.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 182311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts18.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 182411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts18.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 182511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts18.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 182611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts18.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 182711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts18.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 182811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts18.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 182911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts18.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 183011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts18.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 183111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts18.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 183211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts18.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 183311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 183411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 183511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 183611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 183711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 183811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 183911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 184011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 184111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 184211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 184311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts19.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 184411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts19.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 184511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts19.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 184611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts19.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 184711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts19.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 184811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts19.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 184911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts19.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 185011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts19.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 185111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts19.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 185211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts19.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 185311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts19.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 185411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts19.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 185511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts19.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 185611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts19.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 185711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 185811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 185911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 186011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 186111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 186211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 186311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 186411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 186511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 186611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 186711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts20.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 186811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts20.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 186911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts20.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 187011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts20.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 187111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts20.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 187211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts20.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 187311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts20.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 187411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts20.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 187511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts20.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 187611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts20.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 187711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts20.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 187811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts20.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 187911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts20.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 188011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts20.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 188111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 188211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 188311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 188411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 188511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 188611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 188711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 188811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 188911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 189011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 189111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts21.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 189211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts21.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 189311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts21.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 189411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts21.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 189511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts21.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 189611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts21.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 189711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts21.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 189811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts21.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 189911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts21.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 190011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts21.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 190111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts21.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 190211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts21.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 190311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts21.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 190411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts21.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 190511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 190611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 190711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 190811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 190911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 191011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 191111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 191211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 191311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 191411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 191511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts22.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 191611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts22.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 191711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts22.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 191811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts22.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 191911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts22.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 192011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts22.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 192111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts22.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 192211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts22.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 192311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts22.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 192411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts22.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 192511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts22.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 192611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts22.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 192711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts22.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 192811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts22.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 192911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 193011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 193111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 193211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 193311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 193411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 193511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 193611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 193711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 193811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 193911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts23.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 194011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts23.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 194111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts23.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 194211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts23.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 194311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts23.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 194411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts23.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 194511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts23.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 194611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts23.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 194711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts23.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 194811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts23.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 194911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts23.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 195011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts23.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 195111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts23.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 195211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts23.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 195311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 195411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 195511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 195611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 195711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 195811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 195911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 196011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 196111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 196211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 196311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts24.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 196411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts24.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 196511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts24.timesBlockedDueRAWDependencies 176 # number of times the wf's instructions are blocked due to RAW dependencies 196611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts24.src_reg_operand_dist::samples 34 # number of executed instructions with N source register operands 196711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts24.src_reg_operand_dist::mean 0.852941 # number of executed instructions with N source register operands 196811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts24.src_reg_operand_dist::stdev 0.857493 # number of executed instructions with N source register operands 196911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts24.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands 197011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts24.src_reg_operand_dist::0-1 24 70.59% 70.59% # number of executed instructions with N source register operands 197111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts24.src_reg_operand_dist::2-3 10 29.41% 100.00% # number of executed instructions with N source register operands 197211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts24.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands 197311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts24.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands 197411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts24.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 197511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts24.src_reg_operand_dist::max_value 2 # number of executed instructions with N source register operands 197611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts24.src_reg_operand_dist::total 34 # number of executed instructions with N source register operands 197711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::samples 34 # number of executed instructions with N destination register operands 197811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::mean 0.617647 # number of executed instructions with N destination register operands 197911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::stdev 0.493270 # number of executed instructions with N destination register operands 198011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N destination register operands 198111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::0-1 34 100.00% 100.00% # number of executed instructions with N destination register operands 198211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::2-3 0 0.00% 100.00% # number of executed instructions with N destination register operands 198311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N destination register operands 198411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 198511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::max_value 1 # number of executed instructions with N destination register operands 198611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::total 34 # number of executed instructions with N destination register operands 198711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts25.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 198811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts25.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 198911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts25.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 199011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts25.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 199111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts25.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 199211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts25.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 199311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts25.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 199411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts25.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 199511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts25.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 199611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts25.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 199711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts25.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 199811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts25.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 199911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts25.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 200011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts25.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 200111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 200211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 200311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 200411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 200511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 200611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 200711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 200811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 200911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 201011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 201111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts26.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 201211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts26.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 201311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts26.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 201411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts26.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 201511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts26.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 201611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts26.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 201711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts26.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 201811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts26.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 201911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts26.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 202011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts26.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 202111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts26.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 202211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts26.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 202311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts26.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 202411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts26.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 202511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 202611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 202711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 202811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 202911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 203011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 203111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 203211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 203311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 203411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 203511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts27.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 203611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts27.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 203711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts27.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 203811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts27.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 203911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts27.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 204011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts27.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 204111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts27.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 204211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts27.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 204311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts27.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 204411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts27.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 204511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts27.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 204611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts27.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 204711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts27.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 204811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts27.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 204911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 205011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 205111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 205211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 205311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 205411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 205511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 205611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 205711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 205811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 205911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts28.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 206011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts28.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 206111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts28.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 206211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts28.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 206311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts28.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 206411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts28.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 206511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts28.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 206611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts28.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 206711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts28.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 206811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts28.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 206911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts28.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 207011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts28.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 207111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts28.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 207211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts28.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 207311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 207411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 207511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 207611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 207711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 207811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 207911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 208011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 208111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 208211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 208311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts29.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 208411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts29.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 208511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts29.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 208611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts29.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 208711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts29.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 208811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts29.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 208911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts29.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 209011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts29.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 209111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts29.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 209211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts29.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 209311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts29.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 209411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts29.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 209511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts29.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 209611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts29.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 209711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 209811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 209911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 210011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 210111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 210211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 210311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 210411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 210511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 210611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 210711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts30.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 210811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts30.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 210911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts30.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 211011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts30.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 211111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts30.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 211211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts30.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 211311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts30.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 211411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts30.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 211511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts30.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 211611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts30.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 211711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts30.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 211811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts30.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 211911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts30.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 212011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts30.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 212111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 212211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 212311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 212411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 212511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 212611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 212711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 212811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 212911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 213011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 213111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts31.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability 213211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts31.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies 213311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts31.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 213411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts31.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 213511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts31.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands 213611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts31.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 213711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts31.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands 213811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts31.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 213911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts31.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 214011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts31.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands 214111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts31.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands 214211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts31.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands 214311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts31.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands 214411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts31.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands 214511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands 214611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands 214711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 214811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 214911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 215011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands 215111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 215211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands 215311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 215411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands 215511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::samples 43 # For each instruction fetch request recieved record how many instructions you got from it 215611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::mean 5.813953 # For each instruction fetch request recieved record how many instructions you got from it 215711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::stdev 2.683777 # For each instruction fetch request recieved record how many instructions you got from it 215811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::underflows 0 0.00% 0.00% # For each instruction fetch request recieved record how many instructions you got from it 215911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::1 0 0.00% 0.00% # For each instruction fetch request recieved record how many instructions you got from it 216011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::2 8 18.60% 18.60% # For each instruction fetch request recieved record how many instructions you got from it 216111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::3 8 18.60% 37.21% # For each instruction fetch request recieved record how many instructions you got from it 216211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::4 1 2.33% 39.53% # For each instruction fetch request recieved record how many instructions you got from it 216311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::5 0 0.00% 39.53% # For each instruction fetch request recieved record how many instructions you got from it 216411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::6 1 2.33% 41.86% # For each instruction fetch request recieved record how many instructions you got from it 216511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::7 0 0.00% 41.86% # For each instruction fetch request recieved record how many instructions you got from it 216611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::8 25 58.14% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 216711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::9 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 216811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::10 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 216911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::11 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 217011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::12 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 217111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::13 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 217211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::14 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 217311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::15 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 217411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::16 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 217511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::17 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 217611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::18 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 217711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::19 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 217811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::20 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 217911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::21 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 218011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::22 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 218111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::23 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 218211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::24 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 218311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::25 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 218411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::26 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 218511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::27 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 218611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::28 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 218711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::29 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 218811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::30 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 218911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::31 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 219011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::32 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 219111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::overflows 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it 219211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::min_value 2 # For each instruction fetch request recieved record how many instructions you got from it 219311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::max_value 8 # For each instruction fetch request recieved record how many instructions you got from it 219411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::total 43 # For each instruction fetch request recieved record how many instructions you got from it 219511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.num_cycles_with_no_issue 4667 # number of cycles the CU issues nothing 219611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.num_cycles_with_instr_issued 98 # number of cycles the CU issued at least one instruction 219711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::ALU0 30 # Number of cycles at least one instruction of specific type issued 219811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::ALU1 29 # Number of cycles at least one instruction of specific type issued 219911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::ALU2 29 # Number of cycles at least one instruction of specific type issued 220011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::ALU3 29 # Number of cycles at least one instruction of specific type issued 220111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::GM 18 # Number of cycles at least one instruction of specific type issued 220211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::LM 6 # Number of cycles at least one instruction of specific type issued 220311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::ALU0 2052 # Number of cycles no instruction of specific type issued 220411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::ALU1 327 # Number of cycles no instruction of specific type issued 220511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::ALU2 265 # Number of cycles no instruction of specific type issued 220611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::ALU3 285 # Number of cycles no instruction of specific type issued 220711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::GM 341 # Number of cycles no instruction of specific type issued 220811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::LM 32 # Number of cycles no instruction of specific type issued 220911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.spc::samples 4765 # Execution units active per cycle (Exec unit=SIMD,MemPipe) 221011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.spc::mean 0.029591 # Execution units active per cycle (Exec unit=SIMD,MemPipe) 221111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.spc::stdev 0.218204 # Execution units active per cycle (Exec unit=SIMD,MemPipe) 221211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.spc::underflows 0 0.00% 0.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) 221311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.spc::0 4667 97.94% 97.94% # Execution units active per cycle (Exec unit=SIMD,MemPipe) 221411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.spc::1 57 1.20% 99.14% # Execution units active per cycle (Exec unit=SIMD,MemPipe) 221511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.spc::2 39 0.82% 99.96% # Execution units active per cycle (Exec unit=SIMD,MemPipe) 221611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.spc::3 2 0.04% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) 221711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.spc::4 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) 221811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.spc::5 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) 221911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.spc::6 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) 222011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.spc::overflows 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) 222111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.spc::min_value 0 # Execution units active per cycle (Exec unit=SIMD,MemPipe) 222211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.spc::max_value 3 # Execution units active per cycle (Exec unit=SIMD,MemPipe) 222311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.spc::total 4765 # Execution units active per cycle (Exec unit=SIMD,MemPipe) 222411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.num_transitions_active_to_idle 68 # number of CU transitions from active to idle 222511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.idle_duration_in_cycles::samples 68 # duration of idle periods in cycles 222611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.idle_duration_in_cycles::mean 61 # duration of idle periods in cycles 222711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.idle_duration_in_cycles::stdev 257.808908 # duration of idle periods in cycles 222811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.idle_duration_in_cycles::underflows 0 0.00% 0.00% # duration of idle periods in cycles 222911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.idle_duration_in_cycles::0-4 49 72.06% 72.06% # duration of idle periods in cycles 223011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.idle_duration_in_cycles::5-9 8 11.76% 83.82% # duration of idle periods in cycles 223111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.idle_duration_in_cycles::10-14 0 0.00% 83.82% # duration of idle periods in cycles 223211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.idle_duration_in_cycles::15-19 2 2.94% 86.76% # duration of idle periods in cycles 223311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.idle_duration_in_cycles::20-24 1 1.47% 88.24% # duration of idle periods in cycles 223411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.idle_duration_in_cycles::25-29 1 1.47% 89.71% # duration of idle periods in cycles 223511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.idle_duration_in_cycles::30-34 0 0.00% 89.71% # duration of idle periods in cycles 223611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.idle_duration_in_cycles::35-39 0 0.00% 89.71% # duration of idle periods in cycles 223711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.idle_duration_in_cycles::40-44 0 0.00% 89.71% # duration of idle periods in cycles 223811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.idle_duration_in_cycles::45-49 0 0.00% 89.71% # duration of idle periods in cycles 223911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.idle_duration_in_cycles::50-54 0 0.00% 89.71% # duration of idle periods in cycles 224011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.idle_duration_in_cycles::55-59 0 0.00% 89.71% # duration of idle periods in cycles 224111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.idle_duration_in_cycles::60-64 0 0.00% 89.71% # duration of idle periods in cycles 224211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.idle_duration_in_cycles::65-69 0 0.00% 89.71% # duration of idle periods in cycles 224311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.idle_duration_in_cycles::70-74 0 0.00% 89.71% # duration of idle periods in cycles 224411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.idle_duration_in_cycles::75 0 0.00% 89.71% # duration of idle periods in cycles 224511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.idle_duration_in_cycles::overflows 7 10.29% 100.00% # duration of idle periods in cycles 224611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.idle_duration_in_cycles::min_value 1 # duration of idle periods in cycles 224711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.idle_duration_in_cycles::max_value 1764 # duration of idle periods in cycles 224811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ExecStage.idle_duration_in_cycles::total 68 # duration of idle periods in cycles 224911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.GlobalMemPipeline.load_vrf_bank_conflict_cycles 0 # total number of cycles GM data are delayed before updating the VRF 225011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.LocalMemPipeline.load_vrf_bank_conflict_cycles 0 # total number of cycles LDS data are delayed before updating the VRF 225111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.tlb_requests 769 # number of uncoalesced requests 225211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.tlb_cycles -212991830500 # total number of cycles for all uncoalesced requests 225311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.avg_translation_latency -276972471.391417 # Avg. translation latency for data translations 225411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.TLB_hits_distribution::page_table 769 # TLB hits distribution (0 for page table, x for Lx-TLB 225511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.TLB_hits_distribution::L1_TLB 0 # TLB hits distribution (0 for page table, x for Lx-TLB 225611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.TLB_hits_distribution::L2_TLB 0 # TLB hits distribution (0 for page table, x for Lx-TLB 225711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.TLB_hits_distribution::L3_TLB 0 # TLB hits distribution (0 for page table, x for Lx-TLB 225811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_access_cnt 53 # Total number of LDS bank accesses 225911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::samples 6 # Number of bank conflicts per LDS memory packet 226011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::mean 7.833333 # Number of bank conflicts per LDS memory packet 226111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::stdev 6.080022 # Number of bank conflicts per LDS memory packet 226211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::underflows 0 0.00% 0.00% # Number of bank conflicts per LDS memory packet 226311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::0-1 2 33.33% 33.33% # Number of bank conflicts per LDS memory packet 226411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::2-3 0 0.00% 33.33% # Number of bank conflicts per LDS memory packet 226511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::4-5 0 0.00% 33.33% # Number of bank conflicts per LDS memory packet 226611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::6-7 0 0.00% 33.33% # Number of bank conflicts per LDS memory packet 226711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::8-9 0 0.00% 33.33% # Number of bank conflicts per LDS memory packet 226811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::10-11 1 16.67% 50.00% # Number of bank conflicts per LDS memory packet 226911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::12-13 3 50.00% 100.00% # Number of bank conflicts per LDS memory packet 227011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::14-15 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 227111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::16-17 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 227211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::18-19 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 227311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::20-21 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 227411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::22-23 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 227511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::24-25 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 227611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::26-27 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 227711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::28-29 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 227811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::30-31 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 227911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::32-33 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 228011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::34-35 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 228111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::36-37 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 228211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::38-39 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 228311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::40-41 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 228411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::42-43 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 228511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::44-45 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 228611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::46-47 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 228711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::48-49 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 228811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::50-51 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 228911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::52-53 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 229011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::54-55 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 229111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::56-57 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 229211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::58-59 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 229311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::60-61 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 229411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::62-63 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 229511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::64 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 229611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::overflows 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet 229711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::min_value 0 # Number of bank conflicts per LDS memory packet 229811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::max_value 12 # Number of bank conflicts per LDS memory packet 229911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lds_bank_conflicts::total 6 # Number of bank conflicts per LDS memory packet 230011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.page_divergence_dist::samples 17 # pages touched per wf (over all mem. instr.) 230111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.page_divergence_dist::mean 1 # pages touched per wf (over all mem. instr.) 230211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.page_divergence_dist::stdev 0 # pages touched per wf (over all mem. instr.) 230311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.page_divergence_dist::underflows 0 0.00% 0.00% # pages touched per wf (over all mem. instr.) 230411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.page_divergence_dist::1-4 17 100.00% 100.00% # pages touched per wf (over all mem. instr.) 230511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.page_divergence_dist::5-8 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 230611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.page_divergence_dist::9-12 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 230711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.page_divergence_dist::13-16 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 230811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.page_divergence_dist::17-20 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 230911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.page_divergence_dist::21-24 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 231011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.page_divergence_dist::25-28 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 231111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.page_divergence_dist::29-32 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 231211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.page_divergence_dist::33-36 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 231311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.page_divergence_dist::37-40 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 231411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.page_divergence_dist::41-44 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 231511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.page_divergence_dist::45-48 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 231611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.page_divergence_dist::49-52 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 231711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.page_divergence_dist::53-56 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 231811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.page_divergence_dist::57-60 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 231911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.page_divergence_dist::61-64 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 232011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.page_divergence_dist::overflows 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) 232111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.page_divergence_dist::min_value 1 # pages touched per wf (over all mem. instr.) 232211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.page_divergence_dist::max_value 1 # pages touched per wf (over all mem. instr.) 232311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.page_divergence_dist::total 17 # pages touched per wf (over all mem. instr.) 232411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.global_mem_instr_cnt 17 # dynamic global memory instructions count 232511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.local_mem_instr_cnt 6 # dynamic local memory intruction count 232611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.wg_blocked_due_lds_alloc 0 # Workgroup blocked due to LDS capacity 232711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.num_instr_executed 141 # number of instructions executed 232811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.inst_exec_rate::samples 141 # Instruction Execution Rate: Number of executed vector instructions per cycle 232911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.inst_exec_rate::mean 82.212766 # Instruction Execution Rate: Number of executed vector instructions per cycle 233011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.inst_exec_rate::stdev 248.914352 # Instruction Execution Rate: Number of executed vector instructions per cycle 233111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.inst_exec_rate::underflows 0 0.00% 0.00% # Instruction Execution Rate: Number of executed vector instructions per cycle 233211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.inst_exec_rate::0-1 1 0.71% 0.71% # Instruction Execution Rate: Number of executed vector instructions per cycle 233311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.inst_exec_rate::2-3 12 8.51% 9.22% # Instruction Execution Rate: Number of executed vector instructions per cycle 233411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.inst_exec_rate::4-5 53 37.59% 46.81% # Instruction Execution Rate: Number of executed vector instructions per cycle 233511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.inst_exec_rate::6-7 28 19.86% 66.67% # Instruction Execution Rate: Number of executed vector instructions per cycle 233611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.inst_exec_rate::8-9 5 3.55% 70.21% # Instruction Execution Rate: Number of executed vector instructions per cycle 233711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.inst_exec_rate::10 1 0.71% 70.92% # Instruction Execution Rate: Number of executed vector instructions per cycle 233811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.inst_exec_rate::overflows 41 29.08% 100.00% # Instruction Execution Rate: Number of executed vector instructions per cycle 233911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.inst_exec_rate::min_value 1 # Instruction Execution Rate: Number of executed vector instructions per cycle 234011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.inst_exec_rate::max_value 1765 # Instruction Execution Rate: Number of executed vector instructions per cycle 234111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.inst_exec_rate::total 141 # Instruction Execution Rate: Number of executed vector instructions per cycle 234211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.num_vec_ops_executed 6762 # number of vec ops executed (e.g. VSZ/inst) 234311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.num_total_cycles 4765 # number of cycles the CU ran for 234411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.vpc 1.419098 # Vector Operations per cycle (this CU only) 234511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.ipc 0.029591 # Instructions per cycle (this CU only) 234611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.warp_execution_dist::samples 141 # number of lanes active per instruction (oval all instructions) 234711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.warp_execution_dist::mean 47.957447 # number of lanes active per instruction (oval all instructions) 234811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.warp_execution_dist::stdev 23.818022 # number of lanes active per instruction (oval all instructions) 234911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.warp_execution_dist::underflows 0 0.00% 0.00% # number of lanes active per instruction (oval all instructions) 235011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.warp_execution_dist::1-4 5 3.55% 3.55% # number of lanes active per instruction (oval all instructions) 235111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.warp_execution_dist::5-8 0 0.00% 3.55% # number of lanes active per instruction (oval all instructions) 235211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.warp_execution_dist::9-12 9 6.38% 9.93% # number of lanes active per instruction (oval all instructions) 235311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.warp_execution_dist::13-16 27 19.15% 29.08% # number of lanes active per instruction (oval all instructions) 235411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.warp_execution_dist::17-20 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) 235511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.warp_execution_dist::21-24 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) 235611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.warp_execution_dist::25-28 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) 235711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.warp_execution_dist::29-32 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) 235811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.warp_execution_dist::33-36 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) 235911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.warp_execution_dist::37-40 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) 236011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.warp_execution_dist::41-44 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) 236111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.warp_execution_dist::45-48 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) 236211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.warp_execution_dist::49-52 8 5.67% 34.75% # number of lanes active per instruction (oval all instructions) 236311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.warp_execution_dist::53-56 0 0.00% 34.75% # number of lanes active per instruction (oval all instructions) 236411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.warp_execution_dist::57-60 0 0.00% 34.75% # number of lanes active per instruction (oval all instructions) 236511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.warp_execution_dist::61-64 92 65.25% 100.00% # number of lanes active per instruction (oval all instructions) 236611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.warp_execution_dist::overflows 0 0.00% 100.00% # number of lanes active per instruction (oval all instructions) 236711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.warp_execution_dist::min_value 1 # number of lanes active per instruction (oval all instructions) 236811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.warp_execution_dist::max_value 64 # number of lanes active per instruction (oval all instructions) 236911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.warp_execution_dist::total 141 # number of lanes active per instruction (oval all instructions) 237011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.gmem_lanes_execution_dist::samples 18 # number of active lanes per global memory instruction 237111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.gmem_lanes_execution_dist::mean 37.722222 # number of active lanes per global memory instruction 237211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.gmem_lanes_execution_dist::stdev 27.174394 # number of active lanes per global memory instruction 237311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.gmem_lanes_execution_dist::underflows 0 0.00% 0.00% # number of active lanes per global memory instruction 237411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.gmem_lanes_execution_dist::1-4 1 5.56% 5.56% # number of active lanes per global memory instruction 237511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.gmem_lanes_execution_dist::5-8 0 0.00% 5.56% # number of active lanes per global memory instruction 237611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.gmem_lanes_execution_dist::9-12 2 11.11% 16.67% # number of active lanes per global memory instruction 237711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.gmem_lanes_execution_dist::13-16 6 33.33% 50.00% # number of active lanes per global memory instruction 237811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.gmem_lanes_execution_dist::17-20 0 0.00% 50.00% # number of active lanes per global memory instruction 237911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.gmem_lanes_execution_dist::21-24 0 0.00% 50.00% # number of active lanes per global memory instruction 238011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.gmem_lanes_execution_dist::25-28 0 0.00% 50.00% # number of active lanes per global memory instruction 238111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.gmem_lanes_execution_dist::29-32 0 0.00% 50.00% # number of active lanes per global memory instruction 238211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.gmem_lanes_execution_dist::33-36 0 0.00% 50.00% # number of active lanes per global memory instruction 238311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.gmem_lanes_execution_dist::37-40 0 0.00% 50.00% # number of active lanes per global memory instruction 238411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.gmem_lanes_execution_dist::41-44 0 0.00% 50.00% # number of active lanes per global memory instruction 238511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.gmem_lanes_execution_dist::45-48 0 0.00% 50.00% # number of active lanes per global memory instruction 238611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.gmem_lanes_execution_dist::49-52 0 0.00% 50.00% # number of active lanes per global memory instruction 238711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.gmem_lanes_execution_dist::53-56 0 0.00% 50.00% # number of active lanes per global memory instruction 238811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.gmem_lanes_execution_dist::57-60 0 0.00% 50.00% # number of active lanes per global memory instruction 238911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.gmem_lanes_execution_dist::61-64 9 50.00% 100.00% # number of active lanes per global memory instruction 239011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.gmem_lanes_execution_dist::overflows 0 0.00% 100.00% # number of active lanes per global memory instruction 239111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.gmem_lanes_execution_dist::min_value 1 # number of active lanes per global memory instruction 239211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.gmem_lanes_execution_dist::max_value 64 # number of active lanes per global memory instruction 239311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.gmem_lanes_execution_dist::total 18 # number of active lanes per global memory instruction 239411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lmem_lanes_execution_dist::samples 6 # number of active lanes per local memory instruction 239511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lmem_lanes_execution_dist::mean 19.333333 # number of active lanes per local memory instruction 239611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lmem_lanes_execution_dist::stdev 22.384518 # number of active lanes per local memory instruction 239711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lmem_lanes_execution_dist::underflows 0 0.00% 0.00% # number of active lanes per local memory instruction 239811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lmem_lanes_execution_dist::1-4 1 16.67% 16.67% # number of active lanes per local memory instruction 239911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lmem_lanes_execution_dist::5-8 0 0.00% 16.67% # number of active lanes per local memory instruction 240011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lmem_lanes_execution_dist::9-12 1 16.67% 33.33% # number of active lanes per local memory instruction 240111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lmem_lanes_execution_dist::13-16 3 50.00% 83.33% # number of active lanes per local memory instruction 240211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lmem_lanes_execution_dist::17-20 0 0.00% 83.33% # number of active lanes per local memory instruction 240311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lmem_lanes_execution_dist::21-24 0 0.00% 83.33% # number of active lanes per local memory instruction 240411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lmem_lanes_execution_dist::25-28 0 0.00% 83.33% # number of active lanes per local memory instruction 240511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lmem_lanes_execution_dist::29-32 0 0.00% 83.33% # number of active lanes per local memory instruction 240611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lmem_lanes_execution_dist::33-36 0 0.00% 83.33% # number of active lanes per local memory instruction 240711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lmem_lanes_execution_dist::37-40 0 0.00% 83.33% # number of active lanes per local memory instruction 240811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lmem_lanes_execution_dist::41-44 0 0.00% 83.33% # number of active lanes per local memory instruction 240911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lmem_lanes_execution_dist::45-48 0 0.00% 83.33% # number of active lanes per local memory instruction 241011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lmem_lanes_execution_dist::49-52 0 0.00% 83.33% # number of active lanes per local memory instruction 241111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lmem_lanes_execution_dist::53-56 0 0.00% 83.33% # number of active lanes per local memory instruction 241211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lmem_lanes_execution_dist::57-60 0 0.00% 83.33% # number of active lanes per local memory instruction 241311308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lmem_lanes_execution_dist::61-64 1 16.67% 100.00% # number of active lanes per local memory instruction 241411308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lmem_lanes_execution_dist::overflows 0 0.00% 100.00% # number of active lanes per local memory instruction 241511308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lmem_lanes_execution_dist::min_value 1 # number of active lanes per local memory instruction 241611308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lmem_lanes_execution_dist::max_value 64 # number of active lanes per local memory instruction 241711308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.lmem_lanes_execution_dist::total 6 # number of active lanes per local memory instruction 241811308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.num_alu_insts_executed 118 # Number of dynamic non-GM memory insts executed 241911308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.times_wg_blocked_due_vgpr_alloc 0 # Number of times WGs are blocked due to VGPR allocation per SIMD 242011308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.num_CAS_ops 0 # number of compare and swap operations 242111308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.num_failed_CAS_ops 0 # number of compare and swap operations that failed 242211308Santhony.gutierrez@amd.comsystem.cpu1.CUs1.num_completed_wfs 4 # number of completed wavefronts 242311308Santhony.gutierrez@amd.comsystem.cpu2.num_kernel_launched 1 # number of kernel launched 242411308Santhony.gutierrez@amd.comsystem.dispatcher_coalescer.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 242511308Santhony.gutierrez@amd.comsystem.dispatcher_coalescer.clk_domain.clock 1000 # Clock period in ticks 242611308Santhony.gutierrez@amd.comsystem.dispatcher_coalescer.uncoalesced_accesses 0 # Number of uncoalesced TLB accesses 242711308Santhony.gutierrez@amd.comsystem.dispatcher_coalescer.coalesced_accesses 0 # Number of coalesced TLB accesses 242811308Santhony.gutierrez@amd.comsystem.dispatcher_coalescer.queuing_cycles 0 # Number of cycles spent in queue 242911308Santhony.gutierrez@amd.comsystem.dispatcher_coalescer.local_queuing_cycles 0 # Number of cycles spent in queue for all incoming reqs 243011308Santhony.gutierrez@amd.comsystem.dispatcher_coalescer.local_latency nan # Avg. latency over all incoming pkts 243111308Santhony.gutierrez@amd.comsystem.dispatcher_tlb.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 243211308Santhony.gutierrez@amd.comsystem.dispatcher_tlb.clk_domain.clock 1000 # Clock period in ticks 243311308Santhony.gutierrez@amd.comsystem.dispatcher_tlb.local_TLB_accesses 0 # Number of TLB accesses 243411308Santhony.gutierrez@amd.comsystem.dispatcher_tlb.local_TLB_hits 0 # Number of TLB hits 243511308Santhony.gutierrez@amd.comsystem.dispatcher_tlb.local_TLB_misses 0 # Number of TLB misses 243611308Santhony.gutierrez@amd.comsystem.dispatcher_tlb.local_TLB_miss_rate nan # TLB miss rate 243711308Santhony.gutierrez@amd.comsystem.dispatcher_tlb.global_TLB_accesses 0 # Number of TLB accesses 243811308Santhony.gutierrez@amd.comsystem.dispatcher_tlb.global_TLB_hits 0 # Number of TLB hits 243911308Santhony.gutierrez@amd.comsystem.dispatcher_tlb.global_TLB_misses 0 # Number of TLB misses 244011308Santhony.gutierrez@amd.comsystem.dispatcher_tlb.global_TLB_miss_rate nan # TLB miss rate 244111308Santhony.gutierrez@amd.comsystem.dispatcher_tlb.access_cycles 0 # Cycles spent accessing this TLB level 244211308Santhony.gutierrez@amd.comsystem.dispatcher_tlb.page_table_cycles 0 # Cycles spent accessing the page table 244311308Santhony.gutierrez@amd.comsystem.dispatcher_tlb.unique_pages 0 # Number of unique pages touched 244411308Santhony.gutierrez@amd.comsystem.dispatcher_tlb.local_cycles 0 # Number of cycles spent in queue for all incoming reqs 244511308Santhony.gutierrez@amd.comsystem.dispatcher_tlb.local_latency nan # Avg. latency over incoming coalesced reqs 244611308Santhony.gutierrez@amd.comsystem.dispatcher_tlb.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks) 244711308Santhony.gutierrez@amd.comsystem.l1_coalescer0.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 244811308Santhony.gutierrez@amd.comsystem.l1_coalescer0.clk_domain.clock 1000 # Clock period in ticks 244911308Santhony.gutierrez@amd.comsystem.l1_coalescer0.uncoalesced_accesses 778 # Number of uncoalesced TLB accesses 245011308Santhony.gutierrez@amd.comsystem.l1_coalescer0.coalesced_accesses 0 # Number of coalesced TLB accesses 245111308Santhony.gutierrez@amd.comsystem.l1_coalescer0.queuing_cycles 0 # Number of cycles spent in queue 245211308Santhony.gutierrez@amd.comsystem.l1_coalescer0.local_queuing_cycles 0 # Number of cycles spent in queue for all incoming reqs 245311308Santhony.gutierrez@amd.comsystem.l1_coalescer0.local_latency 0 # Avg. latency over all incoming pkts 245411308Santhony.gutierrez@amd.comsystem.l1_coalescer1.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 245511308Santhony.gutierrez@amd.comsystem.l1_coalescer1.clk_domain.clock 1000 # Clock period in ticks 245611308Santhony.gutierrez@amd.comsystem.l1_coalescer1.uncoalesced_accesses 769 # Number of uncoalesced TLB accesses 245711308Santhony.gutierrez@amd.comsystem.l1_coalescer1.coalesced_accesses 0 # Number of coalesced TLB accesses 245811308Santhony.gutierrez@amd.comsystem.l1_coalescer1.queuing_cycles 0 # Number of cycles spent in queue 245911308Santhony.gutierrez@amd.comsystem.l1_coalescer1.local_queuing_cycles 0 # Number of cycles spent in queue for all incoming reqs 246011308Santhony.gutierrez@amd.comsystem.l1_coalescer1.local_latency 0 # Avg. latency over all incoming pkts 246111308Santhony.gutierrez@amd.comsystem.l1_tlb0.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 246211308Santhony.gutierrez@amd.comsystem.l1_tlb0.clk_domain.clock 1000 # Clock period in ticks 246311308Santhony.gutierrez@amd.comsystem.l1_tlb0.local_TLB_accesses 778 # Number of TLB accesses 246411308Santhony.gutierrez@amd.comsystem.l1_tlb0.local_TLB_hits 774 # Number of TLB hits 246511308Santhony.gutierrez@amd.comsystem.l1_tlb0.local_TLB_misses 4 # Number of TLB misses 246611308Santhony.gutierrez@amd.comsystem.l1_tlb0.local_TLB_miss_rate 0.514139 # TLB miss rate 246711308Santhony.gutierrez@amd.comsystem.l1_tlb0.global_TLB_accesses 778 # Number of TLB accesses 246811308Santhony.gutierrez@amd.comsystem.l1_tlb0.global_TLB_hits 774 # Number of TLB hits 246911308Santhony.gutierrez@amd.comsystem.l1_tlb0.global_TLB_misses 4 # Number of TLB misses 247011308Santhony.gutierrez@amd.comsystem.l1_tlb0.global_TLB_miss_rate 0.514139 # TLB miss rate 247111308Santhony.gutierrez@amd.comsystem.l1_tlb0.access_cycles 0 # Cycles spent accessing this TLB level 247211308Santhony.gutierrez@amd.comsystem.l1_tlb0.page_table_cycles 0 # Cycles spent accessing the page table 247311308Santhony.gutierrez@amd.comsystem.l1_tlb0.unique_pages 4 # Number of unique pages touched 247411308Santhony.gutierrez@amd.comsystem.l1_tlb0.local_cycles 0 # Number of cycles spent in queue for all incoming reqs 247511308Santhony.gutierrez@amd.comsystem.l1_tlb0.local_latency 0 # Avg. latency over incoming coalesced reqs 247611308Santhony.gutierrez@amd.comsystem.l1_tlb0.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks) 247711308Santhony.gutierrez@amd.comsystem.l1_tlb1.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 247811308Santhony.gutierrez@amd.comsystem.l1_tlb1.clk_domain.clock 1000 # Clock period in ticks 247911308Santhony.gutierrez@amd.comsystem.l1_tlb1.local_TLB_accesses 769 # Number of TLB accesses 248011308Santhony.gutierrez@amd.comsystem.l1_tlb1.local_TLB_hits 766 # Number of TLB hits 248111308Santhony.gutierrez@amd.comsystem.l1_tlb1.local_TLB_misses 3 # Number of TLB misses 248211308Santhony.gutierrez@amd.comsystem.l1_tlb1.local_TLB_miss_rate 0.390117 # TLB miss rate 248311308Santhony.gutierrez@amd.comsystem.l1_tlb1.global_TLB_accesses 769 # Number of TLB accesses 248411308Santhony.gutierrez@amd.comsystem.l1_tlb1.global_TLB_hits 766 # Number of TLB hits 248511308Santhony.gutierrez@amd.comsystem.l1_tlb1.global_TLB_misses 3 # Number of TLB misses 248611308Santhony.gutierrez@amd.comsystem.l1_tlb1.global_TLB_miss_rate 0.390117 # TLB miss rate 248711308Santhony.gutierrez@amd.comsystem.l1_tlb1.access_cycles 0 # Cycles spent accessing this TLB level 248811308Santhony.gutierrez@amd.comsystem.l1_tlb1.page_table_cycles 0 # Cycles spent accessing the page table 248911308Santhony.gutierrez@amd.comsystem.l1_tlb1.unique_pages 3 # Number of unique pages touched 249011308Santhony.gutierrez@amd.comsystem.l1_tlb1.local_cycles 0 # Number of cycles spent in queue for all incoming reqs 249111308Santhony.gutierrez@amd.comsystem.l1_tlb1.local_latency 0 # Avg. latency over incoming coalesced reqs 249211308Santhony.gutierrez@amd.comsystem.l1_tlb1.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks) 249311308Santhony.gutierrez@amd.comsystem.l2_coalescer.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 249411308Santhony.gutierrez@amd.comsystem.l2_coalescer.clk_domain.clock 1000 # Clock period in ticks 249511308Santhony.gutierrez@amd.comsystem.l2_coalescer.uncoalesced_accesses 8 # Number of uncoalesced TLB accesses 249611308Santhony.gutierrez@amd.comsystem.l2_coalescer.coalesced_accesses 1 # Number of coalesced TLB accesses 249711308Santhony.gutierrez@amd.comsystem.l2_coalescer.queuing_cycles 8000 # Number of cycles spent in queue 249811308Santhony.gutierrez@amd.comsystem.l2_coalescer.local_queuing_cycles 1000 # Number of cycles spent in queue for all incoming reqs 249911308Santhony.gutierrez@amd.comsystem.l2_coalescer.local_latency 125 # Avg. latency over all incoming pkts 250011308Santhony.gutierrez@amd.comsystem.l2_tlb.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 250111308Santhony.gutierrez@amd.comsystem.l2_tlb.clk_domain.clock 1000 # Clock period in ticks 250211308Santhony.gutierrez@amd.comsystem.l2_tlb.local_TLB_accesses 8 # Number of TLB accesses 250311308Santhony.gutierrez@amd.comsystem.l2_tlb.local_TLB_hits 3 # Number of TLB hits 250411308Santhony.gutierrez@amd.comsystem.l2_tlb.local_TLB_misses 5 # Number of TLB misses 250511308Santhony.gutierrez@amd.comsystem.l2_tlb.local_TLB_miss_rate 62.500000 # TLB miss rate 250611308Santhony.gutierrez@amd.comsystem.l2_tlb.global_TLB_accesses 15 # Number of TLB accesses 250711308Santhony.gutierrez@amd.comsystem.l2_tlb.global_TLB_hits 3 # Number of TLB hits 250811308Santhony.gutierrez@amd.comsystem.l2_tlb.global_TLB_misses 12 # Number of TLB misses 250911308Santhony.gutierrez@amd.comsystem.l2_tlb.global_TLB_miss_rate 80 # TLB miss rate 251011308Santhony.gutierrez@amd.comsystem.l2_tlb.access_cycles 552008 # Cycles spent accessing this TLB level 251111308Santhony.gutierrez@amd.comsystem.l2_tlb.page_table_cycles 0 # Cycles spent accessing the page table 251211308Santhony.gutierrez@amd.comsystem.l2_tlb.unique_pages 5 # Number of unique pages touched 251311308Santhony.gutierrez@amd.comsystem.l2_tlb.local_cycles 69001 # Number of cycles spent in queue for all incoming reqs 251411308Santhony.gutierrez@amd.comsystem.l2_tlb.local_latency 8625.125000 # Avg. latency over incoming coalesced reqs 251511308Santhony.gutierrez@amd.comsystem.l2_tlb.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks) 251611308Santhony.gutierrez@amd.comsystem.l3_coalescer.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 251711308Santhony.gutierrez@amd.comsystem.l3_coalescer.clk_domain.clock 1000 # Clock period in ticks 251811308Santhony.gutierrez@amd.comsystem.l3_coalescer.uncoalesced_accesses 5 # Number of uncoalesced TLB accesses 251911308Santhony.gutierrez@amd.comsystem.l3_coalescer.coalesced_accesses 1 # Number of coalesced TLB accesses 252011308Santhony.gutierrez@amd.comsystem.l3_coalescer.queuing_cycles 8000 # Number of cycles spent in queue 252111308Santhony.gutierrez@amd.comsystem.l3_coalescer.local_queuing_cycles 1000 # Number of cycles spent in queue for all incoming reqs 252211308Santhony.gutierrez@amd.comsystem.l3_coalescer.local_latency 200 # Avg. latency over all incoming pkts 252311308Santhony.gutierrez@amd.comsystem.l3_tlb.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 252411308Santhony.gutierrez@amd.comsystem.l3_tlb.clk_domain.clock 1000 # Clock period in ticks 252511308Santhony.gutierrez@amd.comsystem.l3_tlb.local_TLB_accesses 5 # Number of TLB accesses 252611308Santhony.gutierrez@amd.comsystem.l3_tlb.local_TLB_hits 0 # Number of TLB hits 252711308Santhony.gutierrez@amd.comsystem.l3_tlb.local_TLB_misses 5 # Number of TLB misses 252811308Santhony.gutierrez@amd.comsystem.l3_tlb.local_TLB_miss_rate 100 # TLB miss rate 252911308Santhony.gutierrez@amd.comsystem.l3_tlb.global_TLB_accesses 12 # Number of TLB accesses 253011308Santhony.gutierrez@amd.comsystem.l3_tlb.global_TLB_hits 0 # Number of TLB hits 253111308Santhony.gutierrez@amd.comsystem.l3_tlb.global_TLB_misses 12 # Number of TLB misses 253211308Santhony.gutierrez@amd.comsystem.l3_tlb.global_TLB_miss_rate 100 # TLB miss rate 253311308Santhony.gutierrez@amd.comsystem.l3_tlb.access_cycles 1200000 # Cycles spent accessing this TLB level 253411308Santhony.gutierrez@amd.comsystem.l3_tlb.page_table_cycles 6000000 # Cycles spent accessing the page table 253511308Santhony.gutierrez@amd.comsystem.l3_tlb.unique_pages 5 # Number of unique pages touched 253611308Santhony.gutierrez@amd.comsystem.l3_tlb.local_cycles 150000 # Number of cycles spent in queue for all incoming reqs 253711308Santhony.gutierrez@amd.comsystem.l3_tlb.local_latency 30000 # Avg. latency over incoming coalesced reqs 253811308Santhony.gutierrez@amd.comsystem.l3_tlb.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks) 253911308Santhony.gutierrez@amd.comsystem.piobus.trans_dist::WriteReq 94 # Transaction distribution 254011308Santhony.gutierrez@amd.comsystem.piobus.trans_dist::WriteResp 94 # Transaction distribution 254111308Santhony.gutierrez@amd.comsystem.piobus.pkt_count_system.ruby.cp_cntrl0.sequencer.mem-master-port::system.cpu2.pio 188 # Packet count per connected master and slave (bytes) 254211308Santhony.gutierrez@amd.comsystem.piobus.pkt_count::total 188 # Packet count per connected master and slave (bytes) 254311308Santhony.gutierrez@amd.comsystem.piobus.pkt_size_system.ruby.cp_cntrl0.sequencer.mem-master-port::system.cpu2.pio 748 # Cumulative packet size per connected master and slave (bytes) 254411308Santhony.gutierrez@amd.comsystem.piobus.pkt_size::total 748 # Cumulative packet size per connected master and slave (bytes) 254511308Santhony.gutierrez@amd.comsystem.piobus.reqLayer0.occupancy 234500 # Layer occupancy (ticks) 254611308Santhony.gutierrez@amd.comsystem.piobus.reqLayer0.utilization 0.1 # Layer utilization (%) 254711308Santhony.gutierrez@amd.comsystem.piobus.respLayer0.occupancy 94000 # Layer occupancy (ticks) 254811308Santhony.gutierrez@amd.comsystem.piobus.respLayer0.utilization 0.0 # Layer utilization (%) 254911308Santhony.gutierrez@amd.comsystem.ruby.outstanding_req_hist::bucket_size 1 255011308Santhony.gutierrez@amd.comsystem.ruby.outstanding_req_hist::max_bucket 9 255111308Santhony.gutierrez@amd.comsystem.ruby.outstanding_req_hist::samples 114203 255211308Santhony.gutierrez@amd.comsystem.ruby.outstanding_req_hist::mean 1.000035 255311308Santhony.gutierrez@amd.comsystem.ruby.outstanding_req_hist::gmean 1.000024 255411308Santhony.gutierrez@amd.comsystem.ruby.outstanding_req_hist::stdev 0.005918 255511308Santhony.gutierrez@amd.comsystem.ruby.outstanding_req_hist | 0 0.00% 0.00% | 114199 100.00% 100.00% | 4 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 255611308Santhony.gutierrez@amd.comsystem.ruby.outstanding_req_hist::total 114203 255711308Santhony.gutierrez@amd.comsystem.ruby.latency_hist::bucket_size 128 255811308Santhony.gutierrez@amd.comsystem.ruby.latency_hist::max_bucket 1279 255911308Santhony.gutierrez@amd.comsystem.ruby.latency_hist::samples 114203 256011308Santhony.gutierrez@amd.comsystem.ruby.latency_hist::mean 4.423518 256111308Santhony.gutierrez@amd.comsystem.ruby.latency_hist::gmean 1.078765 256211308Santhony.gutierrez@amd.comsystem.ruby.latency_hist::stdev 30.010569 256311308Santhony.gutierrez@amd.comsystem.ruby.latency_hist | 112668 98.66% 98.66% | 1136 0.99% 99.65% | 372 0.33% 99.98% | 3 0.00% 99.98% | 8 0.01% 99.99% | 14 0.01% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 256411308Santhony.gutierrez@amd.comsystem.ruby.latency_hist::total 114203 256511308Santhony.gutierrez@amd.comsystem.ruby.hit_latency_hist::bucket_size 128 256611308Santhony.gutierrez@amd.comsystem.ruby.hit_latency_hist::max_bucket 1279 256711308Santhony.gutierrez@amd.comsystem.ruby.hit_latency_hist::samples 1535 256811308Santhony.gutierrez@amd.comsystem.ruby.hit_latency_hist::mean 255.015635 256911308Santhony.gutierrez@amd.comsystem.ruby.hit_latency_hist::gmean 251.519163 257011308Santhony.gutierrez@amd.comsystem.ruby.hit_latency_hist::stdev 57.825523 257111308Santhony.gutierrez@amd.comsystem.ruby.hit_latency_hist | 0 0.00% 0.00% | 1136 74.01% 74.01% | 372 24.23% 98.24% | 3 0.20% 98.44% | 8 0.52% 98.96% | 14 0.91% 99.87% | 2 0.13% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 257211308Santhony.gutierrez@amd.comsystem.ruby.hit_latency_hist::total 1535 257311308Santhony.gutierrez@amd.comsystem.ruby.miss_latency_hist::bucket_size 2 257411308Santhony.gutierrez@amd.comsystem.ruby.miss_latency_hist::max_bucket 19 257511308Santhony.gutierrez@amd.comsystem.ruby.miss_latency_hist::samples 112668 257611308Santhony.gutierrez@amd.comsystem.ruby.miss_latency_hist::mean 1.009426 257711308Santhony.gutierrez@amd.comsystem.ruby.miss_latency_hist::gmean 1.001543 257811308Santhony.gutierrez@amd.comsystem.ruby.miss_latency_hist::stdev 0.411800 257911308Santhony.gutierrez@amd.comsystem.ruby.miss_latency_hist | 112609 99.95% 99.95% | 0 0.00% 99.95% | 0 0.00% 99.95% | 0 0.00% 99.95% | 0 0.00% 99.95% | 0 0.00% 99.95% | 0 0.00% 99.95% | 0 0.00% 99.95% | 0 0.00% 99.95% | 59 0.05% 100.00% 258011308Santhony.gutierrez@amd.comsystem.ruby.miss_latency_hist::total 112668 258111308Santhony.gutierrez@amd.comsystem.ruby.L1Cache.incomplete_times 112609 258211308Santhony.gutierrez@amd.comsystem.ruby.L2Cache.incomplete_times 59 258311308Santhony.gutierrez@amd.comsystem.ruby.cp_cntrl0.L1D0cache.demand_hits 0 # Number of cache demand hits 258411308Santhony.gutierrez@amd.comsystem.ruby.cp_cntrl0.L1D0cache.demand_misses 506 # Number of cache demand misses 258511308Santhony.gutierrez@amd.comsystem.ruby.cp_cntrl0.L1D0cache.demand_accesses 506 # Number of cache demand accesses 258611308Santhony.gutierrez@amd.comsystem.ruby.cp_cntrl0.L1D0cache.num_data_array_reads 16155 # number of data array reads 258711308Santhony.gutierrez@amd.comsystem.ruby.cp_cntrl0.L1D0cache.num_data_array_writes 11985 # number of data array writes 258811308Santhony.gutierrez@amd.comsystem.ruby.cp_cntrl0.L1D0cache.num_tag_array_reads 27132 # number of tag array reads 258911308Santhony.gutierrez@amd.comsystem.ruby.cp_cntrl0.L1D0cache.num_tag_array_writes 1584 # number of tag array writes 259011308Santhony.gutierrez@amd.comsystem.ruby.cp_cntrl0.L1D1cache.demand_hits 0 # Number of cache demand hits 259111308Santhony.gutierrez@amd.comsystem.ruby.cp_cntrl0.L1D1cache.demand_misses 0 # Number of cache demand misses 259211308Santhony.gutierrez@amd.comsystem.ruby.cp_cntrl0.L1D1cache.demand_accesses 0 # Number of cache demand accesses 259311308Santhony.gutierrez@amd.comsystem.ruby.cp_cntrl0.L1Icache.demand_hits 0 # Number of cache demand hits 259411308Santhony.gutierrez@amd.comsystem.ruby.cp_cntrl0.L1Icache.demand_misses 1088 # Number of cache demand misses 259511308Santhony.gutierrez@amd.comsystem.ruby.cp_cntrl0.L1Icache.demand_accesses 1088 # Number of cache demand accesses 259611308Santhony.gutierrez@amd.comsystem.ruby.cp_cntrl0.L1Icache.num_data_array_reads 86007 # number of data array reads 259711308Santhony.gutierrez@amd.comsystem.ruby.cp_cntrl0.L1Icache.num_data_array_writes 54 # number of data array writes 259811308Santhony.gutierrez@amd.comsystem.ruby.cp_cntrl0.L1Icache.num_tag_array_reads 87684 # number of tag array reads 259911308Santhony.gutierrez@amd.comsystem.ruby.cp_cntrl0.L1Icache.num_tag_array_writes 54 # number of tag array writes 260011308Santhony.gutierrez@amd.comsystem.ruby.cp_cntrl0.L2cache.demand_hits 0 # Number of cache demand hits 260111308Santhony.gutierrez@amd.comsystem.ruby.cp_cntrl0.L2cache.demand_misses 1535 # Number of cache demand misses 260211308Santhony.gutierrez@amd.comsystem.ruby.cp_cntrl0.L2cache.demand_accesses 1535 # Number of cache demand accesses 260311308Santhony.gutierrez@amd.comsystem.ruby.cp_cntrl0.L2cache.num_data_array_reads 120 # number of data array reads 260411308Santhony.gutierrez@amd.comsystem.ruby.cp_cntrl0.L2cache.num_data_array_writes 11982 # number of data array writes 260511308Santhony.gutierrez@amd.comsystem.ruby.cp_cntrl0.L2cache.num_tag_array_reads 12068 # number of tag array reads 260611308Santhony.gutierrez@amd.comsystem.ruby.cp_cntrl0.L2cache.num_tag_array_writes 1658 # number of tag array writes 260711308Santhony.gutierrez@amd.comsystem.ruby.dir_cntrl0.L3CacheMemory.demand_hits 0 # Number of cache demand hits 260811308Santhony.gutierrez@amd.comsystem.ruby.dir_cntrl0.L3CacheMemory.demand_misses 0 # Number of cache demand misses 260911308Santhony.gutierrez@amd.comsystem.ruby.dir_cntrl0.L3CacheMemory.demand_accesses 0 # Number of cache demand accesses 261011308Santhony.gutierrez@amd.comsystem.ruby.dir_cntrl0.L3CacheMemory.num_data_array_writes 1560 # number of data array writes 261111308Santhony.gutierrez@amd.comsystem.ruby.dir_cntrl0.L3CacheMemory.num_tag_array_reads 1560 # number of tag array reads 261211308Santhony.gutierrez@amd.comsystem.ruby.dir_cntrl0.L3CacheMemory.num_tag_array_writes 1578 # number of tag array writes 261311308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links0.int_node.percent_links_utilized 1.075754 261411308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links0.int_node.msg_count.Control::0 1560 261511308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links0.int_node.msg_count.Data::0 18 261611308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links0.int_node.msg_count.Request_Control::0 1542 261711308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links0.int_node.msg_count.Response_Data::2 1546 261811308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links0.int_node.msg_count.Response_Control::2 1558 261911308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links0.int_node.msg_count.Writeback_Control::2 16 262011308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links0.int_node.msg_count.Unblock_Control::4 1541 262111308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links0.int_node.msg_bytes.Control::0 12480 262211308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links0.int_node.msg_bytes.Data::0 1296 262311308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links0.int_node.msg_bytes.Request_Control::0 12336 262411308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links0.int_node.msg_bytes.Response_Data::2 111312 262511308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links0.int_node.msg_bytes.Response_Control::2 12464 262611308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links0.int_node.msg_bytes.Writeback_Control::2 128 262711308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links0.int_node.msg_bytes.Unblock_Control::4 12328 262811308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links1.int_node.percent_links_utilized 1.347807 262911308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links1.int_node.msg_count.Control::0 25 263011308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links1.int_node.msg_count.Request_Control::0 1535 263111308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links1.int_node.msg_count.Response_Data::2 1537 263211308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links1.int_node.msg_count.Response_Control::2 23 263311308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links1.int_node.msg_count.Unblock_Control::4 1534 263411308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links1.int_node.msg_bytes.Control::0 200 263511308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links1.int_node.msg_bytes.Request_Control::0 12280 263611308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links1.int_node.msg_bytes.Response_Data::2 110664 263711308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links1.int_node.msg_bytes.Response_Control::2 184 263811308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links1.int_node.msg_bytes.Unblock_Control::4 12272 263911308Santhony.gutierrez@amd.comsystem.ruby.tcp_cntrl0.L1cache.demand_hits 0 # Number of cache demand hits 264011308Santhony.gutierrez@amd.comsystem.ruby.tcp_cntrl0.L1cache.demand_misses 0 # Number of cache demand misses 264111308Santhony.gutierrez@amd.comsystem.ruby.tcp_cntrl0.L1cache.demand_accesses 0 # Number of cache demand accesses 264211308Santhony.gutierrez@amd.comsystem.ruby.tcp_cntrl0.L1cache.num_data_array_reads 6 # number of data array reads 264311308Santhony.gutierrez@amd.comsystem.ruby.tcp_cntrl0.L1cache.num_data_array_writes 11 # number of data array writes 264411308Santhony.gutierrez@amd.comsystem.ruby.tcp_cntrl0.L1cache.num_tag_array_reads 1297 # number of tag array reads 264511308Santhony.gutierrez@amd.comsystem.ruby.tcp_cntrl0.L1cache.num_tag_array_writes 11 # number of tag array writes 264611308Santhony.gutierrez@amd.comsystem.ruby.tcp_cntrl0.L1cache.num_tag_array_stalls 5082 # number of stalls caused by tag array 264711308Santhony.gutierrez@amd.comsystem.ruby.tcp_cntrl0.L1cache.num_data_array_stalls 6 # number of stalls caused by data array 264811308Santhony.gutierrez@amd.comsystem.ruby.tcp_cntrl0.coalescer.gpu_tcp_ld_hits 0 # loads that hit in the TCP 264911308Santhony.gutierrez@amd.comsystem.ruby.tcp_cntrl0.coalescer.gpu_tcp_ld_transfers 0 # TCP to TCP load transfers 265011308Santhony.gutierrez@amd.comsystem.ruby.tcp_cntrl0.coalescer.gpu_tcc_ld_hits 0 # loads that hit in the TCC 265111308Santhony.gutierrez@amd.comsystem.ruby.tcp_cntrl0.coalescer.gpu_ld_misses 5 # loads that miss in the GPU 265211308Santhony.gutierrez@amd.comsystem.ruby.tcp_cntrl0.coalescer.gpu_tcp_st_hits 0 # stores that hit in the TCP 265311308Santhony.gutierrez@amd.comsystem.ruby.tcp_cntrl0.coalescer.gpu_tcp_st_transfers 0 # TCP to TCP store transfers 265411308Santhony.gutierrez@amd.comsystem.ruby.tcp_cntrl0.coalescer.gpu_tcc_st_hits 0 # stores that hit in the TCC 265511308Santhony.gutierrez@amd.comsystem.ruby.tcp_cntrl0.coalescer.gpu_st_misses 9 # stores that miss in the GPU 265611308Santhony.gutierrez@amd.comsystem.ruby.tcp_cntrl0.coalescer.cp_tcp_ld_hits 0 # loads that hit in the TCP 265711308Santhony.gutierrez@amd.comsystem.ruby.tcp_cntrl0.coalescer.cp_tcp_ld_transfers 0 # TCP to TCP load transfers 265811308Santhony.gutierrez@amd.comsystem.ruby.tcp_cntrl0.coalescer.cp_tcc_ld_hits 0 # loads that hit in the TCC 265911308Santhony.gutierrez@amd.comsystem.ruby.tcp_cntrl0.coalescer.cp_ld_misses 0 # loads that miss in the GPU 266011308Santhony.gutierrez@amd.comsystem.ruby.tcp_cntrl0.coalescer.cp_tcp_st_hits 0 # stores that hit in the TCP 266111308Santhony.gutierrez@amd.comsystem.ruby.tcp_cntrl0.coalescer.cp_tcp_st_transfers 0 # TCP to TCP store transfers 266211308Santhony.gutierrez@amd.comsystem.ruby.tcp_cntrl0.coalescer.cp_tcc_st_hits 0 # stores that hit in the TCC 266311308Santhony.gutierrez@amd.comsystem.ruby.tcp_cntrl0.coalescer.cp_st_misses 0 # stores that miss in the GPU 266411308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.percent_links_utilized 0.115426 266511308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.msg_count.Control::0 1535 266611308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.msg_count.Data::0 18 266711308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.msg_count.Data::1 18 266811308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.msg_count.Request_Control::0 7 266911308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.msg_count.Request_Control::1 9 267011308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.msg_count.Response_Data::2 9 267111308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.msg_count.Response_Data::3 11 267211308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.msg_count.Response_Control::2 1535 267311308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.msg_count.Writeback_Control::2 16 267411308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.msg_count.Writeback_Control::3 16 267511308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.msg_count.Unblock_Control::4 7 267611308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.msg_bytes.Control::0 12280 267711308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.msg_bytes.Data::0 1296 267811308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.msg_bytes.Data::1 1296 267911308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.msg_bytes.Request_Control::0 56 268011308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.msg_bytes.Request_Control::1 72 268111308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.msg_bytes.Response_Data::2 648 268211308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.msg_bytes.Response_Data::3 792 268311308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.msg_bytes.Response_Control::2 12280 268411308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.msg_bytes.Writeback_Control::2 128 268511308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.msg_bytes.Writeback_Control::3 128 268611308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.msg_bytes.Unblock_Control::4 56 268711308Santhony.gutierrez@amd.comsystem.ruby.tcp_cntrl1.L1cache.demand_hits 0 # Number of cache demand hits 268811308Santhony.gutierrez@amd.comsystem.ruby.tcp_cntrl1.L1cache.demand_misses 0 # Number of cache demand misses 268911308Santhony.gutierrez@amd.comsystem.ruby.tcp_cntrl1.L1cache.demand_accesses 0 # Number of cache demand accesses 269011308Santhony.gutierrez@amd.comsystem.ruby.tcp_cntrl1.L1cache.num_data_array_reads 6 # number of data array reads 269111308Santhony.gutierrez@amd.comsystem.ruby.tcp_cntrl1.L1cache.num_data_array_writes 11 # number of data array writes 269211308Santhony.gutierrez@amd.comsystem.ruby.tcp_cntrl1.L1cache.num_tag_array_reads 1297 # number of tag array reads 269311308Santhony.gutierrez@amd.comsystem.ruby.tcp_cntrl1.L1cache.num_tag_array_writes 11 # number of tag array writes 269411308Santhony.gutierrez@amd.comsystem.ruby.tcp_cntrl1.L1cache.num_tag_array_stalls 5082 # number of stalls caused by tag array 269511308Santhony.gutierrez@amd.comsystem.ruby.tcp_cntrl1.L1cache.num_data_array_stalls 6 # number of stalls caused by data array 269611308Santhony.gutierrez@amd.comsystem.ruby.tcp_cntrl1.coalescer.gpu_tcp_ld_hits 0 # loads that hit in the TCP 269711308Santhony.gutierrez@amd.comsystem.ruby.tcp_cntrl1.coalescer.gpu_tcp_ld_transfers 0 # TCP to TCP load transfers 269811308Santhony.gutierrez@amd.comsystem.ruby.tcp_cntrl1.coalescer.gpu_tcc_ld_hits 0 # loads that hit in the TCC 269911308Santhony.gutierrez@amd.comsystem.ruby.tcp_cntrl1.coalescer.gpu_ld_misses 5 # loads that miss in the GPU 270011308Santhony.gutierrez@amd.comsystem.ruby.tcp_cntrl1.coalescer.gpu_tcp_st_hits 0 # stores that hit in the TCP 270111308Santhony.gutierrez@amd.comsystem.ruby.tcp_cntrl1.coalescer.gpu_tcp_st_transfers 0 # TCP to TCP store transfers 270211308Santhony.gutierrez@amd.comsystem.ruby.tcp_cntrl1.coalescer.gpu_tcc_st_hits 0 # stores that hit in the TCC 270311308Santhony.gutierrez@amd.comsystem.ruby.tcp_cntrl1.coalescer.gpu_st_misses 9 # stores that miss in the GPU 270411308Santhony.gutierrez@amd.comsystem.ruby.tcp_cntrl1.coalescer.cp_tcp_ld_hits 0 # loads that hit in the TCP 270511308Santhony.gutierrez@amd.comsystem.ruby.tcp_cntrl1.coalescer.cp_tcp_ld_transfers 0 # TCP to TCP load transfers 270611308Santhony.gutierrez@amd.comsystem.ruby.tcp_cntrl1.coalescer.cp_tcc_ld_hits 0 # loads that hit in the TCC 270711308Santhony.gutierrez@amd.comsystem.ruby.tcp_cntrl1.coalescer.cp_ld_misses 0 # loads that miss in the GPU 270811308Santhony.gutierrez@amd.comsystem.ruby.tcp_cntrl1.coalescer.cp_tcp_st_hits 0 # stores that hit in the TCP 270911308Santhony.gutierrez@amd.comsystem.ruby.tcp_cntrl1.coalescer.cp_tcp_st_transfers 0 # TCP to TCP store transfers 271011308Santhony.gutierrez@amd.comsystem.ruby.tcp_cntrl1.coalescer.cp_tcc_st_hits 0 # stores that hit in the TCC 271111308Santhony.gutierrez@amd.comsystem.ruby.tcp_cntrl1.coalescer.cp_st_misses 0 # stores that miss in the GPU 271211308Santhony.gutierrez@amd.comsystem.ruby.sqc_cntrl0.L1cache.demand_hits 0 # Number of cache demand hits 271311308Santhony.gutierrez@amd.comsystem.ruby.sqc_cntrl0.L1cache.demand_misses 0 # Number of cache demand misses 271411308Santhony.gutierrez@amd.comsystem.ruby.sqc_cntrl0.L1cache.demand_accesses 0 # Number of cache demand accesses 271511308Santhony.gutierrez@amd.comsystem.ruby.sqc_cntrl0.L1cache.num_data_array_reads 86 # number of data array reads 271611308Santhony.gutierrez@amd.comsystem.ruby.sqc_cntrl0.L1cache.num_tag_array_reads 91 # number of tag array reads 271711308Santhony.gutierrez@amd.comsystem.ruby.sqc_cntrl0.L1cache.num_tag_array_writes 10 # number of tag array writes 271811308Santhony.gutierrez@amd.comsystem.ruby.sqc_cntrl0.sequencer.load_waiting_on_load 97 # Number of times a load aliased with a pending load 271911308Santhony.gutierrez@amd.comsystem.ruby.tcc_cntrl0.L2cache.demand_hits 0 # Number of cache demand hits 272011308Santhony.gutierrez@amd.comsystem.ruby.tcc_cntrl0.L2cache.demand_misses 0 # Number of cache demand misses 272111308Santhony.gutierrez@amd.comsystem.ruby.tcc_cntrl0.L2cache.demand_accesses 0 # Number of cache demand accesses 272211308Santhony.gutierrez@amd.comsystem.ruby.tcc_cntrl0.L2cache.num_data_array_writes 9 # number of data array writes 272311308Santhony.gutierrez@amd.comsystem.ruby.tcc_cntrl0.L2cache.num_tag_array_reads 1569 # number of tag array reads 272411308Santhony.gutierrez@amd.comsystem.ruby.tcc_cntrl0.L2cache.num_tag_array_writes 1545 # number of tag array writes 272511308Santhony.gutierrez@amd.comsystem.ruby.tcc_cntrl0.L2cache.num_tag_array_stalls 1 # number of stalls caused by tag array 272611308Santhony.gutierrez@amd.comsystem.ruby.network.msg_count.Control 3120 272711308Santhony.gutierrez@amd.comsystem.ruby.network.msg_count.Data 54 272811308Santhony.gutierrez@amd.comsystem.ruby.network.msg_count.Request_Control 3093 272911308Santhony.gutierrez@amd.comsystem.ruby.network.msg_count.Response_Data 3103 273011308Santhony.gutierrez@amd.comsystem.ruby.network.msg_count.Response_Control 3116 273111308Santhony.gutierrez@amd.comsystem.ruby.network.msg_count.Writeback_Control 48 273211308Santhony.gutierrez@amd.comsystem.ruby.network.msg_count.Unblock_Control 3082 273311308Santhony.gutierrez@amd.comsystem.ruby.network.msg_byte.Control 24960 273411308Santhony.gutierrez@amd.comsystem.ruby.network.msg_byte.Data 3888 273511308Santhony.gutierrez@amd.comsystem.ruby.network.msg_byte.Request_Control 24744 273611308Santhony.gutierrez@amd.comsystem.ruby.network.msg_byte.Response_Data 223416 273711308Santhony.gutierrez@amd.comsystem.ruby.network.msg_byte.Response_Control 24928 273811308Santhony.gutierrez@amd.comsystem.ruby.network.msg_byte.Writeback_Control 384 273911308Santhony.gutierrez@amd.comsystem.ruby.network.msg_byte.Unblock_Control 24656 274011308Santhony.gutierrez@amd.comsystem.sqc_coalescer.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 274111308Santhony.gutierrez@amd.comsystem.sqc_coalescer.clk_domain.clock 1000 # Clock period in ticks 274211308Santhony.gutierrez@amd.comsystem.sqc_coalescer.uncoalesced_accesses 86 # Number of uncoalesced TLB accesses 274311308Santhony.gutierrez@amd.comsystem.sqc_coalescer.coalesced_accesses 48 # Number of coalesced TLB accesses 274411308Santhony.gutierrez@amd.comsystem.sqc_coalescer.queuing_cycles 211000 # Number of cycles spent in queue 274511308Santhony.gutierrez@amd.comsystem.sqc_coalescer.local_queuing_cycles 211000 # Number of cycles spent in queue for all incoming reqs 274611308Santhony.gutierrez@amd.comsystem.sqc_coalescer.local_latency 2453.488372 # Avg. latency over all incoming pkts 274711308Santhony.gutierrez@amd.comsystem.sqc_tlb.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 274811308Santhony.gutierrez@amd.comsystem.sqc_tlb.clk_domain.clock 1000 # Clock period in ticks 274911308Santhony.gutierrez@amd.comsystem.sqc_tlb.local_TLB_accesses 48 # Number of TLB accesses 275011308Santhony.gutierrez@amd.comsystem.sqc_tlb.local_TLB_hits 47 # Number of TLB hits 275111308Santhony.gutierrez@amd.comsystem.sqc_tlb.local_TLB_misses 1 # Number of TLB misses 275211308Santhony.gutierrez@amd.comsystem.sqc_tlb.local_TLB_miss_rate 2.083333 # TLB miss rate 275311308Santhony.gutierrez@amd.comsystem.sqc_tlb.global_TLB_accesses 86 # Number of TLB accesses 275411308Santhony.gutierrez@amd.comsystem.sqc_tlb.global_TLB_hits 78 # Number of TLB hits 275511308Santhony.gutierrez@amd.comsystem.sqc_tlb.global_TLB_misses 8 # Number of TLB misses 275611308Santhony.gutierrez@amd.comsystem.sqc_tlb.global_TLB_miss_rate 9.302326 # TLB miss rate 275711308Santhony.gutierrez@amd.comsystem.sqc_tlb.access_cycles 86008 # Cycles spent accessing this TLB level 275811308Santhony.gutierrez@amd.comsystem.sqc_tlb.page_table_cycles 0 # Cycles spent accessing the page table 275911308Santhony.gutierrez@amd.comsystem.sqc_tlb.unique_pages 1 # Number of unique pages touched 276011308Santhony.gutierrez@amd.comsystem.sqc_tlb.local_cycles 48001 # Number of cycles spent in queue for all incoming reqs 276111308Santhony.gutierrez@amd.comsystem.sqc_tlb.local_latency 1000.020833 # Avg. latency over incoming coalesced reqs 276211308Santhony.gutierrez@amd.comsystem.sqc_tlb.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks) 276311308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links0.int_node.throttle0.link_utilization 0.766700 276411308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links0.int_node.throttle0.msg_count.Data::0 18 276511308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links0.int_node.throttle0.msg_count.Request_Control::0 1542 276611308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links0.int_node.throttle0.msg_count.Response_Data::2 2 276711308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links0.int_node.throttle0.msg_count.Response_Control::2 1558 276811308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links0.int_node.throttle0.msg_count.Unblock_Control::4 1541 276911308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links0.int_node.throttle0.msg_bytes.Data::0 1296 277011308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links0.int_node.throttle0.msg_bytes.Request_Control::0 12336 277111308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links0.int_node.throttle0.msg_bytes.Response_Data::2 144 277211308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links0.int_node.throttle0.msg_bytes.Response_Control::2 12464 277311308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links0.int_node.throttle0.msg_bytes.Unblock_Control::4 12328 277411308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links0.int_node.throttle1.link_utilization 2.201021 277511308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links0.int_node.throttle1.msg_count.Control::0 25 277611308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links0.int_node.throttle1.msg_count.Response_Data::2 1535 277711308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links0.int_node.throttle1.msg_bytes.Control::0 200 277811308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links0.int_node.throttle1.msg_bytes.Response_Data::2 110520 277911308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links0.int_node.throttle2.link_utilization 0.259542 278011308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links0.int_node.throttle2.msg_count.Control::0 1535 278111308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links0.int_node.throttle2.msg_count.Response_Data::2 9 278211308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links0.int_node.throttle2.msg_count.Writeback_Control::2 16 278311308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links0.int_node.throttle2.msg_bytes.Control::0 12280 278411308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links0.int_node.throttle2.msg_bytes.Response_Data::2 648 278511308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links0.int_node.throttle2.msg_bytes.Writeback_Control::2 128 278611308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links1.int_node.throttle0.link_utilization 2.201021 278711308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links1.int_node.throttle0.msg_count.Control::0 25 278811308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links1.int_node.throttle0.msg_count.Response_Data::2 1535 278911308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links1.int_node.throttle0.msg_bytes.Control::0 200 279011308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links1.int_node.throttle0.msg_bytes.Response_Data::2 110520 279111308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links1.int_node.throttle1.link_utilization 0.494594 279211308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links1.int_node.throttle1.msg_count.Request_Control::0 1535 279311308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links1.int_node.throttle1.msg_count.Response_Data::2 2 279411308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links1.int_node.throttle1.msg_count.Response_Control::2 23 279511308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links1.int_node.throttle1.msg_count.Unblock_Control::4 1534 279611308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links1.int_node.throttle1.msg_bytes.Request_Control::0 12280 279711308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links1.int_node.throttle1.msg_bytes.Response_Data::2 144 279811308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links1.int_node.throttle1.msg_bytes.Response_Control::2 184 279911308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links1.int_node.throttle1.msg_bytes.Unblock_Control::4 12272 280011308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.throttle0.link_utilization 0.005566 280111308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.throttle0.msg_count.Response_Data::3 3 280211308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.throttle0.msg_count.Writeback_Control::3 8 280311308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.throttle0.msg_bytes.Response_Data::3 216 280411308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.throttle0.msg_bytes.Writeback_Control::3 64 280511308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.throttle1.link_utilization 0.005566 280611308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.throttle1.msg_count.Response_Data::3 3 280711308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.throttle1.msg_count.Writeback_Control::3 8 280811308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.throttle1.msg_bytes.Response_Data::3 216 280911308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.throttle1.msg_bytes.Writeback_Control::3 64 281011308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.throttle2.link_utilization 0.286737 281111308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.throttle2.msg_count.Control::0 1535 281211308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.throttle2.msg_count.Data::1 18 281311308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.throttle2.msg_count.Request_Control::1 9 281411308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.throttle2.msg_count.Response_Data::2 9 281511308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.throttle2.msg_count.Writeback_Control::2 16 281611308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.throttle2.msg_bytes.Control::0 12280 281711308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.throttle2.msg_bytes.Data::1 1296 281811308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.throttle2.msg_bytes.Request_Control::1 72 281911308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.throttle2.msg_bytes.Response_Data::2 648 282011308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.throttle2.msg_bytes.Writeback_Control::2 128 282111308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.throttle3.link_utilization 0.007156 282211308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.throttle3.msg_count.Response_Data::3 5 282311308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.throttle3.msg_bytes.Response_Data::3 360 282411308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.throttle4.link_utilization 0.272106 282511308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.throttle4.msg_count.Data::0 18 282611308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.throttle4.msg_count.Request_Control::0 7 282711308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.throttle4.msg_count.Response_Control::2 1535 282811308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.throttle4.msg_count.Unblock_Control::4 7 282911308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.throttle4.msg_bytes.Data::0 1296 283011308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.throttle4.msg_bytes.Request_Control::0 56 283111308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.throttle4.msg_bytes.Response_Control::2 12280 283211308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links2.int_node.throttle4.msg_bytes.Unblock_Control::4 56 283311308Santhony.gutierrez@amd.comsystem.ruby.LD.latency_hist::bucket_size 128 283411308Santhony.gutierrez@amd.comsystem.ruby.LD.latency_hist::max_bucket 1279 283511308Santhony.gutierrez@amd.comsystem.ruby.LD.latency_hist::samples 16335 283611308Santhony.gutierrez@amd.comsystem.ruby.LD.latency_hist::mean 3.784451 283711308Santhony.gutierrez@amd.comsystem.ruby.LD.latency_hist::gmean 1.062267 283811308Santhony.gutierrez@amd.comsystem.ruby.LD.latency_hist::stdev 27.056562 283911308Santhony.gutierrez@amd.comsystem.ruby.LD.latency_hist | 16160 98.93% 98.93% | 90 0.55% 99.48% | 84 0.51% 99.99% | 0 0.00% 99.99% | 0 0.00% 99.99% | 1 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 284011308Santhony.gutierrez@amd.comsystem.ruby.LD.latency_hist::total 16335 284111308Santhony.gutierrez@amd.comsystem.ruby.LD.hit_latency_hist::bucket_size 128 284211308Santhony.gutierrez@amd.comsystem.ruby.LD.hit_latency_hist::max_bucket 1279 284311308Santhony.gutierrez@amd.comsystem.ruby.LD.hit_latency_hist::samples 175 284411308Santhony.gutierrez@amd.comsystem.ruby.LD.hit_latency_hist::mean 260.394286 284511308Santhony.gutierrez@amd.comsystem.ruby.LD.hit_latency_hist::gmean 258.339713 284611308Santhony.gutierrez@amd.comsystem.ruby.LD.hit_latency_hist::stdev 42.039376 284711308Santhony.gutierrez@amd.comsystem.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 90 51.43% 51.43% | 84 48.00% 99.43% | 0 0.00% 99.43% | 0 0.00% 99.43% | 1 0.57% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 284811308Santhony.gutierrez@amd.comsystem.ruby.LD.hit_latency_hist::total 175 284911308Santhony.gutierrez@amd.comsystem.ruby.LD.miss_latency_hist::bucket_size 2 285011308Santhony.gutierrez@amd.comsystem.ruby.LD.miss_latency_hist::max_bucket 19 285111308Santhony.gutierrez@amd.comsystem.ruby.LD.miss_latency_hist::samples 16160 285211308Santhony.gutierrez@amd.comsystem.ruby.LD.miss_latency_hist::mean 1.005569 285311308Santhony.gutierrez@amd.comsystem.ruby.LD.miss_latency_hist::gmean 1.000911 285411308Santhony.gutierrez@amd.comsystem.ruby.LD.miss_latency_hist::stdev 0.316580 285511308Santhony.gutierrez@amd.comsystem.ruby.LD.miss_latency_hist | 16155 99.97% 99.97% | 0 0.00% 99.97% | 0 0.00% 99.97% | 0 0.00% 99.97% | 0 0.00% 99.97% | 0 0.00% 99.97% | 0 0.00% 99.97% | 0 0.00% 99.97% | 0 0.00% 99.97% | 5 0.03% 100.00% 285611308Santhony.gutierrez@amd.comsystem.ruby.LD.miss_latency_hist::total 16160 285711308Santhony.gutierrez@amd.comsystem.ruby.ST.latency_hist::bucket_size 128 285811308Santhony.gutierrez@amd.comsystem.ruby.ST.latency_hist::max_bucket 1279 285911308Santhony.gutierrez@amd.comsystem.ruby.ST.latency_hist::samples 10412 286011308Santhony.gutierrez@amd.comsystem.ruby.ST.latency_hist::mean 8.839992 286111308Santhony.gutierrez@amd.comsystem.ruby.ST.latency_hist::gmean 1.186243 286211308Santhony.gutierrez@amd.comsystem.ruby.ST.latency_hist::stdev 45.390081 286311308Santhony.gutierrez@amd.comsystem.ruby.ST.latency_hist | 10090 96.91% 96.91% | 254 2.44% 99.35% | 62 0.60% 99.94% | 0 0.00% 99.94% | 1 0.01% 99.95% | 4 0.04% 99.99% | 1 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 286411308Santhony.gutierrez@amd.comsystem.ruby.ST.latency_hist::total 10412 286511308Santhony.gutierrez@amd.comsystem.ruby.ST.hit_latency_hist::bucket_size 128 286611308Santhony.gutierrez@amd.comsystem.ruby.ST.hit_latency_hist::max_bucket 1279 286711308Santhony.gutierrez@amd.comsystem.ruby.ST.hit_latency_hist::samples 322 286811308Santhony.gutierrez@amd.comsystem.ruby.ST.hit_latency_hist::mean 254.509317 286911308Santhony.gutierrez@amd.comsystem.ruby.ST.hit_latency_hist::gmean 250.282441 287011308Santhony.gutierrez@amd.comsystem.ruby.ST.hit_latency_hist::stdev 65.931487 287111308Santhony.gutierrez@amd.comsystem.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 254 78.88% 78.88% | 62 19.25% 98.14% | 0 0.00% 98.14% | 1 0.31% 98.45% | 4 1.24% 99.69% | 1 0.31% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 287211308Santhony.gutierrez@amd.comsystem.ruby.ST.hit_latency_hist::total 322 287311308Santhony.gutierrez@amd.comsystem.ruby.ST.miss_latency_hist::bucket_size 1 287411308Santhony.gutierrez@amd.comsystem.ruby.ST.miss_latency_hist::max_bucket 9 287511308Santhony.gutierrez@amd.comsystem.ruby.ST.miss_latency_hist::samples 10090 287611308Santhony.gutierrez@amd.comsystem.ruby.ST.miss_latency_hist::mean 1 287711308Santhony.gutierrez@amd.comsystem.ruby.ST.miss_latency_hist::gmean 1 287811308Santhony.gutierrez@amd.comsystem.ruby.ST.miss_latency_hist | 0 0.00% 0.00% | 10090 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 287911308Santhony.gutierrez@amd.comsystem.ruby.ST.miss_latency_hist::total 10090 288011308Santhony.gutierrez@amd.comsystem.ruby.IFETCH.latency_hist::bucket_size 128 288111308Santhony.gutierrez@amd.comsystem.ruby.IFETCH.latency_hist::max_bucket 1279 288211308Santhony.gutierrez@amd.comsystem.ruby.IFETCH.latency_hist::samples 87095 288311308Santhony.gutierrez@amd.comsystem.ruby.IFETCH.latency_hist::mean 4.017395 288411308Santhony.gutierrez@amd.comsystem.ruby.IFETCH.latency_hist::gmean 1.069735 288511308Santhony.gutierrez@amd.comsystem.ruby.IFETCH.latency_hist::stdev 28.134930 288611308Santhony.gutierrez@amd.comsystem.ruby.IFETCH.latency_hist | 86061 98.81% 98.81% | 790 0.91% 99.72% | 224 0.26% 99.98% | 3 0.00% 99.98% | 7 0.01% 99.99% | 9 0.01% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 288711308Santhony.gutierrez@amd.comsystem.ruby.IFETCH.latency_hist::total 87095 288811308Santhony.gutierrez@amd.comsystem.ruby.IFETCH.hit_latency_hist::bucket_size 128 288911308Santhony.gutierrez@amd.comsystem.ruby.IFETCH.hit_latency_hist::max_bucket 1279 289011308Santhony.gutierrez@amd.comsystem.ruby.IFETCH.hit_latency_hist::samples 1034 289111308Santhony.gutierrez@amd.comsystem.ruby.IFETCH.hit_latency_hist::mean 254.218569 289211308Santhony.gutierrez@amd.comsystem.ruby.IFETCH.hit_latency_hist::gmean 250.716467 289311308Santhony.gutierrez@amd.comsystem.ruby.IFETCH.hit_latency_hist::stdev 57.514968 289411308Santhony.gutierrez@amd.comsystem.ruby.IFETCH.hit_latency_hist | 0 0.00% 0.00% | 790 76.40% 76.40% | 224 21.66% 98.07% | 3 0.29% 98.36% | 7 0.68% 99.03% | 9 0.87% 99.90% | 1 0.10% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 289511308Santhony.gutierrez@amd.comsystem.ruby.IFETCH.hit_latency_hist::total 1034 289611308Santhony.gutierrez@amd.comsystem.ruby.IFETCH.miss_latency_hist::bucket_size 2 289711308Santhony.gutierrez@amd.comsystem.ruby.IFETCH.miss_latency_hist::max_bucket 19 289811308Santhony.gutierrez@amd.comsystem.ruby.IFETCH.miss_latency_hist::samples 86061 289911308Santhony.gutierrez@amd.comsystem.ruby.IFETCH.miss_latency_hist::mean 1.011294 290011308Santhony.gutierrez@amd.comsystem.ruby.IFETCH.miss_latency_hist::gmean 1.001849 290111308Santhony.gutierrez@amd.comsystem.ruby.IFETCH.miss_latency_hist::stdev 0.450747 290211308Santhony.gutierrez@amd.comsystem.ruby.IFETCH.miss_latency_hist | 86007 99.94% 99.94% | 0 0.00% 99.94% | 0 0.00% 99.94% | 0 0.00% 99.94% | 0 0.00% 99.94% | 0 0.00% 99.94% | 0 0.00% 99.94% | 0 0.00% 99.94% | 0 0.00% 99.94% | 54 0.06% 100.00% 290311308Santhony.gutierrez@amd.comsystem.ruby.IFETCH.miss_latency_hist::total 86061 290411308Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.latency_hist::bucket_size 32 290511308Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.latency_hist::max_bucket 319 290611308Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.latency_hist::samples 341 290711308Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.latency_hist::mean 4.114370 290811308Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.latency_hist::gmean 1.067644 290911308Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.latency_hist::stdev 28.783090 291011308Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.latency_hist | 337 98.83% 98.83% | 0 0.00% 98.83% | 0 0.00% 98.83% | 0 0.00% 98.83% | 0 0.00% 98.83% | 0 0.00% 98.83% | 0 0.00% 98.83% | 2 0.59% 99.41% | 0 0.00% 99.41% | 2 0.59% 100.00% 291111308Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.latency_hist::total 341 291211308Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.hit_latency_hist::bucket_size 32 291311308Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.hit_latency_hist::max_bucket 319 291411308Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.hit_latency_hist::samples 4 291511308Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.hit_latency_hist::mean 266.500000 291611308Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.hit_latency_hist::gmean 265.077347 291711308Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.hit_latency_hist::stdev 31.754265 291811308Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 2 50.00% 50.00% | 0 0.00% 50.00% | 2 50.00% 100.00% 291911308Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.hit_latency_hist::total 4 292011308Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.miss_latency_hist::bucket_size 1 292111308Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.miss_latency_hist::max_bucket 9 292211308Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.miss_latency_hist::samples 337 292311308Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.miss_latency_hist::mean 1 292411308Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.miss_latency_hist::gmean 1 292511308Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.miss_latency_hist | 0 0.00% 0.00% | 337 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 292611308Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.miss_latency_hist::total 337 292711308Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Read.latency_hist::bucket_size 1 292811308Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Read.latency_hist::max_bucket 9 292911308Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Read.latency_hist::samples 10 293011308Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Read.latency_hist::mean 1 293111308Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Read.latency_hist::gmean 1 293211308Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Read.latency_hist | 0 0.00% 0.00% | 10 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 293311308Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Read.latency_hist::total 10 293411308Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Read.miss_latency_hist::bucket_size 1 293511308Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Read.miss_latency_hist::max_bucket 9 293611308Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Read.miss_latency_hist::samples 10 293711308Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Read.miss_latency_hist::mean 1 293811308Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Read.miss_latency_hist::gmean 1 293911308Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Read.miss_latency_hist | 0 0.00% 0.00% | 10 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 294011308Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Read.miss_latency_hist::total 10 294111308Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Write.latency_hist::bucket_size 1 294211308Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Write.latency_hist::max_bucket 9 294311308Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Write.latency_hist::samples 10 294411308Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Write.latency_hist::mean 1 294511308Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Write.latency_hist::gmean 1 294611308Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Write.latency_hist | 0 0.00% 0.00% | 10 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 294711308Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Write.latency_hist::total 10 294811308Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Write.miss_latency_hist::bucket_size 1 294911308Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Write.miss_latency_hist::max_bucket 9 295011308Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Write.miss_latency_hist::samples 10 295111308Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Write.miss_latency_hist::mean 1 295211308Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Write.miss_latency_hist::gmean 1 295311308Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Write.miss_latency_hist | 0 0.00% 0.00% | 10 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 295411308Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Write.miss_latency_hist::total 10 295511308Santhony.gutierrez@amd.comsystem.ruby.L1Cache.miss_mach_latency_hist::bucket_size 1 295611308Santhony.gutierrez@amd.comsystem.ruby.L1Cache.miss_mach_latency_hist::max_bucket 9 295711308Santhony.gutierrez@amd.comsystem.ruby.L1Cache.miss_mach_latency_hist::samples 112609 295811308Santhony.gutierrez@amd.comsystem.ruby.L1Cache.miss_mach_latency_hist::mean 1 295911308Santhony.gutierrez@amd.comsystem.ruby.L1Cache.miss_mach_latency_hist::gmean 1 296011308Santhony.gutierrez@amd.comsystem.ruby.L1Cache.miss_mach_latency_hist | 0 0.00% 0.00% | 112609 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 296111308Santhony.gutierrez@amd.comsystem.ruby.L1Cache.miss_mach_latency_hist::total 112609 296211308Santhony.gutierrez@amd.comsystem.ruby.L2Cache.miss_mach_latency_hist::bucket_size 2 296311308Santhony.gutierrez@amd.comsystem.ruby.L2Cache.miss_mach_latency_hist::max_bucket 19 296411308Santhony.gutierrez@amd.comsystem.ruby.L2Cache.miss_mach_latency_hist::samples 59 296511308Santhony.gutierrez@amd.comsystem.ruby.L2Cache.miss_mach_latency_hist::mean 19 296611308Santhony.gutierrez@amd.comsystem.ruby.L2Cache.miss_mach_latency_hist::gmean 19.000000 296711308Santhony.gutierrez@amd.comsystem.ruby.L2Cache.miss_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 59 100.00% 100.00% 296811308Santhony.gutierrez@amd.comsystem.ruby.L2Cache.miss_mach_latency_hist::total 59 296911308Santhony.gutierrez@amd.comsystem.ruby.Directory.hit_mach_latency_hist::bucket_size 128 297011308Santhony.gutierrez@amd.comsystem.ruby.Directory.hit_mach_latency_hist::max_bucket 1279 297111308Santhony.gutierrez@amd.comsystem.ruby.Directory.hit_mach_latency_hist::samples 1535 297211308Santhony.gutierrez@amd.comsystem.ruby.Directory.hit_mach_latency_hist::mean 255.015635 297311308Santhony.gutierrez@amd.comsystem.ruby.Directory.hit_mach_latency_hist::gmean 251.519163 297411308Santhony.gutierrez@amd.comsystem.ruby.Directory.hit_mach_latency_hist::stdev 57.825523 297511308Santhony.gutierrez@amd.comsystem.ruby.Directory.hit_mach_latency_hist | 0 0.00% 0.00% | 1136 74.01% 74.01% | 372 24.23% 98.24% | 3 0.20% 98.44% | 8 0.52% 98.96% | 14 0.91% 99.87% | 2 0.13% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 297611308Santhony.gutierrez@amd.comsystem.ruby.Directory.hit_mach_latency_hist::total 1535 297711308Santhony.gutierrez@amd.comsystem.ruby.LD.L1Cache.miss_type_mach_latency_hist::bucket_size 1 297811308Santhony.gutierrez@amd.comsystem.ruby.LD.L1Cache.miss_type_mach_latency_hist::max_bucket 9 297911308Santhony.gutierrez@amd.comsystem.ruby.LD.L1Cache.miss_type_mach_latency_hist::samples 16155 298011308Santhony.gutierrez@amd.comsystem.ruby.LD.L1Cache.miss_type_mach_latency_hist::mean 1 298111308Santhony.gutierrez@amd.comsystem.ruby.LD.L1Cache.miss_type_mach_latency_hist::gmean 1 298211308Santhony.gutierrez@amd.comsystem.ruby.LD.L1Cache.miss_type_mach_latency_hist | 0 0.00% 0.00% | 16155 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 298311308Santhony.gutierrez@amd.comsystem.ruby.LD.L1Cache.miss_type_mach_latency_hist::total 16155 298411308Santhony.gutierrez@amd.comsystem.ruby.LD.L2Cache.miss_type_mach_latency_hist::bucket_size 2 298511308Santhony.gutierrez@amd.comsystem.ruby.LD.L2Cache.miss_type_mach_latency_hist::max_bucket 19 298611308Santhony.gutierrez@amd.comsystem.ruby.LD.L2Cache.miss_type_mach_latency_hist::samples 5 298711308Santhony.gutierrez@amd.comsystem.ruby.LD.L2Cache.miss_type_mach_latency_hist::mean 19 298811308Santhony.gutierrez@amd.comsystem.ruby.LD.L2Cache.miss_type_mach_latency_hist::gmean 19.000000 298911308Santhony.gutierrez@amd.comsystem.ruby.LD.L2Cache.miss_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 5 100.00% 100.00% 299011308Santhony.gutierrez@amd.comsystem.ruby.LD.L2Cache.miss_type_mach_latency_hist::total 5 299111308Santhony.gutierrez@amd.comsystem.ruby.LD.Directory.hit_type_mach_latency_hist::bucket_size 128 299211308Santhony.gutierrez@amd.comsystem.ruby.LD.Directory.hit_type_mach_latency_hist::max_bucket 1279 299311308Santhony.gutierrez@amd.comsystem.ruby.LD.Directory.hit_type_mach_latency_hist::samples 175 299411308Santhony.gutierrez@amd.comsystem.ruby.LD.Directory.hit_type_mach_latency_hist::mean 260.394286 299511308Santhony.gutierrez@amd.comsystem.ruby.LD.Directory.hit_type_mach_latency_hist::gmean 258.339713 299611308Santhony.gutierrez@amd.comsystem.ruby.LD.Directory.hit_type_mach_latency_hist::stdev 42.039376 299711308Santhony.gutierrez@amd.comsystem.ruby.LD.Directory.hit_type_mach_latency_hist | 0 0.00% 0.00% | 90 51.43% 51.43% | 84 48.00% 99.43% | 0 0.00% 99.43% | 0 0.00% 99.43% | 1 0.57% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 299811308Santhony.gutierrez@amd.comsystem.ruby.LD.Directory.hit_type_mach_latency_hist::total 175 299911308Santhony.gutierrez@amd.comsystem.ruby.ST.L1Cache.miss_type_mach_latency_hist::bucket_size 1 300011308Santhony.gutierrez@amd.comsystem.ruby.ST.L1Cache.miss_type_mach_latency_hist::max_bucket 9 300111308Santhony.gutierrez@amd.comsystem.ruby.ST.L1Cache.miss_type_mach_latency_hist::samples 10090 300211308Santhony.gutierrez@amd.comsystem.ruby.ST.L1Cache.miss_type_mach_latency_hist::mean 1 300311308Santhony.gutierrez@amd.comsystem.ruby.ST.L1Cache.miss_type_mach_latency_hist::gmean 1 300411308Santhony.gutierrez@amd.comsystem.ruby.ST.L1Cache.miss_type_mach_latency_hist | 0 0.00% 0.00% | 10090 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 300511308Santhony.gutierrez@amd.comsystem.ruby.ST.L1Cache.miss_type_mach_latency_hist::total 10090 300611308Santhony.gutierrez@amd.comsystem.ruby.ST.Directory.hit_type_mach_latency_hist::bucket_size 128 300711308Santhony.gutierrez@amd.comsystem.ruby.ST.Directory.hit_type_mach_latency_hist::max_bucket 1279 300811308Santhony.gutierrez@amd.comsystem.ruby.ST.Directory.hit_type_mach_latency_hist::samples 322 300911308Santhony.gutierrez@amd.comsystem.ruby.ST.Directory.hit_type_mach_latency_hist::mean 254.509317 301011308Santhony.gutierrez@amd.comsystem.ruby.ST.Directory.hit_type_mach_latency_hist::gmean 250.282441 301111308Santhony.gutierrez@amd.comsystem.ruby.ST.Directory.hit_type_mach_latency_hist::stdev 65.931487 301211308Santhony.gutierrez@amd.comsystem.ruby.ST.Directory.hit_type_mach_latency_hist | 0 0.00% 0.00% | 254 78.88% 78.88% | 62 19.25% 98.14% | 0 0.00% 98.14% | 1 0.31% 98.45% | 4 1.24% 99.69% | 1 0.31% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 301311308Santhony.gutierrez@amd.comsystem.ruby.ST.Directory.hit_type_mach_latency_hist::total 322 301411308Santhony.gutierrez@amd.comsystem.ruby.IFETCH.L1Cache.miss_type_mach_latency_hist::bucket_size 1 301511308Santhony.gutierrez@amd.comsystem.ruby.IFETCH.L1Cache.miss_type_mach_latency_hist::max_bucket 9 301611308Santhony.gutierrez@amd.comsystem.ruby.IFETCH.L1Cache.miss_type_mach_latency_hist::samples 86007 301711308Santhony.gutierrez@amd.comsystem.ruby.IFETCH.L1Cache.miss_type_mach_latency_hist::mean 1 301811308Santhony.gutierrez@amd.comsystem.ruby.IFETCH.L1Cache.miss_type_mach_latency_hist::gmean 1 301911308Santhony.gutierrez@amd.comsystem.ruby.IFETCH.L1Cache.miss_type_mach_latency_hist | 0 0.00% 0.00% | 86007 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 302011308Santhony.gutierrez@amd.comsystem.ruby.IFETCH.L1Cache.miss_type_mach_latency_hist::total 86007 302111308Santhony.gutierrez@amd.comsystem.ruby.IFETCH.L2Cache.miss_type_mach_latency_hist::bucket_size 2 302211308Santhony.gutierrez@amd.comsystem.ruby.IFETCH.L2Cache.miss_type_mach_latency_hist::max_bucket 19 302311308Santhony.gutierrez@amd.comsystem.ruby.IFETCH.L2Cache.miss_type_mach_latency_hist::samples 54 302411308Santhony.gutierrez@amd.comsystem.ruby.IFETCH.L2Cache.miss_type_mach_latency_hist::mean 19 302511308Santhony.gutierrez@amd.comsystem.ruby.IFETCH.L2Cache.miss_type_mach_latency_hist::gmean 19.000000 302611308Santhony.gutierrez@amd.comsystem.ruby.IFETCH.L2Cache.miss_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 54 100.00% 100.00% 302711308Santhony.gutierrez@amd.comsystem.ruby.IFETCH.L2Cache.miss_type_mach_latency_hist::total 54 302811308Santhony.gutierrez@amd.comsystem.ruby.IFETCH.Directory.hit_type_mach_latency_hist::bucket_size 128 302911308Santhony.gutierrez@amd.comsystem.ruby.IFETCH.Directory.hit_type_mach_latency_hist::max_bucket 1279 303011308Santhony.gutierrez@amd.comsystem.ruby.IFETCH.Directory.hit_type_mach_latency_hist::samples 1034 303111308Santhony.gutierrez@amd.comsystem.ruby.IFETCH.Directory.hit_type_mach_latency_hist::mean 254.218569 303211308Santhony.gutierrez@amd.comsystem.ruby.IFETCH.Directory.hit_type_mach_latency_hist::gmean 250.716467 303311308Santhony.gutierrez@amd.comsystem.ruby.IFETCH.Directory.hit_type_mach_latency_hist::stdev 57.514968 303411308Santhony.gutierrez@amd.comsystem.ruby.IFETCH.Directory.hit_type_mach_latency_hist | 0 0.00% 0.00% | 790 76.40% 76.40% | 224 21.66% 98.07% | 3 0.29% 98.36% | 7 0.68% 99.03% | 9 0.87% 99.90% | 1 0.10% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 303511308Santhony.gutierrez@amd.comsystem.ruby.IFETCH.Directory.hit_type_mach_latency_hist::total 1034 303611308Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist::bucket_size 1 303711308Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist::max_bucket 9 303811308Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist::samples 337 303911308Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist::mean 1 304011308Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist::gmean 1 304111308Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist | 0 0.00% 0.00% | 337 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 304211308Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist::total 337 304311308Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.Directory.hit_type_mach_latency_hist::bucket_size 32 304411308Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.Directory.hit_type_mach_latency_hist::max_bucket 319 304511308Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.Directory.hit_type_mach_latency_hist::samples 4 304611308Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.Directory.hit_type_mach_latency_hist::mean 266.500000 304711308Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.Directory.hit_type_mach_latency_hist::gmean 265.077347 304811308Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.Directory.hit_type_mach_latency_hist::stdev 31.754265 304911308Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.Directory.hit_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 2 50.00% 50.00% | 0 0.00% 50.00% | 2 50.00% 100.00% 305011308Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.Directory.hit_type_mach_latency_hist::total 4 305111308Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Read.L1Cache.miss_type_mach_latency_hist::bucket_size 1 305211308Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Read.L1Cache.miss_type_mach_latency_hist::max_bucket 9 305311308Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Read.L1Cache.miss_type_mach_latency_hist::samples 10 305411308Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Read.L1Cache.miss_type_mach_latency_hist::mean 1 305511308Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Read.L1Cache.miss_type_mach_latency_hist::gmean 1 305611308Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Read.L1Cache.miss_type_mach_latency_hist | 0 0.00% 0.00% | 10 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 305711308Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Read.L1Cache.miss_type_mach_latency_hist::total 10 305811308Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Write.L1Cache.miss_type_mach_latency_hist::bucket_size 1 305911308Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Write.L1Cache.miss_type_mach_latency_hist::max_bucket 9 306011308Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Write.L1Cache.miss_type_mach_latency_hist::samples 10 306111308Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Write.L1Cache.miss_type_mach_latency_hist::mean 1 306211308Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Write.L1Cache.miss_type_mach_latency_hist::gmean 1 306311308Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Write.L1Cache.miss_type_mach_latency_hist | 0 0.00% 0.00% | 10 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 306411308Santhony.gutierrez@amd.comsystem.ruby.Locked_RMW_Write.L1Cache.miss_type_mach_latency_hist::total 10 306511308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.C0_Load_L1miss 180 0.00% 0.00% 306611308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.C0_Load_L1hit 16155 0.00% 0.00% 306711308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.Ifetch0_L1hit 86007 0.00% 0.00% 306811308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.Ifetch0_L1miss 1088 0.00% 0.00% 306911308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.C0_Store_L1miss 325 0.00% 0.00% 307011308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.C0_Store_L1hit 10448 0.00% 0.00% 307111308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.NB_AckS 1034 0.00% 0.00% 307211308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.NB_AckM 326 0.00% 0.00% 307311308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.NB_AckE 175 0.00% 0.00% 307411308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.L1I_Repl 589 0.00% 0.00% 307511308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.L1D0_Repl 24 0.00% 0.00% 307611308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.L2_to_L1D0 5 0.00% 0.00% 307711308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.L2_to_L1I 54 0.00% 0.00% 307811308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.PrbInvData 18 0.00% 0.00% 307911308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.PrbShrData 7 0.00% 0.00% 308011308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.I.C0_Load_L1miss 175 0.00% 0.00% 308111308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.I.Ifetch0_L1miss 1034 0.00% 0.00% 308211308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.I.C0_Store_L1miss 325 0.00% 0.00% 308311308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.I.PrbInvData 17 0.00% 0.00% 308411308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.I.PrbShrData 5 0.00% 0.00% 308511308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.S.Ifetch0_L1hit 86007 0.00% 0.00% 308611308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.S.Ifetch0_L1miss 54 0.00% 0.00% 308711308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.S.L1I_Repl 589 0.00% 0.00% 308811308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.E0.C0_Load_L1miss 2 0.00% 0.00% 308911308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.E0.C0_Load_L1hit 3356 0.00% 0.00% 309011308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.E0.C0_Store_L1hit 46 0.00% 0.00% 309111308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.E0.L1D0_Repl 16 0.00% 0.00% 309211308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.E0.PrbShrData 1 0.00% 0.00% 309311308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.O.C0_Load_L1hit 3 0.00% 0.00% 309411308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.O.C0_Store_L1hit 1 0.00% 0.00% 309511308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.M0.C0_Load_L1miss 3 0.00% 0.00% 309611308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.M0.C0_Load_L1hit 12796 0.00% 0.00% 309711308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.M0.C0_Store_L1hit 10401 0.00% 0.00% 309811308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.M0.L1D0_Repl 8 0.00% 0.00% 309911308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.M0.PrbInvData 1 0.00% 0.00% 310011308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.M0.PrbShrData 1 0.00% 0.00% 310111308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.I_M0.NB_AckM 325 0.00% 0.00% 310211308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.I_E0S.NB_AckE 175 0.00% 0.00% 310311308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.Si_F0.L2_to_L1I 54 0.00% 0.00% 310411308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.O_M0.NB_AckM 1 0.00% 0.00% 310511308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.S0.NB_AckS 1034 0.00% 0.00% 310611308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.E0_F.L2_to_L1D0 2 0.00% 0.00% 310711308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.M0_F.L2_to_L1D0 3 0.00% 0.00% 310811308Santhony.gutierrez@amd.comsystem.ruby.Directory_Controller.RdBlkS 1034 0.00% 0.00% 310911308Santhony.gutierrez@amd.comsystem.ruby.Directory_Controller.RdBlkM 326 0.00% 0.00% 311011308Santhony.gutierrez@amd.comsystem.ruby.Directory_Controller.RdBlk 182 0.00% 0.00% 311111308Santhony.gutierrez@amd.comsystem.ruby.Directory_Controller.WriteThrough 16 0.00% 0.00% 311211308Santhony.gutierrez@amd.comsystem.ruby.Directory_Controller.Atomic 3 0.00% 0.00% 311311308Santhony.gutierrez@amd.comsystem.ruby.Directory_Controller.CPUPrbResp 1560 0.00% 0.00% 311411308Santhony.gutierrez@amd.comsystem.ruby.Directory_Controller.ProbeAcksComplete 1560 0.00% 0.00% 311511308Santhony.gutierrez@amd.comsystem.ruby.Directory_Controller.MemData 1560 0.00% 0.00% 311611308Santhony.gutierrez@amd.comsystem.ruby.Directory_Controller.CoreUnblock 1541 0.00% 0.00% 311711308Santhony.gutierrez@amd.comsystem.ruby.Directory_Controller.UnblockWriteThrough 18 0.00% 0.00% 311811308Santhony.gutierrez@amd.comsystem.ruby.Directory_Controller.U.RdBlkS 1034 0.00% 0.00% 311911308Santhony.gutierrez@amd.comsystem.ruby.Directory_Controller.U.RdBlkM 326 0.00% 0.00% 312011308Santhony.gutierrez@amd.comsystem.ruby.Directory_Controller.U.RdBlk 182 0.00% 0.00% 312111308Santhony.gutierrez@amd.comsystem.ruby.Directory_Controller.U.WriteThrough 16 0.00% 0.00% 312211308Santhony.gutierrez@amd.comsystem.ruby.Directory_Controller.U.Atomic 2 0.00% 0.00% 312311308Santhony.gutierrez@amd.comsystem.ruby.Directory_Controller.BS_M.MemData 1034 0.00% 0.00% 312411308Santhony.gutierrez@amd.comsystem.ruby.Directory_Controller.BM_M.MemData 326 0.00% 0.00% 312511308Santhony.gutierrez@amd.comsystem.ruby.Directory_Controller.B_M.MemData 175 0.00% 0.00% 312611308Santhony.gutierrez@amd.comsystem.ruby.Directory_Controller.BS_PM.CPUPrbResp 1034 0.00% 0.00% 312711308Santhony.gutierrez@amd.comsystem.ruby.Directory_Controller.BS_PM.ProbeAcksComplete 1034 0.00% 0.00% 312811308Santhony.gutierrez@amd.comsystem.ruby.Directory_Controller.BM_PM.Atomic 1 0.00% 0.00% 312911308Santhony.gutierrez@amd.comsystem.ruby.Directory_Controller.BM_PM.CPUPrbResp 326 0.00% 0.00% 313011308Santhony.gutierrez@amd.comsystem.ruby.Directory_Controller.BM_PM.ProbeAcksComplete 326 0.00% 0.00% 313111308Santhony.gutierrez@amd.comsystem.ruby.Directory_Controller.BM_PM.MemData 18 0.00% 0.00% 313211308Santhony.gutierrez@amd.comsystem.ruby.Directory_Controller.B_PM.CPUPrbResp 175 0.00% 0.00% 313311308Santhony.gutierrez@amd.comsystem.ruby.Directory_Controller.B_PM.ProbeAcksComplete 175 0.00% 0.00% 313411308Santhony.gutierrez@amd.comsystem.ruby.Directory_Controller.B_PM.MemData 7 0.00% 0.00% 313511308Santhony.gutierrez@amd.comsystem.ruby.Directory_Controller.BM_Pm.CPUPrbResp 18 0.00% 0.00% 313611308Santhony.gutierrez@amd.comsystem.ruby.Directory_Controller.BM_Pm.ProbeAcksComplete 18 0.00% 0.00% 313711308Santhony.gutierrez@amd.comsystem.ruby.Directory_Controller.B_Pm.CPUPrbResp 7 0.00% 0.00% 313811308Santhony.gutierrez@amd.comsystem.ruby.Directory_Controller.B_Pm.ProbeAcksComplete 7 0.00% 0.00% 313911308Santhony.gutierrez@amd.comsystem.ruby.Directory_Controller.B.CoreUnblock 1541 0.00% 0.00% 314011308Santhony.gutierrez@amd.comsystem.ruby.Directory_Controller.B.UnblockWriteThrough 18 0.00% 0.00% 314111308Santhony.gutierrez@amd.comsystem.ruby.SQC_Controller.Fetch 86 0.00% 0.00% 314211308Santhony.gutierrez@amd.comsystem.ruby.SQC_Controller.Data 5 0.00% 0.00% 314311308Santhony.gutierrez@amd.comsystem.ruby.SQC_Controller.I.Fetch 5 0.00% 0.00% 314411308Santhony.gutierrez@amd.comsystem.ruby.SQC_Controller.I.Data 5 0.00% 0.00% 314511308Santhony.gutierrez@amd.comsystem.ruby.SQC_Controller.V.Fetch 81 0.00% 0.00% 314611308Santhony.gutierrez@amd.comsystem.ruby.TCC_Controller.RdBlk 9 0.00% 0.00% 314711308Santhony.gutierrez@amd.comsystem.ruby.TCC_Controller.WrVicBlk 16 0.00% 0.00% 314811308Santhony.gutierrez@amd.comsystem.ruby.TCC_Controller.Atomic 2 0.00% 0.00% 314911308Santhony.gutierrez@amd.comsystem.ruby.TCC_Controller.AtomicDone 1 0.00% 0.00% 315011308Santhony.gutierrez@amd.comsystem.ruby.TCC_Controller.Data 9 0.00% 0.00% 315111308Santhony.gutierrez@amd.comsystem.ruby.TCC_Controller.PrbInv 1535 0.00% 0.00% 315211308Santhony.gutierrez@amd.comsystem.ruby.TCC_Controller.WBAck 16 0.00% 0.00% 315311308Santhony.gutierrez@amd.comsystem.ruby.TCC_Controller.V.PrbInv 1 0.00% 0.00% 315411308Santhony.gutierrez@amd.comsystem.ruby.TCC_Controller.I.RdBlk 7 0.00% 0.00% 315511308Santhony.gutierrez@amd.comsystem.ruby.TCC_Controller.I.WrVicBlk 16 0.00% 0.00% 315611308Santhony.gutierrez@amd.comsystem.ruby.TCC_Controller.I.Atomic 1 0.00% 0.00% 315711308Santhony.gutierrez@amd.comsystem.ruby.TCC_Controller.I.PrbInv 1534 0.00% 0.00% 315811308Santhony.gutierrez@amd.comsystem.ruby.TCC_Controller.I.WBAck 16 0.00% 0.00% 315911308Santhony.gutierrez@amd.comsystem.ruby.TCC_Controller.IV.RdBlk 2 0.00% 0.00% 316011308Santhony.gutierrez@amd.comsystem.ruby.TCC_Controller.IV.Data 7 0.00% 0.00% 316111308Santhony.gutierrez@amd.comsystem.ruby.TCC_Controller.A.Atomic 1 0.00% 0.00% 316211308Santhony.gutierrez@amd.comsystem.ruby.TCC_Controller.A.AtomicDone 1 0.00% 0.00% 316311308Santhony.gutierrez@amd.comsystem.ruby.TCC_Controller.A.Data 2 0.00% 0.00% 316411308Santhony.gutierrez@amd.comsystem.ruby.TCP_Controller.Load | 5 50.00% 50.00% | 5 50.00% 100.00% 316511308Santhony.gutierrez@amd.comsystem.ruby.TCP_Controller.Load::total 10 316611308Santhony.gutierrez@amd.comsystem.ruby.TCP_Controller.StoreThrough | 8 50.00% 50.00% | 8 50.00% 100.00% 316711308Santhony.gutierrez@amd.comsystem.ruby.TCP_Controller.StoreThrough::total 16 316811308Santhony.gutierrez@amd.comsystem.ruby.TCP_Controller.Atomic | 1 50.00% 50.00% | 1 50.00% 100.00% 316911308Santhony.gutierrez@amd.comsystem.ruby.TCP_Controller.Atomic::total 2 317011308Santhony.gutierrez@amd.comsystem.ruby.TCP_Controller.Flush | 768 50.00% 50.00% | 768 50.00% 100.00% 317111308Santhony.gutierrez@amd.comsystem.ruby.TCP_Controller.Flush::total 1536 317211308Santhony.gutierrez@amd.comsystem.ruby.TCP_Controller.Evict | 512 50.00% 50.00% | 512 50.00% 100.00% 317311308Santhony.gutierrez@amd.comsystem.ruby.TCP_Controller.Evict::total 1024 317411308Santhony.gutierrez@amd.comsystem.ruby.TCP_Controller.TCC_Ack | 3 50.00% 50.00% | 3 50.00% 100.00% 317511308Santhony.gutierrez@amd.comsystem.ruby.TCP_Controller.TCC_Ack::total 6 317611308Santhony.gutierrez@amd.comsystem.ruby.TCP_Controller.TCC_AckWB | 8 50.00% 50.00% | 8 50.00% 100.00% 317711308Santhony.gutierrez@amd.comsystem.ruby.TCP_Controller.TCC_AckWB::total 16 317811308Santhony.gutierrez@amd.comsystem.ruby.TCP_Controller.I.Load | 2 50.00% 50.00% | 2 50.00% 100.00% 317911308Santhony.gutierrez@amd.comsystem.ruby.TCP_Controller.I.Load::total 4 318011308Santhony.gutierrez@amd.comsystem.ruby.TCP_Controller.I.StoreThrough | 8 50.00% 50.00% | 8 50.00% 100.00% 318111308Santhony.gutierrez@amd.comsystem.ruby.TCP_Controller.I.StoreThrough::total 16 318211308Santhony.gutierrez@amd.comsystem.ruby.TCP_Controller.I.Atomic | 1 50.00% 50.00% | 1 50.00% 100.00% 318311308Santhony.gutierrez@amd.comsystem.ruby.TCP_Controller.I.Atomic::total 2 318411308Santhony.gutierrez@amd.comsystem.ruby.TCP_Controller.I.Flush | 766 50.00% 50.00% | 766 50.00% 100.00% 318511308Santhony.gutierrez@amd.comsystem.ruby.TCP_Controller.I.Flush::total 1532 318611308Santhony.gutierrez@amd.comsystem.ruby.TCP_Controller.I.Evict | 510 50.00% 50.00% | 510 50.00% 100.00% 318711308Santhony.gutierrez@amd.comsystem.ruby.TCP_Controller.I.Evict::total 1020 318811308Santhony.gutierrez@amd.comsystem.ruby.TCP_Controller.I.TCC_Ack | 2 50.00% 50.00% | 2 50.00% 100.00% 318911308Santhony.gutierrez@amd.comsystem.ruby.TCP_Controller.I.TCC_Ack::total 4 319011308Santhony.gutierrez@amd.comsystem.ruby.TCP_Controller.I.TCC_AckWB | 8 50.00% 50.00% | 8 50.00% 100.00% 319111308Santhony.gutierrez@amd.comsystem.ruby.TCP_Controller.I.TCC_AckWB::total 16 319211308Santhony.gutierrez@amd.comsystem.ruby.TCP_Controller.V.Load | 3 50.00% 50.00% | 3 50.00% 100.00% 319311308Santhony.gutierrez@amd.comsystem.ruby.TCP_Controller.V.Load::total 6 319411308Santhony.gutierrez@amd.comsystem.ruby.TCP_Controller.V.Flush | 2 50.00% 50.00% | 2 50.00% 100.00% 319511308Santhony.gutierrez@amd.comsystem.ruby.TCP_Controller.V.Flush::total 4 319611308Santhony.gutierrez@amd.comsystem.ruby.TCP_Controller.V.Evict | 2 50.00% 50.00% | 2 50.00% 100.00% 319711308Santhony.gutierrez@amd.comsystem.ruby.TCP_Controller.V.Evict::total 4 319811308Santhony.gutierrez@amd.comsystem.ruby.TCP_Controller.A.TCC_Ack | 1 50.00% 50.00% | 1 50.00% 100.00% 319911308Santhony.gutierrez@amd.comsystem.ruby.TCP_Controller.A.TCC_Ack::total 2 320011308Santhony.gutierrez@amd.com 320111308Santhony.gutierrez@amd.com---------- End Simulation Statistics ---------- 3202