stats.txt revision 11312:3d7a85d71bd1
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000056 # Number of seconds simulated 4sim_ticks 55844000 # Number of ticks simulated 5final_tick 55844000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 84620 # Simulator instruction rate (inst/s) 8host_op_rate 152747 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 826790083 # Simulator tick rate (ticks/s) 10host_mem_usage 634592 # Number of bytes of host memory used 11host_seconds 0.07 # Real time elapsed on the host 12sim_insts 5712 # Number of instructions simulated 13sim_ops 10314 # Number of ops (including micro ops) simulated 14system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.mem_ctrl.bytes_read::cpu.inst 14656 # Number of bytes read from this memory 17system.mem_ctrl.bytes_read::cpu.data 8640 # Number of bytes read from this memory 18system.mem_ctrl.bytes_read::total 23296 # Number of bytes read from this memory 19system.mem_ctrl.bytes_inst_read::cpu.inst 14656 # Number of instructions bytes read from this memory 20system.mem_ctrl.bytes_inst_read::total 14656 # Number of instructions bytes read from this memory 21system.mem_ctrl.num_reads::cpu.inst 229 # Number of read requests responded to by this memory 22system.mem_ctrl.num_reads::cpu.data 135 # Number of read requests responded to by this memory 23system.mem_ctrl.num_reads::total 364 # Number of read requests responded to by this memory 24system.mem_ctrl.bw_read::cpu.inst 262445384 # Total read bandwidth from this memory (bytes/s) 25system.mem_ctrl.bw_read::cpu.data 154716711 # Total read bandwidth from this memory (bytes/s) 26system.mem_ctrl.bw_read::total 417162094 # Total read bandwidth from this memory (bytes/s) 27system.mem_ctrl.bw_inst_read::cpu.inst 262445384 # Instruction read bandwidth from this memory (bytes/s) 28system.mem_ctrl.bw_inst_read::total 262445384 # Instruction read bandwidth from this memory (bytes/s) 29system.mem_ctrl.bw_total::cpu.inst 262445384 # Total bandwidth to/from this memory (bytes/s) 30system.mem_ctrl.bw_total::cpu.data 154716711 # Total bandwidth to/from this memory (bytes/s) 31system.mem_ctrl.bw_total::total 417162094 # Total bandwidth to/from this memory (bytes/s) 32system.mem_ctrl.readReqs 364 # Number of read requests accepted 33system.mem_ctrl.writeReqs 0 # Number of write requests accepted 34system.mem_ctrl.readBursts 364 # Number of DRAM read bursts, including those serviced by the write queue 35system.mem_ctrl.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 36system.mem_ctrl.bytesReadDRAM 23296 # Total number of bytes read from DRAM 37system.mem_ctrl.bytesReadWrQ 0 # Total number of bytes read from write queue 38system.mem_ctrl.bytesWritten 0 # Total number of bytes written to DRAM 39system.mem_ctrl.bytesReadSys 23296 # Total read bytes from the system interface side 40system.mem_ctrl.bytesWrittenSys 0 # Total written bytes from the system interface side 41system.mem_ctrl.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 42system.mem_ctrl.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 43system.mem_ctrl.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 44system.mem_ctrl.perBankRdBursts::0 30 # Per bank write bursts 45system.mem_ctrl.perBankRdBursts::1 1 # Per bank write bursts 46system.mem_ctrl.perBankRdBursts::2 5 # Per bank write bursts 47system.mem_ctrl.perBankRdBursts::3 8 # Per bank write bursts 48system.mem_ctrl.perBankRdBursts::4 43 # Per bank write bursts 49system.mem_ctrl.perBankRdBursts::5 40 # Per bank write bursts 50system.mem_ctrl.perBankRdBursts::6 13 # Per bank write bursts 51system.mem_ctrl.perBankRdBursts::7 24 # Per bank write bursts 52system.mem_ctrl.perBankRdBursts::8 17 # Per bank write bursts 53system.mem_ctrl.perBankRdBursts::9 71 # Per bank write bursts 54system.mem_ctrl.perBankRdBursts::10 62 # Per bank write bursts 55system.mem_ctrl.perBankRdBursts::11 14 # Per bank write bursts 56system.mem_ctrl.perBankRdBursts::12 2 # Per bank write bursts 57system.mem_ctrl.perBankRdBursts::13 14 # Per bank write bursts 58system.mem_ctrl.perBankRdBursts::14 4 # Per bank write bursts 59system.mem_ctrl.perBankRdBursts::15 16 # Per bank write bursts 60system.mem_ctrl.perBankWrBursts::0 0 # Per bank write bursts 61system.mem_ctrl.perBankWrBursts::1 0 # Per bank write bursts 62system.mem_ctrl.perBankWrBursts::2 0 # Per bank write bursts 63system.mem_ctrl.perBankWrBursts::3 0 # Per bank write bursts 64system.mem_ctrl.perBankWrBursts::4 0 # Per bank write bursts 65system.mem_ctrl.perBankWrBursts::5 0 # Per bank write bursts 66system.mem_ctrl.perBankWrBursts::6 0 # Per bank write bursts 67system.mem_ctrl.perBankWrBursts::7 0 # Per bank write bursts 68system.mem_ctrl.perBankWrBursts::8 0 # Per bank write bursts 69system.mem_ctrl.perBankWrBursts::9 0 # Per bank write bursts 70system.mem_ctrl.perBankWrBursts::10 0 # Per bank write bursts 71system.mem_ctrl.perBankWrBursts::11 0 # Per bank write bursts 72system.mem_ctrl.perBankWrBursts::12 0 # Per bank write bursts 73system.mem_ctrl.perBankWrBursts::13 0 # Per bank write bursts 74system.mem_ctrl.perBankWrBursts::14 0 # Per bank write bursts 75system.mem_ctrl.perBankWrBursts::15 0 # Per bank write bursts 76system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry 77system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry 78system.mem_ctrl.totGap 55714000 # Total gap between requests 79system.mem_ctrl.readPktSize::0 0 # Read request sizes (log2) 80system.mem_ctrl.readPktSize::1 0 # Read request sizes (log2) 81system.mem_ctrl.readPktSize::2 0 # Read request sizes (log2) 82system.mem_ctrl.readPktSize::3 0 # Read request sizes (log2) 83system.mem_ctrl.readPktSize::4 0 # Read request sizes (log2) 84system.mem_ctrl.readPktSize::5 0 # Read request sizes (log2) 85system.mem_ctrl.readPktSize::6 364 # Read request sizes (log2) 86system.mem_ctrl.writePktSize::0 0 # Write request sizes (log2) 87system.mem_ctrl.writePktSize::1 0 # Write request sizes (log2) 88system.mem_ctrl.writePktSize::2 0 # Write request sizes (log2) 89system.mem_ctrl.writePktSize::3 0 # Write request sizes (log2) 90system.mem_ctrl.writePktSize::4 0 # Write request sizes (log2) 91system.mem_ctrl.writePktSize::5 0 # Write request sizes (log2) 92system.mem_ctrl.writePktSize::6 0 # Write request sizes (log2) 93system.mem_ctrl.rdQLenPdf::0 364 # What read queue length does an incoming req see 94system.mem_ctrl.rdQLenPdf::1 0 # What read queue length does an incoming req see 95system.mem_ctrl.rdQLenPdf::2 0 # What read queue length does an incoming req see 96system.mem_ctrl.rdQLenPdf::3 0 # What read queue length does an incoming req see 97system.mem_ctrl.rdQLenPdf::4 0 # What read queue length does an incoming req see 98system.mem_ctrl.rdQLenPdf::5 0 # What read queue length does an incoming req see 99system.mem_ctrl.rdQLenPdf::6 0 # What read queue length does an incoming req see 100system.mem_ctrl.rdQLenPdf::7 0 # What read queue length does an incoming req see 101system.mem_ctrl.rdQLenPdf::8 0 # What read queue length does an incoming req see 102system.mem_ctrl.rdQLenPdf::9 0 # What read queue length does an incoming req see 103system.mem_ctrl.rdQLenPdf::10 0 # What read queue length does an incoming req see 104system.mem_ctrl.rdQLenPdf::11 0 # What read queue length does an incoming req see 105system.mem_ctrl.rdQLenPdf::12 0 # What read queue length does an incoming req see 106system.mem_ctrl.rdQLenPdf::13 0 # What read queue length does an incoming req see 107system.mem_ctrl.rdQLenPdf::14 0 # What read queue length does an incoming req see 108system.mem_ctrl.rdQLenPdf::15 0 # What read queue length does an incoming req see 109system.mem_ctrl.rdQLenPdf::16 0 # What read queue length does an incoming req see 110system.mem_ctrl.rdQLenPdf::17 0 # What read queue length does an incoming req see 111system.mem_ctrl.rdQLenPdf::18 0 # What read queue length does an incoming req see 112system.mem_ctrl.rdQLenPdf::19 0 # What read queue length does an incoming req see 113system.mem_ctrl.rdQLenPdf::20 0 # What read queue length does an incoming req see 114system.mem_ctrl.rdQLenPdf::21 0 # What read queue length does an incoming req see 115system.mem_ctrl.rdQLenPdf::22 0 # What read queue length does an incoming req see 116system.mem_ctrl.rdQLenPdf::23 0 # What read queue length does an incoming req see 117system.mem_ctrl.rdQLenPdf::24 0 # What read queue length does an incoming req see 118system.mem_ctrl.rdQLenPdf::25 0 # What read queue length does an incoming req see 119system.mem_ctrl.rdQLenPdf::26 0 # What read queue length does an incoming req see 120system.mem_ctrl.rdQLenPdf::27 0 # What read queue length does an incoming req see 121system.mem_ctrl.rdQLenPdf::28 0 # What read queue length does an incoming req see 122system.mem_ctrl.rdQLenPdf::29 0 # What read queue length does an incoming req see 123system.mem_ctrl.rdQLenPdf::30 0 # What read queue length does an incoming req see 124system.mem_ctrl.rdQLenPdf::31 0 # What read queue length does an incoming req see 125system.mem_ctrl.wrQLenPdf::0 0 # What write queue length does an incoming req see 126system.mem_ctrl.wrQLenPdf::1 0 # What write queue length does an incoming req see 127system.mem_ctrl.wrQLenPdf::2 0 # What write queue length does an incoming req see 128system.mem_ctrl.wrQLenPdf::3 0 # What write queue length does an incoming req see 129system.mem_ctrl.wrQLenPdf::4 0 # What write queue length does an incoming req see 130system.mem_ctrl.wrQLenPdf::5 0 # What write queue length does an incoming req see 131system.mem_ctrl.wrQLenPdf::6 0 # What write queue length does an incoming req see 132system.mem_ctrl.wrQLenPdf::7 0 # What write queue length does an incoming req see 133system.mem_ctrl.wrQLenPdf::8 0 # What write queue length does an incoming req see 134system.mem_ctrl.wrQLenPdf::9 0 # What write queue length does an incoming req see 135system.mem_ctrl.wrQLenPdf::10 0 # What write queue length does an incoming req see 136system.mem_ctrl.wrQLenPdf::11 0 # What write queue length does an incoming req see 137system.mem_ctrl.wrQLenPdf::12 0 # What write queue length does an incoming req see 138system.mem_ctrl.wrQLenPdf::13 0 # What write queue length does an incoming req see 139system.mem_ctrl.wrQLenPdf::14 0 # What write queue length does an incoming req see 140system.mem_ctrl.wrQLenPdf::15 0 # What write queue length does an incoming req see 141system.mem_ctrl.wrQLenPdf::16 0 # What write queue length does an incoming req see 142system.mem_ctrl.wrQLenPdf::17 0 # What write queue length does an incoming req see 143system.mem_ctrl.wrQLenPdf::18 0 # What write queue length does an incoming req see 144system.mem_ctrl.wrQLenPdf::19 0 # What write queue length does an incoming req see 145system.mem_ctrl.wrQLenPdf::20 0 # What write queue length does an incoming req see 146system.mem_ctrl.wrQLenPdf::21 0 # What write queue length does an incoming req see 147system.mem_ctrl.wrQLenPdf::22 0 # What write queue length does an incoming req see 148system.mem_ctrl.wrQLenPdf::23 0 # What write queue length does an incoming req see 149system.mem_ctrl.wrQLenPdf::24 0 # What write queue length does an incoming req see 150system.mem_ctrl.wrQLenPdf::25 0 # What write queue length does an incoming req see 151system.mem_ctrl.wrQLenPdf::26 0 # What write queue length does an incoming req see 152system.mem_ctrl.wrQLenPdf::27 0 # What write queue length does an incoming req see 153system.mem_ctrl.wrQLenPdf::28 0 # What write queue length does an incoming req see 154system.mem_ctrl.wrQLenPdf::29 0 # What write queue length does an incoming req see 155system.mem_ctrl.wrQLenPdf::30 0 # What write queue length does an incoming req see 156system.mem_ctrl.wrQLenPdf::31 0 # What write queue length does an incoming req see 157system.mem_ctrl.wrQLenPdf::32 0 # What write queue length does an incoming req see 158system.mem_ctrl.wrQLenPdf::33 0 # What write queue length does an incoming req see 159system.mem_ctrl.wrQLenPdf::34 0 # What write queue length does an incoming req see 160system.mem_ctrl.wrQLenPdf::35 0 # What write queue length does an incoming req see 161system.mem_ctrl.wrQLenPdf::36 0 # What write queue length does an incoming req see 162system.mem_ctrl.wrQLenPdf::37 0 # What write queue length does an incoming req see 163system.mem_ctrl.wrQLenPdf::38 0 # What write queue length does an incoming req see 164system.mem_ctrl.wrQLenPdf::39 0 # What write queue length does an incoming req see 165system.mem_ctrl.wrQLenPdf::40 0 # What write queue length does an incoming req see 166system.mem_ctrl.wrQLenPdf::41 0 # What write queue length does an incoming req see 167system.mem_ctrl.wrQLenPdf::42 0 # What write queue length does an incoming req see 168system.mem_ctrl.wrQLenPdf::43 0 # What write queue length does an incoming req see 169system.mem_ctrl.wrQLenPdf::44 0 # What write queue length does an incoming req see 170system.mem_ctrl.wrQLenPdf::45 0 # What write queue length does an incoming req see 171system.mem_ctrl.wrQLenPdf::46 0 # What write queue length does an incoming req see 172system.mem_ctrl.wrQLenPdf::47 0 # What write queue length does an incoming req see 173system.mem_ctrl.wrQLenPdf::48 0 # What write queue length does an incoming req see 174system.mem_ctrl.wrQLenPdf::49 0 # What write queue length does an incoming req see 175system.mem_ctrl.wrQLenPdf::50 0 # What write queue length does an incoming req see 176system.mem_ctrl.wrQLenPdf::51 0 # What write queue length does an incoming req see 177system.mem_ctrl.wrQLenPdf::52 0 # What write queue length does an incoming req see 178system.mem_ctrl.wrQLenPdf::53 0 # What write queue length does an incoming req see 179system.mem_ctrl.wrQLenPdf::54 0 # What write queue length does an incoming req see 180system.mem_ctrl.wrQLenPdf::55 0 # What write queue length does an incoming req see 181system.mem_ctrl.wrQLenPdf::56 0 # What write queue length does an incoming req see 182system.mem_ctrl.wrQLenPdf::57 0 # What write queue length does an incoming req see 183system.mem_ctrl.wrQLenPdf::58 0 # What write queue length does an incoming req see 184system.mem_ctrl.wrQLenPdf::59 0 # What write queue length does an incoming req see 185system.mem_ctrl.wrQLenPdf::60 0 # What write queue length does an incoming req see 186system.mem_ctrl.wrQLenPdf::61 0 # What write queue length does an incoming req see 187system.mem_ctrl.wrQLenPdf::62 0 # What write queue length does an incoming req see 188system.mem_ctrl.wrQLenPdf::63 0 # What write queue length does an incoming req see 189system.mem_ctrl.bytesPerActivate::samples 115 # Bytes accessed per row activation 190system.mem_ctrl.bytesPerActivate::mean 199.234783 # Bytes accessed per row activation 191system.mem_ctrl.bytesPerActivate::gmean 135.588464 # Bytes accessed per row activation 192system.mem_ctrl.bytesPerActivate::stdev 217.243914 # Bytes accessed per row activation 193system.mem_ctrl.bytesPerActivate::0-127 49 42.61% 42.61% # Bytes accessed per row activation 194system.mem_ctrl.bytesPerActivate::128-255 34 29.57% 72.17% # Bytes accessed per row activation 195system.mem_ctrl.bytesPerActivate::256-383 16 13.91% 86.09% # Bytes accessed per row activation 196system.mem_ctrl.bytesPerActivate::384-511 6 5.22% 91.30% # Bytes accessed per row activation 197system.mem_ctrl.bytesPerActivate::512-639 2 1.74% 93.04% # Bytes accessed per row activation 198system.mem_ctrl.bytesPerActivate::640-767 2 1.74% 94.78% # Bytes accessed per row activation 199system.mem_ctrl.bytesPerActivate::768-895 2 1.74% 96.52% # Bytes accessed per row activation 200system.mem_ctrl.bytesPerActivate::896-1023 1 0.87% 97.39% # Bytes accessed per row activation 201system.mem_ctrl.bytesPerActivate::1024-1151 3 2.61% 100.00% # Bytes accessed per row activation 202system.mem_ctrl.bytesPerActivate::total 115 # Bytes accessed per row activation 203system.mem_ctrl.totQLat 3552250 # Total ticks spent queuing 204system.mem_ctrl.totMemAccLat 10377250 # Total ticks spent from burst creation until serviced by the DRAM 205system.mem_ctrl.totBusLat 1820000 # Total ticks spent in databus transfers 206system.mem_ctrl.avgQLat 9758.93 # Average queueing delay per DRAM burst 207system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst 208system.mem_ctrl.avgMemAccLat 28508.93 # Average memory access latency per DRAM burst 209system.mem_ctrl.avgRdBW 417.16 # Average DRAM read bandwidth in MiByte/s 210system.mem_ctrl.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 211system.mem_ctrl.avgRdBWSys 417.16 # Average system read bandwidth in MiByte/s 212system.mem_ctrl.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 213system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 214system.mem_ctrl.busUtil 3.26 # Data bus utilization in percentage 215system.mem_ctrl.busUtilRead 3.26 # Data bus utilization in percentage for reads 216system.mem_ctrl.busUtilWrite 0.00 # Data bus utilization in percentage for writes 217system.mem_ctrl.avgRdQLen 1.00 # Average read queue length when enqueuing 218system.mem_ctrl.avgWrQLen 0.00 # Average write queue length when enqueuing 219system.mem_ctrl.readRowHits 244 # Number of row buffer hits during reads 220system.mem_ctrl.writeRowHits 0 # Number of row buffer hits during writes 221system.mem_ctrl.readRowHitRate 67.03 # Row buffer hit rate for reads 222system.mem_ctrl.writeRowHitRate nan # Row buffer hit rate for writes 223system.mem_ctrl.avgGap 153060.44 # Average gap between requests 224system.mem_ctrl.pageHitRate 67.03 # Row buffer hit rate, read and write combined 225system.mem_ctrl_0.actEnergy 302400 # Energy for activate commands per rank (pJ) 226system.mem_ctrl_0.preEnergy 165000 # Energy for precharge commands per rank (pJ) 227system.mem_ctrl_0.readEnergy 1240200 # Energy for read commands per rank (pJ) 228system.mem_ctrl_0.writeEnergy 0 # Energy for write commands per rank (pJ) 229system.mem_ctrl_0.refreshEnergy 3559920 # Energy for refresh commands per rank (pJ) 230system.mem_ctrl_0.actBackEnergy 32401080 # Energy for active background per rank (pJ) 231system.mem_ctrl_0.preBackEnergy 4436250 # Energy for precharge background per rank (pJ) 232system.mem_ctrl_0.totalEnergy 42104850 # Total energy per rank (pJ) 233system.mem_ctrl_0.averagePower 768.845267 # Core power per rank (mW) 234system.mem_ctrl_0.memoryStateTime::IDLE 7212250 # Time in different power states 235system.mem_ctrl_0.memoryStateTime::REF 1820000 # Time in different power states 236system.mem_ctrl_0.memoryStateTime::PRE_PDN 0 # Time in different power states 237system.mem_ctrl_0.memoryStateTime::ACT 45745250 # Time in different power states 238system.mem_ctrl_0.memoryStateTime::ACT_PDN 0 # Time in different power states 239system.mem_ctrl_1.actEnergy 567000 # Energy for activate commands per rank (pJ) 240system.mem_ctrl_1.preEnergy 309375 # Energy for precharge commands per rank (pJ) 241system.mem_ctrl_1.readEnergy 1552200 # Energy for read commands per rank (pJ) 242system.mem_ctrl_1.writeEnergy 0 # Energy for write commands per rank (pJ) 243system.mem_ctrl_1.refreshEnergy 3559920 # Energy for refresh commands per rank (pJ) 244system.mem_ctrl_1.actBackEnergy 36016020 # Energy for active background per rank (pJ) 245system.mem_ctrl_1.preBackEnergy 1265250 # Energy for precharge background per rank (pJ) 246system.mem_ctrl_1.totalEnergy 43269765 # Total energy per rank (pJ) 247system.mem_ctrl_1.averagePower 790.116911 # Core power per rank (mW) 248system.mem_ctrl_1.memoryStateTime::IDLE 2847000 # Time in different power states 249system.mem_ctrl_1.memoryStateTime::REF 1820000 # Time in different power states 250system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # Time in different power states 251system.mem_ctrl_1.memoryStateTime::ACT 51070000 # Time in different power states 252system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states 253system.cpu.apic_clk_domain.clock 16000 # Clock period in ticks 254system.cpu.workload.num_syscalls 11 # Number of system calls 255system.cpu.numCycles 55844 # number of cpu cycles simulated 256system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 257system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 258system.cpu.committedInsts 5712 # Number of instructions committed 259system.cpu.committedOps 10314 # Number of ops (including micro ops) committed 260system.cpu.num_int_alu_accesses 10205 # Number of integer alu accesses 261system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses 262system.cpu.num_func_calls 221 # number of times a function call or return occured 263system.cpu.num_conditional_control_insts 986 # number of instructions that are conditional controls 264system.cpu.num_int_insts 10205 # number of integer instructions 265system.cpu.num_fp_insts 0 # number of float instructions 266system.cpu.num_int_register_reads 19296 # number of times the integer registers were read 267system.cpu.num_int_register_writes 7977 # number of times the integer registers were written 268system.cpu.num_fp_register_reads 0 # number of times the floating registers were read 269system.cpu.num_fp_register_writes 0 # number of times the floating registers were written 270system.cpu.num_cc_register_reads 7020 # number of times the CC registers were read 271system.cpu.num_cc_register_writes 3825 # number of times the CC registers were written 272system.cpu.num_mem_refs 2025 # number of memory refs 273system.cpu.num_load_insts 1084 # Number of load instructions 274system.cpu.num_store_insts 941 # Number of store instructions 275system.cpu.num_idle_cycles 0.001000 # Number of idle cycles 276system.cpu.num_busy_cycles 55843.999000 # Number of busy cycles 277system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles 278system.cpu.idle_fraction 0.000000 # Percentage of idle cycles 279system.cpu.Branches 1306 # Number of branches fetched 280system.cpu.op_class::No_OpClass 1 0.01% 0.01% # Class of executed instruction 281system.cpu.op_class::IntAlu 8275 80.23% 80.24% # Class of executed instruction 282system.cpu.op_class::IntMult 6 0.06% 80.30% # Class of executed instruction 283system.cpu.op_class::IntDiv 7 0.07% 80.37% # Class of executed instruction 284system.cpu.op_class::FloatAdd 0 0.00% 80.37% # Class of executed instruction 285system.cpu.op_class::FloatCmp 0 0.00% 80.37% # Class of executed instruction 286system.cpu.op_class::FloatCvt 0 0.00% 80.37% # Class of executed instruction 287system.cpu.op_class::FloatMult 0 0.00% 80.37% # Class of executed instruction 288system.cpu.op_class::FloatDiv 0 0.00% 80.37% # Class of executed instruction 289system.cpu.op_class::FloatSqrt 0 0.00% 80.37% # Class of executed instruction 290system.cpu.op_class::SimdAdd 0 0.00% 80.37% # Class of executed instruction 291system.cpu.op_class::SimdAddAcc 0 0.00% 80.37% # Class of executed instruction 292system.cpu.op_class::SimdAlu 0 0.00% 80.37% # Class of executed instruction 293system.cpu.op_class::SimdCmp 0 0.00% 80.37% # Class of executed instruction 294system.cpu.op_class::SimdCvt 0 0.00% 80.37% # Class of executed instruction 295system.cpu.op_class::SimdMisc 0 0.00% 80.37% # Class of executed instruction 296system.cpu.op_class::SimdMult 0 0.00% 80.37% # Class of executed instruction 297system.cpu.op_class::SimdMultAcc 0 0.00% 80.37% # Class of executed instruction 298system.cpu.op_class::SimdShift 0 0.00% 80.37% # Class of executed instruction 299system.cpu.op_class::SimdShiftAcc 0 0.00% 80.37% # Class of executed instruction 300system.cpu.op_class::SimdSqrt 0 0.00% 80.37% # Class of executed instruction 301system.cpu.op_class::SimdFloatAdd 0 0.00% 80.37% # Class of executed instruction 302system.cpu.op_class::SimdFloatAlu 0 0.00% 80.37% # Class of executed instruction 303system.cpu.op_class::SimdFloatCmp 0 0.00% 80.37% # Class of executed instruction 304system.cpu.op_class::SimdFloatCvt 0 0.00% 80.37% # Class of executed instruction 305system.cpu.op_class::SimdFloatDiv 0 0.00% 80.37% # Class of executed instruction 306system.cpu.op_class::SimdFloatMisc 0 0.00% 80.37% # Class of executed instruction 307system.cpu.op_class::SimdFloatMult 0 0.00% 80.37% # Class of executed instruction 308system.cpu.op_class::SimdFloatMultAcc 0 0.00% 80.37% # Class of executed instruction 309system.cpu.op_class::SimdFloatSqrt 0 0.00% 80.37% # Class of executed instruction 310system.cpu.op_class::MemRead 1084 10.51% 90.88% # Class of executed instruction 311system.cpu.op_class::MemWrite 941 9.12% 100.00% # Class of executed instruction 312system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 313system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 314system.cpu.op_class::total 10314 # Class of executed instruction 315system.cpu.dcache.tags.replacements 0 # number of replacements 316system.cpu.dcache.tags.tagsinuse 81.671640 # Cycle average of tags in use 317system.cpu.dcache.tags.total_refs 1890 # Total number of references to valid blocks. 318system.cpu.dcache.tags.sampled_refs 135 # Sample count of references to valid blocks. 319system.cpu.dcache.tags.avg_refs 14 # Average number of references to valid blocks. 320system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 321system.cpu.dcache.tags.occ_blocks::cpu.data 81.671640 # Average occupied blocks per requestor 322system.cpu.dcache.tags.occ_percent::cpu.data 0.079757 # Average percentage of cache occupancy 323system.cpu.dcache.tags.occ_percent::total 0.079757 # Average percentage of cache occupancy 324system.cpu.dcache.tags.occ_task_id_blocks::1024 135 # Occupied blocks per task id 325system.cpu.dcache.tags.age_task_id_blocks_1024::0 12 # Occupied blocks per task id 326system.cpu.dcache.tags.age_task_id_blocks_1024::1 123 # Occupied blocks per task id 327system.cpu.dcache.tags.occ_task_id_percent::1024 0.131836 # Percentage of cache occupancy per task id 328system.cpu.dcache.tags.tag_accesses 4185 # Number of tag accesses 329system.cpu.dcache.tags.data_accesses 4185 # Number of data accesses 330system.cpu.dcache.ReadReq_hits::cpu.data 1028 # number of ReadReq hits 331system.cpu.dcache.ReadReq_hits::total 1028 # number of ReadReq hits 332system.cpu.dcache.WriteReq_hits::cpu.data 862 # number of WriteReq hits 333system.cpu.dcache.WriteReq_hits::total 862 # number of WriteReq hits 334system.cpu.dcache.demand_hits::cpu.data 1890 # number of demand (read+write) hits 335system.cpu.dcache.demand_hits::total 1890 # number of demand (read+write) hits 336system.cpu.dcache.overall_hits::cpu.data 1890 # number of overall hits 337system.cpu.dcache.overall_hits::total 1890 # number of overall hits 338system.cpu.dcache.ReadReq_misses::cpu.data 56 # number of ReadReq misses 339system.cpu.dcache.ReadReq_misses::total 56 # number of ReadReq misses 340system.cpu.dcache.WriteReq_misses::cpu.data 79 # number of WriteReq misses 341system.cpu.dcache.WriteReq_misses::total 79 # number of WriteReq misses 342system.cpu.dcache.demand_misses::cpu.data 135 # number of demand (read+write) misses 343system.cpu.dcache.demand_misses::total 135 # number of demand (read+write) misses 344system.cpu.dcache.overall_misses::cpu.data 135 # number of overall misses 345system.cpu.dcache.overall_misses::total 135 # number of overall misses 346system.cpu.dcache.ReadReq_miss_latency::cpu.data 6006000 # number of ReadReq miss cycles 347system.cpu.dcache.ReadReq_miss_latency::total 6006000 # number of ReadReq miss cycles 348system.cpu.dcache.WriteReq_miss_latency::cpu.data 8260000 # number of WriteReq miss cycles 349system.cpu.dcache.WriteReq_miss_latency::total 8260000 # number of WriteReq miss cycles 350system.cpu.dcache.demand_miss_latency::cpu.data 14266000 # number of demand (read+write) miss cycles 351system.cpu.dcache.demand_miss_latency::total 14266000 # number of demand (read+write) miss cycles 352system.cpu.dcache.overall_miss_latency::cpu.data 14266000 # number of overall miss cycles 353system.cpu.dcache.overall_miss_latency::total 14266000 # number of overall miss cycles 354system.cpu.dcache.ReadReq_accesses::cpu.data 1084 # number of ReadReq accesses(hits+misses) 355system.cpu.dcache.ReadReq_accesses::total 1084 # number of ReadReq accesses(hits+misses) 356system.cpu.dcache.WriteReq_accesses::cpu.data 941 # number of WriteReq accesses(hits+misses) 357system.cpu.dcache.WriteReq_accesses::total 941 # number of WriteReq accesses(hits+misses) 358system.cpu.dcache.demand_accesses::cpu.data 2025 # number of demand (read+write) accesses 359system.cpu.dcache.demand_accesses::total 2025 # number of demand (read+write) accesses 360system.cpu.dcache.overall_accesses::cpu.data 2025 # number of overall (read+write) accesses 361system.cpu.dcache.overall_accesses::total 2025 # number of overall (read+write) accesses 362system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.051661 # miss rate for ReadReq accesses 363system.cpu.dcache.ReadReq_miss_rate::total 0.051661 # miss rate for ReadReq accesses 364system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.083953 # miss rate for WriteReq accesses 365system.cpu.dcache.WriteReq_miss_rate::total 0.083953 # miss rate for WriteReq accesses 366system.cpu.dcache.demand_miss_rate::cpu.data 0.066667 # miss rate for demand accesses 367system.cpu.dcache.demand_miss_rate::total 0.066667 # miss rate for demand accesses 368system.cpu.dcache.overall_miss_rate::cpu.data 0.066667 # miss rate for overall accesses 369system.cpu.dcache.overall_miss_rate::total 0.066667 # miss rate for overall accesses 370system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 107250 # average ReadReq miss latency 371system.cpu.dcache.ReadReq_avg_miss_latency::total 107250 # average ReadReq miss latency 372system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 104556.962025 # average WriteReq miss latency 373system.cpu.dcache.WriteReq_avg_miss_latency::total 104556.962025 # average WriteReq miss latency 374system.cpu.dcache.demand_avg_miss_latency::cpu.data 105674.074074 # average overall miss latency 375system.cpu.dcache.demand_avg_miss_latency::total 105674.074074 # average overall miss latency 376system.cpu.dcache.overall_avg_miss_latency::cpu.data 105674.074074 # average overall miss latency 377system.cpu.dcache.overall_avg_miss_latency::total 105674.074074 # average overall miss latency 378system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 379system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 380system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 381system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 382system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 383system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 384system.cpu.dcache.fast_writes 0 # number of fast writes performed 385system.cpu.dcache.cache_copies 0 # number of cache copies performed 386system.cpu.dcache.ReadReq_mshr_misses::cpu.data 56 # number of ReadReq MSHR misses 387system.cpu.dcache.ReadReq_mshr_misses::total 56 # number of ReadReq MSHR misses 388system.cpu.dcache.WriteReq_mshr_misses::cpu.data 79 # number of WriteReq MSHR misses 389system.cpu.dcache.WriteReq_mshr_misses::total 79 # number of WriteReq MSHR misses 390system.cpu.dcache.demand_mshr_misses::cpu.data 135 # number of demand (read+write) MSHR misses 391system.cpu.dcache.demand_mshr_misses::total 135 # number of demand (read+write) MSHR misses 392system.cpu.dcache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses 393system.cpu.dcache.overall_mshr_misses::total 135 # number of overall MSHR misses 394system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5894000 # number of ReadReq MSHR miss cycles 395system.cpu.dcache.ReadReq_mshr_miss_latency::total 5894000 # number of ReadReq MSHR miss cycles 396system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8102000 # number of WriteReq MSHR miss cycles 397system.cpu.dcache.WriteReq_mshr_miss_latency::total 8102000 # number of WriteReq MSHR miss cycles 398system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13996000 # number of demand (read+write) MSHR miss cycles 399system.cpu.dcache.demand_mshr_miss_latency::total 13996000 # number of demand (read+write) MSHR miss cycles 400system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13996000 # number of overall MSHR miss cycles 401system.cpu.dcache.overall_mshr_miss_latency::total 13996000 # number of overall MSHR miss cycles 402system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.051661 # mshr miss rate for ReadReq accesses 403system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.051661 # mshr miss rate for ReadReq accesses 404system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083953 # mshr miss rate for WriteReq accesses 405system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.083953 # mshr miss rate for WriteReq accesses 406system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.066667 # mshr miss rate for demand accesses 407system.cpu.dcache.demand_mshr_miss_rate::total 0.066667 # mshr miss rate for demand accesses 408system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.066667 # mshr miss rate for overall accesses 409system.cpu.dcache.overall_mshr_miss_rate::total 0.066667 # mshr miss rate for overall accesses 410system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 105250 # average ReadReq mshr miss latency 411system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 105250 # average ReadReq mshr miss latency 412system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 102556.962025 # average WriteReq mshr miss latency 413system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 102556.962025 # average WriteReq mshr miss latency 414system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 103674.074074 # average overall mshr miss latency 415system.cpu.dcache.demand_avg_mshr_miss_latency::total 103674.074074 # average overall mshr miss latency 416system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 103674.074074 # average overall mshr miss latency 417system.cpu.dcache.overall_avg_mshr_miss_latency::total 103674.074074 # average overall mshr miss latency 418system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 419system.cpu.icache.tags.replacements 58 # number of replacements 420system.cpu.icache.tags.tagsinuse 91.239705 # Cycle average of tags in use 421system.cpu.icache.tags.total_refs 7048 # Total number of references to valid blocks. 422system.cpu.icache.tags.sampled_refs 235 # Sample count of references to valid blocks. 423system.cpu.icache.tags.avg_refs 29.991489 # Average number of references to valid blocks. 424system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 425system.cpu.icache.tags.occ_blocks::cpu.inst 91.239705 # Average occupied blocks per requestor 426system.cpu.icache.tags.occ_percent::cpu.inst 0.356405 # Average percentage of cache occupancy 427system.cpu.icache.tags.occ_percent::total 0.356405 # Average percentage of cache occupancy 428system.cpu.icache.tags.occ_task_id_blocks::1024 177 # Occupied blocks per task id 429system.cpu.icache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id 430system.cpu.icache.tags.age_task_id_blocks_1024::1 133 # Occupied blocks per task id 431system.cpu.icache.tags.occ_task_id_percent::1024 0.691406 # Percentage of cache occupancy per task id 432system.cpu.icache.tags.tag_accesses 14801 # Number of tag accesses 433system.cpu.icache.tags.data_accesses 14801 # Number of data accesses 434system.cpu.icache.ReadReq_hits::cpu.inst 7048 # number of ReadReq hits 435system.cpu.icache.ReadReq_hits::total 7048 # number of ReadReq hits 436system.cpu.icache.demand_hits::cpu.inst 7048 # number of demand (read+write) hits 437system.cpu.icache.demand_hits::total 7048 # number of demand (read+write) hits 438system.cpu.icache.overall_hits::cpu.inst 7048 # number of overall hits 439system.cpu.icache.overall_hits::total 7048 # number of overall hits 440system.cpu.icache.ReadReq_misses::cpu.inst 235 # number of ReadReq misses 441system.cpu.icache.ReadReq_misses::total 235 # number of ReadReq misses 442system.cpu.icache.demand_misses::cpu.inst 235 # number of demand (read+write) misses 443system.cpu.icache.demand_misses::total 235 # number of demand (read+write) misses 444system.cpu.icache.overall_misses::cpu.inst 235 # number of overall misses 445system.cpu.icache.overall_misses::total 235 # number of overall misses 446system.cpu.icache.ReadReq_miss_latency::cpu.inst 23702000 # number of ReadReq miss cycles 447system.cpu.icache.ReadReq_miss_latency::total 23702000 # number of ReadReq miss cycles 448system.cpu.icache.demand_miss_latency::cpu.inst 23702000 # number of demand (read+write) miss cycles 449system.cpu.icache.demand_miss_latency::total 23702000 # number of demand (read+write) miss cycles 450system.cpu.icache.overall_miss_latency::cpu.inst 23702000 # number of overall miss cycles 451system.cpu.icache.overall_miss_latency::total 23702000 # number of overall miss cycles 452system.cpu.icache.ReadReq_accesses::cpu.inst 7283 # number of ReadReq accesses(hits+misses) 453system.cpu.icache.ReadReq_accesses::total 7283 # number of ReadReq accesses(hits+misses) 454system.cpu.icache.demand_accesses::cpu.inst 7283 # number of demand (read+write) accesses 455system.cpu.icache.demand_accesses::total 7283 # number of demand (read+write) accesses 456system.cpu.icache.overall_accesses::cpu.inst 7283 # number of overall (read+write) accesses 457system.cpu.icache.overall_accesses::total 7283 # number of overall (read+write) accesses 458system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.032267 # miss rate for ReadReq accesses 459system.cpu.icache.ReadReq_miss_rate::total 0.032267 # miss rate for ReadReq accesses 460system.cpu.icache.demand_miss_rate::cpu.inst 0.032267 # miss rate for demand accesses 461system.cpu.icache.demand_miss_rate::total 0.032267 # miss rate for demand accesses 462system.cpu.icache.overall_miss_rate::cpu.inst 0.032267 # miss rate for overall accesses 463system.cpu.icache.overall_miss_rate::total 0.032267 # miss rate for overall accesses 464system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 100859.574468 # average ReadReq miss latency 465system.cpu.icache.ReadReq_avg_miss_latency::total 100859.574468 # average ReadReq miss latency 466system.cpu.icache.demand_avg_miss_latency::cpu.inst 100859.574468 # average overall miss latency 467system.cpu.icache.demand_avg_miss_latency::total 100859.574468 # average overall miss latency 468system.cpu.icache.overall_avg_miss_latency::cpu.inst 100859.574468 # average overall miss latency 469system.cpu.icache.overall_avg_miss_latency::total 100859.574468 # average overall miss latency 470system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 471system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 472system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 473system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 474system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 475system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 476system.cpu.icache.fast_writes 0 # number of fast writes performed 477system.cpu.icache.cache_copies 0 # number of cache copies performed 478system.cpu.icache.ReadReq_mshr_misses::cpu.inst 235 # number of ReadReq MSHR misses 479system.cpu.icache.ReadReq_mshr_misses::total 235 # number of ReadReq MSHR misses 480system.cpu.icache.demand_mshr_misses::cpu.inst 235 # number of demand (read+write) MSHR misses 481system.cpu.icache.demand_mshr_misses::total 235 # number of demand (read+write) MSHR misses 482system.cpu.icache.overall_mshr_misses::cpu.inst 235 # number of overall MSHR misses 483system.cpu.icache.overall_mshr_misses::total 235 # number of overall MSHR misses 484system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23232000 # number of ReadReq MSHR miss cycles 485system.cpu.icache.ReadReq_mshr_miss_latency::total 23232000 # number of ReadReq MSHR miss cycles 486system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23232000 # number of demand (read+write) MSHR miss cycles 487system.cpu.icache.demand_mshr_miss_latency::total 23232000 # number of demand (read+write) MSHR miss cycles 488system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23232000 # number of overall MSHR miss cycles 489system.cpu.icache.overall_mshr_miss_latency::total 23232000 # number of overall MSHR miss cycles 490system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.032267 # mshr miss rate for ReadReq accesses 491system.cpu.icache.ReadReq_mshr_miss_rate::total 0.032267 # mshr miss rate for ReadReq accesses 492system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.032267 # mshr miss rate for demand accesses 493system.cpu.icache.demand_mshr_miss_rate::total 0.032267 # mshr miss rate for demand accesses 494system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.032267 # mshr miss rate for overall accesses 495system.cpu.icache.overall_mshr_miss_rate::total 0.032267 # mshr miss rate for overall accesses 496system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 98859.574468 # average ReadReq mshr miss latency 497system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 98859.574468 # average ReadReq mshr miss latency 498system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 98859.574468 # average overall mshr miss latency 499system.cpu.icache.demand_avg_mshr_miss_latency::total 98859.574468 # average overall mshr miss latency 500system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 98859.574468 # average overall mshr miss latency 501system.cpu.icache.overall_avg_mshr_miss_latency::total 98859.574468 # average overall mshr miss latency 502system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 503system.l2bus.snoop_filter.tot_requests 428 # Total number of requests made to the snoop filter. 504system.l2bus.snoop_filter.hit_single_requests 59 # Number of requests hitting in the snoop filter with a single holder of the requested data. 505system.l2bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 506system.l2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 507system.l2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 508system.l2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 509system.l2bus.trans_dist::ReadResp 291 # Transaction distribution 510system.l2bus.trans_dist::CleanEvict 58 # Transaction distribution 511system.l2bus.trans_dist::ReadExReq 79 # Transaction distribution 512system.l2bus.trans_dist::ReadExResp 79 # Transaction distribution 513system.l2bus.trans_dist::ReadSharedReq 291 # Transaction distribution 514system.l2bus.pkt_count_system.cpu.icache.mem_side::system.l2cache.cpu_side 528 # Packet count per connected master and slave (bytes) 515system.l2bus.pkt_count_system.cpu.dcache.mem_side::system.l2cache.cpu_side 270 # Packet count per connected master and slave (bytes) 516system.l2bus.pkt_count::total 798 # Packet count per connected master and slave (bytes) 517system.l2bus.pkt_size_system.cpu.icache.mem_side::system.l2cache.cpu_side 15040 # Cumulative packet size per connected master and slave (bytes) 518system.l2bus.pkt_size_system.cpu.dcache.mem_side::system.l2cache.cpu_side 8640 # Cumulative packet size per connected master and slave (bytes) 519system.l2bus.pkt_size::total 23680 # Cumulative packet size per connected master and slave (bytes) 520system.l2bus.snoops 0 # Total snoops (count) 521system.l2bus.snoop_fanout::samples 370 # Request fanout histogram 522system.l2bus.snoop_fanout::mean 0.002703 # Request fanout histogram 523system.l2bus.snoop_fanout::stdev 0.051988 # Request fanout histogram 524system.l2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 525system.l2bus.snoop_fanout::0 369 99.73% 99.73% # Request fanout histogram 526system.l2bus.snoop_fanout::1 1 0.27% 100.00% # Request fanout histogram 527system.l2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 528system.l2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 529system.l2bus.snoop_fanout::min_value 0 # Request fanout histogram 530system.l2bus.snoop_fanout::max_value 1 # Request fanout histogram 531system.l2bus.snoop_fanout::total 370 # Request fanout histogram 532system.l2bus.reqLayer0.occupancy 428000 # Layer occupancy (ticks) 533system.l2bus.reqLayer0.utilization 0.8 # Layer utilization (%) 534system.l2bus.respLayer0.occupancy 705000 # Layer occupancy (ticks) 535system.l2bus.respLayer0.utilization 1.3 # Layer utilization (%) 536system.l2bus.respLayer1.occupancy 405000 # Layer occupancy (ticks) 537system.l2bus.respLayer1.utilization 0.7 # Layer utilization (%) 538system.l2cache.tags.replacements 0 # number of replacements 539system.l2cache.tags.tagsinuse 135.848259 # Cycle average of tags in use 540system.l2cache.tags.total_refs 64 # Total number of references to valid blocks. 541system.l2cache.tags.sampled_refs 285 # Sample count of references to valid blocks. 542system.l2cache.tags.avg_refs 0.224561 # Average number of references to valid blocks. 543system.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 544system.l2cache.tags.occ_blocks::cpu.inst 106.898398 # Average occupied blocks per requestor 545system.l2cache.tags.occ_blocks::cpu.data 28.949861 # Average occupied blocks per requestor 546system.l2cache.tags.occ_percent::cpu.inst 0.026098 # Average percentage of cache occupancy 547system.l2cache.tags.occ_percent::cpu.data 0.007068 # Average percentage of cache occupancy 548system.l2cache.tags.occ_percent::total 0.033166 # Average percentage of cache occupancy 549system.l2cache.tags.occ_task_id_blocks::1024 285 # Occupied blocks per task id 550system.l2cache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id 551system.l2cache.tags.age_task_id_blocks_1024::1 231 # Occupied blocks per task id 552system.l2cache.tags.occ_task_id_percent::1024 0.069580 # Percentage of cache occupancy per task id 553system.l2cache.tags.tag_accesses 3788 # Number of tag accesses 554system.l2cache.tags.data_accesses 3788 # Number of data accesses 555system.l2cache.ReadSharedReq_hits::cpu.inst 6 # number of ReadSharedReq hits 556system.l2cache.ReadSharedReq_hits::total 6 # number of ReadSharedReq hits 557system.l2cache.demand_hits::cpu.inst 6 # number of demand (read+write) hits 558system.l2cache.demand_hits::total 6 # number of demand (read+write) hits 559system.l2cache.overall_hits::cpu.inst 6 # number of overall hits 560system.l2cache.overall_hits::total 6 # number of overall hits 561system.l2cache.ReadExReq_misses::cpu.data 79 # number of ReadExReq misses 562system.l2cache.ReadExReq_misses::total 79 # number of ReadExReq misses 563system.l2cache.ReadSharedReq_misses::cpu.inst 229 # number of ReadSharedReq misses 564system.l2cache.ReadSharedReq_misses::cpu.data 56 # number of ReadSharedReq misses 565system.l2cache.ReadSharedReq_misses::total 285 # number of ReadSharedReq misses 566system.l2cache.demand_misses::cpu.inst 229 # number of demand (read+write) misses 567system.l2cache.demand_misses::cpu.data 135 # number of demand (read+write) misses 568system.l2cache.demand_misses::total 364 # number of demand (read+write) misses 569system.l2cache.overall_misses::cpu.inst 229 # number of overall misses 570system.l2cache.overall_misses::cpu.data 135 # number of overall misses 571system.l2cache.overall_misses::total 364 # number of overall misses 572system.l2cache.ReadExReq_miss_latency::cpu.data 7865000 # number of ReadExReq miss cycles 573system.l2cache.ReadExReq_miss_latency::total 7865000 # number of ReadExReq miss cycles 574system.l2cache.ReadSharedReq_miss_latency::cpu.inst 22399000 # number of ReadSharedReq miss cycles 575system.l2cache.ReadSharedReq_miss_latency::cpu.data 5726000 # number of ReadSharedReq miss cycles 576system.l2cache.ReadSharedReq_miss_latency::total 28125000 # number of ReadSharedReq miss cycles 577system.l2cache.demand_miss_latency::cpu.inst 22399000 # number of demand (read+write) miss cycles 578system.l2cache.demand_miss_latency::cpu.data 13591000 # number of demand (read+write) miss cycles 579system.l2cache.demand_miss_latency::total 35990000 # number of demand (read+write) miss cycles 580system.l2cache.overall_miss_latency::cpu.inst 22399000 # number of overall miss cycles 581system.l2cache.overall_miss_latency::cpu.data 13591000 # number of overall miss cycles 582system.l2cache.overall_miss_latency::total 35990000 # number of overall miss cycles 583system.l2cache.ReadExReq_accesses::cpu.data 79 # number of ReadExReq accesses(hits+misses) 584system.l2cache.ReadExReq_accesses::total 79 # number of ReadExReq accesses(hits+misses) 585system.l2cache.ReadSharedReq_accesses::cpu.inst 235 # number of ReadSharedReq accesses(hits+misses) 586system.l2cache.ReadSharedReq_accesses::cpu.data 56 # number of ReadSharedReq accesses(hits+misses) 587system.l2cache.ReadSharedReq_accesses::total 291 # number of ReadSharedReq accesses(hits+misses) 588system.l2cache.demand_accesses::cpu.inst 235 # number of demand (read+write) accesses 589system.l2cache.demand_accesses::cpu.data 135 # number of demand (read+write) accesses 590system.l2cache.demand_accesses::total 370 # number of demand (read+write) accesses 591system.l2cache.overall_accesses::cpu.inst 235 # number of overall (read+write) accesses 592system.l2cache.overall_accesses::cpu.data 135 # number of overall (read+write) accesses 593system.l2cache.overall_accesses::total 370 # number of overall (read+write) accesses 594system.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 595system.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 596system.l2cache.ReadSharedReq_miss_rate::cpu.inst 0.974468 # miss rate for ReadSharedReq accesses 597system.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses 598system.l2cache.ReadSharedReq_miss_rate::total 0.979381 # miss rate for ReadSharedReq accesses 599system.l2cache.demand_miss_rate::cpu.inst 0.974468 # miss rate for demand accesses 600system.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 601system.l2cache.demand_miss_rate::total 0.983784 # miss rate for demand accesses 602system.l2cache.overall_miss_rate::cpu.inst 0.974468 # miss rate for overall accesses 603system.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 604system.l2cache.overall_miss_rate::total 0.983784 # miss rate for overall accesses 605system.l2cache.ReadExReq_avg_miss_latency::cpu.data 99556.962025 # average ReadExReq miss latency 606system.l2cache.ReadExReq_avg_miss_latency::total 99556.962025 # average ReadExReq miss latency 607system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 97812.227074 # average ReadSharedReq miss latency 608system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 102250 # average ReadSharedReq miss latency 609system.l2cache.ReadSharedReq_avg_miss_latency::total 98684.210526 # average ReadSharedReq miss latency 610system.l2cache.demand_avg_miss_latency::cpu.inst 97812.227074 # average overall miss latency 611system.l2cache.demand_avg_miss_latency::cpu.data 100674.074074 # average overall miss latency 612system.l2cache.demand_avg_miss_latency::total 98873.626374 # average overall miss latency 613system.l2cache.overall_avg_miss_latency::cpu.inst 97812.227074 # average overall miss latency 614system.l2cache.overall_avg_miss_latency::cpu.data 100674.074074 # average overall miss latency 615system.l2cache.overall_avg_miss_latency::total 98873.626374 # average overall miss latency 616system.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 617system.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 618system.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 619system.l2cache.blocked::no_targets 0 # number of cycles access was blocked 620system.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 621system.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 622system.l2cache.fast_writes 0 # number of fast writes performed 623system.l2cache.cache_copies 0 # number of cache copies performed 624system.l2cache.ReadExReq_mshr_misses::cpu.data 79 # number of ReadExReq MSHR misses 625system.l2cache.ReadExReq_mshr_misses::total 79 # number of ReadExReq MSHR misses 626system.l2cache.ReadSharedReq_mshr_misses::cpu.inst 229 # number of ReadSharedReq MSHR misses 627system.l2cache.ReadSharedReq_mshr_misses::cpu.data 56 # number of ReadSharedReq MSHR misses 628system.l2cache.ReadSharedReq_mshr_misses::total 285 # number of ReadSharedReq MSHR misses 629system.l2cache.demand_mshr_misses::cpu.inst 229 # number of demand (read+write) MSHR misses 630system.l2cache.demand_mshr_misses::cpu.data 135 # number of demand (read+write) MSHR misses 631system.l2cache.demand_mshr_misses::total 364 # number of demand (read+write) MSHR misses 632system.l2cache.overall_mshr_misses::cpu.inst 229 # number of overall MSHR misses 633system.l2cache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses 634system.l2cache.overall_mshr_misses::total 364 # number of overall MSHR misses 635system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6285000 # number of ReadExReq MSHR miss cycles 636system.l2cache.ReadExReq_mshr_miss_latency::total 6285000 # number of ReadExReq MSHR miss cycles 637system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 17819000 # number of ReadSharedReq MSHR miss cycles 638system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4606000 # number of ReadSharedReq MSHR miss cycles 639system.l2cache.ReadSharedReq_mshr_miss_latency::total 22425000 # number of ReadSharedReq MSHR miss cycles 640system.l2cache.demand_mshr_miss_latency::cpu.inst 17819000 # number of demand (read+write) MSHR miss cycles 641system.l2cache.demand_mshr_miss_latency::cpu.data 10891000 # number of demand (read+write) MSHR miss cycles 642system.l2cache.demand_mshr_miss_latency::total 28710000 # number of demand (read+write) MSHR miss cycles 643system.l2cache.overall_mshr_miss_latency::cpu.inst 17819000 # number of overall MSHR miss cycles 644system.l2cache.overall_mshr_miss_latency::cpu.data 10891000 # number of overall MSHR miss cycles 645system.l2cache.overall_mshr_miss_latency::total 28710000 # number of overall MSHR miss cycles 646system.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 647system.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 648system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.inst 0.974468 # mshr miss rate for ReadSharedReq accesses 649system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses 650system.l2cache.ReadSharedReq_mshr_miss_rate::total 0.979381 # mshr miss rate for ReadSharedReq accesses 651system.l2cache.demand_mshr_miss_rate::cpu.inst 0.974468 # mshr miss rate for demand accesses 652system.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 653system.l2cache.demand_mshr_miss_rate::total 0.983784 # mshr miss rate for demand accesses 654system.l2cache.overall_mshr_miss_rate::cpu.inst 0.974468 # mshr miss rate for overall accesses 655system.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 656system.l2cache.overall_mshr_miss_rate::total 0.983784 # mshr miss rate for overall accesses 657system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79556.962025 # average ReadExReq mshr miss latency 658system.l2cache.ReadExReq_avg_mshr_miss_latency::total 79556.962025 # average ReadExReq mshr miss latency 659system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 77812.227074 # average ReadSharedReq mshr miss latency 660system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 82250 # average ReadSharedReq mshr miss latency 661system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 78684.210526 # average ReadSharedReq mshr miss latency 662system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 77812.227074 # average overall mshr miss latency 663system.l2cache.demand_avg_mshr_miss_latency::cpu.data 80674.074074 # average overall mshr miss latency 664system.l2cache.demand_avg_mshr_miss_latency::total 78873.626374 # average overall mshr miss latency 665system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 77812.227074 # average overall mshr miss latency 666system.l2cache.overall_avg_mshr_miss_latency::cpu.data 80674.074074 # average overall mshr miss latency 667system.l2cache.overall_avg_mshr_miss_latency::total 78873.626374 # average overall mshr miss latency 668system.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 669system.membus.trans_dist::ReadResp 285 # Transaction distribution 670system.membus.trans_dist::ReadExReq 79 # Transaction distribution 671system.membus.trans_dist::ReadExResp 79 # Transaction distribution 672system.membus.trans_dist::ReadSharedReq 285 # Transaction distribution 673system.membus.pkt_count_system.l2cache.mem_side::system.mem_ctrl.port 728 # Packet count per connected master and slave (bytes) 674system.membus.pkt_count_system.l2cache.mem_side::total 728 # Packet count per connected master and slave (bytes) 675system.membus.pkt_count::total 728 # Packet count per connected master and slave (bytes) 676system.membus.pkt_size_system.l2cache.mem_side::system.mem_ctrl.port 23296 # Cumulative packet size per connected master and slave (bytes) 677system.membus.pkt_size_system.l2cache.mem_side::total 23296 # Cumulative packet size per connected master and slave (bytes) 678system.membus.pkt_size::total 23296 # Cumulative packet size per connected master and slave (bytes) 679system.membus.snoops 0 # Total snoops (count) 680system.membus.snoop_fanout::samples 364 # Request fanout histogram 681system.membus.snoop_fanout::mean 0 # Request fanout histogram 682system.membus.snoop_fanout::stdev 0 # Request fanout histogram 683system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 684system.membus.snoop_fanout::0 364 100.00% 100.00% # Request fanout histogram 685system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 686system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 687system.membus.snoop_fanout::min_value 0 # Request fanout histogram 688system.membus.snoop_fanout::max_value 0 # Request fanout histogram 689system.membus.snoop_fanout::total 364 # Request fanout histogram 690system.membus.reqLayer2.occupancy 364000 # Layer occupancy (ticks) 691system.membus.reqLayer2.utilization 0.7 # Layer utilization (%) 692system.membus.respLayer0.occupancy 1952750 # Layer occupancy (ticks) 693system.membus.respLayer0.utilization 3.5 # Layer utilization (%) 694 695---------- End Simulation Statistics ---------- 696