config.ini revision 11440:76b5639162af
1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu dvfs_handler l2bus l2cache mem_ctrl membus 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain 17eventq_index=0 18exit_on_work_items=false 19init_param=0 20kernel= 21kernel_addr_check=true 22load_addr_mask=1099511627775 23load_offset=0 24mem_mode=timing 25mem_ranges=0:536870911 26memories=system.mem_ctrl 27mmap_using_noreserve=false 28multi_thread=false 29num_work_ids=16 30readfile= 31symbolfile= 32thermal_components= 33thermal_model=Null 34work_begin_ckpt_count=0 35work_begin_cpu_id_exit=-1 36work_begin_exit_count=0 37work_cpus_ckpt_count=0 38work_end_ckpt_count=0 39work_end_exit_count=0 40work_item_id=-1 41system_port=system.membus.slave[1] 42 43[system.clk_domain] 44type=SrcClockDomain 45children=voltage_domain 46clock=1000 47domain_id=-1 48eventq_index=0 49init_perf_level=0 50voltage_domain=system.clk_domain.voltage_domain 51 52[system.clk_domain.voltage_domain] 53type=VoltageDomain 54eventq_index=0 55voltage=1.000000 56 57[system.cpu] 58type=TimingSimpleCPU 59children=dcache dtb icache interrupts isa itb tracer workload 60branchPred=Null 61checker=Null 62clk_domain=system.clk_domain 63cpu_id=-1 64do_checkpoint_insts=true 65do_quiesce=true 66do_statistics_insts=true 67dtb=system.cpu.dtb 68eventq_index=0 69function_trace=false 70function_trace_start=0 71interrupts=system.cpu.interrupts 72isa=system.cpu.isa 73itb=system.cpu.itb 74max_insts_all_threads=0 75max_insts_any_thread=0 76max_loads_all_threads=0 77max_loads_any_thread=0 78numThreads=1 79profile=0 80progress_interval=0 81simpoint_start_insts= 82socket_id=0 83switched_out=false 84system=system 85tracer=system.cpu.tracer 86workload=system.cpu.workload 87dcache_port=system.cpu.dcache.cpu_side 88icache_port=system.cpu.icache.cpu_side 89 90[system.cpu.dcache] 91type=Cache 92children=tags 93addr_ranges=0:18446744073709551615 94assoc=2 95clk_domain=system.clk_domain 96clusivity=mostly_incl 97demand_mshr_reserve=1 98eventq_index=0 99hit_latency=2 100is_read_only=false 101max_miss_count=0 102mshrs=4 103prefetch_on_access=false 104prefetcher=Null 105response_latency=2 106sequential_access=false 107size=65536 108system=system 109tags=system.cpu.dcache.tags 110tgts_per_mshr=20 111write_buffers=8 112writeback_clean=false 113cpu_side=system.cpu.dcache_port 114mem_side=system.l2bus.slave[1] 115 116[system.cpu.dcache.tags] 117type=LRU 118assoc=2 119block_size=64 120clk_domain=system.clk_domain 121eventq_index=0 122hit_latency=2 123sequential_access=false 124size=65536 125 126[system.cpu.dtb] 127type=SparcTLB 128eventq_index=0 129size=64 130 131[system.cpu.icache] 132type=Cache 133children=tags 134addr_ranges=0:18446744073709551615 135assoc=2 136clk_domain=system.clk_domain 137clusivity=mostly_incl 138demand_mshr_reserve=1 139eventq_index=0 140hit_latency=2 141is_read_only=false 142max_miss_count=0 143mshrs=4 144prefetch_on_access=false 145prefetcher=Null 146response_latency=2 147sequential_access=false 148size=16384 149system=system 150tags=system.cpu.icache.tags 151tgts_per_mshr=20 152write_buffers=8 153writeback_clean=false 154cpu_side=system.cpu.icache_port 155mem_side=system.l2bus.slave[0] 156 157[system.cpu.icache.tags] 158type=LRU 159assoc=2 160block_size=64 161clk_domain=system.clk_domain 162eventq_index=0 163hit_latency=2 164sequential_access=false 165size=16384 166 167[system.cpu.interrupts] 168type=SparcInterrupts 169eventq_index=0 170 171[system.cpu.isa] 172type=SparcISA 173eventq_index=0 174 175[system.cpu.itb] 176type=SparcTLB 177eventq_index=0 178size=64 179 180[system.cpu.tracer] 181type=ExeTracer 182eventq_index=0 183 184[system.cpu.workload] 185type=LiveProcess 186cmd=tests/test-progs/hello/bin/sparc/linux/hello 187cwd= 188drivers= 189egid=100 190env= 191errout=cerr 192euid=100 193eventq_index=0 194executable= 195gid=100 196input=cin 197kvmInSE=false 198max_stack_size=67108864 199output=cout 200pid=100 201ppid=99 202simpoint=0 203system=system 204uid=100 205useArchPT=false 206 207[system.dvfs_handler] 208type=DVFSHandler 209domains= 210enable=false 211eventq_index=0 212sys_clk_domain=system.clk_domain 213transition_latency=100000000 214 215[system.l2bus] 216type=CoherentXBar 217children=snoop_filter 218clk_domain=system.clk_domain 219eventq_index=0 220forward_latency=0 221frontend_latency=1 222point_of_coherency=false 223response_latency=1 224snoop_filter=system.l2bus.snoop_filter 225snoop_response_latency=1 226system=system 227use_default_range=false 228width=32 229master=system.l2cache.cpu_side 230slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side 231 232[system.l2bus.snoop_filter] 233type=SnoopFilter 234eventq_index=0 235lookup_latency=0 236max_capacity=8388608 237system=system 238 239[system.l2cache] 240type=Cache 241children=tags 242addr_ranges=0:18446744073709551615 243assoc=8 244clk_domain=system.clk_domain 245clusivity=mostly_incl 246demand_mshr_reserve=1 247eventq_index=0 248hit_latency=20 249is_read_only=false 250max_miss_count=0 251mshrs=20 252prefetch_on_access=false 253prefetcher=Null 254response_latency=20 255sequential_access=false 256size=262144 257system=system 258tags=system.l2cache.tags 259tgts_per_mshr=12 260write_buffers=8 261writeback_clean=false 262cpu_side=system.l2bus.master[0] 263mem_side=system.membus.slave[0] 264 265[system.l2cache.tags] 266type=LRU 267assoc=8 268block_size=64 269clk_domain=system.clk_domain 270eventq_index=0 271hit_latency=20 272sequential_access=false 273size=262144 274 275[system.mem_ctrl] 276type=DRAMCtrl 277IDD0=0.075000 278IDD02=0.000000 279IDD2N=0.050000 280IDD2N2=0.000000 281IDD2P0=0.000000 282IDD2P02=0.000000 283IDD2P1=0.000000 284IDD2P12=0.000000 285IDD3N=0.057000 286IDD3N2=0.000000 287IDD3P0=0.000000 288IDD3P02=0.000000 289IDD3P1=0.000000 290IDD3P12=0.000000 291IDD4R=0.187000 292IDD4R2=0.000000 293IDD4W=0.165000 294IDD4W2=0.000000 295IDD5=0.220000 296IDD52=0.000000 297IDD6=0.000000 298IDD62=0.000000 299VDD=1.500000 300VDD2=0.000000 301activation_limit=4 302addr_mapping=RoRaBaCoCh 303bank_groups_per_rank=0 304banks_per_rank=8 305burst_length=8 306channels=1 307clk_domain=system.clk_domain 308conf_table_reported=true 309device_bus_width=8 310device_rowbuffer_size=1024 311device_size=536870912 312devices_per_rank=8 313dll=true 314eventq_index=0 315in_addr_map=true 316max_accesses_per_row=16 317mem_sched_policy=frfcfs 318min_writes_per_switch=16 319null=false 320page_policy=open_adaptive 321range=0:536870911 322ranks_per_channel=2 323read_buffer_size=32 324static_backend_latency=10000 325static_frontend_latency=10000 326tBURST=5000 327tCCD_L=0 328tCK=1250 329tCL=13750 330tCS=2500 331tRAS=35000 332tRCD=13750 333tREFI=7800000 334tRFC=260000 335tRP=13750 336tRRD=6000 337tRRD_L=0 338tRTP=7500 339tRTW=2500 340tWR=15000 341tWTR=7500 342tXAW=30000 343tXP=0 344tXPDLL=0 345tXS=0 346tXSDLL=0 347write_buffer_size=64 348write_high_thresh_perc=85 349write_low_thresh_perc=50 350port=system.membus.master[0] 351 352[system.membus] 353type=CoherentXBar 354clk_domain=system.clk_domain 355eventq_index=0 356forward_latency=4 357frontend_latency=3 358point_of_coherency=true 359response_latency=2 360snoop_filter=Null 361snoop_response_latency=4 362system=system 363use_default_range=false 364width=16 365master=system.mem_ctrl.port 366slave=system.l2cache.mem_side system.system_port 367 368