stats.txt revision 11680:b4d943429dc6
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000052 # Number of seconds simulated 4sim_ticks 52453000 # Number of ticks simulated 5final_tick 52453000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 234245 # Simulator instruction rate (inst/s) 8host_op_rate 270642 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2457731659 # Simulator tick rate (ticks/s) 10host_mem_usage 654144 # Number of bytes of host memory used 11host_seconds 0.02 # Real time elapsed on the host 12sim_insts 4988 # Number of instructions simulated 13sim_ops 5770 # Number of ops (including micro ops) simulated 14system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 52453000 # Cumulative time (in ticks) in various power states 17system.mem_ctrl.bytes_read::cpu.inst 14400 # Number of bytes read from this memory 18system.mem_ctrl.bytes_read::cpu.data 8064 # Number of bytes read from this memory 19system.mem_ctrl.bytes_read::total 22464 # Number of bytes read from this memory 20system.mem_ctrl.bytes_inst_read::cpu.inst 14400 # Number of instructions bytes read from this memory 21system.mem_ctrl.bytes_inst_read::total 14400 # Number of instructions bytes read from this memory 22system.mem_ctrl.num_reads::cpu.inst 225 # Number of read requests responded to by this memory 23system.mem_ctrl.num_reads::cpu.data 126 # Number of read requests responded to by this memory 24system.mem_ctrl.num_reads::total 351 # Number of read requests responded to by this memory 25system.mem_ctrl.bw_read::cpu.inst 274531485 # Total read bandwidth from this memory (bytes/s) 26system.mem_ctrl.bw_read::cpu.data 153737632 # Total read bandwidth from this memory (bytes/s) 27system.mem_ctrl.bw_read::total 428269117 # Total read bandwidth from this memory (bytes/s) 28system.mem_ctrl.bw_inst_read::cpu.inst 274531485 # Instruction read bandwidth from this memory (bytes/s) 29system.mem_ctrl.bw_inst_read::total 274531485 # Instruction read bandwidth from this memory (bytes/s) 30system.mem_ctrl.bw_total::cpu.inst 274531485 # Total bandwidth to/from this memory (bytes/s) 31system.mem_ctrl.bw_total::cpu.data 153737632 # Total bandwidth to/from this memory (bytes/s) 32system.mem_ctrl.bw_total::total 428269117 # Total bandwidth to/from this memory (bytes/s) 33system.mem_ctrl.readReqs 351 # Number of read requests accepted 34system.mem_ctrl.writeReqs 0 # Number of write requests accepted 35system.mem_ctrl.readBursts 351 # Number of DRAM read bursts, including those serviced by the write queue 36system.mem_ctrl.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 37system.mem_ctrl.bytesReadDRAM 22464 # Total number of bytes read from DRAM 38system.mem_ctrl.bytesReadWrQ 0 # Total number of bytes read from write queue 39system.mem_ctrl.bytesWritten 0 # Total number of bytes written to DRAM 40system.mem_ctrl.bytesReadSys 22464 # Total read bytes from the system interface side 41system.mem_ctrl.bytesWrittenSys 0 # Total written bytes from the system interface side 42system.mem_ctrl.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 43system.mem_ctrl.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 44system.mem_ctrl.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 45system.mem_ctrl.perBankRdBursts::0 78 # Per bank write bursts 46system.mem_ctrl.perBankRdBursts::1 42 # Per bank write bursts 47system.mem_ctrl.perBankRdBursts::2 13 # Per bank write bursts 48system.mem_ctrl.perBankRdBursts::3 33 # Per bank write bursts 49system.mem_ctrl.perBankRdBursts::4 14 # Per bank write bursts 50system.mem_ctrl.perBankRdBursts::5 31 # Per bank write bursts 51system.mem_ctrl.perBankRdBursts::6 34 # Per bank write bursts 52system.mem_ctrl.perBankRdBursts::7 9 # Per bank write bursts 53system.mem_ctrl.perBankRdBursts::8 4 # Per bank write bursts 54system.mem_ctrl.perBankRdBursts::9 6 # Per bank write bursts 55system.mem_ctrl.perBankRdBursts::10 25 # Per bank write bursts 56system.mem_ctrl.perBankRdBursts::11 43 # Per bank write bursts 57system.mem_ctrl.perBankRdBursts::12 8 # Per bank write bursts 58system.mem_ctrl.perBankRdBursts::13 5 # Per bank write bursts 59system.mem_ctrl.perBankRdBursts::14 0 # Per bank write bursts 60system.mem_ctrl.perBankRdBursts::15 6 # Per bank write bursts 61system.mem_ctrl.perBankWrBursts::0 0 # Per bank write bursts 62system.mem_ctrl.perBankWrBursts::1 0 # Per bank write bursts 63system.mem_ctrl.perBankWrBursts::2 0 # Per bank write bursts 64system.mem_ctrl.perBankWrBursts::3 0 # Per bank write bursts 65system.mem_ctrl.perBankWrBursts::4 0 # Per bank write bursts 66system.mem_ctrl.perBankWrBursts::5 0 # Per bank write bursts 67system.mem_ctrl.perBankWrBursts::6 0 # Per bank write bursts 68system.mem_ctrl.perBankWrBursts::7 0 # Per bank write bursts 69system.mem_ctrl.perBankWrBursts::8 0 # Per bank write bursts 70system.mem_ctrl.perBankWrBursts::9 0 # Per bank write bursts 71system.mem_ctrl.perBankWrBursts::10 0 # Per bank write bursts 72system.mem_ctrl.perBankWrBursts::11 0 # Per bank write bursts 73system.mem_ctrl.perBankWrBursts::12 0 # Per bank write bursts 74system.mem_ctrl.perBankWrBursts::13 0 # Per bank write bursts 75system.mem_ctrl.perBankWrBursts::14 0 # Per bank write bursts 76system.mem_ctrl.perBankWrBursts::15 0 # Per bank write bursts 77system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry 78system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry 79system.mem_ctrl.totGap 52348000 # Total gap between requests 80system.mem_ctrl.readPktSize::0 0 # Read request sizes (log2) 81system.mem_ctrl.readPktSize::1 0 # Read request sizes (log2) 82system.mem_ctrl.readPktSize::2 0 # Read request sizes (log2) 83system.mem_ctrl.readPktSize::3 0 # Read request sizes (log2) 84system.mem_ctrl.readPktSize::4 0 # Read request sizes (log2) 85system.mem_ctrl.readPktSize::5 0 # Read request sizes (log2) 86system.mem_ctrl.readPktSize::6 351 # Read request sizes (log2) 87system.mem_ctrl.writePktSize::0 0 # Write request sizes (log2) 88system.mem_ctrl.writePktSize::1 0 # Write request sizes (log2) 89system.mem_ctrl.writePktSize::2 0 # Write request sizes (log2) 90system.mem_ctrl.writePktSize::3 0 # Write request sizes (log2) 91system.mem_ctrl.writePktSize::4 0 # Write request sizes (log2) 92system.mem_ctrl.writePktSize::5 0 # Write request sizes (log2) 93system.mem_ctrl.writePktSize::6 0 # Write request sizes (log2) 94system.mem_ctrl.rdQLenPdf::0 351 # What read queue length does an incoming req see 95system.mem_ctrl.rdQLenPdf::1 0 # What read queue length does an incoming req see 96system.mem_ctrl.rdQLenPdf::2 0 # What read queue length does an incoming req see 97system.mem_ctrl.rdQLenPdf::3 0 # What read queue length does an incoming req see 98system.mem_ctrl.rdQLenPdf::4 0 # What read queue length does an incoming req see 99system.mem_ctrl.rdQLenPdf::5 0 # What read queue length does an incoming req see 100system.mem_ctrl.rdQLenPdf::6 0 # What read queue length does an incoming req see 101system.mem_ctrl.rdQLenPdf::7 0 # What read queue length does an incoming req see 102system.mem_ctrl.rdQLenPdf::8 0 # What read queue length does an incoming req see 103system.mem_ctrl.rdQLenPdf::9 0 # What read queue length does an incoming req see 104system.mem_ctrl.rdQLenPdf::10 0 # What read queue length does an incoming req see 105system.mem_ctrl.rdQLenPdf::11 0 # What read queue length does an incoming req see 106system.mem_ctrl.rdQLenPdf::12 0 # What read queue length does an incoming req see 107system.mem_ctrl.rdQLenPdf::13 0 # What read queue length does an incoming req see 108system.mem_ctrl.rdQLenPdf::14 0 # What read queue length does an incoming req see 109system.mem_ctrl.rdQLenPdf::15 0 # What read queue length does an incoming req see 110system.mem_ctrl.rdQLenPdf::16 0 # What read queue length does an incoming req see 111system.mem_ctrl.rdQLenPdf::17 0 # What read queue length does an incoming req see 112system.mem_ctrl.rdQLenPdf::18 0 # What read queue length does an incoming req see 113system.mem_ctrl.rdQLenPdf::19 0 # What read queue length does an incoming req see 114system.mem_ctrl.rdQLenPdf::20 0 # What read queue length does an incoming req see 115system.mem_ctrl.rdQLenPdf::21 0 # What read queue length does an incoming req see 116system.mem_ctrl.rdQLenPdf::22 0 # What read queue length does an incoming req see 117system.mem_ctrl.rdQLenPdf::23 0 # What read queue length does an incoming req see 118system.mem_ctrl.rdQLenPdf::24 0 # What read queue length does an incoming req see 119system.mem_ctrl.rdQLenPdf::25 0 # What read queue length does an incoming req see 120system.mem_ctrl.rdQLenPdf::26 0 # What read queue length does an incoming req see 121system.mem_ctrl.rdQLenPdf::27 0 # What read queue length does an incoming req see 122system.mem_ctrl.rdQLenPdf::28 0 # What read queue length does an incoming req see 123system.mem_ctrl.rdQLenPdf::29 0 # What read queue length does an incoming req see 124system.mem_ctrl.rdQLenPdf::30 0 # What read queue length does an incoming req see 125system.mem_ctrl.rdQLenPdf::31 0 # What read queue length does an incoming req see 126system.mem_ctrl.wrQLenPdf::0 0 # What write queue length does an incoming req see 127system.mem_ctrl.wrQLenPdf::1 0 # What write queue length does an incoming req see 128system.mem_ctrl.wrQLenPdf::2 0 # What write queue length does an incoming req see 129system.mem_ctrl.wrQLenPdf::3 0 # What write queue length does an incoming req see 130system.mem_ctrl.wrQLenPdf::4 0 # What write queue length does an incoming req see 131system.mem_ctrl.wrQLenPdf::5 0 # What write queue length does an incoming req see 132system.mem_ctrl.wrQLenPdf::6 0 # What write queue length does an incoming req see 133system.mem_ctrl.wrQLenPdf::7 0 # What write queue length does an incoming req see 134system.mem_ctrl.wrQLenPdf::8 0 # What write queue length does an incoming req see 135system.mem_ctrl.wrQLenPdf::9 0 # What write queue length does an incoming req see 136system.mem_ctrl.wrQLenPdf::10 0 # What write queue length does an incoming req see 137system.mem_ctrl.wrQLenPdf::11 0 # What write queue length does an incoming req see 138system.mem_ctrl.wrQLenPdf::12 0 # What write queue length does an incoming req see 139system.mem_ctrl.wrQLenPdf::13 0 # What write queue length does an incoming req see 140system.mem_ctrl.wrQLenPdf::14 0 # What write queue length does an incoming req see 141system.mem_ctrl.wrQLenPdf::15 0 # What write queue length does an incoming req see 142system.mem_ctrl.wrQLenPdf::16 0 # What write queue length does an incoming req see 143system.mem_ctrl.wrQLenPdf::17 0 # What write queue length does an incoming req see 144system.mem_ctrl.wrQLenPdf::18 0 # What write queue length does an incoming req see 145system.mem_ctrl.wrQLenPdf::19 0 # What write queue length does an incoming req see 146system.mem_ctrl.wrQLenPdf::20 0 # What write queue length does an incoming req see 147system.mem_ctrl.wrQLenPdf::21 0 # What write queue length does an incoming req see 148system.mem_ctrl.wrQLenPdf::22 0 # What write queue length does an incoming req see 149system.mem_ctrl.wrQLenPdf::23 0 # What write queue length does an incoming req see 150system.mem_ctrl.wrQLenPdf::24 0 # What write queue length does an incoming req see 151system.mem_ctrl.wrQLenPdf::25 0 # What write queue length does an incoming req see 152system.mem_ctrl.wrQLenPdf::26 0 # What write queue length does an incoming req see 153system.mem_ctrl.wrQLenPdf::27 0 # What write queue length does an incoming req see 154system.mem_ctrl.wrQLenPdf::28 0 # What write queue length does an incoming req see 155system.mem_ctrl.wrQLenPdf::29 0 # What write queue length does an incoming req see 156system.mem_ctrl.wrQLenPdf::30 0 # What write queue length does an incoming req see 157system.mem_ctrl.wrQLenPdf::31 0 # What write queue length does an incoming req see 158system.mem_ctrl.wrQLenPdf::32 0 # What write queue length does an incoming req see 159system.mem_ctrl.wrQLenPdf::33 0 # What write queue length does an incoming req see 160system.mem_ctrl.wrQLenPdf::34 0 # What write queue length does an incoming req see 161system.mem_ctrl.wrQLenPdf::35 0 # What write queue length does an incoming req see 162system.mem_ctrl.wrQLenPdf::36 0 # What write queue length does an incoming req see 163system.mem_ctrl.wrQLenPdf::37 0 # What write queue length does an incoming req see 164system.mem_ctrl.wrQLenPdf::38 0 # What write queue length does an incoming req see 165system.mem_ctrl.wrQLenPdf::39 0 # What write queue length does an incoming req see 166system.mem_ctrl.wrQLenPdf::40 0 # What write queue length does an incoming req see 167system.mem_ctrl.wrQLenPdf::41 0 # What write queue length does an incoming req see 168system.mem_ctrl.wrQLenPdf::42 0 # What write queue length does an incoming req see 169system.mem_ctrl.wrQLenPdf::43 0 # What write queue length does an incoming req see 170system.mem_ctrl.wrQLenPdf::44 0 # What write queue length does an incoming req see 171system.mem_ctrl.wrQLenPdf::45 0 # What write queue length does an incoming req see 172system.mem_ctrl.wrQLenPdf::46 0 # What write queue length does an incoming req see 173system.mem_ctrl.wrQLenPdf::47 0 # What write queue length does an incoming req see 174system.mem_ctrl.wrQLenPdf::48 0 # What write queue length does an incoming req see 175system.mem_ctrl.wrQLenPdf::49 0 # What write queue length does an incoming req see 176system.mem_ctrl.wrQLenPdf::50 0 # What write queue length does an incoming req see 177system.mem_ctrl.wrQLenPdf::51 0 # What write queue length does an incoming req see 178system.mem_ctrl.wrQLenPdf::52 0 # What write queue length does an incoming req see 179system.mem_ctrl.wrQLenPdf::53 0 # What write queue length does an incoming req see 180system.mem_ctrl.wrQLenPdf::54 0 # What write queue length does an incoming req see 181system.mem_ctrl.wrQLenPdf::55 0 # What write queue length does an incoming req see 182system.mem_ctrl.wrQLenPdf::56 0 # What write queue length does an incoming req see 183system.mem_ctrl.wrQLenPdf::57 0 # What write queue length does an incoming req see 184system.mem_ctrl.wrQLenPdf::58 0 # What write queue length does an incoming req see 185system.mem_ctrl.wrQLenPdf::59 0 # What write queue length does an incoming req see 186system.mem_ctrl.wrQLenPdf::60 0 # What write queue length does an incoming req see 187system.mem_ctrl.wrQLenPdf::61 0 # What write queue length does an incoming req see 188system.mem_ctrl.wrQLenPdf::62 0 # What write queue length does an incoming req see 189system.mem_ctrl.wrQLenPdf::63 0 # What write queue length does an incoming req see 190system.mem_ctrl.bytesPerActivate::samples 75 # Bytes accessed per row activation 191system.mem_ctrl.bytesPerActivate::mean 285.866667 # Bytes accessed per row activation 192system.mem_ctrl.bytesPerActivate::gmean 188.503913 # Bytes accessed per row activation 193system.mem_ctrl.bytesPerActivate::stdev 282.583704 # Bytes accessed per row activation 194system.mem_ctrl.bytesPerActivate::0-127 22 29.33% 29.33% # Bytes accessed per row activation 195system.mem_ctrl.bytesPerActivate::128-255 20 26.67% 56.00% # Bytes accessed per row activation 196system.mem_ctrl.bytesPerActivate::256-383 15 20.00% 76.00% # Bytes accessed per row activation 197system.mem_ctrl.bytesPerActivate::384-511 4 5.33% 81.33% # Bytes accessed per row activation 198system.mem_ctrl.bytesPerActivate::512-639 4 5.33% 86.67% # Bytes accessed per row activation 199system.mem_ctrl.bytesPerActivate::640-767 2 2.67% 89.33% # Bytes accessed per row activation 200system.mem_ctrl.bytesPerActivate::768-895 2 2.67% 92.00% # Bytes accessed per row activation 201system.mem_ctrl.bytesPerActivate::1024-1151 6 8.00% 100.00% # Bytes accessed per row activation 202system.mem_ctrl.bytesPerActivate::total 75 # Bytes accessed per row activation 203system.mem_ctrl.totQLat 4720500 # Total ticks spent queuing 204system.mem_ctrl.totMemAccLat 11301750 # Total ticks spent from burst creation until serviced by the DRAM 205system.mem_ctrl.totBusLat 1755000 # Total ticks spent in databus transfers 206system.mem_ctrl.avgQLat 13448.72 # Average queueing delay per DRAM burst 207system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst 208system.mem_ctrl.avgMemAccLat 32198.72 # Average memory access latency per DRAM burst 209system.mem_ctrl.avgRdBW 428.27 # Average DRAM read bandwidth in MiByte/s 210system.mem_ctrl.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 211system.mem_ctrl.avgRdBWSys 428.27 # Average system read bandwidth in MiByte/s 212system.mem_ctrl.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 213system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 214system.mem_ctrl.busUtil 3.35 # Data bus utilization in percentage 215system.mem_ctrl.busUtilRead 3.35 # Data bus utilization in percentage for reads 216system.mem_ctrl.busUtilWrite 0.00 # Data bus utilization in percentage for writes 217system.mem_ctrl.avgRdQLen 1.00 # Average read queue length when enqueuing 218system.mem_ctrl.avgWrQLen 0.00 # Average write queue length when enqueuing 219system.mem_ctrl.readRowHits 270 # Number of row buffer hits during reads 220system.mem_ctrl.writeRowHits 0 # Number of row buffer hits during writes 221system.mem_ctrl.readRowHitRate 76.92 # Row buffer hit rate for reads 222system.mem_ctrl.writeRowHitRate nan # Row buffer hit rate for writes 223system.mem_ctrl.avgGap 149139.60 # Average gap between requests 224system.mem_ctrl.pageHitRate 76.92 # Row buffer hit rate, read and write combined 225system.mem_ctrl_0.actEnergy 378420 # Energy for activate commands per rank (pJ) 226system.mem_ctrl_0.preEnergy 189750 # Energy for precharge commands per rank (pJ) 227system.mem_ctrl_0.readEnergy 1813560 # Energy for read commands per rank (pJ) 228system.mem_ctrl_0.writeEnergy 0 # Energy for write commands per rank (pJ) 229system.mem_ctrl_0.refreshEnergy 3687840.000000 # Energy for refresh commands per rank (pJ) 230system.mem_ctrl_0.actBackEnergy 4500720 # Energy for active background per rank (pJ) 231system.mem_ctrl_0.preBackEnergy 84480 # Energy for precharge background per rank (pJ) 232system.mem_ctrl_0.actPowerDownEnergy 19212990 # Energy for active power-down per rank (pJ) 233system.mem_ctrl_0.prePowerDownEnergy 88320 # Energy for precharge power-down per rank (pJ) 234system.mem_ctrl_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) 235system.mem_ctrl_0.totalEnergy 29956080 # Total energy per rank (pJ) 236system.mem_ctrl_0.averagePower 571.095108 # Core power per rank (mW) 237system.mem_ctrl_0.totalIdleTime 42304000 # Total Idle time Per DRAM Rank 238system.mem_ctrl_0.memoryStateTime::IDLE 53000 # Time in different power states 239system.mem_ctrl_0.memoryStateTime::REF 1560000 # Time in different power states 240system.mem_ctrl_0.memoryStateTime::SREF 0 # Time in different power states 241system.mem_ctrl_0.memoryStateTime::PRE_PDN 229750 # Time in different power states 242system.mem_ctrl_0.memoryStateTime::ACT 8478750 # Time in different power states 243system.mem_ctrl_0.memoryStateTime::ACT_PDN 42131500 # Time in different power states 244system.mem_ctrl_1.actEnergy 199920 # Energy for activate commands per rank (pJ) 245system.mem_ctrl_1.preEnergy 94875 # Energy for precharge commands per rank (pJ) 246system.mem_ctrl_1.readEnergy 692580 # Energy for read commands per rank (pJ) 247system.mem_ctrl_1.writeEnergy 0 # Energy for write commands per rank (pJ) 248system.mem_ctrl_1.refreshEnergy 3687840.000000 # Energy for refresh commands per rank (pJ) 249system.mem_ctrl_1.actBackEnergy 2032620 # Energy for active background per rank (pJ) 250system.mem_ctrl_1.preBackEnergy 139680 # Energy for precharge background per rank (pJ) 251system.mem_ctrl_1.actPowerDownEnergy 19936320 # Energy for active power-down per rank (pJ) 252system.mem_ctrl_1.prePowerDownEnergy 1502400 # Energy for precharge power-down per rank (pJ) 253system.mem_ctrl_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) 254system.mem_ctrl_1.totalEnergy 28286235 # Total energy per rank (pJ) 255system.mem_ctrl_1.averagePower 539.260491 # Core power per rank (mW) 256system.mem_ctrl_1.totalIdleTime 44784500 # Total Idle time Per DRAM Rank 257system.mem_ctrl_1.memoryStateTime::IDLE 200000 # Time in different power states 258system.mem_ctrl_1.memoryStateTime::REF 1560000 # Time in different power states 259system.mem_ctrl_1.memoryStateTime::SREF 0 # Time in different power states 260system.mem_ctrl_1.memoryStateTime::PRE_PDN 3909750 # Time in different power states 261system.mem_ctrl_1.memoryStateTime::ACT 3056250 # Time in different power states 262system.mem_ctrl_1.memoryStateTime::ACT_PDN 43727000 # Time in different power states 263system.pwrStateResidencyTicks::UNDEFINED 52453000 # Cumulative time (in ticks) in various power states 264system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 52453000 # Cumulative time (in ticks) in various power states 265system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 266system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 267system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 268system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 269system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 270system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 271system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 272system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 273system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 274system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 275system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 276system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 277system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 278system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 279system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 280system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 281system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 282system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 283system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 284system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 285system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 286system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 287system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 288system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 289system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 290system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 291system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 292system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 293system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 294system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 52453000 # Cumulative time (in ticks) in various power states 295system.cpu.dtb.walker.walks 0 # Table walker walks requested 296system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 297system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 298system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 299system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 300system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 301system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 302system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 303system.cpu.dtb.inst_hits 0 # ITB inst hits 304system.cpu.dtb.inst_misses 0 # ITB inst misses 305system.cpu.dtb.read_hits 0 # DTB read hits 306system.cpu.dtb.read_misses 0 # DTB read misses 307system.cpu.dtb.write_hits 0 # DTB write hits 308system.cpu.dtb.write_misses 0 # DTB write misses 309system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 310system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 311system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 312system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 313system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 314system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 315system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 316system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 317system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 318system.cpu.dtb.read_accesses 0 # DTB read accesses 319system.cpu.dtb.write_accesses 0 # DTB write accesses 320system.cpu.dtb.inst_accesses 0 # ITB inst accesses 321system.cpu.dtb.hits 0 # DTB hits 322system.cpu.dtb.misses 0 # DTB misses 323system.cpu.dtb.accesses 0 # DTB accesses 324system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 52453000 # Cumulative time (in ticks) in various power states 325system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 326system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 327system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 328system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 329system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 330system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 331system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 332system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 333system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 334system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 335system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 336system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 337system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 338system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 339system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 340system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 341system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 342system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 343system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 344system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 345system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 346system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 347system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 348system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 349system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 350system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 351system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 352system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 353system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 354system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 52453000 # Cumulative time (in ticks) in various power states 355system.cpu.itb.walker.walks 0 # Table walker walks requested 356system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 357system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 358system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 359system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 360system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 361system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 362system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 363system.cpu.itb.inst_hits 0 # ITB inst hits 364system.cpu.itb.inst_misses 0 # ITB inst misses 365system.cpu.itb.read_hits 0 # DTB read hits 366system.cpu.itb.read_misses 0 # DTB read misses 367system.cpu.itb.write_hits 0 # DTB write hits 368system.cpu.itb.write_misses 0 # DTB write misses 369system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 370system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 371system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 372system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 373system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 374system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 375system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 376system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 377system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 378system.cpu.itb.read_accesses 0 # DTB read accesses 379system.cpu.itb.write_accesses 0 # DTB write accesses 380system.cpu.itb.inst_accesses 0 # ITB inst accesses 381system.cpu.itb.hits 0 # DTB hits 382system.cpu.itb.misses 0 # DTB misses 383system.cpu.itb.accesses 0 # DTB accesses 384system.cpu.workload.num_syscalls 13 # Number of system calls 385system.cpu.pwrStateResidencyTicks::ON 52453000 # Cumulative time (in ticks) in various power states 386system.cpu.numCycles 52453 # number of cpu cycles simulated 387system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 388system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 389system.cpu.committedInsts 4988 # Number of instructions committed 390system.cpu.committedOps 5770 # Number of ops (including micro ops) committed 391system.cpu.num_int_alu_accesses 4977 # Number of integer alu accesses 392system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses 393system.cpu.num_func_calls 215 # number of times a function call or return occured 394system.cpu.num_conditional_control_insts 800 # number of instructions that are conditional controls 395system.cpu.num_int_insts 4977 # number of integer instructions 396system.cpu.num_fp_insts 16 # number of float instructions 397system.cpu.num_int_register_reads 8049 # number of times the integer registers were read 398system.cpu.num_int_register_writes 2992 # number of times the integer registers were written 399system.cpu.num_fp_register_reads 16 # number of times the floating registers were read 400system.cpu.num_fp_register_writes 0 # number of times the floating registers were written 401system.cpu.num_cc_register_reads 20681 # number of times the CC registers were read 402system.cpu.num_cc_register_writes 2647 # number of times the CC registers were written 403system.cpu.num_mem_refs 2035 # number of memory refs 404system.cpu.num_load_insts 1085 # Number of load instructions 405system.cpu.num_store_insts 950 # Number of store instructions 406system.cpu.num_idle_cycles 0.001000 # Number of idle cycles 407system.cpu.num_busy_cycles 52452.999000 # Number of busy cycles 408system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles 409system.cpu.idle_fraction 0.000000 # Percentage of idle cycles 410system.cpu.Branches 1107 # Number of branches fetched 411system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction 412system.cpu.op_class::IntAlu 3789 64.98% 64.98% # Class of executed instruction 413system.cpu.op_class::IntMult 4 0.07% 65.05% # Class of executed instruction 414system.cpu.op_class::IntDiv 0 0.00% 65.05% # Class of executed instruction 415system.cpu.op_class::FloatAdd 0 0.00% 65.05% # Class of executed instruction 416system.cpu.op_class::FloatCmp 0 0.00% 65.05% # Class of executed instruction 417system.cpu.op_class::FloatCvt 0 0.00% 65.05% # Class of executed instruction 418system.cpu.op_class::FloatMult 0 0.00% 65.05% # Class of executed instruction 419system.cpu.op_class::FloatDiv 0 0.00% 65.05% # Class of executed instruction 420system.cpu.op_class::FloatSqrt 0 0.00% 65.05% # Class of executed instruction 421system.cpu.op_class::SimdAdd 0 0.00% 65.05% # Class of executed instruction 422system.cpu.op_class::SimdAddAcc 0 0.00% 65.05% # Class of executed instruction 423system.cpu.op_class::SimdAlu 0 0.00% 65.05% # Class of executed instruction 424system.cpu.op_class::SimdCmp 0 0.00% 65.05% # Class of executed instruction 425system.cpu.op_class::SimdCvt 0 0.00% 65.05% # Class of executed instruction 426system.cpu.op_class::SimdMisc 0 0.00% 65.05% # Class of executed instruction 427system.cpu.op_class::SimdMult 0 0.00% 65.05% # Class of executed instruction 428system.cpu.op_class::SimdMultAcc 0 0.00% 65.05% # Class of executed instruction 429system.cpu.op_class::SimdShift 0 0.00% 65.05% # Class of executed instruction 430system.cpu.op_class::SimdShiftAcc 0 0.00% 65.05% # Class of executed instruction 431system.cpu.op_class::SimdSqrt 0 0.00% 65.05% # Class of executed instruction 432system.cpu.op_class::SimdFloatAdd 0 0.00% 65.05% # Class of executed instruction 433system.cpu.op_class::SimdFloatAlu 0 0.00% 65.05% # Class of executed instruction 434system.cpu.op_class::SimdFloatCmp 0 0.00% 65.05% # Class of executed instruction 435system.cpu.op_class::SimdFloatCvt 0 0.00% 65.05% # Class of executed instruction 436system.cpu.op_class::SimdFloatDiv 0 0.00% 65.05% # Class of executed instruction 437system.cpu.op_class::SimdFloatMisc 3 0.05% 65.10% # Class of executed instruction 438system.cpu.op_class::SimdFloatMult 0 0.00% 65.10% # Class of executed instruction 439system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.10% # Class of executed instruction 440system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.10% # Class of executed instruction 441system.cpu.op_class::MemRead 1085 18.61% 83.71% # Class of executed instruction 442system.cpu.op_class::MemWrite 950 16.29% 100.00% # Class of executed instruction 443system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 444system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 445system.cpu.op_class::total 5831 # Class of executed instruction 446system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 52453000 # Cumulative time (in ticks) in various power states 447system.cpu.dcache.tags.replacements 0 # number of replacements 448system.cpu.dcache.tags.tagsinuse 84.380856 # Cycle average of tags in use 449system.cpu.dcache.tags.total_refs 1855 # Total number of references to valid blocks. 450system.cpu.dcache.tags.sampled_refs 142 # Sample count of references to valid blocks. 451system.cpu.dcache.tags.avg_refs 13.063380 # Average number of references to valid blocks. 452system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 453system.cpu.dcache.tags.occ_blocks::cpu.data 84.380856 # Average occupied blocks per requestor 454system.cpu.dcache.tags.occ_percent::cpu.data 0.082403 # Average percentage of cache occupancy 455system.cpu.dcache.tags.occ_percent::total 0.082403 # Average percentage of cache occupancy 456system.cpu.dcache.tags.occ_task_id_blocks::1024 142 # Occupied blocks per task id 457system.cpu.dcache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id 458system.cpu.dcache.tags.age_task_id_blocks_1024::1 123 # Occupied blocks per task id 459system.cpu.dcache.tags.occ_task_id_percent::1024 0.138672 # Percentage of cache occupancy per task id 460system.cpu.dcache.tags.tag_accesses 4136 # Number of tag accesses 461system.cpu.dcache.tags.data_accesses 4136 # Number of data accesses 462system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 52453000 # Cumulative time (in ticks) in various power states 463system.cpu.dcache.ReadReq_hits::cpu.data 951 # number of ReadReq hits 464system.cpu.dcache.ReadReq_hits::total 951 # number of ReadReq hits 465system.cpu.dcache.WriteReq_hits::cpu.data 882 # number of WriteReq hits 466system.cpu.dcache.WriteReq_hits::total 882 # number of WriteReq hits 467system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits 468system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits 469system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits 470system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits 471system.cpu.dcache.demand_hits::cpu.data 1833 # number of demand (read+write) hits 472system.cpu.dcache.demand_hits::total 1833 # number of demand (read+write) hits 473system.cpu.dcache.overall_hits::cpu.data 1833 # number of overall hits 474system.cpu.dcache.overall_hits::total 1833 # number of overall hits 475system.cpu.dcache.ReadReq_misses::cpu.data 99 # number of ReadReq misses 476system.cpu.dcache.ReadReq_misses::total 99 # number of ReadReq misses 477system.cpu.dcache.WriteReq_misses::cpu.data 43 # number of WriteReq misses 478system.cpu.dcache.WriteReq_misses::total 43 # number of WriteReq misses 479system.cpu.dcache.demand_misses::cpu.data 142 # number of demand (read+write) misses 480system.cpu.dcache.demand_misses::total 142 # number of demand (read+write) misses 481system.cpu.dcache.overall_misses::cpu.data 142 # number of overall misses 482system.cpu.dcache.overall_misses::total 142 # number of overall misses 483system.cpu.dcache.ReadReq_miss_latency::cpu.data 9073000 # number of ReadReq miss cycles 484system.cpu.dcache.ReadReq_miss_latency::total 9073000 # number of ReadReq miss cycles 485system.cpu.dcache.WriteReq_miss_latency::cpu.data 4652000 # number of WriteReq miss cycles 486system.cpu.dcache.WriteReq_miss_latency::total 4652000 # number of WriteReq miss cycles 487system.cpu.dcache.demand_miss_latency::cpu.data 13725000 # number of demand (read+write) miss cycles 488system.cpu.dcache.demand_miss_latency::total 13725000 # number of demand (read+write) miss cycles 489system.cpu.dcache.overall_miss_latency::cpu.data 13725000 # number of overall miss cycles 490system.cpu.dcache.overall_miss_latency::total 13725000 # number of overall miss cycles 491system.cpu.dcache.ReadReq_accesses::cpu.data 1050 # number of ReadReq accesses(hits+misses) 492system.cpu.dcache.ReadReq_accesses::total 1050 # number of ReadReq accesses(hits+misses) 493system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses) 494system.cpu.dcache.WriteReq_accesses::total 925 # number of WriteReq accesses(hits+misses) 495system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses) 496system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses) 497system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) 498system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) 499system.cpu.dcache.demand_accesses::cpu.data 1975 # number of demand (read+write) accesses 500system.cpu.dcache.demand_accesses::total 1975 # number of demand (read+write) accesses 501system.cpu.dcache.overall_accesses::cpu.data 1975 # number of overall (read+write) accesses 502system.cpu.dcache.overall_accesses::total 1975 # number of overall (read+write) accesses 503system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.094286 # miss rate for ReadReq accesses 504system.cpu.dcache.ReadReq_miss_rate::total 0.094286 # miss rate for ReadReq accesses 505system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.046486 # miss rate for WriteReq accesses 506system.cpu.dcache.WriteReq_miss_rate::total 0.046486 # miss rate for WriteReq accesses 507system.cpu.dcache.demand_miss_rate::cpu.data 0.071899 # miss rate for demand accesses 508system.cpu.dcache.demand_miss_rate::total 0.071899 # miss rate for demand accesses 509system.cpu.dcache.overall_miss_rate::cpu.data 0.071899 # miss rate for overall accesses 510system.cpu.dcache.overall_miss_rate::total 0.071899 # miss rate for overall accesses 511system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 91646.464646 # average ReadReq miss latency 512system.cpu.dcache.ReadReq_avg_miss_latency::total 91646.464646 # average ReadReq miss latency 513system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 108186.046512 # average WriteReq miss latency 514system.cpu.dcache.WriteReq_avg_miss_latency::total 108186.046512 # average WriteReq miss latency 515system.cpu.dcache.demand_avg_miss_latency::cpu.data 96654.929577 # average overall miss latency 516system.cpu.dcache.demand_avg_miss_latency::total 96654.929577 # average overall miss latency 517system.cpu.dcache.overall_avg_miss_latency::cpu.data 96654.929577 # average overall miss latency 518system.cpu.dcache.overall_avg_miss_latency::total 96654.929577 # average overall miss latency 519system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 520system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 521system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 522system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 523system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 524system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 525system.cpu.dcache.ReadReq_mshr_misses::cpu.data 99 # number of ReadReq MSHR misses 526system.cpu.dcache.ReadReq_mshr_misses::total 99 # number of ReadReq MSHR misses 527system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43 # number of WriteReq MSHR misses 528system.cpu.dcache.WriteReq_mshr_misses::total 43 # number of WriteReq MSHR misses 529system.cpu.dcache.demand_mshr_misses::cpu.data 142 # number of demand (read+write) MSHR misses 530system.cpu.dcache.demand_mshr_misses::total 142 # number of demand (read+write) MSHR misses 531system.cpu.dcache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses 532system.cpu.dcache.overall_mshr_misses::total 142 # number of overall MSHR misses 533system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8875000 # number of ReadReq MSHR miss cycles 534system.cpu.dcache.ReadReq_mshr_miss_latency::total 8875000 # number of ReadReq MSHR miss cycles 535system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4566000 # number of WriteReq MSHR miss cycles 536system.cpu.dcache.WriteReq_mshr_miss_latency::total 4566000 # number of WriteReq MSHR miss cycles 537system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13441000 # number of demand (read+write) MSHR miss cycles 538system.cpu.dcache.demand_mshr_miss_latency::total 13441000 # number of demand (read+write) MSHR miss cycles 539system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13441000 # number of overall MSHR miss cycles 540system.cpu.dcache.overall_mshr_miss_latency::total 13441000 # number of overall MSHR miss cycles 541system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.094286 # mshr miss rate for ReadReq accesses 542system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.094286 # mshr miss rate for ReadReq accesses 543system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046486 # mshr miss rate for WriteReq accesses 544system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046486 # mshr miss rate for WriteReq accesses 545system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.071899 # mshr miss rate for demand accesses 546system.cpu.dcache.demand_mshr_miss_rate::total 0.071899 # mshr miss rate for demand accesses 547system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.071899 # mshr miss rate for overall accesses 548system.cpu.dcache.overall_mshr_miss_rate::total 0.071899 # mshr miss rate for overall accesses 549system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 89646.464646 # average ReadReq mshr miss latency 550system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 89646.464646 # average ReadReq mshr miss latency 551system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 106186.046512 # average WriteReq mshr miss latency 552system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 106186.046512 # average WriteReq mshr miss latency 553system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 94654.929577 # average overall mshr miss latency 554system.cpu.dcache.demand_avg_mshr_miss_latency::total 94654.929577 # average overall mshr miss latency 555system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 94654.929577 # average overall mshr miss latency 556system.cpu.dcache.overall_avg_mshr_miss_latency::total 94654.929577 # average overall mshr miss latency 557system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 52453000 # Cumulative time (in ticks) in various power states 558system.cpu.icache.tags.replacements 70 # number of replacements 559system.cpu.icache.tags.tagsinuse 96.586088 # Cycle average of tags in use 560system.cpu.icache.tags.total_refs 4779 # Total number of references to valid blocks. 561system.cpu.icache.tags.sampled_refs 249 # Sample count of references to valid blocks. 562system.cpu.icache.tags.avg_refs 19.192771 # Average number of references to valid blocks. 563system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 564system.cpu.icache.tags.occ_blocks::cpu.inst 96.586088 # Average occupied blocks per requestor 565system.cpu.icache.tags.occ_percent::cpu.inst 0.377289 # Average percentage of cache occupancy 566system.cpu.icache.tags.occ_percent::total 0.377289 # Average percentage of cache occupancy 567system.cpu.icache.tags.occ_task_id_blocks::1024 179 # Occupied blocks per task id 568system.cpu.icache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id 569system.cpu.icache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id 570system.cpu.icache.tags.occ_task_id_percent::1024 0.699219 # Percentage of cache occupancy per task id 571system.cpu.icache.tags.tag_accesses 10305 # Number of tag accesses 572system.cpu.icache.tags.data_accesses 10305 # Number of data accesses 573system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 52453000 # Cumulative time (in ticks) in various power states 574system.cpu.icache.ReadReq_hits::cpu.inst 4779 # number of ReadReq hits 575system.cpu.icache.ReadReq_hits::total 4779 # number of ReadReq hits 576system.cpu.icache.demand_hits::cpu.inst 4779 # number of demand (read+write) hits 577system.cpu.icache.demand_hits::total 4779 # number of demand (read+write) hits 578system.cpu.icache.overall_hits::cpu.inst 4779 # number of overall hits 579system.cpu.icache.overall_hits::total 4779 # number of overall hits 580system.cpu.icache.ReadReq_misses::cpu.inst 249 # number of ReadReq misses 581system.cpu.icache.ReadReq_misses::total 249 # number of ReadReq misses 582system.cpu.icache.demand_misses::cpu.inst 249 # number of demand (read+write) misses 583system.cpu.icache.demand_misses::total 249 # number of demand (read+write) misses 584system.cpu.icache.overall_misses::cpu.inst 249 # number of overall misses 585system.cpu.icache.overall_misses::total 249 # number of overall misses 586system.cpu.icache.ReadReq_miss_latency::cpu.inst 25472000 # number of ReadReq miss cycles 587system.cpu.icache.ReadReq_miss_latency::total 25472000 # number of ReadReq miss cycles 588system.cpu.icache.demand_miss_latency::cpu.inst 25472000 # number of demand (read+write) miss cycles 589system.cpu.icache.demand_miss_latency::total 25472000 # number of demand (read+write) miss cycles 590system.cpu.icache.overall_miss_latency::cpu.inst 25472000 # number of overall miss cycles 591system.cpu.icache.overall_miss_latency::total 25472000 # number of overall miss cycles 592system.cpu.icache.ReadReq_accesses::cpu.inst 5028 # number of ReadReq accesses(hits+misses) 593system.cpu.icache.ReadReq_accesses::total 5028 # number of ReadReq accesses(hits+misses) 594system.cpu.icache.demand_accesses::cpu.inst 5028 # number of demand (read+write) accesses 595system.cpu.icache.demand_accesses::total 5028 # number of demand (read+write) accesses 596system.cpu.icache.overall_accesses::cpu.inst 5028 # number of overall (read+write) accesses 597system.cpu.icache.overall_accesses::total 5028 # number of overall (read+write) accesses 598system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.049523 # miss rate for ReadReq accesses 599system.cpu.icache.ReadReq_miss_rate::total 0.049523 # miss rate for ReadReq accesses 600system.cpu.icache.demand_miss_rate::cpu.inst 0.049523 # miss rate for demand accesses 601system.cpu.icache.demand_miss_rate::total 0.049523 # miss rate for demand accesses 602system.cpu.icache.overall_miss_rate::cpu.inst 0.049523 # miss rate for overall accesses 603system.cpu.icache.overall_miss_rate::total 0.049523 # miss rate for overall accesses 604system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 102297.188755 # average ReadReq miss latency 605system.cpu.icache.ReadReq_avg_miss_latency::total 102297.188755 # average ReadReq miss latency 606system.cpu.icache.demand_avg_miss_latency::cpu.inst 102297.188755 # average overall miss latency 607system.cpu.icache.demand_avg_miss_latency::total 102297.188755 # average overall miss latency 608system.cpu.icache.overall_avg_miss_latency::cpu.inst 102297.188755 # average overall miss latency 609system.cpu.icache.overall_avg_miss_latency::total 102297.188755 # average overall miss latency 610system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 611system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 612system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 613system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 614system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 615system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 616system.cpu.icache.ReadReq_mshr_misses::cpu.inst 249 # number of ReadReq MSHR misses 617system.cpu.icache.ReadReq_mshr_misses::total 249 # number of ReadReq MSHR misses 618system.cpu.icache.demand_mshr_misses::cpu.inst 249 # number of demand (read+write) MSHR misses 619system.cpu.icache.demand_mshr_misses::total 249 # number of demand (read+write) MSHR misses 620system.cpu.icache.overall_mshr_misses::cpu.inst 249 # number of overall MSHR misses 621system.cpu.icache.overall_mshr_misses::total 249 # number of overall MSHR misses 622system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24974000 # number of ReadReq MSHR miss cycles 623system.cpu.icache.ReadReq_mshr_miss_latency::total 24974000 # number of ReadReq MSHR miss cycles 624system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24974000 # number of demand (read+write) MSHR miss cycles 625system.cpu.icache.demand_mshr_miss_latency::total 24974000 # number of demand (read+write) MSHR miss cycles 626system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24974000 # number of overall MSHR miss cycles 627system.cpu.icache.overall_mshr_miss_latency::total 24974000 # number of overall MSHR miss cycles 628system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.049523 # mshr miss rate for ReadReq accesses 629system.cpu.icache.ReadReq_mshr_miss_rate::total 0.049523 # mshr miss rate for ReadReq accesses 630system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.049523 # mshr miss rate for demand accesses 631system.cpu.icache.demand_mshr_miss_rate::total 0.049523 # mshr miss rate for demand accesses 632system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.049523 # mshr miss rate for overall accesses 633system.cpu.icache.overall_mshr_miss_rate::total 0.049523 # mshr miss rate for overall accesses 634system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 100297.188755 # average ReadReq mshr miss latency 635system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 100297.188755 # average ReadReq mshr miss latency 636system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 100297.188755 # average overall mshr miss latency 637system.cpu.icache.demand_avg_mshr_miss_latency::total 100297.188755 # average overall mshr miss latency 638system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 100297.188755 # average overall mshr miss latency 639system.cpu.icache.overall_avg_mshr_miss_latency::total 100297.188755 # average overall mshr miss latency 640system.l2bus.snoop_filter.tot_requests 461 # Total number of requests made to the snoop filter. 641system.l2bus.snoop_filter.hit_single_requests 94 # Number of requests hitting in the snoop filter with a single holder of the requested data. 642system.l2bus.snoop_filter.hit_multi_requests 10 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 643system.l2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 644system.l2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 645system.l2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 646system.l2bus.pwrStateResidencyTicks::UNDEFINED 52453000 # Cumulative time (in ticks) in various power states 647system.l2bus.trans_dist::ReadResp 348 # Transaction distribution 648system.l2bus.trans_dist::CleanEvict 70 # Transaction distribution 649system.l2bus.trans_dist::ReadExReq 43 # Transaction distribution 650system.l2bus.trans_dist::ReadExResp 43 # Transaction distribution 651system.l2bus.trans_dist::ReadSharedReq 348 # Transaction distribution 652system.l2bus.pkt_count_system.cpu.icache.mem_side::system.l2cache.cpu_side 568 # Packet count per connected master and slave (bytes) 653system.l2bus.pkt_count_system.cpu.dcache.mem_side::system.l2cache.cpu_side 284 # Packet count per connected master and slave (bytes) 654system.l2bus.pkt_count::total 852 # Packet count per connected master and slave (bytes) 655system.l2bus.pkt_size_system.cpu.icache.mem_side::system.l2cache.cpu_side 15936 # Cumulative packet size per connected master and slave (bytes) 656system.l2bus.pkt_size_system.cpu.dcache.mem_side::system.l2cache.cpu_side 9088 # Cumulative packet size per connected master and slave (bytes) 657system.l2bus.pkt_size::total 25024 # Cumulative packet size per connected master and slave (bytes) 658system.l2bus.snoops 0 # Total snoops (count) 659system.l2bus.snoopTraffic 0 # Total snoop traffic (bytes) 660system.l2bus.snoop_fanout::samples 391 # Request fanout histogram 661system.l2bus.snoop_fanout::mean 0.086957 # Request fanout histogram 662system.l2bus.snoop_fanout::stdev 0.282132 # Request fanout histogram 663system.l2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 664system.l2bus.snoop_fanout::0 357 91.30% 91.30% # Request fanout histogram 665system.l2bus.snoop_fanout::1 34 8.70% 100.00% # Request fanout histogram 666system.l2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 667system.l2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 668system.l2bus.snoop_fanout::min_value 0 # Request fanout histogram 669system.l2bus.snoop_fanout::max_value 1 # Request fanout histogram 670system.l2bus.snoop_fanout::total 391 # Request fanout histogram 671system.l2bus.reqLayer0.occupancy 461000 # Layer occupancy (ticks) 672system.l2bus.reqLayer0.utilization 0.9 # Layer utilization (%) 673system.l2bus.respLayer0.occupancy 747000 # Layer occupancy (ticks) 674system.l2bus.respLayer0.utilization 1.4 # Layer utilization (%) 675system.l2bus.respLayer1.occupancy 426000 # Layer occupancy (ticks) 676system.l2bus.respLayer1.utilization 0.8 # Layer utilization (%) 677system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 52453000 # Cumulative time (in ticks) in various power states 678system.l2cache.tags.replacements 0 # number of replacements 679system.l2cache.tags.tagsinuse 184.362995 # Cycle average of tags in use 680system.l2cache.tags.total_refs 100 # Total number of references to valid blocks. 681system.l2cache.tags.sampled_refs 351 # Sample count of references to valid blocks. 682system.l2cache.tags.avg_refs 0.284900 # Average number of references to valid blocks. 683system.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 684system.l2cache.tags.occ_blocks::cpu.inst 107.367017 # Average occupied blocks per requestor 685system.l2cache.tags.occ_blocks::cpu.data 76.995978 # Average occupied blocks per requestor 686system.l2cache.tags.occ_percent::cpu.inst 0.026213 # Average percentage of cache occupancy 687system.l2cache.tags.occ_percent::cpu.data 0.018798 # Average percentage of cache occupancy 688system.l2cache.tags.occ_percent::total 0.045010 # Average percentage of cache occupancy 689system.l2cache.tags.occ_task_id_blocks::1024 351 # Occupied blocks per task id 690system.l2cache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id 691system.l2cache.tags.age_task_id_blocks_1024::1 292 # Occupied blocks per task id 692system.l2cache.tags.occ_task_id_percent::1024 0.085693 # Percentage of cache occupancy per task id 693system.l2cache.tags.tag_accesses 3959 # Number of tag accesses 694system.l2cache.tags.data_accesses 3959 # Number of data accesses 695system.l2cache.pwrStateResidencyTicks::UNDEFINED 52453000 # Cumulative time (in ticks) in various power states 696system.l2cache.ReadSharedReq_hits::cpu.inst 24 # number of ReadSharedReq hits 697system.l2cache.ReadSharedReq_hits::cpu.data 16 # number of ReadSharedReq hits 698system.l2cache.ReadSharedReq_hits::total 40 # number of ReadSharedReq hits 699system.l2cache.demand_hits::cpu.inst 24 # number of demand (read+write) hits 700system.l2cache.demand_hits::cpu.data 16 # number of demand (read+write) hits 701system.l2cache.demand_hits::total 40 # number of demand (read+write) hits 702system.l2cache.overall_hits::cpu.inst 24 # number of overall hits 703system.l2cache.overall_hits::cpu.data 16 # number of overall hits 704system.l2cache.overall_hits::total 40 # number of overall hits 705system.l2cache.ReadExReq_misses::cpu.data 43 # number of ReadExReq misses 706system.l2cache.ReadExReq_misses::total 43 # number of ReadExReq misses 707system.l2cache.ReadSharedReq_misses::cpu.inst 225 # number of ReadSharedReq misses 708system.l2cache.ReadSharedReq_misses::cpu.data 83 # number of ReadSharedReq misses 709system.l2cache.ReadSharedReq_misses::total 308 # number of ReadSharedReq misses 710system.l2cache.demand_misses::cpu.inst 225 # number of demand (read+write) misses 711system.l2cache.demand_misses::cpu.data 126 # number of demand (read+write) misses 712system.l2cache.demand_misses::total 351 # number of demand (read+write) misses 713system.l2cache.overall_misses::cpu.inst 225 # number of overall misses 714system.l2cache.overall_misses::cpu.data 126 # number of overall misses 715system.l2cache.overall_misses::total 351 # number of overall misses 716system.l2cache.ReadExReq_miss_latency::cpu.data 4437000 # number of ReadExReq miss cycles 717system.l2cache.ReadExReq_miss_latency::total 4437000 # number of ReadExReq miss cycles 718system.l2cache.ReadSharedReq_miss_latency::cpu.inst 23683000 # number of ReadSharedReq miss cycles 719system.l2cache.ReadSharedReq_miss_latency::cpu.data 8214000 # number of ReadSharedReq miss cycles 720system.l2cache.ReadSharedReq_miss_latency::total 31897000 # number of ReadSharedReq miss cycles 721system.l2cache.demand_miss_latency::cpu.inst 23683000 # number of demand (read+write) miss cycles 722system.l2cache.demand_miss_latency::cpu.data 12651000 # number of demand (read+write) miss cycles 723system.l2cache.demand_miss_latency::total 36334000 # number of demand (read+write) miss cycles 724system.l2cache.overall_miss_latency::cpu.inst 23683000 # number of overall miss cycles 725system.l2cache.overall_miss_latency::cpu.data 12651000 # number of overall miss cycles 726system.l2cache.overall_miss_latency::total 36334000 # number of overall miss cycles 727system.l2cache.ReadExReq_accesses::cpu.data 43 # number of ReadExReq accesses(hits+misses) 728system.l2cache.ReadExReq_accesses::total 43 # number of ReadExReq accesses(hits+misses) 729system.l2cache.ReadSharedReq_accesses::cpu.inst 249 # number of ReadSharedReq accesses(hits+misses) 730system.l2cache.ReadSharedReq_accesses::cpu.data 99 # number of ReadSharedReq accesses(hits+misses) 731system.l2cache.ReadSharedReq_accesses::total 348 # number of ReadSharedReq accesses(hits+misses) 732system.l2cache.demand_accesses::cpu.inst 249 # number of demand (read+write) accesses 733system.l2cache.demand_accesses::cpu.data 142 # number of demand (read+write) accesses 734system.l2cache.demand_accesses::total 391 # number of demand (read+write) accesses 735system.l2cache.overall_accesses::cpu.inst 249 # number of overall (read+write) accesses 736system.l2cache.overall_accesses::cpu.data 142 # number of overall (read+write) accesses 737system.l2cache.overall_accesses::total 391 # number of overall (read+write) accesses 738system.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 739system.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 740system.l2cache.ReadSharedReq_miss_rate::cpu.inst 0.903614 # miss rate for ReadSharedReq accesses 741system.l2cache.ReadSharedReq_miss_rate::cpu.data 0.838384 # miss rate for ReadSharedReq accesses 742system.l2cache.ReadSharedReq_miss_rate::total 0.885057 # miss rate for ReadSharedReq accesses 743system.l2cache.demand_miss_rate::cpu.inst 0.903614 # miss rate for demand accesses 744system.l2cache.demand_miss_rate::cpu.data 0.887324 # miss rate for demand accesses 745system.l2cache.demand_miss_rate::total 0.897698 # miss rate for demand accesses 746system.l2cache.overall_miss_rate::cpu.inst 0.903614 # miss rate for overall accesses 747system.l2cache.overall_miss_rate::cpu.data 0.887324 # miss rate for overall accesses 748system.l2cache.overall_miss_rate::total 0.897698 # miss rate for overall accesses 749system.l2cache.ReadExReq_avg_miss_latency::cpu.data 103186.046512 # average ReadExReq miss latency 750system.l2cache.ReadExReq_avg_miss_latency::total 103186.046512 # average ReadExReq miss latency 751system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 105257.777778 # average ReadSharedReq miss latency 752system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 98963.855422 # average ReadSharedReq miss latency 753system.l2cache.ReadSharedReq_avg_miss_latency::total 103561.688312 # average ReadSharedReq miss latency 754system.l2cache.demand_avg_miss_latency::cpu.inst 105257.777778 # average overall miss latency 755system.l2cache.demand_avg_miss_latency::cpu.data 100404.761905 # average overall miss latency 756system.l2cache.demand_avg_miss_latency::total 103515.669516 # average overall miss latency 757system.l2cache.overall_avg_miss_latency::cpu.inst 105257.777778 # average overall miss latency 758system.l2cache.overall_avg_miss_latency::cpu.data 100404.761905 # average overall miss latency 759system.l2cache.overall_avg_miss_latency::total 103515.669516 # average overall miss latency 760system.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 761system.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 762system.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 763system.l2cache.blocked::no_targets 0 # number of cycles access was blocked 764system.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 765system.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 766system.l2cache.ReadExReq_mshr_misses::cpu.data 43 # number of ReadExReq MSHR misses 767system.l2cache.ReadExReq_mshr_misses::total 43 # number of ReadExReq MSHR misses 768system.l2cache.ReadSharedReq_mshr_misses::cpu.inst 225 # number of ReadSharedReq MSHR misses 769system.l2cache.ReadSharedReq_mshr_misses::cpu.data 83 # number of ReadSharedReq MSHR misses 770system.l2cache.ReadSharedReq_mshr_misses::total 308 # number of ReadSharedReq MSHR misses 771system.l2cache.demand_mshr_misses::cpu.inst 225 # number of demand (read+write) MSHR misses 772system.l2cache.demand_mshr_misses::cpu.data 126 # number of demand (read+write) MSHR misses 773system.l2cache.demand_mshr_misses::total 351 # number of demand (read+write) MSHR misses 774system.l2cache.overall_mshr_misses::cpu.inst 225 # number of overall MSHR misses 775system.l2cache.overall_mshr_misses::cpu.data 126 # number of overall MSHR misses 776system.l2cache.overall_mshr_misses::total 351 # number of overall MSHR misses 777system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3577000 # number of ReadExReq MSHR miss cycles 778system.l2cache.ReadExReq_mshr_miss_latency::total 3577000 # number of ReadExReq MSHR miss cycles 779system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 19183000 # number of ReadSharedReq MSHR miss cycles 780system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6554000 # number of ReadSharedReq MSHR miss cycles 781system.l2cache.ReadSharedReq_mshr_miss_latency::total 25737000 # number of ReadSharedReq MSHR miss cycles 782system.l2cache.demand_mshr_miss_latency::cpu.inst 19183000 # number of demand (read+write) MSHR miss cycles 783system.l2cache.demand_mshr_miss_latency::cpu.data 10131000 # number of demand (read+write) MSHR miss cycles 784system.l2cache.demand_mshr_miss_latency::total 29314000 # number of demand (read+write) MSHR miss cycles 785system.l2cache.overall_mshr_miss_latency::cpu.inst 19183000 # number of overall MSHR miss cycles 786system.l2cache.overall_mshr_miss_latency::cpu.data 10131000 # number of overall MSHR miss cycles 787system.l2cache.overall_mshr_miss_latency::total 29314000 # number of overall MSHR miss cycles 788system.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 789system.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 790system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.inst 0.903614 # mshr miss rate for ReadSharedReq accesses 791system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.838384 # mshr miss rate for ReadSharedReq accesses 792system.l2cache.ReadSharedReq_mshr_miss_rate::total 0.885057 # mshr miss rate for ReadSharedReq accesses 793system.l2cache.demand_mshr_miss_rate::cpu.inst 0.903614 # mshr miss rate for demand accesses 794system.l2cache.demand_mshr_miss_rate::cpu.data 0.887324 # mshr miss rate for demand accesses 795system.l2cache.demand_mshr_miss_rate::total 0.897698 # mshr miss rate for demand accesses 796system.l2cache.overall_mshr_miss_rate::cpu.inst 0.903614 # mshr miss rate for overall accesses 797system.l2cache.overall_mshr_miss_rate::cpu.data 0.887324 # mshr miss rate for overall accesses 798system.l2cache.overall_mshr_miss_rate::total 0.897698 # mshr miss rate for overall accesses 799system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 83186.046512 # average ReadExReq mshr miss latency 800system.l2cache.ReadExReq_avg_mshr_miss_latency::total 83186.046512 # average ReadExReq mshr miss latency 801system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 85257.777778 # average ReadSharedReq mshr miss latency 802system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 78963.855422 # average ReadSharedReq mshr miss latency 803system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 83561.688312 # average ReadSharedReq mshr miss latency 804system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 85257.777778 # average overall mshr miss latency 805system.l2cache.demand_avg_mshr_miss_latency::cpu.data 80404.761905 # average overall mshr miss latency 806system.l2cache.demand_avg_mshr_miss_latency::total 83515.669516 # average overall mshr miss latency 807system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 85257.777778 # average overall mshr miss latency 808system.l2cache.overall_avg_mshr_miss_latency::cpu.data 80404.761905 # average overall mshr miss latency 809system.l2cache.overall_avg_mshr_miss_latency::total 83515.669516 # average overall mshr miss latency 810system.membus.snoop_filter.tot_requests 351 # Total number of requests made to the snoop filter. 811system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. 812system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 813system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 814system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 815system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 816system.membus.pwrStateResidencyTicks::UNDEFINED 52453000 # Cumulative time (in ticks) in various power states 817system.membus.trans_dist::ReadResp 308 # Transaction distribution 818system.membus.trans_dist::ReadExReq 43 # Transaction distribution 819system.membus.trans_dist::ReadExResp 43 # Transaction distribution 820system.membus.trans_dist::ReadSharedReq 308 # Transaction distribution 821system.membus.pkt_count_system.l2cache.mem_side::system.mem_ctrl.port 702 # Packet count per connected master and slave (bytes) 822system.membus.pkt_count::total 702 # Packet count per connected master and slave (bytes) 823system.membus.pkt_size_system.l2cache.mem_side::system.mem_ctrl.port 22464 # Cumulative packet size per connected master and slave (bytes) 824system.membus.pkt_size::total 22464 # Cumulative packet size per connected master and slave (bytes) 825system.membus.snoops 0 # Total snoops (count) 826system.membus.snoopTraffic 0 # Total snoop traffic (bytes) 827system.membus.snoop_fanout::samples 351 # Request fanout histogram 828system.membus.snoop_fanout::mean 0 # Request fanout histogram 829system.membus.snoop_fanout::stdev 0 # Request fanout histogram 830system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 831system.membus.snoop_fanout::0 351 100.00% 100.00% # Request fanout histogram 832system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 833system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 834system.membus.snoop_fanout::min_value 0 # Request fanout histogram 835system.membus.snoop_fanout::max_value 0 # Request fanout histogram 836system.membus.snoop_fanout::total 351 # Request fanout histogram 837system.membus.reqLayer0.occupancy 351000 # Layer occupancy (ticks) 838system.membus.reqLayer0.utilization 0.7 # Layer utilization (%) 839system.membus.respLayer0.occupancy 1866250 # Layer occupancy (ticks) 840system.membus.respLayer0.utilization 3.6 # Layer utilization (%) 841 842---------- End Simulation Statistics ---------- 843