xref: /gem5/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.000326                       # Number of seconds simulated
sim_ticks                                   325849000                       # Number of ticks simulated
final_tick                                  325849000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                  60983                       # Simulator instruction rate (inst/s)
host_op_rate                                    70534                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             3982742967                       # Simulator tick rate (ticks/s)
host_mem_usage                                 686060                       # Number of bytes of host memory used
host_seconds                                     0.08                       # Real time elapsed on the host
sim_insts                                        4988                       # Number of instructions simulated
sim_ops                                          5770                       # Number of ops (including micro ops) simulated
system.clk_domain.voltage_domain.voltage            1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.mem_ctrl.bytes_read::cpu.inst            20108                       # Number of bytes read from this memory
system.mem_ctrl.bytes_read::cpu.data             4672                       # Number of bytes read from this memory
system.mem_ctrl.bytes_read::total               24780                       # Number of bytes read from this memory
system.mem_ctrl.bytes_inst_read::cpu.inst        20108                       # Number of instructions bytes read from this memory
system.mem_ctrl.bytes_inst_read::total          20108                       # Number of instructions bytes read from this memory
system.mem_ctrl.bytes_written::cpu.data          3696                       # Number of bytes written to this memory
system.mem_ctrl.bytes_written::total             3696                       # Number of bytes written to this memory
system.mem_ctrl.num_reads::cpu.inst              5027                       # Number of read requests responded to by this memory
system.mem_ctrl.num_reads::cpu.data              1061                       # Number of read requests responded to by this memory
system.mem_ctrl.num_reads::total                 6088                       # Number of read requests responded to by this memory
system.mem_ctrl.num_writes::cpu.data              936                       # Number of write requests responded to by this memory
system.mem_ctrl.num_writes::total                 936                       # Number of write requests responded to by this memory
system.mem_ctrl.bw_read::cpu.inst            61709565                       # Total read bandwidth from this memory (bytes/s)
system.mem_ctrl.bw_read::cpu.data            14337930                       # Total read bandwidth from this memory (bytes/s)
system.mem_ctrl.bw_read::total               76047494                       # Total read bandwidth from this memory (bytes/s)
system.mem_ctrl.bw_inst_read::cpu.inst       61709565                       # Instruction read bandwidth from this memory (bytes/s)
system.mem_ctrl.bw_inst_read::total          61709565                       # Instruction read bandwidth from this memory (bytes/s)
system.mem_ctrl.bw_write::cpu.data           11342677                       # Write bandwidth from this memory (bytes/s)
system.mem_ctrl.bw_write::total              11342677                       # Write bandwidth from this memory (bytes/s)
system.mem_ctrl.bw_total::cpu.inst           61709565                       # Total bandwidth to/from this memory (bytes/s)
system.mem_ctrl.bw_total::cpu.data           25680607                       # Total bandwidth to/from this memory (bytes/s)
system.mem_ctrl.bw_total::total              87390172                       # Total bandwidth to/from this memory (bytes/s)
system.mem_ctrl.readReqs                         6089                       # Number of read requests accepted
system.mem_ctrl.writeReqs                         936                       # Number of write requests accepted
system.mem_ctrl.readBursts                       6089                       # Number of DRAM read bursts, including those serviced by the write queue
system.mem_ctrl.writeBursts                       936                       # Number of DRAM write bursts, including those merged in the write queue
system.mem_ctrl.bytesReadDRAM                  384000                       # Total number of bytes read from DRAM
system.mem_ctrl.bytesReadWrQ                     5696                       # Total number of bytes read from write queue
system.mem_ctrl.bytesWritten                     3072                       # Total number of bytes written to DRAM
system.mem_ctrl.bytesReadSys                    24784                       # Total read bytes from the system interface side
system.mem_ctrl.bytesWrittenSys                  3696                       # Total written bytes from the system interface side
system.mem_ctrl.servicedByWrQ                      89                       # Number of DRAM read bursts serviced by the write queue
system.mem_ctrl.mergedWrBursts                    856                       # Number of DRAM write bursts merged with an existing one
system.mem_ctrl.neitherReadNorWriteReqs             0                       # Number of requests that are neither read nor write
system.mem_ctrl.perBankRdBursts::0                911                       # Per bank write bursts
system.mem_ctrl.perBankRdBursts::1               1454                       # Per bank write bursts
system.mem_ctrl.perBankRdBursts::2                724                       # Per bank write bursts
system.mem_ctrl.perBankRdBursts::3                364                       # Per bank write bursts
system.mem_ctrl.perBankRdBursts::4                505                       # Per bank write bursts
system.mem_ctrl.perBankRdBursts::5                303                       # Per bank write bursts
system.mem_ctrl.perBankRdBursts::6                487                       # Per bank write bursts
system.mem_ctrl.perBankRdBursts::7                206                       # Per bank write bursts
system.mem_ctrl.perBankRdBursts::8                 42                       # Per bank write bursts
system.mem_ctrl.perBankRdBursts::9                155                       # Per bank write bursts
system.mem_ctrl.perBankRdBursts::10               194                       # Per bank write bursts
system.mem_ctrl.perBankRdBursts::11               431                       # Per bank write bursts
system.mem_ctrl.perBankRdBursts::12               108                       # Per bank write bursts
system.mem_ctrl.perBankRdBursts::13                36                       # Per bank write bursts
system.mem_ctrl.perBankRdBursts::14                 0                       # Per bank write bursts
system.mem_ctrl.perBankRdBursts::15                80                       # Per bank write bursts
system.mem_ctrl.perBankWrBursts::0                  0                       # Per bank write bursts
system.mem_ctrl.perBankWrBursts::1                  0                       # Per bank write bursts
system.mem_ctrl.perBankWrBursts::2                  0                       # Per bank write bursts
system.mem_ctrl.perBankWrBursts::3                  0                       # Per bank write bursts
system.mem_ctrl.perBankWrBursts::4                  0                       # Per bank write bursts
system.mem_ctrl.perBankWrBursts::5                  0                       # Per bank write bursts
system.mem_ctrl.perBankWrBursts::6                  0                       # Per bank write bursts
system.mem_ctrl.perBankWrBursts::7                  0                       # Per bank write bursts
system.mem_ctrl.perBankWrBursts::8                  0                       # Per bank write bursts
system.mem_ctrl.perBankWrBursts::9                  0                       # Per bank write bursts
system.mem_ctrl.perBankWrBursts::10                13                       # Per bank write bursts
system.mem_ctrl.perBankWrBursts::11                30                       # Per bank write bursts
system.mem_ctrl.perBankWrBursts::12                 5                       # Per bank write bursts
system.mem_ctrl.perBankWrBursts::13                 0                       # Per bank write bursts
system.mem_ctrl.perBankWrBursts::14                 0                       # Per bank write bursts
system.mem_ctrl.perBankWrBursts::15                 0                       # Per bank write bursts
system.mem_ctrl.numRdRetry                          0                       # Number of times read queue was full causing retry
system.mem_ctrl.numWrRetry                          0                       # Number of times write queue was full causing retry
system.mem_ctrl.totGap                      325773000                       # Total gap between requests
system.mem_ctrl.readPktSize::0                     70                       # Read request sizes (log2)
system.mem_ctrl.readPktSize::1                      1                       # Read request sizes (log2)
system.mem_ctrl.readPktSize::2                   5858                       # Read request sizes (log2)
system.mem_ctrl.readPktSize::3                    160                       # Read request sizes (log2)
system.mem_ctrl.readPktSize::4                      0                       # Read request sizes (log2)
system.mem_ctrl.readPktSize::5                      0                       # Read request sizes (log2)
system.mem_ctrl.readPktSize::6                      0                       # Read request sizes (log2)
system.mem_ctrl.writePktSize::0                    16                       # Write request sizes (log2)
system.mem_ctrl.writePktSize::1                     0                       # Write request sizes (log2)
system.mem_ctrl.writePktSize::2                   920                       # Write request sizes (log2)
system.mem_ctrl.writePktSize::3                     0                       # Write request sizes (log2)
system.mem_ctrl.writePktSize::4                     0                       # Write request sizes (log2)
system.mem_ctrl.writePktSize::5                     0                       # Write request sizes (log2)
system.mem_ctrl.writePktSize::6                     0                       # Write request sizes (log2)
system.mem_ctrl.rdQLenPdf::0                     5991                       # What read queue length does an incoming req see
system.mem_ctrl.rdQLenPdf::1                        9                       # What read queue length does an incoming req see
system.mem_ctrl.rdQLenPdf::2                        0                       # What read queue length does an incoming req see
system.mem_ctrl.rdQLenPdf::3                        0                       # What read queue length does an incoming req see
system.mem_ctrl.rdQLenPdf::4                        0                       # What read queue length does an incoming req see
system.mem_ctrl.rdQLenPdf::5                        0                       # What read queue length does an incoming req see
system.mem_ctrl.rdQLenPdf::6                        0                       # What read queue length does an incoming req see
system.mem_ctrl.rdQLenPdf::7                        0                       # What read queue length does an incoming req see
system.mem_ctrl.rdQLenPdf::8                        0                       # What read queue length does an incoming req see
system.mem_ctrl.rdQLenPdf::9                        0                       # What read queue length does an incoming req see
system.mem_ctrl.rdQLenPdf::10                       0                       # What read queue length does an incoming req see
system.mem_ctrl.rdQLenPdf::11                       0                       # What read queue length does an incoming req see
system.mem_ctrl.rdQLenPdf::12                       0                       # What read queue length does an incoming req see
system.mem_ctrl.rdQLenPdf::13                       0                       # What read queue length does an incoming req see
system.mem_ctrl.rdQLenPdf::14                       0                       # What read queue length does an incoming req see
system.mem_ctrl.rdQLenPdf::15                       0                       # What read queue length does an incoming req see
system.mem_ctrl.rdQLenPdf::16                       0                       # What read queue length does an incoming req see
system.mem_ctrl.rdQLenPdf::17                       0                       # What read queue length does an incoming req see
system.mem_ctrl.rdQLenPdf::18                       0                       # What read queue length does an incoming req see
system.mem_ctrl.rdQLenPdf::19                       0                       # What read queue length does an incoming req see
system.mem_ctrl.rdQLenPdf::20                       0                       # What read queue length does an incoming req see
system.mem_ctrl.rdQLenPdf::21                       0                       # What read queue length does an incoming req see
system.mem_ctrl.rdQLenPdf::22                       0                       # What read queue length does an incoming req see
system.mem_ctrl.rdQLenPdf::23                       0                       # What read queue length does an incoming req see
system.mem_ctrl.rdQLenPdf::24                       0                       # What read queue length does an incoming req see
system.mem_ctrl.rdQLenPdf::25                       0                       # What read queue length does an incoming req see
system.mem_ctrl.rdQLenPdf::26                       0                       # What read queue length does an incoming req see
system.mem_ctrl.rdQLenPdf::27                       0                       # What read queue length does an incoming req see
system.mem_ctrl.rdQLenPdf::28                       0                       # What read queue length does an incoming req see
system.mem_ctrl.rdQLenPdf::29                       0                       # What read queue length does an incoming req see
system.mem_ctrl.rdQLenPdf::30                       0                       # What read queue length does an incoming req see
system.mem_ctrl.rdQLenPdf::31                       0                       # What read queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::0                        1                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::1                        1                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::2                        1                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::3                        1                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::4                        1                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::5                        1                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::6                        1                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::7                        1                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::8                        1                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::9                        1                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::10                       1                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::11                       1                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::12                       1                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::13                       1                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::14                       1                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::15                       1                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::16                       1                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::17                       4                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::18                       4                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::19                       4                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::20                       4                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::21                       4                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::22                       4                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::23                       4                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::24                       4                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::25                       4                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::26                       4                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::27                       4                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::28                       4                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::29                       4                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::30                       4                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::31                       4                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::32                       3                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::33                       0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::34                       0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::35                       0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::36                       0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::37                       0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::38                       0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::39                       0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::40                       0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::41                       0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::42                       0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::43                       0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::44                       0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::45                       0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::46                       0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::47                       0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::48                       0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::49                       0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::50                       0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::51                       0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::52                       0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::53                       0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::54                       0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::55                       0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::56                       0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::57                       0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::58                       0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::59                       0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::60                       0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::61                       0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::62                       0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::63                       0                       # What write queue length does an incoming req see
system.mem_ctrl.bytesPerActivate::samples          495                       # Bytes accessed per row activation
system.mem_ctrl.bytesPerActivate::mean     775.886869                       # Bytes accessed per row activation
system.mem_ctrl.bytesPerActivate::gmean    648.412049                       # Bytes accessed per row activation
system.mem_ctrl.bytesPerActivate::stdev    330.044561                       # Bytes accessed per row activation
system.mem_ctrl.bytesPerActivate::0-127            19      3.84%      3.84% # Bytes accessed per row activation
system.mem_ctrl.bytesPerActivate::128-255           31      6.26%     10.10% # Bytes accessed per row activation
system.mem_ctrl.bytesPerActivate::256-383           37      7.47%     17.58% # Bytes accessed per row activation
system.mem_ctrl.bytesPerActivate::384-511           33      6.67%     24.24% # Bytes accessed per row activation
system.mem_ctrl.bytesPerActivate::512-639           20      4.04%     28.28% # Bytes accessed per row activation
system.mem_ctrl.bytesPerActivate::640-767           33      6.67%     34.95% # Bytes accessed per row activation
system.mem_ctrl.bytesPerActivate::768-895           27      5.45%     40.40% # Bytes accessed per row activation
system.mem_ctrl.bytesPerActivate::896-1023           25      5.05%     45.45% # Bytes accessed per row activation
system.mem_ctrl.bytesPerActivate::1024-1151          270     54.55%    100.00% # Bytes accessed per row activation
system.mem_ctrl.bytesPerActivate::total           495                       # Bytes accessed per row activation
system.mem_ctrl.rdPerTurnAround::samples            3                       # Reads before turning the bus around for writes
system.mem_ctrl.rdPerTurnAround::mean     1299.666667                       # Reads before turning the bus around for writes
system.mem_ctrl.rdPerTurnAround::gmean    1199.462709                       # Reads before turning the bus around for writes
system.mem_ctrl.rdPerTurnAround::stdev     577.403094                       # Reads before turning the bus around for writes
system.mem_ctrl.rdPerTurnAround::640-703            1     33.33%     33.33% # Reads before turning the bus around for writes
system.mem_ctrl.rdPerTurnAround::1408-1471            1     33.33%     66.67% # Reads before turning the bus around for writes
system.mem_ctrl.rdPerTurnAround::1792-1855            1     33.33%    100.00% # Reads before turning the bus around for writes
system.mem_ctrl.rdPerTurnAround::total              3                       # Reads before turning the bus around for writes
system.mem_ctrl.wrPerTurnAround::samples            3                       # Writes before turning the bus around for reads
system.mem_ctrl.wrPerTurnAround::mean              16                       # Writes before turning the bus around for reads
system.mem_ctrl.wrPerTurnAround::gmean      16.000000                       # Writes before turning the bus around for reads
system.mem_ctrl.wrPerTurnAround::16                 3    100.00%    100.00% # Writes before turning the bus around for reads
system.mem_ctrl.wrPerTurnAround::total              3                       # Writes before turning the bus around for reads
system.mem_ctrl.totQLat                      17801000                       # Total ticks spent queuing
system.mem_ctrl.totMemAccLat                130301000                       # Total ticks spent from burst creation until serviced by the DRAM
system.mem_ctrl.totBusLat                    30000000                       # Total ticks spent in databus transfers
system.mem_ctrl.avgQLat                       2966.83                       # Average queueing delay per DRAM burst
system.mem_ctrl.avgBusLat                     5000.00                       # Average bus latency per DRAM burst
system.mem_ctrl.avgMemAccLat                 21716.83                       # Average memory access latency per DRAM burst
system.mem_ctrl.avgRdBW                       1178.46                       # Average DRAM read bandwidth in MiByte/s
system.mem_ctrl.avgWrBW                          9.43                       # Average achieved write bandwidth in MiByte/s
system.mem_ctrl.avgRdBWSys                      76.06                       # Average system read bandwidth in MiByte/s
system.mem_ctrl.avgWrBWSys                      11.34                       # Average system write bandwidth in MiByte/s
system.mem_ctrl.peakBW                       12800.00                       # Theoretical peak bandwidth in MiByte/s
system.mem_ctrl.busUtil                          9.28                       # Data bus utilization in percentage
system.mem_ctrl.busUtilRead                      9.21                       # Data bus utilization in percentage for reads
system.mem_ctrl.busUtilWrite                     0.07                       # Data bus utilization in percentage for writes
system.mem_ctrl.avgRdQLen                        1.00                       # Average read queue length when enqueuing
system.mem_ctrl.avgWrQLen                       24.64                       # Average write queue length when enqueuing
system.mem_ctrl.readRowHits                      5504                       # Number of row buffer hits during reads
system.mem_ctrl.writeRowHits                       44                       # Number of row buffer hits during writes
system.mem_ctrl.readRowHitRate                  91.73                       # Row buffer hit rate for reads
system.mem_ctrl.writeRowHitRate                 55.00                       # Row buffer hit rate for writes
system.mem_ctrl.avgGap                       46373.38                       # Average gap between requests
system.mem_ctrl.pageHitRate                     91.25                       # Row buffer hit rate, read and write combined
system.mem_ctrl_0.actEnergy                   2782080                       # Energy for activate commands per rank (pJ)
system.mem_ctrl_0.preEnergy                   1518000                       # Energy for precharge commands per rank (pJ)
system.mem_ctrl_0.readEnergy                 37915800                       # Energy for read commands per rank (pJ)
system.mem_ctrl_0.writeEnergy                       0                       # Energy for write commands per rank (pJ)
system.mem_ctrl_0.refreshEnergy              20850960                       # Energy for refresh commands per rank (pJ)
system.mem_ctrl_0.actBackEnergy             212134050                       # Energy for active background per rank (pJ)
system.mem_ctrl_0.preBackEnergy               5616000                       # Energy for precharge background per rank (pJ)
system.mem_ctrl_0.totalEnergy               280816890                       # Total energy per rank (pJ)
system.mem_ctrl_0.averagePower             878.932981                       # Core power per rank (mW)
system.mem_ctrl_0.memoryStateTime::IDLE       6234500                       # Time in different power states
system.mem_ctrl_0.memoryStateTime::REF       10660000                       # Time in different power states
system.mem_ctrl_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.mem_ctrl_0.memoryStateTime::ACT      303655500                       # Time in different power states
system.mem_ctrl_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.mem_ctrl_1.actEnergy                    922320                       # Energy for activate commands per rank (pJ)
system.mem_ctrl_1.preEnergy                    503250                       # Energy for precharge commands per rank (pJ)
system.mem_ctrl_1.readEnergy                  7932600                       # Energy for read commands per rank (pJ)
system.mem_ctrl_1.writeEnergy                  311040                       # Energy for write commands per rank (pJ)
system.mem_ctrl_1.refreshEnergy              20850960                       # Energy for refresh commands per rank (pJ)
system.mem_ctrl_1.actBackEnergy             182238975                       # Energy for active background per rank (pJ)
system.mem_ctrl_1.preBackEnergy              31839000                       # Energy for precharge background per rank (pJ)
system.mem_ctrl_1.totalEnergy               244598145                       # Total energy per rank (pJ)
system.mem_ctrl_1.averagePower             765.574385                       # Core power per rank (mW)
system.mem_ctrl_1.memoryStateTime::IDLE      52679500                       # Time in different power states
system.mem_ctrl_1.memoryStateTime::REF       10660000                       # Time in different power states
system.mem_ctrl_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.mem_ctrl_1.memoryStateTime::ACT      256888500                       # Time in different power states
system.mem_ctrl_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.dtb.walker.walks                         0                       # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                            0                       # DTB read hits
system.cpu.dtb.read_misses                          0                       # DTB read misses
system.cpu.dtb.write_hits                           0                       # DTB write hits
system.cpu.dtb.write_misses                         0                       # DTB write misses
system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                        0                       # DTB read accesses
system.cpu.dtb.write_accesses                       0                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                                 0                       # DTB hits
system.cpu.dtb.misses                               0                       # DTB misses
system.cpu.dtb.accesses                             0                       # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.itb.walker.walks                         0                       # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits                            0                       # ITB inst hits
system.cpu.itb.inst_misses                          0                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
system.cpu.itb.hits                                 0                       # DTB hits
system.cpu.itb.misses                               0                       # DTB misses
system.cpu.itb.accesses                             0                       # DTB accesses
system.cpu.workload.num_syscalls                   13                       # Number of system calls
system.cpu.numCycles                           325849                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.committedInsts                        4988                       # Number of instructions committed
system.cpu.committedOps                          5770                       # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses                  4977                       # Number of integer alu accesses
system.cpu.num_fp_alu_accesses                     16                       # Number of float alu accesses
system.cpu.num_func_calls                         215                       # number of times a function call or return occured
system.cpu.num_conditional_control_insts          800                       # number of instructions that are conditional controls
system.cpu.num_int_insts                         4977                       # number of integer instructions
system.cpu.num_fp_insts                            16                       # number of float instructions
system.cpu.num_int_register_reads                8084                       # number of times the integer registers were read
system.cpu.num_int_register_writes               2992                       # number of times the integer registers were written
system.cpu.num_fp_register_reads                   16                       # number of times the floating registers were read
system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
system.cpu.num_cc_register_reads                20681                       # number of times the CC registers were read
system.cpu.num_cc_register_writes                2647                       # number of times the CC registers were written
system.cpu.num_mem_refs                          2035                       # number of memory refs
system.cpu.num_load_insts                        1085                       # Number of load instructions
system.cpu.num_store_insts                        950                       # Number of store instructions
system.cpu.num_idle_cycles                   0.001000                       # Number of idle cycles
system.cpu.num_busy_cycles               325848.999000                       # Number of busy cycles
system.cpu.not_idle_fraction                 1.000000                       # Percentage of non-idle cycles
system.cpu.idle_fraction                     0.000000                       # Percentage of idle cycles
system.cpu.Branches                              1107                       # Number of branches fetched
system.cpu.op_class::No_OpClass                     0      0.00%      0.00% # Class of executed instruction
system.cpu.op_class::IntAlu                      3789     64.98%     64.98% # Class of executed instruction
system.cpu.op_class::IntMult                        4      0.07%     65.05% # Class of executed instruction
system.cpu.op_class::IntDiv                         0      0.00%     65.05% # Class of executed instruction
system.cpu.op_class::FloatAdd                       0      0.00%     65.05% # Class of executed instruction
system.cpu.op_class::FloatCmp                       0      0.00%     65.05% # Class of executed instruction
system.cpu.op_class::FloatCvt                       0      0.00%     65.05% # Class of executed instruction
system.cpu.op_class::FloatMult                      0      0.00%     65.05% # Class of executed instruction
system.cpu.op_class::FloatDiv                       0      0.00%     65.05% # Class of executed instruction
system.cpu.op_class::FloatSqrt                      0      0.00%     65.05% # Class of executed instruction
system.cpu.op_class::SimdAdd                        0      0.00%     65.05% # Class of executed instruction
system.cpu.op_class::SimdAddAcc                     0      0.00%     65.05% # Class of executed instruction
system.cpu.op_class::SimdAlu                        0      0.00%     65.05% # Class of executed instruction
system.cpu.op_class::SimdCmp                        0      0.00%     65.05% # Class of executed instruction
system.cpu.op_class::SimdCvt                        0      0.00%     65.05% # Class of executed instruction
system.cpu.op_class::SimdMisc                       0      0.00%     65.05% # Class of executed instruction
system.cpu.op_class::SimdMult                       0      0.00%     65.05% # Class of executed instruction
system.cpu.op_class::SimdMultAcc                    0      0.00%     65.05% # Class of executed instruction
system.cpu.op_class::SimdShift                      0      0.00%     65.05% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc                   0      0.00%     65.05% # Class of executed instruction
system.cpu.op_class::SimdSqrt                       0      0.00%     65.05% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd                   0      0.00%     65.05% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu                   0      0.00%     65.05% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp                   0      0.00%     65.05% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt                   0      0.00%     65.05% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv                   0      0.00%     65.05% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc                  3      0.05%     65.10% # Class of executed instruction
system.cpu.op_class::SimdFloatMult                  0      0.00%     65.10% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc               0      0.00%     65.10% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt                  0      0.00%     65.10% # Class of executed instruction
system.cpu.op_class::MemRead                     1085     18.61%     83.71% # Class of executed instruction
system.cpu.op_class::MemWrite                     950     16.29%    100.00% # Class of executed instruction
system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
system.cpu.op_class::total                       5831                       # Class of executed instruction
system.membus.trans_dist::ReadReq                6078                       # Transaction distribution
system.membus.trans_dist::ReadResp               6088                       # Transaction distribution
system.membus.trans_dist::WriteReq                925                       # Transaction distribution
system.membus.trans_dist::WriteResp               925                       # Transaction distribution
system.membus.trans_dist::LoadLockedReq            11                       # Transaction distribution
system.membus.trans_dist::StoreCondReq             11                       # Transaction distribution
system.membus.trans_dist::StoreCondResp            11                       # Transaction distribution
system.membus.pkt_count_system.cpu.icache_port::system.mem_ctrl.port        10055                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.dcache_port::system.mem_ctrl.port         3994                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                  14049                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.icache_port::system.mem_ctrl.port        20108                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.dcache_port::system.mem_ctrl.port         8368                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                   28476                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                                0                       # Total snoops (count)
system.membus.snoop_fanout::samples              7025                       # Request fanout histogram
system.membus.snoop_fanout::mean             0.715730                       # Request fanout histogram
system.membus.snoop_fanout::stdev            0.451098                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                    1997     28.43%     28.43% # Request fanout histogram
system.membus.snoop_fanout::1                    5028     71.57%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total                7025                       # Request fanout histogram
system.membus.reqLayer0.occupancy             7961000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               2.4                       # Layer utilization (%)
system.membus.respLayer0.occupancy           11411750                       # Layer occupancy (ticks)
system.membus.respLayer0.utilization              3.5                       # Layer utilization (%)
system.membus.respLayer1.occupancy            3326000                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              1.0                       # Layer utilization (%)

---------- End Simulation Statistics   ----------