stats.txt revision 8835:7c68f84d7c4e
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000042 # Number of seconds simulated 4sim_ticks 41800000 # Number of ticks simulated 5final_tick 41800000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 399467 # Simulator instruction rate (inst/s) 8host_op_rate 399277 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1099343547 # Simulator tick rate (ticks/s) 10host_mem_usage 210560 # Number of bytes of host memory used 11host_seconds 0.04 # Real time elapsed on the host 12sim_insts 15175 # Number of instructions simulated 13sim_ops 15175 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read 26624 # Number of bytes read from this memory 15system.physmem.bytes_inst_read 17792 # Number of instructions bytes read from this memory 16system.physmem.bytes_written 0 # Number of bytes written to this memory 17system.physmem.num_reads 416 # Number of read requests responded to by this memory 18system.physmem.num_writes 0 # Number of write requests responded to by this memory 19system.physmem.num_other 0 # Number of other requests responded to by this memory 20system.physmem.bw_read 636937799 # Total read bandwidth from this memory (bytes/s) 21system.physmem.bw_inst_read 425645933 # Instruction read bandwidth from this memory (bytes/s) 22system.physmem.bw_total 636937799 # Total bandwidth to/from this memory (bytes/s) 23system.cpu.workload.num_syscalls 18 # Number of system calls 24system.cpu.numCycles 83600 # number of cpu cycles simulated 25system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 26system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 27system.cpu.committedInsts 15175 # Number of instructions committed 28system.cpu.committedOps 15175 # Number of ops (including micro ops) committed 29system.cpu.num_int_alu_accesses 12231 # Number of integer alu accesses 30system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses 31system.cpu.num_func_calls 385 # number of times a function call or return occured 32system.cpu.num_conditional_control_insts 2435 # number of instructions that are conditional controls 33system.cpu.num_int_insts 12231 # number of integer instructions 34system.cpu.num_fp_insts 0 # number of float instructions 35system.cpu.num_int_register_reads 29059 # number of times the integer registers were read 36system.cpu.num_int_register_writes 13831 # number of times the integer registers were written 37system.cpu.num_fp_register_reads 0 # number of times the floating registers were read 38system.cpu.num_fp_register_writes 0 # number of times the floating registers were written 39system.cpu.num_mem_refs 3684 # number of memory refs 40system.cpu.num_load_insts 2232 # Number of load instructions 41system.cpu.num_store_insts 1452 # Number of store instructions 42system.cpu.num_idle_cycles 0 # Number of idle cycles 43system.cpu.num_busy_cycles 83600 # Number of busy cycles 44system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 45system.cpu.idle_fraction 0 # Percentage of idle cycles 46system.cpu.icache.replacements 0 # number of replacements 47system.cpu.icache.tagsinuse 153.436702 # Cycle average of tags in use 48system.cpu.icache.total_refs 14941 # Total number of references to valid blocks. 49system.cpu.icache.sampled_refs 280 # Sample count of references to valid blocks. 50system.cpu.icache.avg_refs 53.360714 # Average number of references to valid blocks. 51system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 52system.cpu.icache.occ_blocks::cpu.inst 153.436702 # Average occupied blocks per requestor 53system.cpu.icache.occ_percent::cpu.inst 0.074920 # Average percentage of cache occupancy 54system.cpu.icache.occ_percent::total 0.074920 # Average percentage of cache occupancy 55system.cpu.icache.ReadReq_hits::cpu.inst 14941 # number of ReadReq hits 56system.cpu.icache.ReadReq_hits::total 14941 # number of ReadReq hits 57system.cpu.icache.demand_hits::cpu.inst 14941 # number of demand (read+write) hits 58system.cpu.icache.demand_hits::total 14941 # number of demand (read+write) hits 59system.cpu.icache.overall_hits::cpu.inst 14941 # number of overall hits 60system.cpu.icache.overall_hits::total 14941 # number of overall hits 61system.cpu.icache.ReadReq_misses::cpu.inst 280 # number of ReadReq misses 62system.cpu.icache.ReadReq_misses::total 280 # number of ReadReq misses 63system.cpu.icache.demand_misses::cpu.inst 280 # number of demand (read+write) misses 64system.cpu.icache.demand_misses::total 280 # number of demand (read+write) misses 65system.cpu.icache.overall_misses::cpu.inst 280 # number of overall misses 66system.cpu.icache.overall_misses::total 280 # number of overall misses 67system.cpu.icache.ReadReq_miss_latency::cpu.inst 15596000 # number of ReadReq miss cycles 68system.cpu.icache.ReadReq_miss_latency::total 15596000 # number of ReadReq miss cycles 69system.cpu.icache.demand_miss_latency::cpu.inst 15596000 # number of demand (read+write) miss cycles 70system.cpu.icache.demand_miss_latency::total 15596000 # number of demand (read+write) miss cycles 71system.cpu.icache.overall_miss_latency::cpu.inst 15596000 # number of overall miss cycles 72system.cpu.icache.overall_miss_latency::total 15596000 # number of overall miss cycles 73system.cpu.icache.ReadReq_accesses::cpu.inst 15221 # number of ReadReq accesses(hits+misses) 74system.cpu.icache.ReadReq_accesses::total 15221 # number of ReadReq accesses(hits+misses) 75system.cpu.icache.demand_accesses::cpu.inst 15221 # number of demand (read+write) accesses 76system.cpu.icache.demand_accesses::total 15221 # number of demand (read+write) accesses 77system.cpu.icache.overall_accesses::cpu.inst 15221 # number of overall (read+write) accesses 78system.cpu.icache.overall_accesses::total 15221 # number of overall (read+write) accesses 79system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.018396 # miss rate for ReadReq accesses 80system.cpu.icache.demand_miss_rate::cpu.inst 0.018396 # miss rate for demand accesses 81system.cpu.icache.overall_miss_rate::cpu.inst 0.018396 # miss rate for overall accesses 82system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55700 # average ReadReq miss latency 83system.cpu.icache.demand_avg_miss_latency::cpu.inst 55700 # average overall miss latency 84system.cpu.icache.overall_avg_miss_latency::cpu.inst 55700 # average overall miss latency 85system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 86system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 87system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 88system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 89system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 90system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 91system.cpu.icache.fast_writes 0 # number of fast writes performed 92system.cpu.icache.cache_copies 0 # number of cache copies performed 93system.cpu.icache.ReadReq_mshr_misses::cpu.inst 280 # number of ReadReq MSHR misses 94system.cpu.icache.ReadReq_mshr_misses::total 280 # number of ReadReq MSHR misses 95system.cpu.icache.demand_mshr_misses::cpu.inst 280 # number of demand (read+write) MSHR misses 96system.cpu.icache.demand_mshr_misses::total 280 # number of demand (read+write) MSHR misses 97system.cpu.icache.overall_mshr_misses::cpu.inst 280 # number of overall MSHR misses 98system.cpu.icache.overall_mshr_misses::total 280 # number of overall MSHR misses 99system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14756000 # number of ReadReq MSHR miss cycles 100system.cpu.icache.ReadReq_mshr_miss_latency::total 14756000 # number of ReadReq MSHR miss cycles 101system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14756000 # number of demand (read+write) MSHR miss cycles 102system.cpu.icache.demand_mshr_miss_latency::total 14756000 # number of demand (read+write) MSHR miss cycles 103system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14756000 # number of overall MSHR miss cycles 104system.cpu.icache.overall_mshr_miss_latency::total 14756000 # number of overall MSHR miss cycles 105system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.018396 # mshr miss rate for ReadReq accesses 106system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.018396 # mshr miss rate for demand accesses 107system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.018396 # mshr miss rate for overall accesses 108system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52700 # average ReadReq mshr miss latency 109system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52700 # average overall mshr miss latency 110system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52700 # average overall mshr miss latency 111system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 112system.cpu.dcache.replacements 0 # number of replacements 113system.cpu.dcache.tagsinuse 97.842991 # Cycle average of tags in use 114system.cpu.dcache.total_refs 3536 # Total number of references to valid blocks. 115system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks. 116system.cpu.dcache.avg_refs 25.623188 # Average number of references to valid blocks. 117system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 118system.cpu.dcache.occ_blocks::cpu.data 97.842991 # Average occupied blocks per requestor 119system.cpu.dcache.occ_percent::cpu.data 0.023887 # Average percentage of cache occupancy 120system.cpu.dcache.occ_percent::total 0.023887 # Average percentage of cache occupancy 121system.cpu.dcache.ReadReq_hits::cpu.data 2173 # number of ReadReq hits 122system.cpu.dcache.ReadReq_hits::total 2173 # number of ReadReq hits 123system.cpu.dcache.WriteReq_hits::cpu.data 1357 # number of WriteReq hits 124system.cpu.dcache.WriteReq_hits::total 1357 # number of WriteReq hits 125system.cpu.dcache.SwapReq_hits::cpu.data 6 # number of SwapReq hits 126system.cpu.dcache.SwapReq_hits::total 6 # number of SwapReq hits 127system.cpu.dcache.demand_hits::cpu.data 3530 # number of demand (read+write) hits 128system.cpu.dcache.demand_hits::total 3530 # number of demand (read+write) hits 129system.cpu.dcache.overall_hits::cpu.data 3530 # number of overall hits 130system.cpu.dcache.overall_hits::total 3530 # number of overall hits 131system.cpu.dcache.ReadReq_misses::cpu.data 53 # number of ReadReq misses 132system.cpu.dcache.ReadReq_misses::total 53 # number of ReadReq misses 133system.cpu.dcache.WriteReq_misses::cpu.data 85 # number of WriteReq misses 134system.cpu.dcache.WriteReq_misses::total 85 # number of WriteReq misses 135system.cpu.dcache.demand_misses::cpu.data 138 # number of demand (read+write) misses 136system.cpu.dcache.demand_misses::total 138 # number of demand (read+write) misses 137system.cpu.dcache.overall_misses::cpu.data 138 # number of overall misses 138system.cpu.dcache.overall_misses::total 138 # number of overall misses 139system.cpu.dcache.ReadReq_miss_latency::cpu.data 2968000 # number of ReadReq miss cycles 140system.cpu.dcache.ReadReq_miss_latency::total 2968000 # number of ReadReq miss cycles 141system.cpu.dcache.WriteReq_miss_latency::cpu.data 4760000 # number of WriteReq miss cycles 142system.cpu.dcache.WriteReq_miss_latency::total 4760000 # number of WriteReq miss cycles 143system.cpu.dcache.demand_miss_latency::cpu.data 7728000 # number of demand (read+write) miss cycles 144system.cpu.dcache.demand_miss_latency::total 7728000 # number of demand (read+write) miss cycles 145system.cpu.dcache.overall_miss_latency::cpu.data 7728000 # number of overall miss cycles 146system.cpu.dcache.overall_miss_latency::total 7728000 # number of overall miss cycles 147system.cpu.dcache.ReadReq_accesses::cpu.data 2226 # number of ReadReq accesses(hits+misses) 148system.cpu.dcache.ReadReq_accesses::total 2226 # number of ReadReq accesses(hits+misses) 149system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses) 150system.cpu.dcache.WriteReq_accesses::total 1442 # number of WriteReq accesses(hits+misses) 151system.cpu.dcache.SwapReq_accesses::cpu.data 6 # number of SwapReq accesses(hits+misses) 152system.cpu.dcache.SwapReq_accesses::total 6 # number of SwapReq accesses(hits+misses) 153system.cpu.dcache.demand_accesses::cpu.data 3668 # number of demand (read+write) accesses 154system.cpu.dcache.demand_accesses::total 3668 # number of demand (read+write) accesses 155system.cpu.dcache.overall_accesses::cpu.data 3668 # number of overall (read+write) accesses 156system.cpu.dcache.overall_accesses::total 3668 # number of overall (read+write) accesses 157system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.023810 # miss rate for ReadReq accesses 158system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.058946 # miss rate for WriteReq accesses 159system.cpu.dcache.demand_miss_rate::cpu.data 0.037623 # miss rate for demand accesses 160system.cpu.dcache.overall_miss_rate::cpu.data 0.037623 # miss rate for overall accesses 161system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56000 # average ReadReq miss latency 162system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56000 # average WriteReq miss latency 163system.cpu.dcache.demand_avg_miss_latency::cpu.data 56000 # average overall miss latency 164system.cpu.dcache.overall_avg_miss_latency::cpu.data 56000 # average overall miss latency 165system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 166system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 167system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 168system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 169system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 170system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 171system.cpu.dcache.fast_writes 0 # number of fast writes performed 172system.cpu.dcache.cache_copies 0 # number of cache copies performed 173system.cpu.dcache.ReadReq_mshr_misses::cpu.data 53 # number of ReadReq MSHR misses 174system.cpu.dcache.ReadReq_mshr_misses::total 53 # number of ReadReq MSHR misses 175system.cpu.dcache.WriteReq_mshr_misses::cpu.data 85 # number of WriteReq MSHR misses 176system.cpu.dcache.WriteReq_mshr_misses::total 85 # number of WriteReq MSHR misses 177system.cpu.dcache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses 178system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses 179system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses 180system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses 181system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2809000 # number of ReadReq MSHR miss cycles 182system.cpu.dcache.ReadReq_mshr_miss_latency::total 2809000 # number of ReadReq MSHR miss cycles 183system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4505000 # number of WriteReq MSHR miss cycles 184system.cpu.dcache.WriteReq_mshr_miss_latency::total 4505000 # number of WriteReq MSHR miss cycles 185system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7314000 # number of demand (read+write) MSHR miss cycles 186system.cpu.dcache.demand_mshr_miss_latency::total 7314000 # number of demand (read+write) MSHR miss cycles 187system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7314000 # number of overall MSHR miss cycles 188system.cpu.dcache.overall_mshr_miss_latency::total 7314000 # number of overall MSHR miss cycles 189system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.023810 # mshr miss rate for ReadReq accesses 190system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.058946 # mshr miss rate for WriteReq accesses 191system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.037623 # mshr miss rate for demand accesses 192system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.037623 # mshr miss rate for overall accesses 193system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency 194system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency 195system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency 196system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency 197system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 198system.cpu.l2cache.replacements 0 # number of replacements 199system.cpu.l2cache.tagsinuse 184.236128 # Cycle average of tags in use 200system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. 201system.cpu.l2cache.sampled_refs 331 # Sample count of references to valid blocks. 202system.cpu.l2cache.avg_refs 0.006042 # Average number of references to valid blocks. 203system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 204system.cpu.l2cache.occ_blocks::cpu.inst 152.765242 # Average occupied blocks per requestor 205system.cpu.l2cache.occ_blocks::cpu.data 31.470886 # Average occupied blocks per requestor 206system.cpu.l2cache.occ_percent::cpu.inst 0.004662 # Average percentage of cache occupancy 207system.cpu.l2cache.occ_percent::cpu.data 0.000960 # Average percentage of cache occupancy 208system.cpu.l2cache.occ_percent::total 0.005622 # Average percentage of cache occupancy 209system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits 210system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits 211system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits 212system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits 213system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits 214system.cpu.l2cache.overall_hits::total 2 # number of overall hits 215system.cpu.l2cache.ReadReq_misses::cpu.inst 278 # number of ReadReq misses 216system.cpu.l2cache.ReadReq_misses::cpu.data 53 # number of ReadReq misses 217system.cpu.l2cache.ReadReq_misses::total 331 # number of ReadReq misses 218system.cpu.l2cache.ReadExReq_misses::cpu.data 85 # number of ReadExReq misses 219system.cpu.l2cache.ReadExReq_misses::total 85 # number of ReadExReq misses 220system.cpu.l2cache.demand_misses::cpu.inst 278 # number of demand (read+write) misses 221system.cpu.l2cache.demand_misses::cpu.data 138 # number of demand (read+write) misses 222system.cpu.l2cache.demand_misses::total 416 # number of demand (read+write) misses 223system.cpu.l2cache.overall_misses::cpu.inst 278 # number of overall misses 224system.cpu.l2cache.overall_misses::cpu.data 138 # number of overall misses 225system.cpu.l2cache.overall_misses::total 416 # number of overall misses 226system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14456000 # number of ReadReq miss cycles 227system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2756000 # number of ReadReq miss cycles 228system.cpu.l2cache.ReadReq_miss_latency::total 17212000 # number of ReadReq miss cycles 229system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4420000 # number of ReadExReq miss cycles 230system.cpu.l2cache.ReadExReq_miss_latency::total 4420000 # number of ReadExReq miss cycles 231system.cpu.l2cache.demand_miss_latency::cpu.inst 14456000 # number of demand (read+write) miss cycles 232system.cpu.l2cache.demand_miss_latency::cpu.data 7176000 # number of demand (read+write) miss cycles 233system.cpu.l2cache.demand_miss_latency::total 21632000 # number of demand (read+write) miss cycles 234system.cpu.l2cache.overall_miss_latency::cpu.inst 14456000 # number of overall miss cycles 235system.cpu.l2cache.overall_miss_latency::cpu.data 7176000 # number of overall miss cycles 236system.cpu.l2cache.overall_miss_latency::total 21632000 # number of overall miss cycles 237system.cpu.l2cache.ReadReq_accesses::cpu.inst 280 # number of ReadReq accesses(hits+misses) 238system.cpu.l2cache.ReadReq_accesses::cpu.data 53 # number of ReadReq accesses(hits+misses) 239system.cpu.l2cache.ReadReq_accesses::total 333 # number of ReadReq accesses(hits+misses) 240system.cpu.l2cache.ReadExReq_accesses::cpu.data 85 # number of ReadExReq accesses(hits+misses) 241system.cpu.l2cache.ReadExReq_accesses::total 85 # number of ReadExReq accesses(hits+misses) 242system.cpu.l2cache.demand_accesses::cpu.inst 280 # number of demand (read+write) accesses 243system.cpu.l2cache.demand_accesses::cpu.data 138 # number of demand (read+write) accesses 244system.cpu.l2cache.demand_accesses::total 418 # number of demand (read+write) accesses 245system.cpu.l2cache.overall_accesses::cpu.inst 280 # number of overall (read+write) accesses 246system.cpu.l2cache.overall_accesses::cpu.data 138 # number of overall (read+write) accesses 247system.cpu.l2cache.overall_accesses::total 418 # number of overall (read+write) accesses 248system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.992857 # miss rate for ReadReq accesses 249system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses 250system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 251system.cpu.l2cache.demand_miss_rate::cpu.inst 0.992857 # miss rate for demand accesses 252system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 253system.cpu.l2cache.overall_miss_rate::cpu.inst 0.992857 # miss rate for overall accesses 254system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 255system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency 256system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency 257system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency 258system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency 259system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency 260system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency 261system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency 262system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 263system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 264system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 265system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 266system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 267system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 268system.cpu.l2cache.fast_writes 0 # number of fast writes performed 269system.cpu.l2cache.cache_copies 0 # number of cache copies performed 270system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 278 # number of ReadReq MSHR misses 271system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 53 # number of ReadReq MSHR misses 272system.cpu.l2cache.ReadReq_mshr_misses::total 331 # number of ReadReq MSHR misses 273system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 85 # number of ReadExReq MSHR misses 274system.cpu.l2cache.ReadExReq_mshr_misses::total 85 # number of ReadExReq MSHR misses 275system.cpu.l2cache.demand_mshr_misses::cpu.inst 278 # number of demand (read+write) MSHR misses 276system.cpu.l2cache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses 277system.cpu.l2cache.demand_mshr_misses::total 416 # number of demand (read+write) MSHR misses 278system.cpu.l2cache.overall_mshr_misses::cpu.inst 278 # number of overall MSHR misses 279system.cpu.l2cache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses 280system.cpu.l2cache.overall_mshr_misses::total 416 # number of overall MSHR misses 281system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11120000 # number of ReadReq MSHR miss cycles 282system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2120000 # number of ReadReq MSHR miss cycles 283system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13240000 # number of ReadReq MSHR miss cycles 284system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3400000 # number of ReadExReq MSHR miss cycles 285system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3400000 # number of ReadExReq MSHR miss cycles 286system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11120000 # number of demand (read+write) MSHR miss cycles 287system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5520000 # number of demand (read+write) MSHR miss cycles 288system.cpu.l2cache.demand_mshr_miss_latency::total 16640000 # number of demand (read+write) MSHR miss cycles 289system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11120000 # number of overall MSHR miss cycles 290system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5520000 # number of overall MSHR miss cycles 291system.cpu.l2cache.overall_mshr_miss_latency::total 16640000 # number of overall MSHR miss cycles 292system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.992857 # mshr miss rate for ReadReq accesses 293system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses 294system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 295system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.992857 # mshr miss rate for demand accesses 296system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 297system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.992857 # mshr miss rate for overall accesses 298system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 299system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency 300system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency 301system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency 302system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency 303system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency 304system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency 305system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency 306system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 307 308---------- End Simulation Statistics ---------- 309