stats.txt revision 8802:ef66a9083bc4
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000042 # Number of seconds simulated 4sim_ticks 41800000 # Number of ticks simulated 5final_tick 41800000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 146106 # Simulator instruction rate (inst/s) 8host_tick_rate 402347608 # Simulator tick rate (ticks/s) 9host_mem_usage 212484 # Number of bytes of host memory used 10host_seconds 0.10 # Real time elapsed on the host 11sim_insts 15175 # Number of instructions simulated 12system.physmem.bytes_read 26624 # Number of bytes read from this memory 13system.physmem.bytes_inst_read 17792 # Number of instructions bytes read from this memory 14system.physmem.bytes_written 0 # Number of bytes written to this memory 15system.physmem.num_reads 416 # Number of read requests responded to by this memory 16system.physmem.num_writes 0 # Number of write requests responded to by this memory 17system.physmem.num_other 0 # Number of other requests responded to by this memory 18system.physmem.bw_read 636937799 # Total read bandwidth from this memory (bytes/s) 19system.physmem.bw_inst_read 425645933 # Instruction read bandwidth from this memory (bytes/s) 20system.physmem.bw_total 636937799 # Total bandwidth to/from this memory (bytes/s) 21system.cpu.workload.num_syscalls 18 # Number of system calls 22system.cpu.numCycles 83600 # number of cpu cycles simulated 23system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 24system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 25system.cpu.num_insts 15175 # Number of instructions executed 26system.cpu.num_int_alu_accesses 12231 # Number of integer alu accesses 27system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses 28system.cpu.num_func_calls 385 # number of times a function call or return occured 29system.cpu.num_conditional_control_insts 2435 # number of instructions that are conditional controls 30system.cpu.num_int_insts 12231 # number of integer instructions 31system.cpu.num_fp_insts 0 # number of float instructions 32system.cpu.num_int_register_reads 29059 # number of times the integer registers were read 33system.cpu.num_int_register_writes 13831 # number of times the integer registers were written 34system.cpu.num_fp_register_reads 0 # number of times the floating registers were read 35system.cpu.num_fp_register_writes 0 # number of times the floating registers were written 36system.cpu.num_mem_refs 3684 # number of memory refs 37system.cpu.num_load_insts 2232 # Number of load instructions 38system.cpu.num_store_insts 1452 # Number of store instructions 39system.cpu.num_idle_cycles 0 # Number of idle cycles 40system.cpu.num_busy_cycles 83600 # Number of busy cycles 41system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 42system.cpu.idle_fraction 0 # Percentage of idle cycles 43system.cpu.icache.replacements 0 # number of replacements 44system.cpu.icache.tagsinuse 153.436702 # Cycle average of tags in use 45system.cpu.icache.total_refs 14941 # Total number of references to valid blocks. 46system.cpu.icache.sampled_refs 280 # Sample count of references to valid blocks. 47system.cpu.icache.avg_refs 53.360714 # Average number of references to valid blocks. 48system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 49system.cpu.icache.occ_blocks::0 153.436702 # Average occupied blocks per context 50system.cpu.icache.occ_percent::0 0.074920 # Average percentage of cache occupancy 51system.cpu.icache.ReadReq_hits 14941 # number of ReadReq hits 52system.cpu.icache.demand_hits 14941 # number of demand (read+write) hits 53system.cpu.icache.overall_hits 14941 # number of overall hits 54system.cpu.icache.ReadReq_misses 280 # number of ReadReq misses 55system.cpu.icache.demand_misses 280 # number of demand (read+write) misses 56system.cpu.icache.overall_misses 280 # number of overall misses 57system.cpu.icache.ReadReq_miss_latency 15596000 # number of ReadReq miss cycles 58system.cpu.icache.demand_miss_latency 15596000 # number of demand (read+write) miss cycles 59system.cpu.icache.overall_miss_latency 15596000 # number of overall miss cycles 60system.cpu.icache.ReadReq_accesses 15221 # number of ReadReq accesses(hits+misses) 61system.cpu.icache.demand_accesses 15221 # number of demand (read+write) accesses 62system.cpu.icache.overall_accesses 15221 # number of overall (read+write) accesses 63system.cpu.icache.ReadReq_miss_rate 0.018396 # miss rate for ReadReq accesses 64system.cpu.icache.demand_miss_rate 0.018396 # miss rate for demand accesses 65system.cpu.icache.overall_miss_rate 0.018396 # miss rate for overall accesses 66system.cpu.icache.ReadReq_avg_miss_latency 55700 # average ReadReq miss latency 67system.cpu.icache.demand_avg_miss_latency 55700 # average overall miss latency 68system.cpu.icache.overall_avg_miss_latency 55700 # average overall miss latency 69system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 70system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 71system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 72system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 73system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 74system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 75system.cpu.icache.fast_writes 0 # number of fast writes performed 76system.cpu.icache.cache_copies 0 # number of cache copies performed 77system.cpu.icache.writebacks 0 # number of writebacks 78system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 79system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits 80system.cpu.icache.ReadReq_mshr_misses 280 # number of ReadReq MSHR misses 81system.cpu.icache.demand_mshr_misses 280 # number of demand (read+write) MSHR misses 82system.cpu.icache.overall_mshr_misses 280 # number of overall MSHR misses 83system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 84system.cpu.icache.ReadReq_mshr_miss_latency 14756000 # number of ReadReq MSHR miss cycles 85system.cpu.icache.demand_mshr_miss_latency 14756000 # number of demand (read+write) MSHR miss cycles 86system.cpu.icache.overall_mshr_miss_latency 14756000 # number of overall MSHR miss cycles 87system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 88system.cpu.icache.ReadReq_mshr_miss_rate 0.018396 # mshr miss rate for ReadReq accesses 89system.cpu.icache.demand_mshr_miss_rate 0.018396 # mshr miss rate for demand accesses 90system.cpu.icache.overall_mshr_miss_rate 0.018396 # mshr miss rate for overall accesses 91system.cpu.icache.ReadReq_avg_mshr_miss_latency 52700 # average ReadReq mshr miss latency 92system.cpu.icache.demand_avg_mshr_miss_latency 52700 # average overall mshr miss latency 93system.cpu.icache.overall_avg_mshr_miss_latency 52700 # average overall mshr miss latency 94system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 95system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated 96system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 97system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 98system.cpu.dcache.replacements 0 # number of replacements 99system.cpu.dcache.tagsinuse 97.842991 # Cycle average of tags in use 100system.cpu.dcache.total_refs 3536 # Total number of references to valid blocks. 101system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks. 102system.cpu.dcache.avg_refs 25.623188 # Average number of references to valid blocks. 103system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 104system.cpu.dcache.occ_blocks::0 97.842991 # Average occupied blocks per context 105system.cpu.dcache.occ_percent::0 0.023887 # Average percentage of cache occupancy 106system.cpu.dcache.ReadReq_hits 2173 # number of ReadReq hits 107system.cpu.dcache.WriteReq_hits 1357 # number of WriteReq hits 108system.cpu.dcache.SwapReq_hits 6 # number of SwapReq hits 109system.cpu.dcache.demand_hits 3530 # number of demand (read+write) hits 110system.cpu.dcache.overall_hits 3530 # number of overall hits 111system.cpu.dcache.ReadReq_misses 53 # number of ReadReq misses 112system.cpu.dcache.WriteReq_misses 85 # number of WriteReq misses 113system.cpu.dcache.demand_misses 138 # number of demand (read+write) misses 114system.cpu.dcache.overall_misses 138 # number of overall misses 115system.cpu.dcache.ReadReq_miss_latency 2968000 # number of ReadReq miss cycles 116system.cpu.dcache.WriteReq_miss_latency 4760000 # number of WriteReq miss cycles 117system.cpu.dcache.demand_miss_latency 7728000 # number of demand (read+write) miss cycles 118system.cpu.dcache.overall_miss_latency 7728000 # number of overall miss cycles 119system.cpu.dcache.ReadReq_accesses 2226 # number of ReadReq accesses(hits+misses) 120system.cpu.dcache.WriteReq_accesses 1442 # number of WriteReq accesses(hits+misses) 121system.cpu.dcache.SwapReq_accesses 6 # number of SwapReq accesses(hits+misses) 122system.cpu.dcache.demand_accesses 3668 # number of demand (read+write) accesses 123system.cpu.dcache.overall_accesses 3668 # number of overall (read+write) accesses 124system.cpu.dcache.ReadReq_miss_rate 0.023810 # miss rate for ReadReq accesses 125system.cpu.dcache.WriteReq_miss_rate 0.058946 # miss rate for WriteReq accesses 126system.cpu.dcache.demand_miss_rate 0.037623 # miss rate for demand accesses 127system.cpu.dcache.overall_miss_rate 0.037623 # miss rate for overall accesses 128system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency 129system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency 130system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency 131system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency 132system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 133system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 134system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 135system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 136system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 137system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 138system.cpu.dcache.fast_writes 0 # number of fast writes performed 139system.cpu.dcache.cache_copies 0 # number of cache copies performed 140system.cpu.dcache.writebacks 0 # number of writebacks 141system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 142system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits 143system.cpu.dcache.ReadReq_mshr_misses 53 # number of ReadReq MSHR misses 144system.cpu.dcache.WriteReq_mshr_misses 85 # number of WriteReq MSHR misses 145system.cpu.dcache.demand_mshr_misses 138 # number of demand (read+write) MSHR misses 146system.cpu.dcache.overall_mshr_misses 138 # number of overall MSHR misses 147system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 148system.cpu.dcache.ReadReq_mshr_miss_latency 2809000 # number of ReadReq MSHR miss cycles 149system.cpu.dcache.WriteReq_mshr_miss_latency 4505000 # number of WriteReq MSHR miss cycles 150system.cpu.dcache.demand_mshr_miss_latency 7314000 # number of demand (read+write) MSHR miss cycles 151system.cpu.dcache.overall_mshr_miss_latency 7314000 # number of overall MSHR miss cycles 152system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 153system.cpu.dcache.ReadReq_mshr_miss_rate 0.023810 # mshr miss rate for ReadReq accesses 154system.cpu.dcache.WriteReq_mshr_miss_rate 0.058946 # mshr miss rate for WriteReq accesses 155system.cpu.dcache.demand_mshr_miss_rate 0.037623 # mshr miss rate for demand accesses 156system.cpu.dcache.overall_mshr_miss_rate 0.037623 # mshr miss rate for overall accesses 157system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency 158system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency 159system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency 160system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency 161system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 162system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated 163system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 164system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 165system.cpu.l2cache.replacements 0 # number of replacements 166system.cpu.l2cache.tagsinuse 184.236128 # Cycle average of tags in use 167system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. 168system.cpu.l2cache.sampled_refs 331 # Sample count of references to valid blocks. 169system.cpu.l2cache.avg_refs 0.006042 # Average number of references to valid blocks. 170system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 171system.cpu.l2cache.occ_blocks::0 184.236128 # Average occupied blocks per context 172system.cpu.l2cache.occ_percent::0 0.005622 # Average percentage of cache occupancy 173system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits 174system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits 175system.cpu.l2cache.overall_hits 2 # number of overall hits 176system.cpu.l2cache.ReadReq_misses 331 # number of ReadReq misses 177system.cpu.l2cache.ReadExReq_misses 85 # number of ReadExReq misses 178system.cpu.l2cache.demand_misses 416 # number of demand (read+write) misses 179system.cpu.l2cache.overall_misses 416 # number of overall misses 180system.cpu.l2cache.ReadReq_miss_latency 17212000 # number of ReadReq miss cycles 181system.cpu.l2cache.ReadExReq_miss_latency 4420000 # number of ReadExReq miss cycles 182system.cpu.l2cache.demand_miss_latency 21632000 # number of demand (read+write) miss cycles 183system.cpu.l2cache.overall_miss_latency 21632000 # number of overall miss cycles 184system.cpu.l2cache.ReadReq_accesses 333 # number of ReadReq accesses(hits+misses) 185system.cpu.l2cache.ReadExReq_accesses 85 # number of ReadExReq accesses(hits+misses) 186system.cpu.l2cache.demand_accesses 418 # number of demand (read+write) accesses 187system.cpu.l2cache.overall_accesses 418 # number of overall (read+write) accesses 188system.cpu.l2cache.ReadReq_miss_rate 0.993994 # miss rate for ReadReq accesses 189system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses 190system.cpu.l2cache.demand_miss_rate 0.995215 # miss rate for demand accesses 191system.cpu.l2cache.overall_miss_rate 0.995215 # miss rate for overall accesses 192system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency 193system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency 194system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency 195system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency 196system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 197system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 198system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 199system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 200system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 201system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 202system.cpu.l2cache.fast_writes 0 # number of fast writes performed 203system.cpu.l2cache.cache_copies 0 # number of cache copies performed 204system.cpu.l2cache.writebacks 0 # number of writebacks 205system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 206system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits 207system.cpu.l2cache.ReadReq_mshr_misses 331 # number of ReadReq MSHR misses 208system.cpu.l2cache.ReadExReq_mshr_misses 85 # number of ReadExReq MSHR misses 209system.cpu.l2cache.demand_mshr_misses 416 # number of demand (read+write) MSHR misses 210system.cpu.l2cache.overall_mshr_misses 416 # number of overall MSHR misses 211system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 212system.cpu.l2cache.ReadReq_mshr_miss_latency 13240000 # number of ReadReq MSHR miss cycles 213system.cpu.l2cache.ReadExReq_mshr_miss_latency 3400000 # number of ReadExReq MSHR miss cycles 214system.cpu.l2cache.demand_mshr_miss_latency 16640000 # number of demand (read+write) MSHR miss cycles 215system.cpu.l2cache.overall_mshr_miss_latency 16640000 # number of overall MSHR miss cycles 216system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 217system.cpu.l2cache.ReadReq_mshr_miss_rate 0.993994 # mshr miss rate for ReadReq accesses 218system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses 219system.cpu.l2cache.demand_mshr_miss_rate 0.995215 # mshr miss rate for demand accesses 220system.cpu.l2cache.overall_mshr_miss_rate 0.995215 # mshr miss rate for overall accesses 221system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency 222system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency 223system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency 224system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency 225system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 226system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated 227system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 228system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 229 230---------- End Simulation Statistics ---------- 231