stats.txt revision 11570:4aac82f10951
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000044 # Number of seconds simulated 4sim_ticks 44282500 # Number of ticks simulated 5final_tick 44282500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 322672 # Simulator instruction rate (inst/s) 8host_op_rate 322568 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 941828647 # Simulator tick rate (ticks/s) 10host_mem_usage 247000 # Number of bytes of host memory used 11host_seconds 0.05 # Real time elapsed on the host 12sim_insts 15162 # Number of instructions simulated 13sim_ops 15162 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 44282500 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.inst 17792 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 8832 # Number of bytes read from this memory 19system.physmem.bytes_read::total 26624 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 17792 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 17792 # Number of instructions bytes read from this memory 22system.physmem.num_reads::cpu.inst 278 # Number of read requests responded to by this memory 23system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory 24system.physmem.num_reads::total 416 # Number of read requests responded to by this memory 25system.physmem.bw_read::cpu.inst 401784000 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::cpu.data 199446734 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::total 601230734 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::cpu.inst 401784000 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::total 401784000 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_total::cpu.inst 401784000 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::cpu.data 199446734 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.bw_total::total 601230734 # Total bandwidth to/from this memory (bytes/s) 33system.pwrStateResidencyTicks::UNDEFINED 44282500 # Cumulative time (in ticks) in various power states 34system.cpu_clk_domain.clock 500 # Clock period in ticks 35system.cpu.workload.num_syscalls 18 # Number of system calls 36system.cpu.pwrStateResidencyTicks::ON 44282500 # Cumulative time (in ticks) in various power states 37system.cpu.numCycles 88565 # number of cpu cycles simulated 38system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 39system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 40system.cpu.committedInsts 15162 # Number of instructions committed 41system.cpu.committedOps 15162 # Number of ops (including micro ops) committed 42system.cpu.num_int_alu_accesses 12219 # Number of integer alu accesses 43system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses 44system.cpu.num_func_calls 385 # number of times a function call or return occured 45system.cpu.num_conditional_control_insts 2434 # number of instructions that are conditional controls 46system.cpu.num_int_insts 12219 # number of integer instructions 47system.cpu.num_fp_insts 0 # number of float instructions 48system.cpu.num_int_register_reads 29037 # number of times the integer registers were read 49system.cpu.num_int_register_writes 13818 # number of times the integer registers were written 50system.cpu.num_fp_register_reads 0 # number of times the floating registers were read 51system.cpu.num_fp_register_writes 0 # number of times the floating registers were written 52system.cpu.num_mem_refs 3683 # number of memory refs 53system.cpu.num_load_insts 2231 # Number of load instructions 54system.cpu.num_store_insts 1452 # Number of store instructions 55system.cpu.num_idle_cycles 0.002000 # Number of idle cycles 56system.cpu.num_busy_cycles 88564.998000 # Number of busy cycles 57system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles 58system.cpu.idle_fraction 0.000000 # Percentage of idle cycles 59system.cpu.Branches 3363 # Number of branches fetched 60system.cpu.op_class::No_OpClass 726 4.77% 4.77% # Class of executed instruction 61system.cpu.op_class::IntAlu 10798 71.01% 75.78% # Class of executed instruction 62system.cpu.op_class::IntMult 0 0.00% 75.78% # Class of executed instruction 63system.cpu.op_class::IntDiv 0 0.00% 75.78% # Class of executed instruction 64system.cpu.op_class::FloatAdd 0 0.00% 75.78% # Class of executed instruction 65system.cpu.op_class::FloatCmp 0 0.00% 75.78% # Class of executed instruction 66system.cpu.op_class::FloatCvt 0 0.00% 75.78% # Class of executed instruction 67system.cpu.op_class::FloatMult 0 0.00% 75.78% # Class of executed instruction 68system.cpu.op_class::FloatDiv 0 0.00% 75.78% # Class of executed instruction 69system.cpu.op_class::FloatSqrt 0 0.00% 75.78% # Class of executed instruction 70system.cpu.op_class::SimdAdd 0 0.00% 75.78% # Class of executed instruction 71system.cpu.op_class::SimdAddAcc 0 0.00% 75.78% # Class of executed instruction 72system.cpu.op_class::SimdAlu 0 0.00% 75.78% # Class of executed instruction 73system.cpu.op_class::SimdCmp 0 0.00% 75.78% # Class of executed instruction 74system.cpu.op_class::SimdCvt 0 0.00% 75.78% # Class of executed instruction 75system.cpu.op_class::SimdMisc 0 0.00% 75.78% # Class of executed instruction 76system.cpu.op_class::SimdMult 0 0.00% 75.78% # Class of executed instruction 77system.cpu.op_class::SimdMultAcc 0 0.00% 75.78% # Class of executed instruction 78system.cpu.op_class::SimdShift 0 0.00% 75.78% # Class of executed instruction 79system.cpu.op_class::SimdShiftAcc 0 0.00% 75.78% # Class of executed instruction 80system.cpu.op_class::SimdSqrt 0 0.00% 75.78% # Class of executed instruction 81system.cpu.op_class::SimdFloatAdd 0 0.00% 75.78% # Class of executed instruction 82system.cpu.op_class::SimdFloatAlu 0 0.00% 75.78% # Class of executed instruction 83system.cpu.op_class::SimdFloatCmp 0 0.00% 75.78% # Class of executed instruction 84system.cpu.op_class::SimdFloatCvt 0 0.00% 75.78% # Class of executed instruction 85system.cpu.op_class::SimdFloatDiv 0 0.00% 75.78% # Class of executed instruction 86system.cpu.op_class::SimdFloatMisc 0 0.00% 75.78% # Class of executed instruction 87system.cpu.op_class::SimdFloatMult 0 0.00% 75.78% # Class of executed instruction 88system.cpu.op_class::SimdFloatMultAcc 0 0.00% 75.78% # Class of executed instruction 89system.cpu.op_class::SimdFloatSqrt 0 0.00% 75.78% # Class of executed instruction 90system.cpu.op_class::MemRead 2231 14.67% 90.45% # Class of executed instruction 91system.cpu.op_class::MemWrite 1452 9.55% 100.00% # Class of executed instruction 92system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 93system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 94system.cpu.op_class::total 15207 # Class of executed instruction 95system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 44282500 # Cumulative time (in ticks) in various power states 96system.cpu.dcache.tags.replacements 0 # number of replacements 97system.cpu.dcache.tags.tagsinuse 97.148649 # Cycle average of tags in use 98system.cpu.dcache.tags.total_refs 3535 # Total number of references to valid blocks. 99system.cpu.dcache.tags.sampled_refs 138 # Sample count of references to valid blocks. 100system.cpu.dcache.tags.avg_refs 25.615942 # Average number of references to valid blocks. 101system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 102system.cpu.dcache.tags.occ_blocks::cpu.data 97.148649 # Average occupied blocks per requestor 103system.cpu.dcache.tags.occ_percent::cpu.data 0.023718 # Average percentage of cache occupancy 104system.cpu.dcache.tags.occ_percent::total 0.023718 # Average percentage of cache occupancy 105system.cpu.dcache.tags.occ_task_id_blocks::1024 138 # Occupied blocks per task id 106system.cpu.dcache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id 107system.cpu.dcache.tags.age_task_id_blocks_1024::1 127 # Occupied blocks per task id 108system.cpu.dcache.tags.occ_task_id_percent::1024 0.033691 # Percentage of cache occupancy per task id 109system.cpu.dcache.tags.tag_accesses 7484 # Number of tag accesses 110system.cpu.dcache.tags.data_accesses 7484 # Number of data accesses 111system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 44282500 # Cumulative time (in ticks) in various power states 112system.cpu.dcache.ReadReq_hits::cpu.data 2172 # number of ReadReq hits 113system.cpu.dcache.ReadReq_hits::total 2172 # number of ReadReq hits 114system.cpu.dcache.WriteReq_hits::cpu.data 1357 # number of WriteReq hits 115system.cpu.dcache.WriteReq_hits::total 1357 # number of WriteReq hits 116system.cpu.dcache.SwapReq_hits::cpu.data 6 # number of SwapReq hits 117system.cpu.dcache.SwapReq_hits::total 6 # number of SwapReq hits 118system.cpu.dcache.demand_hits::cpu.data 3529 # number of demand (read+write) hits 119system.cpu.dcache.demand_hits::total 3529 # number of demand (read+write) hits 120system.cpu.dcache.overall_hits::cpu.data 3529 # number of overall hits 121system.cpu.dcache.overall_hits::total 3529 # number of overall hits 122system.cpu.dcache.ReadReq_misses::cpu.data 53 # number of ReadReq misses 123system.cpu.dcache.ReadReq_misses::total 53 # number of ReadReq misses 124system.cpu.dcache.WriteReq_misses::cpu.data 85 # number of WriteReq misses 125system.cpu.dcache.WriteReq_misses::total 85 # number of WriteReq misses 126system.cpu.dcache.demand_misses::cpu.data 138 # number of demand (read+write) misses 127system.cpu.dcache.demand_misses::total 138 # number of demand (read+write) misses 128system.cpu.dcache.overall_misses::cpu.data 138 # number of overall misses 129system.cpu.dcache.overall_misses::total 138 # number of overall misses 130system.cpu.dcache.ReadReq_miss_latency::cpu.data 3286000 # number of ReadReq miss cycles 131system.cpu.dcache.ReadReq_miss_latency::total 3286000 # number of ReadReq miss cycles 132system.cpu.dcache.WriteReq_miss_latency::cpu.data 5270000 # number of WriteReq miss cycles 133system.cpu.dcache.WriteReq_miss_latency::total 5270000 # number of WriteReq miss cycles 134system.cpu.dcache.demand_miss_latency::cpu.data 8556000 # number of demand (read+write) miss cycles 135system.cpu.dcache.demand_miss_latency::total 8556000 # number of demand (read+write) miss cycles 136system.cpu.dcache.overall_miss_latency::cpu.data 8556000 # number of overall miss cycles 137system.cpu.dcache.overall_miss_latency::total 8556000 # number of overall miss cycles 138system.cpu.dcache.ReadReq_accesses::cpu.data 2225 # number of ReadReq accesses(hits+misses) 139system.cpu.dcache.ReadReq_accesses::total 2225 # number of ReadReq accesses(hits+misses) 140system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses) 141system.cpu.dcache.WriteReq_accesses::total 1442 # number of WriteReq accesses(hits+misses) 142system.cpu.dcache.SwapReq_accesses::cpu.data 6 # number of SwapReq accesses(hits+misses) 143system.cpu.dcache.SwapReq_accesses::total 6 # number of SwapReq accesses(hits+misses) 144system.cpu.dcache.demand_accesses::cpu.data 3667 # number of demand (read+write) accesses 145system.cpu.dcache.demand_accesses::total 3667 # number of demand (read+write) accesses 146system.cpu.dcache.overall_accesses::cpu.data 3667 # number of overall (read+write) accesses 147system.cpu.dcache.overall_accesses::total 3667 # number of overall (read+write) accesses 148system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.023820 # miss rate for ReadReq accesses 149system.cpu.dcache.ReadReq_miss_rate::total 0.023820 # miss rate for ReadReq accesses 150system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.058946 # miss rate for WriteReq accesses 151system.cpu.dcache.WriteReq_miss_rate::total 0.058946 # miss rate for WriteReq accesses 152system.cpu.dcache.demand_miss_rate::cpu.data 0.037633 # miss rate for demand accesses 153system.cpu.dcache.demand_miss_rate::total 0.037633 # miss rate for demand accesses 154system.cpu.dcache.overall_miss_rate::cpu.data 0.037633 # miss rate for overall accesses 155system.cpu.dcache.overall_miss_rate::total 0.037633 # miss rate for overall accesses 156system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62000 # average ReadReq miss latency 157system.cpu.dcache.ReadReq_avg_miss_latency::total 62000 # average ReadReq miss latency 158system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62000 # average WriteReq miss latency 159system.cpu.dcache.WriteReq_avg_miss_latency::total 62000 # average WriteReq miss latency 160system.cpu.dcache.demand_avg_miss_latency::cpu.data 62000 # average overall miss latency 161system.cpu.dcache.demand_avg_miss_latency::total 62000 # average overall miss latency 162system.cpu.dcache.overall_avg_miss_latency::cpu.data 62000 # average overall miss latency 163system.cpu.dcache.overall_avg_miss_latency::total 62000 # average overall miss latency 164system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 165system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 166system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 167system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 168system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 169system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 170system.cpu.dcache.ReadReq_mshr_misses::cpu.data 53 # number of ReadReq MSHR misses 171system.cpu.dcache.ReadReq_mshr_misses::total 53 # number of ReadReq MSHR misses 172system.cpu.dcache.WriteReq_mshr_misses::cpu.data 85 # number of WriteReq MSHR misses 173system.cpu.dcache.WriteReq_mshr_misses::total 85 # number of WriteReq MSHR misses 174system.cpu.dcache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses 175system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses 176system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses 177system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses 178system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3233000 # number of ReadReq MSHR miss cycles 179system.cpu.dcache.ReadReq_mshr_miss_latency::total 3233000 # number of ReadReq MSHR miss cycles 180system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5185000 # number of WriteReq MSHR miss cycles 181system.cpu.dcache.WriteReq_mshr_miss_latency::total 5185000 # number of WriteReq MSHR miss cycles 182system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8418000 # number of demand (read+write) MSHR miss cycles 183system.cpu.dcache.demand_mshr_miss_latency::total 8418000 # number of demand (read+write) MSHR miss cycles 184system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8418000 # number of overall MSHR miss cycles 185system.cpu.dcache.overall_mshr_miss_latency::total 8418000 # number of overall MSHR miss cycles 186system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.023820 # mshr miss rate for ReadReq accesses 187system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.023820 # mshr miss rate for ReadReq accesses 188system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.058946 # mshr miss rate for WriteReq accesses 189system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.058946 # mshr miss rate for WriteReq accesses 190system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.037633 # mshr miss rate for demand accesses 191system.cpu.dcache.demand_mshr_miss_rate::total 0.037633 # mshr miss rate for demand accesses 192system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.037633 # mshr miss rate for overall accesses 193system.cpu.dcache.overall_mshr_miss_rate::total 0.037633 # mshr miss rate for overall accesses 194system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61000 # average ReadReq mshr miss latency 195system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61000 # average ReadReq mshr miss latency 196system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61000 # average WriteReq mshr miss latency 197system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency 198system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency 199system.cpu.dcache.demand_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency 200system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency 201system.cpu.dcache.overall_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency 202system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 44282500 # Cumulative time (in ticks) in various power states 203system.cpu.icache.tags.replacements 0 # number of replacements 204system.cpu.icache.tags.tagsinuse 151.748662 # Cycle average of tags in use 205system.cpu.icache.tags.total_refs 14928 # Total number of references to valid blocks. 206system.cpu.icache.tags.sampled_refs 280 # Sample count of references to valid blocks. 207system.cpu.icache.tags.avg_refs 53.314286 # Average number of references to valid blocks. 208system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 209system.cpu.icache.tags.occ_blocks::cpu.inst 151.748662 # Average occupied blocks per requestor 210system.cpu.icache.tags.occ_percent::cpu.inst 0.074096 # Average percentage of cache occupancy 211system.cpu.icache.tags.occ_percent::total 0.074096 # Average percentage of cache occupancy 212system.cpu.icache.tags.occ_task_id_blocks::1024 280 # Occupied blocks per task id 213system.cpu.icache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id 214system.cpu.icache.tags.age_task_id_blocks_1024::1 235 # Occupied blocks per task id 215system.cpu.icache.tags.occ_task_id_percent::1024 0.136719 # Percentage of cache occupancy per task id 216system.cpu.icache.tags.tag_accesses 30696 # Number of tag accesses 217system.cpu.icache.tags.data_accesses 30696 # Number of data accesses 218system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 44282500 # Cumulative time (in ticks) in various power states 219system.cpu.icache.ReadReq_hits::cpu.inst 14928 # number of ReadReq hits 220system.cpu.icache.ReadReq_hits::total 14928 # number of ReadReq hits 221system.cpu.icache.demand_hits::cpu.inst 14928 # number of demand (read+write) hits 222system.cpu.icache.demand_hits::total 14928 # number of demand (read+write) hits 223system.cpu.icache.overall_hits::cpu.inst 14928 # number of overall hits 224system.cpu.icache.overall_hits::total 14928 # number of overall hits 225system.cpu.icache.ReadReq_misses::cpu.inst 280 # number of ReadReq misses 226system.cpu.icache.ReadReq_misses::total 280 # number of ReadReq misses 227system.cpu.icache.demand_misses::cpu.inst 280 # number of demand (read+write) misses 228system.cpu.icache.demand_misses::total 280 # number of demand (read+write) misses 229system.cpu.icache.overall_misses::cpu.inst 280 # number of overall misses 230system.cpu.icache.overall_misses::total 280 # number of overall misses 231system.cpu.icache.ReadReq_miss_latency::cpu.inst 17264500 # number of ReadReq miss cycles 232system.cpu.icache.ReadReq_miss_latency::total 17264500 # number of ReadReq miss cycles 233system.cpu.icache.demand_miss_latency::cpu.inst 17264500 # number of demand (read+write) miss cycles 234system.cpu.icache.demand_miss_latency::total 17264500 # number of demand (read+write) miss cycles 235system.cpu.icache.overall_miss_latency::cpu.inst 17264500 # number of overall miss cycles 236system.cpu.icache.overall_miss_latency::total 17264500 # number of overall miss cycles 237system.cpu.icache.ReadReq_accesses::cpu.inst 15208 # number of ReadReq accesses(hits+misses) 238system.cpu.icache.ReadReq_accesses::total 15208 # number of ReadReq accesses(hits+misses) 239system.cpu.icache.demand_accesses::cpu.inst 15208 # number of demand (read+write) accesses 240system.cpu.icache.demand_accesses::total 15208 # number of demand (read+write) accesses 241system.cpu.icache.overall_accesses::cpu.inst 15208 # number of overall (read+write) accesses 242system.cpu.icache.overall_accesses::total 15208 # number of overall (read+write) accesses 243system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.018411 # miss rate for ReadReq accesses 244system.cpu.icache.ReadReq_miss_rate::total 0.018411 # miss rate for ReadReq accesses 245system.cpu.icache.demand_miss_rate::cpu.inst 0.018411 # miss rate for demand accesses 246system.cpu.icache.demand_miss_rate::total 0.018411 # miss rate for demand accesses 247system.cpu.icache.overall_miss_rate::cpu.inst 0.018411 # miss rate for overall accesses 248system.cpu.icache.overall_miss_rate::total 0.018411 # miss rate for overall accesses 249system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61658.928571 # average ReadReq miss latency 250system.cpu.icache.ReadReq_avg_miss_latency::total 61658.928571 # average ReadReq miss latency 251system.cpu.icache.demand_avg_miss_latency::cpu.inst 61658.928571 # average overall miss latency 252system.cpu.icache.demand_avg_miss_latency::total 61658.928571 # average overall miss latency 253system.cpu.icache.overall_avg_miss_latency::cpu.inst 61658.928571 # average overall miss latency 254system.cpu.icache.overall_avg_miss_latency::total 61658.928571 # average overall miss latency 255system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 256system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 257system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 258system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 259system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 260system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 261system.cpu.icache.ReadReq_mshr_misses::cpu.inst 280 # number of ReadReq MSHR misses 262system.cpu.icache.ReadReq_mshr_misses::total 280 # number of ReadReq MSHR misses 263system.cpu.icache.demand_mshr_misses::cpu.inst 280 # number of demand (read+write) MSHR misses 264system.cpu.icache.demand_mshr_misses::total 280 # number of demand (read+write) MSHR misses 265system.cpu.icache.overall_mshr_misses::cpu.inst 280 # number of overall MSHR misses 266system.cpu.icache.overall_mshr_misses::total 280 # number of overall MSHR misses 267system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16984500 # number of ReadReq MSHR miss cycles 268system.cpu.icache.ReadReq_mshr_miss_latency::total 16984500 # number of ReadReq MSHR miss cycles 269system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16984500 # number of demand (read+write) MSHR miss cycles 270system.cpu.icache.demand_mshr_miss_latency::total 16984500 # number of demand (read+write) MSHR miss cycles 271system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16984500 # number of overall MSHR miss cycles 272system.cpu.icache.overall_mshr_miss_latency::total 16984500 # number of overall MSHR miss cycles 273system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.018411 # mshr miss rate for ReadReq accesses 274system.cpu.icache.ReadReq_mshr_miss_rate::total 0.018411 # mshr miss rate for ReadReq accesses 275system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.018411 # mshr miss rate for demand accesses 276system.cpu.icache.demand_mshr_miss_rate::total 0.018411 # mshr miss rate for demand accesses 277system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.018411 # mshr miss rate for overall accesses 278system.cpu.icache.overall_mshr_miss_rate::total 0.018411 # mshr miss rate for overall accesses 279system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60658.928571 # average ReadReq mshr miss latency 280system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60658.928571 # average ReadReq mshr miss latency 281system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60658.928571 # average overall mshr miss latency 282system.cpu.icache.demand_avg_mshr_miss_latency::total 60658.928571 # average overall mshr miss latency 283system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60658.928571 # average overall mshr miss latency 284system.cpu.icache.overall_avg_mshr_miss_latency::total 60658.928571 # average overall mshr miss latency 285system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 44282500 # Cumulative time (in ticks) in various power states 286system.cpu.l2cache.tags.replacements 0 # number of replacements 287system.cpu.l2cache.tags.tagsinuse 182.297739 # Cycle average of tags in use 288system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. 289system.cpu.l2cache.tags.sampled_refs 331 # Sample count of references to valid blocks. 290system.cpu.l2cache.tags.avg_refs 0.006042 # Average number of references to valid blocks. 291system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 292system.cpu.l2cache.tags.occ_blocks::cpu.inst 151.068800 # Average occupied blocks per requestor 293system.cpu.l2cache.tags.occ_blocks::cpu.data 31.228940 # Average occupied blocks per requestor 294system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004610 # Average percentage of cache occupancy 295system.cpu.l2cache.tags.occ_percent::cpu.data 0.000953 # Average percentage of cache occupancy 296system.cpu.l2cache.tags.occ_percent::total 0.005563 # Average percentage of cache occupancy 297system.cpu.l2cache.tags.occ_task_id_blocks::1024 331 # Occupied blocks per task id 298system.cpu.l2cache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id 299system.cpu.l2cache.tags.age_task_id_blocks_1024::1 276 # Occupied blocks per task id 300system.cpu.l2cache.tags.occ_task_id_percent::1024 0.010101 # Percentage of cache occupancy per task id 301system.cpu.l2cache.tags.tag_accesses 3760 # Number of tag accesses 302system.cpu.l2cache.tags.data_accesses 3760 # Number of data accesses 303system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 44282500 # Cumulative time (in ticks) in various power states 304system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2 # number of ReadCleanReq hits 305system.cpu.l2cache.ReadCleanReq_hits::total 2 # number of ReadCleanReq hits 306system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits 307system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits 308system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits 309system.cpu.l2cache.overall_hits::total 2 # number of overall hits 310system.cpu.l2cache.ReadExReq_misses::cpu.data 85 # number of ReadExReq misses 311system.cpu.l2cache.ReadExReq_misses::total 85 # number of ReadExReq misses 312system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 278 # number of ReadCleanReq misses 313system.cpu.l2cache.ReadCleanReq_misses::total 278 # number of ReadCleanReq misses 314system.cpu.l2cache.ReadSharedReq_misses::cpu.data 53 # number of ReadSharedReq misses 315system.cpu.l2cache.ReadSharedReq_misses::total 53 # number of ReadSharedReq misses 316system.cpu.l2cache.demand_misses::cpu.inst 278 # number of demand (read+write) misses 317system.cpu.l2cache.demand_misses::cpu.data 138 # number of demand (read+write) misses 318system.cpu.l2cache.demand_misses::total 416 # number of demand (read+write) misses 319system.cpu.l2cache.overall_misses::cpu.inst 278 # number of overall misses 320system.cpu.l2cache.overall_misses::cpu.data 138 # number of overall misses 321system.cpu.l2cache.overall_misses::total 416 # number of overall misses 322system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5057500 # number of ReadExReq miss cycles 323system.cpu.l2cache.ReadExReq_miss_latency::total 5057500 # number of ReadExReq miss cycles 324system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 16541500 # number of ReadCleanReq miss cycles 325system.cpu.l2cache.ReadCleanReq_miss_latency::total 16541500 # number of ReadCleanReq miss cycles 326system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 3153500 # number of ReadSharedReq miss cycles 327system.cpu.l2cache.ReadSharedReq_miss_latency::total 3153500 # number of ReadSharedReq miss cycles 328system.cpu.l2cache.demand_miss_latency::cpu.inst 16541500 # number of demand (read+write) miss cycles 329system.cpu.l2cache.demand_miss_latency::cpu.data 8211000 # number of demand (read+write) miss cycles 330system.cpu.l2cache.demand_miss_latency::total 24752500 # number of demand (read+write) miss cycles 331system.cpu.l2cache.overall_miss_latency::cpu.inst 16541500 # number of overall miss cycles 332system.cpu.l2cache.overall_miss_latency::cpu.data 8211000 # number of overall miss cycles 333system.cpu.l2cache.overall_miss_latency::total 24752500 # number of overall miss cycles 334system.cpu.l2cache.ReadExReq_accesses::cpu.data 85 # number of ReadExReq accesses(hits+misses) 335system.cpu.l2cache.ReadExReq_accesses::total 85 # number of ReadExReq accesses(hits+misses) 336system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 280 # number of ReadCleanReq accesses(hits+misses) 337system.cpu.l2cache.ReadCleanReq_accesses::total 280 # number of ReadCleanReq accesses(hits+misses) 338system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 53 # number of ReadSharedReq accesses(hits+misses) 339system.cpu.l2cache.ReadSharedReq_accesses::total 53 # number of ReadSharedReq accesses(hits+misses) 340system.cpu.l2cache.demand_accesses::cpu.inst 280 # number of demand (read+write) accesses 341system.cpu.l2cache.demand_accesses::cpu.data 138 # number of demand (read+write) accesses 342system.cpu.l2cache.demand_accesses::total 418 # number of demand (read+write) accesses 343system.cpu.l2cache.overall_accesses::cpu.inst 280 # number of overall (read+write) accesses 344system.cpu.l2cache.overall_accesses::cpu.data 138 # number of overall (read+write) accesses 345system.cpu.l2cache.overall_accesses::total 418 # number of overall (read+write) accesses 346system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 347system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 348system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.992857 # miss rate for ReadCleanReq accesses 349system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.992857 # miss rate for ReadCleanReq accesses 350system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses 351system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses 352system.cpu.l2cache.demand_miss_rate::cpu.inst 0.992857 # miss rate for demand accesses 353system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 354system.cpu.l2cache.demand_miss_rate::total 0.995215 # miss rate for demand accesses 355system.cpu.l2cache.overall_miss_rate::cpu.inst 0.992857 # miss rate for overall accesses 356system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 357system.cpu.l2cache.overall_miss_rate::total 0.995215 # miss rate for overall accesses 358system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500 # average ReadExReq miss latency 359system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500 # average ReadExReq miss latency 360system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59501.798561 # average ReadCleanReq miss latency 361system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59501.798561 # average ReadCleanReq miss latency 362system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500 # average ReadSharedReq miss latency 363system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500 # average ReadSharedReq miss latency 364system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59501.798561 # average overall miss latency 365system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500 # average overall miss latency 366system.cpu.l2cache.demand_avg_miss_latency::total 59501.201923 # average overall miss latency 367system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59501.798561 # average overall miss latency 368system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500 # average overall miss latency 369system.cpu.l2cache.overall_avg_miss_latency::total 59501.201923 # average overall miss latency 370system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 371system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 372system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 373system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 374system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 375system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 376system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 85 # number of ReadExReq MSHR misses 377system.cpu.l2cache.ReadExReq_mshr_misses::total 85 # number of ReadExReq MSHR misses 378system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 278 # number of ReadCleanReq MSHR misses 379system.cpu.l2cache.ReadCleanReq_mshr_misses::total 278 # number of ReadCleanReq MSHR misses 380system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 53 # number of ReadSharedReq MSHR misses 381system.cpu.l2cache.ReadSharedReq_mshr_misses::total 53 # number of ReadSharedReq MSHR misses 382system.cpu.l2cache.demand_mshr_misses::cpu.inst 278 # number of demand (read+write) MSHR misses 383system.cpu.l2cache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses 384system.cpu.l2cache.demand_mshr_misses::total 416 # number of demand (read+write) MSHR misses 385system.cpu.l2cache.overall_mshr_misses::cpu.inst 278 # number of overall MSHR misses 386system.cpu.l2cache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses 387system.cpu.l2cache.overall_mshr_misses::total 416 # number of overall MSHR misses 388system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4207500 # number of ReadExReq MSHR miss cycles 389system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4207500 # number of ReadExReq MSHR miss cycles 390system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 13761500 # number of ReadCleanReq MSHR miss cycles 391system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 13761500 # number of ReadCleanReq MSHR miss cycles 392system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2623500 # number of ReadSharedReq MSHR miss cycles 393system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2623500 # number of ReadSharedReq MSHR miss cycles 394system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 13761500 # number of demand (read+write) MSHR miss cycles 395system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6831000 # number of demand (read+write) MSHR miss cycles 396system.cpu.l2cache.demand_mshr_miss_latency::total 20592500 # number of demand (read+write) MSHR miss cycles 397system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 13761500 # number of overall MSHR miss cycles 398system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6831000 # number of overall MSHR miss cycles 399system.cpu.l2cache.overall_mshr_miss_latency::total 20592500 # number of overall MSHR miss cycles 400system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 401system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 402system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.992857 # mshr miss rate for ReadCleanReq accesses 403system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.992857 # mshr miss rate for ReadCleanReq accesses 404system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses 405system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses 406system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.992857 # mshr miss rate for demand accesses 407system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 408system.cpu.l2cache.demand_mshr_miss_rate::total 0.995215 # mshr miss rate for demand accesses 409system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.992857 # mshr miss rate for overall accesses 410system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 411system.cpu.l2cache.overall_mshr_miss_rate::total 0.995215 # mshr miss rate for overall accesses 412system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadExReq mshr miss latency 413system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500 # average ReadExReq mshr miss latency 414system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49501.798561 # average ReadCleanReq mshr miss latency 415system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49501.798561 # average ReadCleanReq mshr miss latency 416system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadSharedReq mshr miss latency 417system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500 # average ReadSharedReq mshr miss latency 418system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49501.798561 # average overall mshr miss latency 419system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency 420system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49501.201923 # average overall mshr miss latency 421system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49501.798561 # average overall mshr miss latency 422system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency 423system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49501.201923 # average overall mshr miss latency 424system.cpu.toL2Bus.snoop_filter.tot_requests 418 # Total number of requests made to the snoop filter. 425system.cpu.toL2Bus.snoop_filter.hit_single_requests 2 # Number of requests hitting in the snoop filter with a single holder of the requested data. 426system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 427system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 428system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 429system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 430system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 44282500 # Cumulative time (in ticks) in various power states 431system.cpu.toL2Bus.trans_dist::ReadResp 333 # Transaction distribution 432system.cpu.toL2Bus.trans_dist::ReadExReq 85 # Transaction distribution 433system.cpu.toL2Bus.trans_dist::ReadExResp 85 # Transaction distribution 434system.cpu.toL2Bus.trans_dist::ReadCleanReq 280 # Transaction distribution 435system.cpu.toL2Bus.trans_dist::ReadSharedReq 53 # Transaction distribution 436system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 560 # Packet count per connected master and slave (bytes) 437system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 276 # Packet count per connected master and slave (bytes) 438system.cpu.toL2Bus.pkt_count::total 836 # Packet count per connected master and slave (bytes) 439system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17920 # Cumulative packet size per connected master and slave (bytes) 440system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8832 # Cumulative packet size per connected master and slave (bytes) 441system.cpu.toL2Bus.pkt_size::total 26752 # Cumulative packet size per connected master and slave (bytes) 442system.cpu.toL2Bus.snoops 0 # Total snoops (count) 443system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) 444system.cpu.toL2Bus.snoop_fanout::samples 418 # Request fanout histogram 445system.cpu.toL2Bus.snoop_fanout::mean 0.004785 # Request fanout histogram 446system.cpu.toL2Bus.snoop_fanout::stdev 0.069088 # Request fanout histogram 447system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 448system.cpu.toL2Bus.snoop_fanout::0 416 99.52% 99.52% # Request fanout histogram 449system.cpu.toL2Bus.snoop_fanout::1 2 0.48% 100.00% # Request fanout histogram 450system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 451system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 452system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 453system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 454system.cpu.toL2Bus.snoop_fanout::total 418 # Request fanout histogram 455system.cpu.toL2Bus.reqLayer0.occupancy 209000 # Layer occupancy (ticks) 456system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%) 457system.cpu.toL2Bus.respLayer0.occupancy 420000 # Layer occupancy (ticks) 458system.cpu.toL2Bus.respLayer0.utilization 0.9 # Layer utilization (%) 459system.cpu.toL2Bus.respLayer1.occupancy 207000 # Layer occupancy (ticks) 460system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) 461system.membus.pwrStateResidencyTicks::UNDEFINED 44282500 # Cumulative time (in ticks) in various power states 462system.membus.trans_dist::ReadResp 331 # Transaction distribution 463system.membus.trans_dist::ReadExReq 85 # Transaction distribution 464system.membus.trans_dist::ReadExResp 85 # Transaction distribution 465system.membus.trans_dist::ReadSharedReq 331 # Transaction distribution 466system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 832 # Packet count per connected master and slave (bytes) 467system.membus.pkt_count::total 832 # Packet count per connected master and slave (bytes) 468system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26624 # Cumulative packet size per connected master and slave (bytes) 469system.membus.pkt_size::total 26624 # Cumulative packet size per connected master and slave (bytes) 470system.membus.snoops 0 # Total snoops (count) 471system.membus.snoopTraffic 0 # Total snoop traffic (bytes) 472system.membus.snoop_fanout::samples 416 # Request fanout histogram 473system.membus.snoop_fanout::mean 0 # Request fanout histogram 474system.membus.snoop_fanout::stdev 0 # Request fanout histogram 475system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 476system.membus.snoop_fanout::0 416 100.00% 100.00% # Request fanout histogram 477system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 478system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 479system.membus.snoop_fanout::min_value 0 # Request fanout histogram 480system.membus.snoop_fanout::max_value 0 # Request fanout histogram 481system.membus.snoop_fanout::total 416 # Request fanout histogram 482system.membus.reqLayer0.occupancy 416500 # Layer occupancy (ticks) 483system.membus.reqLayer0.utilization 0.9 # Layer utilization (%) 484system.membus.respLayer1.occupancy 2080000 # Layer occupancy (ticks) 485system.membus.respLayer1.utilization 4.7 # Layer utilization (%) 486 487---------- End Simulation Statistics ---------- 488