stats.txt revision 10036:80e84beef3bb
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000041 # Number of seconds simulated 4sim_ticks 41368000 # Number of ticks simulated 5final_tick 41368000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 30355 # Simulator instruction rate (inst/s) 8host_op_rate 30353 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 82811452 # Simulator tick rate (ticks/s) 10host_mem_usage 236788 # Number of bytes of host memory used 11host_seconds 0.50 # Real time elapsed on the host 12sim_insts 15162 # Number of instructions simulated 13sim_ops 15162 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 17792 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 8832 # Number of bytes read from this memory 18system.physmem.bytes_read::total 26624 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 17792 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 17792 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 278 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 416 # Number of read requests responded to by this memory 24system.physmem.bw_read::cpu.inst 430090892 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 213498356 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 643589248 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 430090892 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 430090892 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 430090892 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 213498356 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 643589248 # Total bandwidth to/from this memory (bytes/s) 32system.membus.throughput 643589248 # Throughput (bytes/s) 33system.membus.trans_dist::ReadReq 331 # Transaction distribution 34system.membus.trans_dist::ReadResp 331 # Transaction distribution 35system.membus.trans_dist::ReadExReq 85 # Transaction distribution 36system.membus.trans_dist::ReadExResp 85 # Transaction distribution 37system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 832 # Packet count per connected master and slave (bytes) 38system.membus.pkt_count::total 832 # Packet count per connected master and slave (bytes) 39system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26624 # Cumulative packet size per connected master and slave (bytes) 40system.membus.tot_pkt_size::total 26624 # Cumulative packet size per connected master and slave (bytes) 41system.membus.data_through_bus 26624 # Total data (bytes) 42system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 43system.membus.reqLayer0.occupancy 416000 # Layer occupancy (ticks) 44system.membus.reqLayer0.utilization 1.0 # Layer utilization (%) 45system.membus.respLayer1.occupancy 3744000 # Layer occupancy (ticks) 46system.membus.respLayer1.utilization 9.1 # Layer utilization (%) 47system.cpu_clk_domain.clock 500 # Clock period in ticks 48system.cpu.workload.num_syscalls 18 # Number of system calls 49system.cpu.numCycles 82736 # number of cpu cycles simulated 50system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 51system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 52system.cpu.committedInsts 15162 # Number of instructions committed 53system.cpu.committedOps 15162 # Number of ops (including micro ops) committed 54system.cpu.num_int_alu_accesses 12219 # Number of integer alu accesses 55system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses 56system.cpu.num_func_calls 385 # number of times a function call or return occured 57system.cpu.num_conditional_control_insts 2434 # number of instructions that are conditional controls 58system.cpu.num_int_insts 12219 # number of integer instructions 59system.cpu.num_fp_insts 0 # number of float instructions 60system.cpu.num_int_register_reads 29037 # number of times the integer registers were read 61system.cpu.num_int_register_writes 13818 # number of times the integer registers were written 62system.cpu.num_fp_register_reads 0 # number of times the floating registers were read 63system.cpu.num_fp_register_writes 0 # number of times the floating registers were written 64system.cpu.num_mem_refs 3683 # number of memory refs 65system.cpu.num_load_insts 2231 # Number of load instructions 66system.cpu.num_store_insts 1452 # Number of store instructions 67system.cpu.num_idle_cycles 0 # Number of idle cycles 68system.cpu.num_busy_cycles 82736 # Number of busy cycles 69system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 70system.cpu.idle_fraction 0 # Percentage of idle cycles 71system.cpu.icache.tags.replacements 0 # number of replacements 72system.cpu.icache.tags.tagsinuse 153.782734 # Cycle average of tags in use 73system.cpu.icache.tags.total_refs 14928 # Total number of references to valid blocks. 74system.cpu.icache.tags.sampled_refs 280 # Sample count of references to valid blocks. 75system.cpu.icache.tags.avg_refs 53.314286 # Average number of references to valid blocks. 76system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 77system.cpu.icache.tags.occ_blocks::cpu.inst 153.782734 # Average occupied blocks per requestor 78system.cpu.icache.tags.occ_percent::cpu.inst 0.075089 # Average percentage of cache occupancy 79system.cpu.icache.tags.occ_percent::total 0.075089 # Average percentage of cache occupancy 80system.cpu.icache.tags.occ_task_id_blocks::1024 280 # Occupied blocks per task id 81system.cpu.icache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id 82system.cpu.icache.tags.age_task_id_blocks_1024::1 234 # Occupied blocks per task id 83system.cpu.icache.tags.occ_task_id_percent::1024 0.136719 # Percentage of cache occupancy per task id 84system.cpu.icache.tags.tag_accesses 30696 # Number of tag accesses 85system.cpu.icache.tags.data_accesses 30696 # Number of data accesses 86system.cpu.icache.ReadReq_hits::cpu.inst 14928 # number of ReadReq hits 87system.cpu.icache.ReadReq_hits::total 14928 # number of ReadReq hits 88system.cpu.icache.demand_hits::cpu.inst 14928 # number of demand (read+write) hits 89system.cpu.icache.demand_hits::total 14928 # number of demand (read+write) hits 90system.cpu.icache.overall_hits::cpu.inst 14928 # number of overall hits 91system.cpu.icache.overall_hits::total 14928 # number of overall hits 92system.cpu.icache.ReadReq_misses::cpu.inst 280 # number of ReadReq misses 93system.cpu.icache.ReadReq_misses::total 280 # number of ReadReq misses 94system.cpu.icache.demand_misses::cpu.inst 280 # number of demand (read+write) misses 95system.cpu.icache.demand_misses::total 280 # number of demand (read+write) misses 96system.cpu.icache.overall_misses::cpu.inst 280 # number of overall misses 97system.cpu.icache.overall_misses::total 280 # number of overall misses 98system.cpu.icache.ReadReq_miss_latency::cpu.inst 15316000 # number of ReadReq miss cycles 99system.cpu.icache.ReadReq_miss_latency::total 15316000 # number of ReadReq miss cycles 100system.cpu.icache.demand_miss_latency::cpu.inst 15316000 # number of demand (read+write) miss cycles 101system.cpu.icache.demand_miss_latency::total 15316000 # number of demand (read+write) miss cycles 102system.cpu.icache.overall_miss_latency::cpu.inst 15316000 # number of overall miss cycles 103system.cpu.icache.overall_miss_latency::total 15316000 # number of overall miss cycles 104system.cpu.icache.ReadReq_accesses::cpu.inst 15208 # number of ReadReq accesses(hits+misses) 105system.cpu.icache.ReadReq_accesses::total 15208 # number of ReadReq accesses(hits+misses) 106system.cpu.icache.demand_accesses::cpu.inst 15208 # number of demand (read+write) accesses 107system.cpu.icache.demand_accesses::total 15208 # number of demand (read+write) accesses 108system.cpu.icache.overall_accesses::cpu.inst 15208 # number of overall (read+write) accesses 109system.cpu.icache.overall_accesses::total 15208 # number of overall (read+write) accesses 110system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.018411 # miss rate for ReadReq accesses 111system.cpu.icache.ReadReq_miss_rate::total 0.018411 # miss rate for ReadReq accesses 112system.cpu.icache.demand_miss_rate::cpu.inst 0.018411 # miss rate for demand accesses 113system.cpu.icache.demand_miss_rate::total 0.018411 # miss rate for demand accesses 114system.cpu.icache.overall_miss_rate::cpu.inst 0.018411 # miss rate for overall accesses 115system.cpu.icache.overall_miss_rate::total 0.018411 # miss rate for overall accesses 116system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54700 # average ReadReq miss latency 117system.cpu.icache.ReadReq_avg_miss_latency::total 54700 # average ReadReq miss latency 118system.cpu.icache.demand_avg_miss_latency::cpu.inst 54700 # average overall miss latency 119system.cpu.icache.demand_avg_miss_latency::total 54700 # average overall miss latency 120system.cpu.icache.overall_avg_miss_latency::cpu.inst 54700 # average overall miss latency 121system.cpu.icache.overall_avg_miss_latency::total 54700 # average overall miss latency 122system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 123system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 124system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 125system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 126system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 127system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 128system.cpu.icache.fast_writes 0 # number of fast writes performed 129system.cpu.icache.cache_copies 0 # number of cache copies performed 130system.cpu.icache.ReadReq_mshr_misses::cpu.inst 280 # number of ReadReq MSHR misses 131system.cpu.icache.ReadReq_mshr_misses::total 280 # number of ReadReq MSHR misses 132system.cpu.icache.demand_mshr_misses::cpu.inst 280 # number of demand (read+write) MSHR misses 133system.cpu.icache.demand_mshr_misses::total 280 # number of demand (read+write) MSHR misses 134system.cpu.icache.overall_mshr_misses::cpu.inst 280 # number of overall MSHR misses 135system.cpu.icache.overall_mshr_misses::total 280 # number of overall MSHR misses 136system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14756000 # number of ReadReq MSHR miss cycles 137system.cpu.icache.ReadReq_mshr_miss_latency::total 14756000 # number of ReadReq MSHR miss cycles 138system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14756000 # number of demand (read+write) MSHR miss cycles 139system.cpu.icache.demand_mshr_miss_latency::total 14756000 # number of demand (read+write) MSHR miss cycles 140system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14756000 # number of overall MSHR miss cycles 141system.cpu.icache.overall_mshr_miss_latency::total 14756000 # number of overall MSHR miss cycles 142system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.018411 # mshr miss rate for ReadReq accesses 143system.cpu.icache.ReadReq_mshr_miss_rate::total 0.018411 # mshr miss rate for ReadReq accesses 144system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.018411 # mshr miss rate for demand accesses 145system.cpu.icache.demand_mshr_miss_rate::total 0.018411 # mshr miss rate for demand accesses 146system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.018411 # mshr miss rate for overall accesses 147system.cpu.icache.overall_mshr_miss_rate::total 0.018411 # mshr miss rate for overall accesses 148system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52700 # average ReadReq mshr miss latency 149system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52700 # average ReadReq mshr miss latency 150system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52700 # average overall mshr miss latency 151system.cpu.icache.demand_avg_mshr_miss_latency::total 52700 # average overall mshr miss latency 152system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52700 # average overall mshr miss latency 153system.cpu.icache.overall_avg_mshr_miss_latency::total 52700 # average overall mshr miss latency 154system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 155system.cpu.l2cache.tags.replacements 0 # number of replacements 156system.cpu.l2cache.tags.tagsinuse 184.632038 # Cycle average of tags in use 157system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. 158system.cpu.l2cache.tags.sampled_refs 331 # Sample count of references to valid blocks. 159system.cpu.l2cache.tags.avg_refs 0.006042 # Average number of references to valid blocks. 160system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 161system.cpu.l2cache.tags.occ_blocks::cpu.inst 153.110886 # Average occupied blocks per requestor 162system.cpu.l2cache.tags.occ_blocks::cpu.data 31.521152 # Average occupied blocks per requestor 163system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004673 # Average percentage of cache occupancy 164system.cpu.l2cache.tags.occ_percent::cpu.data 0.000962 # Average percentage of cache occupancy 165system.cpu.l2cache.tags.occ_percent::total 0.005635 # Average percentage of cache occupancy 166system.cpu.l2cache.tags.occ_task_id_blocks::1024 331 # Occupied blocks per task id 167system.cpu.l2cache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id 168system.cpu.l2cache.tags.age_task_id_blocks_1024::1 275 # Occupied blocks per task id 169system.cpu.l2cache.tags.occ_task_id_percent::1024 0.010101 # Percentage of cache occupancy per task id 170system.cpu.l2cache.tags.tag_accesses 3760 # Number of tag accesses 171system.cpu.l2cache.tags.data_accesses 3760 # Number of data accesses 172system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits 173system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits 174system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits 175system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits 176system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits 177system.cpu.l2cache.overall_hits::total 2 # number of overall hits 178system.cpu.l2cache.ReadReq_misses::cpu.inst 278 # number of ReadReq misses 179system.cpu.l2cache.ReadReq_misses::cpu.data 53 # number of ReadReq misses 180system.cpu.l2cache.ReadReq_misses::total 331 # number of ReadReq misses 181system.cpu.l2cache.ReadExReq_misses::cpu.data 85 # number of ReadExReq misses 182system.cpu.l2cache.ReadExReq_misses::total 85 # number of ReadExReq misses 183system.cpu.l2cache.demand_misses::cpu.inst 278 # number of demand (read+write) misses 184system.cpu.l2cache.demand_misses::cpu.data 138 # number of demand (read+write) misses 185system.cpu.l2cache.demand_misses::total 416 # number of demand (read+write) misses 186system.cpu.l2cache.overall_misses::cpu.inst 278 # number of overall misses 187system.cpu.l2cache.overall_misses::cpu.data 138 # number of overall misses 188system.cpu.l2cache.overall_misses::total 416 # number of overall misses 189system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14456000 # number of ReadReq miss cycles 190system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2756000 # number of ReadReq miss cycles 191system.cpu.l2cache.ReadReq_miss_latency::total 17212000 # number of ReadReq miss cycles 192system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4420000 # number of ReadExReq miss cycles 193system.cpu.l2cache.ReadExReq_miss_latency::total 4420000 # number of ReadExReq miss cycles 194system.cpu.l2cache.demand_miss_latency::cpu.inst 14456000 # number of demand (read+write) miss cycles 195system.cpu.l2cache.demand_miss_latency::cpu.data 7176000 # number of demand (read+write) miss cycles 196system.cpu.l2cache.demand_miss_latency::total 21632000 # number of demand (read+write) miss cycles 197system.cpu.l2cache.overall_miss_latency::cpu.inst 14456000 # number of overall miss cycles 198system.cpu.l2cache.overall_miss_latency::cpu.data 7176000 # number of overall miss cycles 199system.cpu.l2cache.overall_miss_latency::total 21632000 # number of overall miss cycles 200system.cpu.l2cache.ReadReq_accesses::cpu.inst 280 # number of ReadReq accesses(hits+misses) 201system.cpu.l2cache.ReadReq_accesses::cpu.data 53 # number of ReadReq accesses(hits+misses) 202system.cpu.l2cache.ReadReq_accesses::total 333 # number of ReadReq accesses(hits+misses) 203system.cpu.l2cache.ReadExReq_accesses::cpu.data 85 # number of ReadExReq accesses(hits+misses) 204system.cpu.l2cache.ReadExReq_accesses::total 85 # number of ReadExReq accesses(hits+misses) 205system.cpu.l2cache.demand_accesses::cpu.inst 280 # number of demand (read+write) accesses 206system.cpu.l2cache.demand_accesses::cpu.data 138 # number of demand (read+write) accesses 207system.cpu.l2cache.demand_accesses::total 418 # number of demand (read+write) accesses 208system.cpu.l2cache.overall_accesses::cpu.inst 280 # number of overall (read+write) accesses 209system.cpu.l2cache.overall_accesses::cpu.data 138 # number of overall (read+write) accesses 210system.cpu.l2cache.overall_accesses::total 418 # number of overall (read+write) accesses 211system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.992857 # miss rate for ReadReq accesses 212system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses 213system.cpu.l2cache.ReadReq_miss_rate::total 0.993994 # miss rate for ReadReq accesses 214system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 215system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 216system.cpu.l2cache.demand_miss_rate::cpu.inst 0.992857 # miss rate for demand accesses 217system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 218system.cpu.l2cache.demand_miss_rate::total 0.995215 # miss rate for demand accesses 219system.cpu.l2cache.overall_miss_rate::cpu.inst 0.992857 # miss rate for overall accesses 220system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 221system.cpu.l2cache.overall_miss_rate::total 0.995215 # miss rate for overall accesses 222system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency 223system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency 224system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency 225system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency 226system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency 227system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency 228system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency 229system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency 230system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency 231system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency 232system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency 233system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 234system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 235system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 236system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 237system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 238system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 239system.cpu.l2cache.fast_writes 0 # number of fast writes performed 240system.cpu.l2cache.cache_copies 0 # number of cache copies performed 241system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 278 # number of ReadReq MSHR misses 242system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 53 # number of ReadReq MSHR misses 243system.cpu.l2cache.ReadReq_mshr_misses::total 331 # number of ReadReq MSHR misses 244system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 85 # number of ReadExReq MSHR misses 245system.cpu.l2cache.ReadExReq_mshr_misses::total 85 # number of ReadExReq MSHR misses 246system.cpu.l2cache.demand_mshr_misses::cpu.inst 278 # number of demand (read+write) MSHR misses 247system.cpu.l2cache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses 248system.cpu.l2cache.demand_mshr_misses::total 416 # number of demand (read+write) MSHR misses 249system.cpu.l2cache.overall_mshr_misses::cpu.inst 278 # number of overall MSHR misses 250system.cpu.l2cache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses 251system.cpu.l2cache.overall_mshr_misses::total 416 # number of overall MSHR misses 252system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11120000 # number of ReadReq MSHR miss cycles 253system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2120000 # number of ReadReq MSHR miss cycles 254system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13240000 # number of ReadReq MSHR miss cycles 255system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3400000 # number of ReadExReq MSHR miss cycles 256system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3400000 # number of ReadExReq MSHR miss cycles 257system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11120000 # number of demand (read+write) MSHR miss cycles 258system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5520000 # number of demand (read+write) MSHR miss cycles 259system.cpu.l2cache.demand_mshr_miss_latency::total 16640000 # number of demand (read+write) MSHR miss cycles 260system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11120000 # number of overall MSHR miss cycles 261system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5520000 # number of overall MSHR miss cycles 262system.cpu.l2cache.overall_mshr_miss_latency::total 16640000 # number of overall MSHR miss cycles 263system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.992857 # mshr miss rate for ReadReq accesses 264system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses 265system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.993994 # mshr miss rate for ReadReq accesses 266system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 267system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 268system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.992857 # mshr miss rate for demand accesses 269system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 270system.cpu.l2cache.demand_mshr_miss_rate::total 0.995215 # mshr miss rate for demand accesses 271system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.992857 # mshr miss rate for overall accesses 272system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 273system.cpu.l2cache.overall_mshr_miss_rate::total 0.995215 # mshr miss rate for overall accesses 274system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency 275system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency 276system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency 277system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency 278system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency 279system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency 280system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency 281system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency 282system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency 283system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency 284system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency 285system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 286system.cpu.dcache.tags.replacements 0 # number of replacements 287system.cpu.dcache.tags.tagsinuse 97.994344 # Cycle average of tags in use 288system.cpu.dcache.tags.total_refs 3535 # Total number of references to valid blocks. 289system.cpu.dcache.tags.sampled_refs 138 # Sample count of references to valid blocks. 290system.cpu.dcache.tags.avg_refs 25.615942 # Average number of references to valid blocks. 291system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 292system.cpu.dcache.tags.occ_blocks::cpu.data 97.994344 # Average occupied blocks per requestor 293system.cpu.dcache.tags.occ_percent::cpu.data 0.023924 # Average percentage of cache occupancy 294system.cpu.dcache.tags.occ_percent::total 0.023924 # Average percentage of cache occupancy 295system.cpu.dcache.tags.occ_task_id_blocks::1024 138 # Occupied blocks per task id 296system.cpu.dcache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id 297system.cpu.dcache.tags.age_task_id_blocks_1024::1 127 # Occupied blocks per task id 298system.cpu.dcache.tags.occ_task_id_percent::1024 0.033691 # Percentage of cache occupancy per task id 299system.cpu.dcache.tags.tag_accesses 7484 # Number of tag accesses 300system.cpu.dcache.tags.data_accesses 7484 # Number of data accesses 301system.cpu.dcache.ReadReq_hits::cpu.data 2172 # number of ReadReq hits 302system.cpu.dcache.ReadReq_hits::total 2172 # number of ReadReq hits 303system.cpu.dcache.WriteReq_hits::cpu.data 1357 # number of WriteReq hits 304system.cpu.dcache.WriteReq_hits::total 1357 # number of WriteReq hits 305system.cpu.dcache.SwapReq_hits::cpu.data 6 # number of SwapReq hits 306system.cpu.dcache.SwapReq_hits::total 6 # number of SwapReq hits 307system.cpu.dcache.demand_hits::cpu.data 3529 # number of demand (read+write) hits 308system.cpu.dcache.demand_hits::total 3529 # number of demand (read+write) hits 309system.cpu.dcache.overall_hits::cpu.data 3529 # number of overall hits 310system.cpu.dcache.overall_hits::total 3529 # number of overall hits 311system.cpu.dcache.ReadReq_misses::cpu.data 53 # number of ReadReq misses 312system.cpu.dcache.ReadReq_misses::total 53 # number of ReadReq misses 313system.cpu.dcache.WriteReq_misses::cpu.data 85 # number of WriteReq misses 314system.cpu.dcache.WriteReq_misses::total 85 # number of WriteReq misses 315system.cpu.dcache.demand_misses::cpu.data 138 # number of demand (read+write) misses 316system.cpu.dcache.demand_misses::total 138 # number of demand (read+write) misses 317system.cpu.dcache.overall_misses::cpu.data 138 # number of overall misses 318system.cpu.dcache.overall_misses::total 138 # number of overall misses 319system.cpu.dcache.ReadReq_miss_latency::cpu.data 2915000 # number of ReadReq miss cycles 320system.cpu.dcache.ReadReq_miss_latency::total 2915000 # number of ReadReq miss cycles 321system.cpu.dcache.WriteReq_miss_latency::cpu.data 4675000 # number of WriteReq miss cycles 322system.cpu.dcache.WriteReq_miss_latency::total 4675000 # number of WriteReq miss cycles 323system.cpu.dcache.demand_miss_latency::cpu.data 7590000 # number of demand (read+write) miss cycles 324system.cpu.dcache.demand_miss_latency::total 7590000 # number of demand (read+write) miss cycles 325system.cpu.dcache.overall_miss_latency::cpu.data 7590000 # number of overall miss cycles 326system.cpu.dcache.overall_miss_latency::total 7590000 # number of overall miss cycles 327system.cpu.dcache.ReadReq_accesses::cpu.data 2225 # number of ReadReq accesses(hits+misses) 328system.cpu.dcache.ReadReq_accesses::total 2225 # number of ReadReq accesses(hits+misses) 329system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses) 330system.cpu.dcache.WriteReq_accesses::total 1442 # number of WriteReq accesses(hits+misses) 331system.cpu.dcache.SwapReq_accesses::cpu.data 6 # number of SwapReq accesses(hits+misses) 332system.cpu.dcache.SwapReq_accesses::total 6 # number of SwapReq accesses(hits+misses) 333system.cpu.dcache.demand_accesses::cpu.data 3667 # number of demand (read+write) accesses 334system.cpu.dcache.demand_accesses::total 3667 # number of demand (read+write) accesses 335system.cpu.dcache.overall_accesses::cpu.data 3667 # number of overall (read+write) accesses 336system.cpu.dcache.overall_accesses::total 3667 # number of overall (read+write) accesses 337system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.023820 # miss rate for ReadReq accesses 338system.cpu.dcache.ReadReq_miss_rate::total 0.023820 # miss rate for ReadReq accesses 339system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.058946 # miss rate for WriteReq accesses 340system.cpu.dcache.WriteReq_miss_rate::total 0.058946 # miss rate for WriteReq accesses 341system.cpu.dcache.demand_miss_rate::cpu.data 0.037633 # miss rate for demand accesses 342system.cpu.dcache.demand_miss_rate::total 0.037633 # miss rate for demand accesses 343system.cpu.dcache.overall_miss_rate::cpu.data 0.037633 # miss rate for overall accesses 344system.cpu.dcache.overall_miss_rate::total 0.037633 # miss rate for overall accesses 345system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency 346system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency 347system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency 348system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency 349system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency 350system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency 351system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency 352system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency 353system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 354system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 355system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 356system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 357system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 358system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 359system.cpu.dcache.fast_writes 0 # number of fast writes performed 360system.cpu.dcache.cache_copies 0 # number of cache copies performed 361system.cpu.dcache.ReadReq_mshr_misses::cpu.data 53 # number of ReadReq MSHR misses 362system.cpu.dcache.ReadReq_mshr_misses::total 53 # number of ReadReq MSHR misses 363system.cpu.dcache.WriteReq_mshr_misses::cpu.data 85 # number of WriteReq MSHR misses 364system.cpu.dcache.WriteReq_mshr_misses::total 85 # number of WriteReq MSHR misses 365system.cpu.dcache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses 366system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses 367system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses 368system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses 369system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2809000 # number of ReadReq MSHR miss cycles 370system.cpu.dcache.ReadReq_mshr_miss_latency::total 2809000 # number of ReadReq MSHR miss cycles 371system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4505000 # number of WriteReq MSHR miss cycles 372system.cpu.dcache.WriteReq_mshr_miss_latency::total 4505000 # number of WriteReq MSHR miss cycles 373system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7314000 # number of demand (read+write) MSHR miss cycles 374system.cpu.dcache.demand_mshr_miss_latency::total 7314000 # number of demand (read+write) MSHR miss cycles 375system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7314000 # number of overall MSHR miss cycles 376system.cpu.dcache.overall_mshr_miss_latency::total 7314000 # number of overall MSHR miss cycles 377system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.023820 # mshr miss rate for ReadReq accesses 378system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.023820 # mshr miss rate for ReadReq accesses 379system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.058946 # mshr miss rate for WriteReq accesses 380system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.058946 # mshr miss rate for WriteReq accesses 381system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.037633 # mshr miss rate for demand accesses 382system.cpu.dcache.demand_mshr_miss_rate::total 0.037633 # mshr miss rate for demand accesses 383system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.037633 # mshr miss rate for overall accesses 384system.cpu.dcache.overall_mshr_miss_rate::total 0.037633 # mshr miss rate for overall accesses 385system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency 386system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency 387system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency 388system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency 389system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency 390system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency 391system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency 392system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency 393system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 394system.cpu.toL2Bus.throughput 646683427 # Throughput (bytes/s) 395system.cpu.toL2Bus.trans_dist::ReadReq 333 # Transaction distribution 396system.cpu.toL2Bus.trans_dist::ReadResp 333 # Transaction distribution 397system.cpu.toL2Bus.trans_dist::ReadExReq 85 # Transaction distribution 398system.cpu.toL2Bus.trans_dist::ReadExResp 85 # Transaction distribution 399system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 560 # Packet count per connected master and slave (bytes) 400system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 276 # Packet count per connected master and slave (bytes) 401system.cpu.toL2Bus.pkt_count::total 836 # Packet count per connected master and slave (bytes) 402system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17920 # Cumulative packet size per connected master and slave (bytes) 403system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8832 # Cumulative packet size per connected master and slave (bytes) 404system.cpu.toL2Bus.tot_pkt_size::total 26752 # Cumulative packet size per connected master and slave (bytes) 405system.cpu.toL2Bus.data_through_bus 26752 # Total data (bytes) 406system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) 407system.cpu.toL2Bus.reqLayer0.occupancy 209000 # Layer occupancy (ticks) 408system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%) 409system.cpu.toL2Bus.respLayer0.occupancy 420000 # Layer occupancy (ticks) 410system.cpu.toL2Bus.respLayer0.utilization 1.0 # Layer utilization (%) 411system.cpu.toL2Bus.respLayer1.occupancy 207000 # Layer occupancy (ticks) 412system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) 413 414---------- End Simulation Statistics ---------- 415