stats.txt revision 8802:ef66a9083bc4
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000018 # Number of seconds simulated 4sim_ticks 18114000 # Number of ticks simulated 5final_tick 18114000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 74785 # Simulator instruction rate (inst/s) 8host_tick_rate 93746300 # Simulator tick rate (ticks/s) 9host_mem_usage 213808 # Number of bytes of host memory used 10host_seconds 0.19 # Real time elapsed on the host 11sim_insts 14449 # Number of instructions simulated 12system.physmem.bytes_read 30464 # Number of bytes read from this memory 13system.physmem.bytes_inst_read 21120 # Number of instructions bytes read from this memory 14system.physmem.bytes_written 0 # Number of bytes written to this memory 15system.physmem.num_reads 476 # Number of read requests responded to by this memory 16system.physmem.num_writes 0 # Number of write requests responded to by this memory 17system.physmem.num_other 0 # Number of other requests responded to by this memory 18system.physmem.bw_read 1681793088 # Total read bandwidth from this memory (bytes/s) 19system.physmem.bw_inst_read 1165948990 # Instruction read bandwidth from this memory (bytes/s) 20system.physmem.bw_total 1681793088 # Total bandwidth to/from this memory (bytes/s) 21system.cpu.workload.num_syscalls 18 # Number of system calls 22system.cpu.numCycles 36229 # number of cpu cycles simulated 23system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 24system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 25system.cpu.BPredUnit.lookups 5641 # Number of BP lookups 26system.cpu.BPredUnit.condPredicted 3757 # Number of conditional branches predicted 27system.cpu.BPredUnit.condIncorrect 847 # Number of conditional branches incorrect 28system.cpu.BPredUnit.BTBLookups 5015 # Number of BTB lookups 29system.cpu.BPredUnit.BTBHits 2638 # Number of BTB hits 30system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 31system.cpu.BPredUnit.usedRAS 357 # Number of times the RAS was used to get a target. 32system.cpu.BPredUnit.RASInCorrect 168 # Number of incorrect RAS predictions. 33system.cpu.fetch.icacheStallCycles 10704 # Number of cycles fetch is stalled on an Icache miss 34system.cpu.fetch.Insts 25822 # Number of instructions fetch has processed 35system.cpu.fetch.Branches 5641 # Number of branches that fetch encountered 36system.cpu.fetch.predictedBranches 2995 # Number of branches that fetch has predicted taken 37system.cpu.fetch.Cycles 8176 # Number of cycles fetch has run and was not squashing or blocked 38system.cpu.fetch.SquashCycles 2307 # Number of cycles fetch has spent squashing 39system.cpu.fetch.BlockedCycles 6717 # Number of cycles fetch has spent blocked 40system.cpu.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 41system.cpu.fetch.PendingTrapStallCycles 641 # Number of stall cycles due to pending traps 42system.cpu.fetch.CacheLines 4608 # Number of cache lines fetched 43system.cpu.fetch.IcacheSquashes 368 # Number of outstanding Icache misses that were squashed 44system.cpu.fetch.rateDist::samples 27606 # Number of instructions fetched each cycle (Total) 45system.cpu.fetch.rateDist::mean 0.935376 # Number of instructions fetched each cycle (Total) 46system.cpu.fetch.rateDist::stdev 2.035144 # Number of instructions fetched each cycle (Total) 47system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 48system.cpu.fetch.rateDist::0 19430 70.38% 70.38% # Number of instructions fetched each cycle (Total) 49system.cpu.fetch.rateDist::1 4056 14.69% 85.08% # Number of instructions fetched each cycle (Total) 50system.cpu.fetch.rateDist::2 538 1.95% 87.02% # Number of instructions fetched each cycle (Total) 51system.cpu.fetch.rateDist::3 472 1.71% 88.73% # Number of instructions fetched each cycle (Total) 52system.cpu.fetch.rateDist::4 725 2.63% 91.36% # Number of instructions fetched each cycle (Total) 53system.cpu.fetch.rateDist::5 639 2.31% 93.68% # Number of instructions fetched each cycle (Total) 54system.cpu.fetch.rateDist::6 274 0.99% 94.67% # Number of instructions fetched each cycle (Total) 55system.cpu.fetch.rateDist::7 241 0.87% 95.54% # Number of instructions fetched each cycle (Total) 56system.cpu.fetch.rateDist::8 1231 4.46% 100.00% # Number of instructions fetched each cycle (Total) 57system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 58system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 59system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 60system.cpu.fetch.rateDist::total 27606 # Number of instructions fetched each cycle (Total) 61system.cpu.fetch.branchRate 0.155704 # Number of branch fetches per cycle 62system.cpu.fetch.rate 0.712744 # Number of inst fetches per cycle 63system.cpu.decode.IdleCycles 11125 # Number of cycles decode is idle 64system.cpu.decode.BlockedCycles 7403 # Number of cycles decode is blocked 65system.cpu.decode.RunCycles 7524 # Number of cycles decode is running 66system.cpu.decode.UnblockCycles 190 # Number of cycles decode is unblocking 67system.cpu.decode.SquashCycles 1364 # Number of cycles decode is squashing 68system.cpu.decode.DecodedInsts 24270 # Number of instructions handled by decode 69system.cpu.rename.SquashCycles 1364 # Number of cycles rename is squashing 70system.cpu.rename.IdleCycles 11622 # Number of cycles rename is idle 71system.cpu.rename.BlockCycles 225 # Number of cycles rename is blocking 72system.cpu.rename.serializeStallCycles 6687 # count of cycles rename stalled for serializing inst 73system.cpu.rename.RunCycles 7253 # Number of cycles rename is running 74system.cpu.rename.UnblockCycles 455 # Number of cycles rename is unblocking 75system.cpu.rename.RenamedInsts 22509 # Number of instructions processed by rename 76system.cpu.rename.IQFullEvents 3 # Number of times rename has blocked due to IQ full 77system.cpu.rename.LSQFullEvents 135 # Number of times rename has blocked due to LSQ full 78system.cpu.rename.RenamedOperands 20189 # Number of destination operands rename has renamed 79system.cpu.rename.RenameLookups 41765 # Number of register rename lookups that rename has made 80system.cpu.rename.int_rename_lookups 41765 # Number of integer rename lookups 81system.cpu.rename.CommittedMaps 13832 # Number of HB maps that are committed 82system.cpu.rename.UndoneMaps 6357 # Number of HB maps that are undone due to squashing 83system.cpu.rename.serializingInsts 639 # count of serializing insts renamed 84system.cpu.rename.tempSerializingInsts 633 # count of temporary serializing insts renamed 85system.cpu.rename.skidInsts 2443 # count of insts added to the skid buffer 86system.cpu.memDep0.insertedLoads 3114 # Number of loads inserted to the mem dependence unit. 87system.cpu.memDep0.insertedStores 1976 # Number of stores inserted to the mem dependence unit. 88system.cpu.memDep0.conflictingLoads 4 # Number of conflicting loads. 89system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. 90system.cpu.iq.iqInstsAdded 19328 # Number of instructions added to the IQ (excludes non-spec) 91system.cpu.iq.iqNonSpecInstsAdded 615 # Number of non-speculative instructions added to the IQ 92system.cpu.iq.iqInstsIssued 18581 # Number of instructions issued 93system.cpu.iq.iqSquashedInstsIssued 81 # Number of squashed instructions issued 94system.cpu.iq.iqSquashedInstsExamined 4856 # Number of squashed instructions iterated over during squash; mainly for profiling 95system.cpu.iq.iqSquashedOperandsExamined 3975 # Number of squashed operands that are examined and possibly removed from graph 96system.cpu.iq.iqSquashedNonSpecRemoved 140 # Number of squashed non-spec instructions that were removed 97system.cpu.iq.issued_per_cycle::samples 27606 # Number of insts issued each cycle 98system.cpu.iq.issued_per_cycle::mean 0.673078 # Number of insts issued each cycle 99system.cpu.iq.issued_per_cycle::stdev 1.254278 # Number of insts issued each cycle 100system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 101system.cpu.iq.issued_per_cycle::0 19117 69.25% 69.25% # Number of insts issued each cycle 102system.cpu.iq.issued_per_cycle::1 3446 12.48% 81.73% # Number of insts issued each cycle 103system.cpu.iq.issued_per_cycle::2 2219 8.04% 89.77% # Number of insts issued each cycle 104system.cpu.iq.issued_per_cycle::3 1536 5.56% 95.33% # Number of insts issued each cycle 105system.cpu.iq.issued_per_cycle::4 657 2.38% 97.71% # Number of insts issued each cycle 106system.cpu.iq.issued_per_cycle::5 384 1.39% 99.11% # Number of insts issued each cycle 107system.cpu.iq.issued_per_cycle::6 197 0.71% 99.82% # Number of insts issued each cycle 108system.cpu.iq.issued_per_cycle::7 41 0.15% 99.97% # Number of insts issued each cycle 109system.cpu.iq.issued_per_cycle::8 9 0.03% 100.00% # Number of insts issued each cycle 110system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 111system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 112system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 113system.cpu.iq.issued_per_cycle::total 27606 # Number of insts issued each cycle 114system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 115system.cpu.iq.fu_full::IntAlu 35 25.18% 25.18% # attempts to use FU when none available 116system.cpu.iq.fu_full::IntMult 0 0.00% 25.18% # attempts to use FU when none available 117system.cpu.iq.fu_full::IntDiv 0 0.00% 25.18% # attempts to use FU when none available 118system.cpu.iq.fu_full::FloatAdd 0 0.00% 25.18% # attempts to use FU when none available 119system.cpu.iq.fu_full::FloatCmp 0 0.00% 25.18% # attempts to use FU when none available 120system.cpu.iq.fu_full::FloatCvt 0 0.00% 25.18% # attempts to use FU when none available 121system.cpu.iq.fu_full::FloatMult 0 0.00% 25.18% # attempts to use FU when none available 122system.cpu.iq.fu_full::FloatDiv 0 0.00% 25.18% # attempts to use FU when none available 123system.cpu.iq.fu_full::FloatSqrt 0 0.00% 25.18% # attempts to use FU when none available 124system.cpu.iq.fu_full::SimdAdd 0 0.00% 25.18% # attempts to use FU when none available 125system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 25.18% # attempts to use FU when none available 126system.cpu.iq.fu_full::SimdAlu 0 0.00% 25.18% # attempts to use FU when none available 127system.cpu.iq.fu_full::SimdCmp 0 0.00% 25.18% # attempts to use FU when none available 128system.cpu.iq.fu_full::SimdCvt 0 0.00% 25.18% # attempts to use FU when none available 129system.cpu.iq.fu_full::SimdMisc 0 0.00% 25.18% # attempts to use FU when none available 130system.cpu.iq.fu_full::SimdMult 0 0.00% 25.18% # attempts to use FU when none available 131system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 25.18% # attempts to use FU when none available 132system.cpu.iq.fu_full::SimdShift 0 0.00% 25.18% # attempts to use FU when none available 133system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 25.18% # attempts to use FU when none available 134system.cpu.iq.fu_full::SimdSqrt 0 0.00% 25.18% # attempts to use FU when none available 135system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 25.18% # attempts to use FU when none available 136system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 25.18% # attempts to use FU when none available 137system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 25.18% # attempts to use FU when none available 138system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 25.18% # attempts to use FU when none available 139system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 25.18% # attempts to use FU when none available 140system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 25.18% # attempts to use FU when none available 141system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 25.18% # attempts to use FU when none available 142system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.18% # attempts to use FU when none available 143system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 25.18% # attempts to use FU when none available 144system.cpu.iq.fu_full::MemRead 26 18.71% 43.88% # attempts to use FU when none available 145system.cpu.iq.fu_full::MemWrite 78 56.12% 100.00% # attempts to use FU when none available 146system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 147system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 148system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 149system.cpu.iq.FU_type_0::IntAlu 13779 74.16% 74.16% # Type of FU issued 150system.cpu.iq.FU_type_0::IntMult 0 0.00% 74.16% # Type of FU issued 151system.cpu.iq.FU_type_0::IntDiv 0 0.00% 74.16% # Type of FU issued 152system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 74.16% # Type of FU issued 153system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 74.16% # Type of FU issued 154system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 74.16% # Type of FU issued 155system.cpu.iq.FU_type_0::FloatMult 0 0.00% 74.16% # Type of FU issued 156system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 74.16% # Type of FU issued 157system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 74.16% # Type of FU issued 158system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 74.16% # Type of FU issued 159system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 74.16% # Type of FU issued 160system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 74.16% # Type of FU issued 161system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 74.16% # Type of FU issued 162system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 74.16% # Type of FU issued 163system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 74.16% # Type of FU issued 164system.cpu.iq.FU_type_0::SimdMult 0 0.00% 74.16% # Type of FU issued 165system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 74.16% # Type of FU issued 166system.cpu.iq.FU_type_0::SimdShift 0 0.00% 74.16% # Type of FU issued 167system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 74.16% # Type of FU issued 168system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 74.16% # Type of FU issued 169system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 74.16% # Type of FU issued 170system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 74.16% # Type of FU issued 171system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 74.16% # Type of FU issued 172system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 74.16% # Type of FU issued 173system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 74.16% # Type of FU issued 174system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 74.16% # Type of FU issued 175system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 74.16% # Type of FU issued 176system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 74.16% # Type of FU issued 177system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 74.16% # Type of FU issued 178system.cpu.iq.FU_type_0::MemRead 2952 15.89% 90.04% # Type of FU issued 179system.cpu.iq.FU_type_0::MemWrite 1850 9.96% 100.00% # Type of FU issued 180system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 181system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 182system.cpu.iq.FU_type_0::total 18581 # Type of FU issued 183system.cpu.iq.rate 0.512876 # Inst issue rate 184system.cpu.iq.fu_busy_cnt 139 # FU busy when requested 185system.cpu.iq.fu_busy_rate 0.007481 # FU busy rate (busy events/executed inst) 186system.cpu.iq.int_inst_queue_reads 64988 # Number of integer instruction queue reads 187system.cpu.iq.int_inst_queue_writes 24825 # Number of integer instruction queue writes 188system.cpu.iq.int_inst_queue_wakeup_accesses 17429 # Number of integer instruction queue wakeup accesses 189system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads 190system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes 191system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses 192system.cpu.iq.int_alu_accesses 18720 # Number of integer alu accesses 193system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses 194system.cpu.iew.lsq.thread0.forwLoads 26 # Number of loads that had data forwarded from stores 195system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 196system.cpu.iew.lsq.thread0.squashedLoads 888 # Number of loads squashed 197system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed 198system.cpu.iew.lsq.thread0.memOrderViolation 27 # Number of memory ordering violations 199system.cpu.iew.lsq.thread0.squashedStores 528 # Number of stores squashed 200system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 201system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 202system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled 203system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked 204system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 205system.cpu.iew.iewSquashCycles 1364 # Number of cycles IEW is squashing 206system.cpu.iew.iewBlockCycles 96 # Number of cycles IEW is blocking 207system.cpu.iew.iewUnblockCycles 10 # Number of cycles IEW is unblocking 208system.cpu.iew.iewDispatchedInsts 21045 # Number of instructions dispatched to IQ 209system.cpu.iew.iewDispSquashedInsts 247 # Number of squashed instructions skipped by dispatch 210system.cpu.iew.iewDispLoadInsts 3114 # Number of dispatched load instructions 211system.cpu.iew.iewDispStoreInsts 1976 # Number of dispatched store instructions 212system.cpu.iew.iewDispNonSpecInsts 615 # Number of dispatched non-speculative instructions 213system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall 214system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 215system.cpu.iew.memOrderViolationEvents 27 # Number of memory order violations 216system.cpu.iew.predictedTakenIncorrect 371 # Number of branches that were predicted taken incorrectly 217system.cpu.iew.predictedNotTakenIncorrect 573 # Number of branches that were predicted not taken incorrectly 218system.cpu.iew.branchMispredicts 944 # Number of branch mispredicts detected at execute 219system.cpu.iew.iewExecutedInsts 17855 # Number of executed instructions 220system.cpu.iew.iewExecLoadInsts 2862 # Number of load instructions executed 221system.cpu.iew.iewExecSquashedInsts 726 # Number of squashed instructions skipped in execute 222system.cpu.iew.exec_swp 0 # number of swp insts executed 223system.cpu.iew.exec_nop 1102 # number of nop insts executed 224system.cpu.iew.exec_refs 4620 # number of memory reference insts executed 225system.cpu.iew.exec_branches 3963 # Number of branches executed 226system.cpu.iew.exec_stores 1758 # Number of stores executed 227system.cpu.iew.exec_rate 0.492837 # Inst execution rate 228system.cpu.iew.wb_sent 17592 # cumulative count of insts sent to commit 229system.cpu.iew.wb_count 17429 # cumulative count of insts written-back 230system.cpu.iew.wb_producers 8123 # num instructions producing a value 231system.cpu.iew.wb_consumers 9726 # num instructions consuming a value 232system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 233system.cpu.iew.wb_rate 0.481079 # insts written-back per cycle 234system.cpu.iew.wb_fanout 0.835184 # average fanout of values written-back 235system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 236system.cpu.commit.commitCommittedInsts 15175 # The number of committed instructions 237system.cpu.commit.commitSquashedInsts 5794 # The number of squashed insts skipped by commit 238system.cpu.commit.commitNonSpecStalls 475 # The number of times commit has been forced to stall to communicate backwards 239system.cpu.commit.branchMispredicts 847 # The number of times a branch was mispredicted 240system.cpu.commit.committed_per_cycle::samples 26259 # Number of insts commited each cycle 241system.cpu.commit.committed_per_cycle::mean 0.577897 # Number of insts commited each cycle 242system.cpu.commit.committed_per_cycle::stdev 1.280480 # Number of insts commited each cycle 243system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 244system.cpu.commit.committed_per_cycle::0 19069 72.62% 72.62% # Number of insts commited each cycle 245system.cpu.commit.committed_per_cycle::1 3994 15.21% 87.83% # Number of insts commited each cycle 246system.cpu.commit.committed_per_cycle::2 1208 4.60% 92.43% # Number of insts commited each cycle 247system.cpu.commit.committed_per_cycle::3 790 3.01% 95.44% # Number of insts commited each cycle 248system.cpu.commit.committed_per_cycle::4 369 1.41% 96.84% # Number of insts commited each cycle 249system.cpu.commit.committed_per_cycle::5 322 1.23% 98.07% # Number of insts commited each cycle 250system.cpu.commit.committed_per_cycle::6 345 1.31% 99.38% # Number of insts commited each cycle 251system.cpu.commit.committed_per_cycle::7 57 0.22% 99.60% # Number of insts commited each cycle 252system.cpu.commit.committed_per_cycle::8 105 0.40% 100.00% # Number of insts commited each cycle 253system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 254system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 255system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 256system.cpu.commit.committed_per_cycle::total 26259 # Number of insts commited each cycle 257system.cpu.commit.count 15175 # Number of instructions committed 258system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 259system.cpu.commit.refs 3674 # Number of memory references committed 260system.cpu.commit.loads 2226 # Number of loads committed 261system.cpu.commit.membars 0 # Number of memory barriers committed 262system.cpu.commit.branches 3359 # Number of branches committed 263system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. 264system.cpu.commit.int_insts 12186 # Number of committed integer instructions. 265system.cpu.commit.function_calls 187 # Number of function calls committed. 266system.cpu.commit.bw_lim_events 105 # number cycles where commit BW limit reached 267system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 268system.cpu.rob.rob_reads 46300 # The number of ROB reads 269system.cpu.rob.rob_writes 43308 # The number of ROB writes 270system.cpu.timesIdled 181 # Number of times that the entire CPU went into an idle state and unscheduled itself 271system.cpu.idleCycles 8623 # Total number of cycles that the CPU has spent unscheduled due to idling 272system.cpu.committedInsts 14449 # Number of Instructions Simulated 273system.cpu.committedInsts_total 14449 # Number of Instructions Simulated 274system.cpu.cpi 2.507371 # CPI: Cycles Per Instruction 275system.cpu.cpi_total 2.507371 # CPI: Total CPI of All Threads 276system.cpu.ipc 0.398824 # IPC: Instructions Per Cycle 277system.cpu.ipc_total 0.398824 # IPC: Total IPC of All Threads 278system.cpu.int_regfile_reads 28557 # number of integer regfile reads 279system.cpu.int_regfile_writes 15938 # number of integer regfile writes 280system.cpu.misc_regfile_reads 6251 # number of misc regfile reads 281system.cpu.misc_regfile_writes 569 # number of misc regfile writes 282system.cpu.icache.replacements 0 # number of replacements 283system.cpu.icache.tagsinuse 193.216525 # Cycle average of tags in use 284system.cpu.icache.total_refs 4151 # Total number of references to valid blocks. 285system.cpu.icache.sampled_refs 332 # Sample count of references to valid blocks. 286system.cpu.icache.avg_refs 12.503012 # Average number of references to valid blocks. 287system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 288system.cpu.icache.occ_blocks::0 193.216525 # Average occupied blocks per context 289system.cpu.icache.occ_percent::0 0.094344 # Average percentage of cache occupancy 290system.cpu.icache.ReadReq_hits 4151 # number of ReadReq hits 291system.cpu.icache.demand_hits 4151 # number of demand (read+write) hits 292system.cpu.icache.overall_hits 4151 # number of overall hits 293system.cpu.icache.ReadReq_misses 457 # number of ReadReq misses 294system.cpu.icache.demand_misses 457 # number of demand (read+write) misses 295system.cpu.icache.overall_misses 457 # number of overall misses 296system.cpu.icache.ReadReq_miss_latency 15956000 # number of ReadReq miss cycles 297system.cpu.icache.demand_miss_latency 15956000 # number of demand (read+write) miss cycles 298system.cpu.icache.overall_miss_latency 15956000 # number of overall miss cycles 299system.cpu.icache.ReadReq_accesses 4608 # number of ReadReq accesses(hits+misses) 300system.cpu.icache.demand_accesses 4608 # number of demand (read+write) accesses 301system.cpu.icache.overall_accesses 4608 # number of overall (read+write) accesses 302system.cpu.icache.ReadReq_miss_rate 0.099175 # miss rate for ReadReq accesses 303system.cpu.icache.demand_miss_rate 0.099175 # miss rate for demand accesses 304system.cpu.icache.overall_miss_rate 0.099175 # miss rate for overall accesses 305system.cpu.icache.ReadReq_avg_miss_latency 34914.660832 # average ReadReq miss latency 306system.cpu.icache.demand_avg_miss_latency 34914.660832 # average overall miss latency 307system.cpu.icache.overall_avg_miss_latency 34914.660832 # average overall miss latency 308system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 309system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 310system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 311system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 312system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 313system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 314system.cpu.icache.fast_writes 0 # number of fast writes performed 315system.cpu.icache.cache_copies 0 # number of cache copies performed 316system.cpu.icache.writebacks 0 # number of writebacks 317system.cpu.icache.ReadReq_mshr_hits 125 # number of ReadReq MSHR hits 318system.cpu.icache.demand_mshr_hits 125 # number of demand (read+write) MSHR hits 319system.cpu.icache.overall_mshr_hits 125 # number of overall MSHR hits 320system.cpu.icache.ReadReq_mshr_misses 332 # number of ReadReq MSHR misses 321system.cpu.icache.demand_mshr_misses 332 # number of demand (read+write) MSHR misses 322system.cpu.icache.overall_mshr_misses 332 # number of overall MSHR misses 323system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 324system.cpu.icache.ReadReq_mshr_miss_latency 11653500 # number of ReadReq MSHR miss cycles 325system.cpu.icache.demand_mshr_miss_latency 11653500 # number of demand (read+write) MSHR miss cycles 326system.cpu.icache.overall_mshr_miss_latency 11653500 # number of overall MSHR miss cycles 327system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 328system.cpu.icache.ReadReq_mshr_miss_rate 0.072049 # mshr miss rate for ReadReq accesses 329system.cpu.icache.demand_mshr_miss_rate 0.072049 # mshr miss rate for demand accesses 330system.cpu.icache.overall_mshr_miss_rate 0.072049 # mshr miss rate for overall accesses 331system.cpu.icache.ReadReq_avg_mshr_miss_latency 35100.903614 # average ReadReq mshr miss latency 332system.cpu.icache.demand_avg_mshr_miss_latency 35100.903614 # average overall mshr miss latency 333system.cpu.icache.overall_avg_mshr_miss_latency 35100.903614 # average overall mshr miss latency 334system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 335system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated 336system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 337system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 338system.cpu.dcache.replacements 0 # number of replacements 339system.cpu.dcache.tagsinuse 102.149831 # Cycle average of tags in use 340system.cpu.dcache.total_refs 3712 # Total number of references to valid blocks. 341system.cpu.dcache.sampled_refs 146 # Sample count of references to valid blocks. 342system.cpu.dcache.avg_refs 25.424658 # Average number of references to valid blocks. 343system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 344system.cpu.dcache.occ_blocks::0 102.149831 # Average occupied blocks per context 345system.cpu.dcache.occ_percent::0 0.024939 # Average percentage of cache occupancy 346system.cpu.dcache.ReadReq_hits 2672 # number of ReadReq hits 347system.cpu.dcache.WriteReq_hits 1034 # number of WriteReq hits 348system.cpu.dcache.SwapReq_hits 6 # number of SwapReq hits 349system.cpu.dcache.demand_hits 3706 # number of demand (read+write) hits 350system.cpu.dcache.overall_hits 3706 # number of overall hits 351system.cpu.dcache.ReadReq_misses 114 # number of ReadReq misses 352system.cpu.dcache.WriteReq_misses 408 # number of WriteReq misses 353system.cpu.dcache.demand_misses 522 # number of demand (read+write) misses 354system.cpu.dcache.overall_misses 522 # number of overall misses 355system.cpu.dcache.ReadReq_miss_latency 3994500 # number of ReadReq miss cycles 356system.cpu.dcache.WriteReq_miss_latency 14649500 # number of WriteReq miss cycles 357system.cpu.dcache.demand_miss_latency 18644000 # number of demand (read+write) miss cycles 358system.cpu.dcache.overall_miss_latency 18644000 # number of overall miss cycles 359system.cpu.dcache.ReadReq_accesses 2786 # number of ReadReq accesses(hits+misses) 360system.cpu.dcache.WriteReq_accesses 1442 # number of WriteReq accesses(hits+misses) 361system.cpu.dcache.SwapReq_accesses 6 # number of SwapReq accesses(hits+misses) 362system.cpu.dcache.demand_accesses 4228 # number of demand (read+write) accesses 363system.cpu.dcache.overall_accesses 4228 # number of overall (read+write) accesses 364system.cpu.dcache.ReadReq_miss_rate 0.040919 # miss rate for ReadReq accesses 365system.cpu.dcache.WriteReq_miss_rate 0.282940 # miss rate for WriteReq accesses 366system.cpu.dcache.demand_miss_rate 0.123463 # miss rate for demand accesses 367system.cpu.dcache.overall_miss_rate 0.123463 # miss rate for overall accesses 368system.cpu.dcache.ReadReq_avg_miss_latency 35039.473684 # average ReadReq miss latency 369system.cpu.dcache.WriteReq_avg_miss_latency 35905.637255 # average WriteReq miss latency 370system.cpu.dcache.demand_avg_miss_latency 35716.475096 # average overall miss latency 371system.cpu.dcache.overall_avg_miss_latency 35716.475096 # average overall miss latency 372system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 373system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 374system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 375system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 376system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 377system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 378system.cpu.dcache.fast_writes 0 # number of fast writes performed 379system.cpu.dcache.cache_copies 0 # number of cache copies performed 380system.cpu.dcache.writebacks 0 # number of writebacks 381system.cpu.dcache.ReadReq_mshr_hits 51 # number of ReadReq MSHR hits 382system.cpu.dcache.WriteReq_mshr_hits 325 # number of WriteReq MSHR hits 383system.cpu.dcache.demand_mshr_hits 376 # number of demand (read+write) MSHR hits 384system.cpu.dcache.overall_mshr_hits 376 # number of overall MSHR hits 385system.cpu.dcache.ReadReq_mshr_misses 63 # number of ReadReq MSHR misses 386system.cpu.dcache.WriteReq_mshr_misses 83 # number of WriteReq MSHR misses 387system.cpu.dcache.demand_mshr_misses 146 # number of demand (read+write) MSHR misses 388system.cpu.dcache.overall_mshr_misses 146 # number of overall MSHR misses 389system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 390system.cpu.dcache.ReadReq_mshr_miss_latency 2241500 # number of ReadReq MSHR miss cycles 391system.cpu.dcache.WriteReq_mshr_miss_latency 2985000 # number of WriteReq MSHR miss cycles 392system.cpu.dcache.demand_mshr_miss_latency 5226500 # number of demand (read+write) MSHR miss cycles 393system.cpu.dcache.overall_mshr_miss_latency 5226500 # number of overall MSHR miss cycles 394system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 395system.cpu.dcache.ReadReq_mshr_miss_rate 0.022613 # mshr miss rate for ReadReq accesses 396system.cpu.dcache.WriteReq_mshr_miss_rate 0.057559 # mshr miss rate for WriteReq accesses 397system.cpu.dcache.demand_mshr_miss_rate 0.034532 # mshr miss rate for demand accesses 398system.cpu.dcache.overall_mshr_miss_rate 0.034532 # mshr miss rate for overall accesses 399system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35579.365079 # average ReadReq mshr miss latency 400system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35963.855422 # average WriteReq mshr miss latency 401system.cpu.dcache.demand_avg_mshr_miss_latency 35797.945205 # average overall mshr miss latency 402system.cpu.dcache.overall_avg_mshr_miss_latency 35797.945205 # average overall mshr miss latency 403system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 404system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated 405system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 406system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 407system.cpu.l2cache.replacements 0 # number of replacements 408system.cpu.l2cache.tagsinuse 228.374360 # Cycle average of tags in use 409system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. 410system.cpu.l2cache.sampled_refs 393 # Sample count of references to valid blocks. 411system.cpu.l2cache.avg_refs 0.005089 # Average number of references to valid blocks. 412system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 413system.cpu.l2cache.occ_blocks::0 228.374360 # Average occupied blocks per context 414system.cpu.l2cache.occ_percent::0 0.006969 # Average percentage of cache occupancy 415system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits 416system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits 417system.cpu.l2cache.overall_hits 2 # number of overall hits 418system.cpu.l2cache.ReadReq_misses 393 # number of ReadReq misses 419system.cpu.l2cache.ReadExReq_misses 83 # number of ReadExReq misses 420system.cpu.l2cache.demand_misses 476 # number of demand (read+write) misses 421system.cpu.l2cache.overall_misses 476 # number of overall misses 422system.cpu.l2cache.ReadReq_miss_latency 13475000 # number of ReadReq miss cycles 423system.cpu.l2cache.ReadExReq_miss_latency 2872000 # number of ReadExReq miss cycles 424system.cpu.l2cache.demand_miss_latency 16347000 # number of demand (read+write) miss cycles 425system.cpu.l2cache.overall_miss_latency 16347000 # number of overall miss cycles 426system.cpu.l2cache.ReadReq_accesses 395 # number of ReadReq accesses(hits+misses) 427system.cpu.l2cache.ReadExReq_accesses 83 # number of ReadExReq accesses(hits+misses) 428system.cpu.l2cache.demand_accesses 478 # number of demand (read+write) accesses 429system.cpu.l2cache.overall_accesses 478 # number of overall (read+write) accesses 430system.cpu.l2cache.ReadReq_miss_rate 0.994937 # miss rate for ReadReq accesses 431system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses 432system.cpu.l2cache.demand_miss_rate 0.995816 # miss rate for demand accesses 433system.cpu.l2cache.overall_miss_rate 0.995816 # miss rate for overall accesses 434system.cpu.l2cache.ReadReq_avg_miss_latency 34287.531807 # average ReadReq miss latency 435system.cpu.l2cache.ReadExReq_avg_miss_latency 34602.409639 # average ReadExReq miss latency 436system.cpu.l2cache.demand_avg_miss_latency 34342.436975 # average overall miss latency 437system.cpu.l2cache.overall_avg_miss_latency 34342.436975 # average overall miss latency 438system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 439system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 440system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 441system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 442system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 443system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 444system.cpu.l2cache.fast_writes 0 # number of fast writes performed 445system.cpu.l2cache.cache_copies 0 # number of cache copies performed 446system.cpu.l2cache.writebacks 0 # number of writebacks 447system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 448system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits 449system.cpu.l2cache.ReadReq_mshr_misses 393 # number of ReadReq MSHR misses 450system.cpu.l2cache.ReadExReq_mshr_misses 83 # number of ReadExReq MSHR misses 451system.cpu.l2cache.demand_mshr_misses 476 # number of demand (read+write) MSHR misses 452system.cpu.l2cache.overall_mshr_misses 476 # number of overall MSHR misses 453system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 454system.cpu.l2cache.ReadReq_mshr_miss_latency 12215000 # number of ReadReq MSHR miss cycles 455system.cpu.l2cache.ReadExReq_mshr_miss_latency 2608500 # number of ReadExReq MSHR miss cycles 456system.cpu.l2cache.demand_mshr_miss_latency 14823500 # number of demand (read+write) MSHR miss cycles 457system.cpu.l2cache.overall_mshr_miss_latency 14823500 # number of overall MSHR miss cycles 458system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 459system.cpu.l2cache.ReadReq_mshr_miss_rate 0.994937 # mshr miss rate for ReadReq accesses 460system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses 461system.cpu.l2cache.demand_mshr_miss_rate 0.995816 # mshr miss rate for demand accesses 462system.cpu.l2cache.overall_mshr_miss_rate 0.995816 # mshr miss rate for overall accesses 463system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31081.424936 # average ReadReq mshr miss latency 464system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31427.710843 # average ReadExReq mshr miss latency 465system.cpu.l2cache.demand_avg_mshr_miss_latency 31141.806723 # average overall mshr miss latency 466system.cpu.l2cache.overall_avg_mshr_miss_latency 31141.806723 # average overall mshr miss latency 467system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 468system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated 469system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 470system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 471 472---------- End Simulation Statistics ---------- 473