stats.txt revision 11680:b4d943429dc6
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000030 # Number of seconds simulated 4sim_ticks 29908500 # Number of ticks simulated 5final_tick 29908500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 58398 # Simulator instruction rate (inst/s) 8host_op_rate 58392 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 120966219 # Simulator tick rate (ticks/s) 10host_mem_usage 251080 # Number of bytes of host memory used 11host_seconds 0.25 # Real time elapsed on the host 12sim_insts 14436 # Number of instructions simulated 13sim_ops 14436 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 29908500 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.inst 23360 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 9408 # Number of bytes read from this memory 19system.physmem.bytes_read::total 32768 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 23360 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 23360 # Number of instructions bytes read from this memory 22system.physmem.num_reads::cpu.inst 365 # Number of read requests responded to by this memory 23system.physmem.num_reads::cpu.data 147 # Number of read requests responded to by this memory 24system.physmem.num_reads::total 512 # Number of read requests responded to by this memory 25system.physmem.bw_read::cpu.inst 781048866 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::cpu.data 314559406 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::total 1095608272 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::cpu.inst 781048866 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::total 781048866 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_total::cpu.inst 781048866 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::cpu.data 314559406 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.bw_total::total 1095608272 # Total bandwidth to/from this memory (bytes/s) 33system.physmem.readReqs 513 # Number of read requests accepted 34system.physmem.writeReqs 0 # Number of write requests accepted 35system.physmem.readBursts 513 # Number of DRAM read bursts, including those serviced by the write queue 36system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 37system.physmem.bytesReadDRAM 32832 # Total number of bytes read from DRAM 38system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 39system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 40system.physmem.bytesReadSys 32832 # Total read bytes from the system interface side 41system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 42system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 43system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 44system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 45system.physmem.perBankRdBursts::0 105 # Per bank write bursts 46system.physmem.perBankRdBursts::1 28 # Per bank write bursts 47system.physmem.perBankRdBursts::2 55 # Per bank write bursts 48system.physmem.perBankRdBursts::3 27 # Per bank write bursts 49system.physmem.perBankRdBursts::4 23 # Per bank write bursts 50system.physmem.perBankRdBursts::5 0 # Per bank write bursts 51system.physmem.perBankRdBursts::6 32 # Per bank write bursts 52system.physmem.perBankRdBursts::7 38 # Per bank write bursts 53system.physmem.perBankRdBursts::8 7 # Per bank write bursts 54system.physmem.perBankRdBursts::9 4 # Per bank write bursts 55system.physmem.perBankRdBursts::10 2 # Per bank write bursts 56system.physmem.perBankRdBursts::11 0 # Per bank write bursts 57system.physmem.perBankRdBursts::12 57 # Per bank write bursts 58system.physmem.perBankRdBursts::13 31 # Per bank write bursts 59system.physmem.perBankRdBursts::14 63 # Per bank write bursts 60system.physmem.perBankRdBursts::15 41 # Per bank write bursts 61system.physmem.perBankWrBursts::0 0 # Per bank write bursts 62system.physmem.perBankWrBursts::1 0 # Per bank write bursts 63system.physmem.perBankWrBursts::2 0 # Per bank write bursts 64system.physmem.perBankWrBursts::3 0 # Per bank write bursts 65system.physmem.perBankWrBursts::4 0 # Per bank write bursts 66system.physmem.perBankWrBursts::5 0 # Per bank write bursts 67system.physmem.perBankWrBursts::6 0 # Per bank write bursts 68system.physmem.perBankWrBursts::7 0 # Per bank write bursts 69system.physmem.perBankWrBursts::8 0 # Per bank write bursts 70system.physmem.perBankWrBursts::9 0 # Per bank write bursts 71system.physmem.perBankWrBursts::10 0 # Per bank write bursts 72system.physmem.perBankWrBursts::11 0 # Per bank write bursts 73system.physmem.perBankWrBursts::12 0 # Per bank write bursts 74system.physmem.perBankWrBursts::13 0 # Per bank write bursts 75system.physmem.perBankWrBursts::14 0 # Per bank write bursts 76system.physmem.perBankWrBursts::15 0 # Per bank write bursts 77system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 78system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 79system.physmem.totGap 29877000 # Total gap between requests 80system.physmem.readPktSize::0 0 # Read request sizes (log2) 81system.physmem.readPktSize::1 0 # Read request sizes (log2) 82system.physmem.readPktSize::2 0 # Read request sizes (log2) 83system.physmem.readPktSize::3 0 # Read request sizes (log2) 84system.physmem.readPktSize::4 0 # Read request sizes (log2) 85system.physmem.readPktSize::5 0 # Read request sizes (log2) 86system.physmem.readPktSize::6 513 # Read request sizes (log2) 87system.physmem.writePktSize::0 0 # Write request sizes (log2) 88system.physmem.writePktSize::1 0 # Write request sizes (log2) 89system.physmem.writePktSize::2 0 # Write request sizes (log2) 90system.physmem.writePktSize::3 0 # Write request sizes (log2) 91system.physmem.writePktSize::4 0 # Write request sizes (log2) 92system.physmem.writePktSize::5 0 # Write request sizes (log2) 93system.physmem.writePktSize::6 0 # Write request sizes (log2) 94system.physmem.rdQLenPdf::0 282 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::1 156 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::2 58 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::3 13 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 126system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 127system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 128system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 129system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 130system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 131system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 132system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 190system.physmem.bytesPerActivate::samples 78 # Bytes accessed per row activation 191system.physmem.bytesPerActivate::mean 394.666667 # Bytes accessed per row activation 192system.physmem.bytesPerActivate::gmean 253.933476 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::stdev 348.475070 # Bytes accessed per row activation 194system.physmem.bytesPerActivate::0-127 17 21.79% 21.79% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::128-255 19 24.36% 46.15% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::256-383 12 15.38% 61.54% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::384-511 5 6.41% 67.95% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::512-639 5 6.41% 74.36% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::640-767 1 1.28% 75.64% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::768-895 6 7.69% 83.33% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::896-1023 1 1.28% 84.62% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::1024-1151 12 15.38% 100.00% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::total 78 # Bytes accessed per row activation 204system.physmem.totQLat 6721500 # Total ticks spent queuing 205system.physmem.totMemAccLat 16340250 # Total ticks spent from burst creation until serviced by the DRAM 206system.physmem.totBusLat 2565000 # Total ticks spent in databus transfers 207system.physmem.avgQLat 13102.34 # Average queueing delay per DRAM burst 208system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 209system.physmem.avgMemAccLat 31852.34 # Average memory access latency per DRAM burst 210system.physmem.avgRdBW 1097.75 # Average DRAM read bandwidth in MiByte/s 211system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 212system.physmem.avgRdBWSys 1097.75 # Average system read bandwidth in MiByte/s 213system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 214system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 215system.physmem.busUtil 8.58 # Data bus utilization in percentage 216system.physmem.busUtilRead 8.58 # Data bus utilization in percentage for reads 217system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 218system.physmem.avgRdQLen 1.64 # Average read queue length when enqueuing 219system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 220system.physmem.readRowHits 424 # Number of row buffer hits during reads 221system.physmem.writeRowHits 0 # Number of row buffer hits during writes 222system.physmem.readRowHitRate 82.65 # Row buffer hit rate for reads 223system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 224system.physmem.avgGap 58239.77 # Average gap between requests 225system.physmem.pageHitRate 82.65 # Row buffer hit rate, read and write combined 226system.physmem_0.actEnergy 357000 # Energy for activate commands per rank (pJ) 227system.physmem_0.preEnergy 174570 # Energy for precharge commands per rank (pJ) 228system.physmem_0.readEnergy 2199120 # Energy for read commands per rank (pJ) 229system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 230system.physmem_0.refreshEnergy 1843920.000000 # Energy for refresh commands per rank (pJ) 231system.physmem_0.actBackEnergy 3642300 # Energy for active background per rank (pJ) 232system.physmem_0.preBackEnergy 63360 # Energy for precharge background per rank (pJ) 233system.physmem_0.actPowerDownEnergy 9900900 # Energy for active power-down per rank (pJ) 234system.physmem_0.prePowerDownEnergy 16800 # Energy for precharge power-down per rank (pJ) 235system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) 236system.physmem_0.totalEnergy 18197970 # Total energy per rank (pJ) 237system.physmem_0.averagePower 608.449701 # Core power per rank (mW) 238system.physmem_0.totalIdleTime 21617000 # Total Idle time Per DRAM Rank 239system.physmem_0.memoryStateTime::IDLE 40500 # Time in different power states 240system.physmem_0.memoryStateTime::REF 780000 # Time in different power states 241system.physmem_0.memoryStateTime::SREF 0 # Time in different power states 242system.physmem_0.memoryStateTime::PRE_PDN 44000 # Time in different power states 243system.physmem_0.memoryStateTime::ACT 7338500 # Time in different power states 244system.physmem_0.memoryStateTime::ACT_PDN 21705500 # Time in different power states 245system.physmem_1.actEnergy 278460 # Energy for activate commands per rank (pJ) 246system.physmem_1.preEnergy 121440 # Energy for precharge commands per rank (pJ) 247system.physmem_1.readEnergy 1463700 # Energy for read commands per rank (pJ) 248system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 249system.physmem_1.refreshEnergy 1843920.000000 # Energy for refresh commands per rank (pJ) 250system.physmem_1.actBackEnergy 2522250 # Energy for active background per rank (pJ) 251system.physmem_1.preBackEnergy 86880 # Energy for precharge background per rank (pJ) 252system.physmem_1.actPowerDownEnergy 10426440 # Energy for active power-down per rank (pJ) 253system.physmem_1.prePowerDownEnergy 493920 # Energy for precharge power-down per rank (pJ) 254system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) 255system.physmem_1.totalEnergy 17237010 # Total energy per rank (pJ) 256system.physmem_1.averagePower 576.319973 # Core power per rank (mW) 257system.physmem_1.totalIdleTime 24154250 # Total Idle time Per DRAM Rank 258system.physmem_1.memoryStateTime::IDLE 143000 # Time in different power states 259system.physmem_1.memoryStateTime::REF 780000 # Time in different power states 260system.physmem_1.memoryStateTime::SREF 0 # Time in different power states 261system.physmem_1.memoryStateTime::PRE_PDN 1286000 # Time in different power states 262system.physmem_1.memoryStateTime::ACT 4831250 # Time in different power states 263system.physmem_1.memoryStateTime::ACT_PDN 22868250 # Time in different power states 264system.pwrStateResidencyTicks::UNDEFINED 29908500 # Cumulative time (in ticks) in various power states 265system.cpu.branchPred.lookups 12304 # Number of BP lookups 266system.cpu.branchPred.condPredicted 7429 # Number of conditional branches predicted 267system.cpu.branchPred.condIncorrect 1435 # Number of conditional branches incorrect 268system.cpu.branchPred.BTBLookups 9156 # Number of BTB lookups 269system.cpu.branchPred.BTBHits 0 # Number of BTB hits 270system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 271system.cpu.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage 272system.cpu.branchPred.usedRAS 730 # Number of times the RAS was used to get a target. 273system.cpu.branchPred.RASInCorrect 166 # Number of incorrect RAS predictions. 274system.cpu.branchPred.indirectLookups 9156 # Number of indirect predictor lookups. 275system.cpu.branchPred.indirectHits 1824 # Number of indirect target hits. 276system.cpu.branchPred.indirectMisses 7332 # Number of indirect misses. 277system.cpu.branchPredindirectMispredicted 865 # Number of mispredicted indirect branches. 278system.cpu_clk_domain.clock 500 # Clock period in ticks 279system.cpu.workload.num_syscalls 18 # Number of system calls 280system.cpu.pwrStateResidencyTicks::ON 29908500 # Cumulative time (in ticks) in various power states 281system.cpu.numCycles 59818 # number of cpu cycles simulated 282system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 283system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 284system.cpu.fetch.icacheStallCycles 15502 # Number of cycles fetch is stalled on an Icache miss 285system.cpu.fetch.Insts 57440 # Number of instructions fetch has processed 286system.cpu.fetch.Branches 12304 # Number of branches that fetch encountered 287system.cpu.fetch.predictedBranches 2554 # Number of branches that fetch has predicted taken 288system.cpu.fetch.Cycles 17524 # Number of cycles fetch has run and was not squashing or blocked 289system.cpu.fetch.SquashCycles 3065 # Number of cycles fetch has spent squashing 290system.cpu.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 291system.cpu.fetch.PendingTrapStallCycles 1117 # Number of stall cycles due to pending traps 292system.cpu.fetch.IcacheWaitRetryStallCycles 12 # Number of stall cycles due to full MSHR 293system.cpu.fetch.CacheLines 7446 # Number of cache lines fetched 294system.cpu.fetch.IcacheSquashes 730 # Number of outstanding Icache misses that were squashed 295system.cpu.fetch.rateDist::samples 35692 # Number of instructions fetched each cycle (Total) 296system.cpu.fetch.rateDist::mean 1.609324 # Number of instructions fetched each cycle (Total) 297system.cpu.fetch.rateDist::stdev 2.874327 # Number of instructions fetched each cycle (Total) 298system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 299system.cpu.fetch.rateDist::0 23194 64.98% 64.98% # Number of instructions fetched each cycle (Total) 300system.cpu.fetch.rateDist::1 4479 12.55% 77.53% # Number of instructions fetched each cycle (Total) 301system.cpu.fetch.rateDist::2 496 1.39% 78.92% # Number of instructions fetched each cycle (Total) 302system.cpu.fetch.rateDist::3 441 1.24% 80.16% # Number of instructions fetched each cycle (Total) 303system.cpu.fetch.rateDist::4 761 2.13% 82.29% # Number of instructions fetched each cycle (Total) 304system.cpu.fetch.rateDist::5 680 1.91% 84.20% # Number of instructions fetched each cycle (Total) 305system.cpu.fetch.rateDist::6 284 0.80% 84.99% # Number of instructions fetched each cycle (Total) 306system.cpu.fetch.rateDist::7 358 1.00% 85.99% # Number of instructions fetched each cycle (Total) 307system.cpu.fetch.rateDist::8 4999 14.01% 100.00% # Number of instructions fetched each cycle (Total) 308system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 309system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 310system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 311system.cpu.fetch.rateDist::total 35692 # Number of instructions fetched each cycle (Total) 312system.cpu.fetch.branchRate 0.205691 # Number of branch fetches per cycle 313system.cpu.fetch.rate 0.960246 # Number of inst fetches per cycle 314system.cpu.decode.IdleCycles 12333 # Number of cycles decode is idle 315system.cpu.decode.BlockedCycles 13299 # Number of cycles decode is blocked 316system.cpu.decode.RunCycles 7732 # Number of cycles decode is running 317system.cpu.decode.UnblockCycles 796 # Number of cycles decode is unblocking 318system.cpu.decode.SquashCycles 1532 # Number of cycles decode is squashing 319system.cpu.decode.DecodedInsts 41071 # Number of instructions handled by decode 320system.cpu.rename.SquashCycles 1532 # Number of cycles rename is squashing 321system.cpu.rename.IdleCycles 13082 # Number of cycles rename is idle 322system.cpu.rename.BlockCycles 2036 # Number of cycles rename is blocking 323system.cpu.rename.serializeStallCycles 9748 # count of cycles rename stalled for serializing inst 324system.cpu.rename.RunCycles 7750 # Number of cycles rename is running 325system.cpu.rename.UnblockCycles 1544 # Number of cycles rename is unblocking 326system.cpu.rename.RenamedInsts 36233 # Number of instructions processed by rename 327system.cpu.rename.IQFullEvents 13 # Number of times rename has blocked due to IQ full 328system.cpu.rename.SQFullEvents 1128 # Number of times rename has blocked due to SQ full 329system.cpu.rename.RenamedOperands 31392 # Number of destination operands rename has renamed 330system.cpu.rename.RenameLookups 65112 # Number of register rename lookups that rename has made 331system.cpu.rename.int_rename_lookups 53717 # Number of integer rename lookups 332system.cpu.rename.CommittedMaps 13819 # Number of HB maps that are committed 333system.cpu.rename.UndoneMaps 17573 # Number of HB maps that are undone due to squashing 334system.cpu.rename.serializingInsts 793 # count of serializing insts renamed 335system.cpu.rename.tempSerializingInsts 793 # count of temporary serializing insts renamed 336system.cpu.rename.skidInsts 4281 # count of insts added to the skid buffer 337system.cpu.memDep0.insertedLoads 4496 # Number of loads inserted to the mem dependence unit. 338system.cpu.memDep0.insertedStores 2885 # Number of stores inserted to the mem dependence unit. 339system.cpu.memDep0.conflictingLoads 12 # Number of conflicting loads. 340system.cpu.memDep0.conflictingStores 8 # Number of conflicting stores. 341system.cpu.iq.iqInstsAdded 28450 # Number of instructions added to the IQ (excludes non-spec) 342system.cpu.iq.iqNonSpecInstsAdded 744 # Number of non-speculative instructions added to the IQ 343system.cpu.iq.iqInstsIssued 25032 # Number of instructions issued 344system.cpu.iq.iqSquashedInstsIssued 132 # Number of squashed instructions issued 345system.cpu.iq.iqSquashedInstsExamined 14758 # Number of squashed instructions iterated over during squash; mainly for profiling 346system.cpu.iq.iqSquashedOperandsExamined 10993 # Number of squashed operands that are examined and possibly removed from graph 347system.cpu.iq.iqSquashedNonSpecRemoved 269 # Number of squashed non-spec instructions that were removed 348system.cpu.iq.issued_per_cycle::samples 35692 # Number of insts issued each cycle 349system.cpu.iq.issued_per_cycle::mean 0.701334 # Number of insts issued each cycle 350system.cpu.iq.issued_per_cycle::stdev 1.501806 # Number of insts issued each cycle 351system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 352system.cpu.iq.issued_per_cycle::0 26613 74.56% 74.56% # Number of insts issued each cycle 353system.cpu.iq.issued_per_cycle::1 3169 8.88% 83.44% # Number of insts issued each cycle 354system.cpu.iq.issued_per_cycle::2 1586 4.44% 87.89% # Number of insts issued each cycle 355system.cpu.iq.issued_per_cycle::3 1525 4.27% 92.16% # Number of insts issued each cycle 356system.cpu.iq.issued_per_cycle::4 1197 3.35% 95.51% # Number of insts issued each cycle 357system.cpu.iq.issued_per_cycle::5 748 2.10% 97.61% # Number of insts issued each cycle 358system.cpu.iq.issued_per_cycle::6 484 1.36% 98.96% # Number of insts issued each cycle 359system.cpu.iq.issued_per_cycle::7 276 0.77% 99.74% # Number of insts issued each cycle 360system.cpu.iq.issued_per_cycle::8 94 0.26% 100.00% # Number of insts issued each cycle 361system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 362system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 363system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 364system.cpu.iq.issued_per_cycle::total 35692 # Number of insts issued each cycle 365system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 366system.cpu.iq.fu_full::IntAlu 164 53.07% 53.07% # attempts to use FU when none available 367system.cpu.iq.fu_full::IntMult 0 0.00% 53.07% # attempts to use FU when none available 368system.cpu.iq.fu_full::IntDiv 0 0.00% 53.07% # attempts to use FU when none available 369system.cpu.iq.fu_full::FloatAdd 0 0.00% 53.07% # attempts to use FU when none available 370system.cpu.iq.fu_full::FloatCmp 0 0.00% 53.07% # attempts to use FU when none available 371system.cpu.iq.fu_full::FloatCvt 0 0.00% 53.07% # attempts to use FU when none available 372system.cpu.iq.fu_full::FloatMult 0 0.00% 53.07% # attempts to use FU when none available 373system.cpu.iq.fu_full::FloatDiv 0 0.00% 53.07% # attempts to use FU when none available 374system.cpu.iq.fu_full::FloatSqrt 0 0.00% 53.07% # attempts to use FU when none available 375system.cpu.iq.fu_full::SimdAdd 0 0.00% 53.07% # attempts to use FU when none available 376system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 53.07% # attempts to use FU when none available 377system.cpu.iq.fu_full::SimdAlu 0 0.00% 53.07% # attempts to use FU when none available 378system.cpu.iq.fu_full::SimdCmp 0 0.00% 53.07% # attempts to use FU when none available 379system.cpu.iq.fu_full::SimdCvt 0 0.00% 53.07% # attempts to use FU when none available 380system.cpu.iq.fu_full::SimdMisc 0 0.00% 53.07% # attempts to use FU when none available 381system.cpu.iq.fu_full::SimdMult 0 0.00% 53.07% # attempts to use FU when none available 382system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 53.07% # attempts to use FU when none available 383system.cpu.iq.fu_full::SimdShift 0 0.00% 53.07% # attempts to use FU when none available 384system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 53.07% # attempts to use FU when none available 385system.cpu.iq.fu_full::SimdSqrt 0 0.00% 53.07% # attempts to use FU when none available 386system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 53.07% # attempts to use FU when none available 387system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 53.07% # attempts to use FU when none available 388system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 53.07% # attempts to use FU when none available 389system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 53.07% # attempts to use FU when none available 390system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 53.07% # attempts to use FU when none available 391system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 53.07% # attempts to use FU when none available 392system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 53.07% # attempts to use FU when none available 393system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 53.07% # attempts to use FU when none available 394system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 53.07% # attempts to use FU when none available 395system.cpu.iq.fu_full::MemRead 53 17.15% 70.23% # attempts to use FU when none available 396system.cpu.iq.fu_full::MemWrite 92 29.77% 100.00% # attempts to use FU when none available 397system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 398system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 399system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 400system.cpu.iq.FU_type_0::IntAlu 18346 73.29% 73.29% # Type of FU issued 401system.cpu.iq.FU_type_0::IntMult 0 0.00% 73.29% # Type of FU issued 402system.cpu.iq.FU_type_0::IntDiv 0 0.00% 73.29% # Type of FU issued 403system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 73.29% # Type of FU issued 404system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 73.29% # Type of FU issued 405system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 73.29% # Type of FU issued 406system.cpu.iq.FU_type_0::FloatMult 0 0.00% 73.29% # Type of FU issued 407system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 73.29% # Type of FU issued 408system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 73.29% # Type of FU issued 409system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 73.29% # Type of FU issued 410system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 73.29% # Type of FU issued 411system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 73.29% # Type of FU issued 412system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 73.29% # Type of FU issued 413system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 73.29% # Type of FU issued 414system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 73.29% # Type of FU issued 415system.cpu.iq.FU_type_0::SimdMult 0 0.00% 73.29% # Type of FU issued 416system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 73.29% # Type of FU issued 417system.cpu.iq.FU_type_0::SimdShift 0 0.00% 73.29% # Type of FU issued 418system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 73.29% # Type of FU issued 419system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 73.29% # Type of FU issued 420system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 73.29% # Type of FU issued 421system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 73.29% # Type of FU issued 422system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 73.29% # Type of FU issued 423system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 73.29% # Type of FU issued 424system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 73.29% # Type of FU issued 425system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 73.29% # Type of FU issued 426system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 73.29% # Type of FU issued 427system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 73.29% # Type of FU issued 428system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 73.29% # Type of FU issued 429system.cpu.iq.FU_type_0::MemRead 4185 16.72% 90.01% # Type of FU issued 430system.cpu.iq.FU_type_0::MemWrite 2501 9.99% 100.00% # Type of FU issued 431system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 432system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 433system.cpu.iq.FU_type_0::total 25032 # Type of FU issued 434system.cpu.iq.rate 0.418469 # Inst issue rate 435system.cpu.iq.fu_busy_cnt 309 # FU busy when requested 436system.cpu.iq.fu_busy_rate 0.012344 # FU busy rate (busy events/executed inst) 437system.cpu.iq.int_inst_queue_reads 86197 # Number of integer instruction queue reads 438system.cpu.iq.int_inst_queue_writes 43979 # Number of integer instruction queue writes 439system.cpu.iq.int_inst_queue_wakeup_accesses 22374 # Number of integer instruction queue wakeup accesses 440system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads 441system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes 442system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses 443system.cpu.iq.int_alu_accesses 25341 # Number of integer alu accesses 444system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses 445system.cpu.iew.lsq.thread0.forwLoads 32 # Number of loads that had data forwarded from stores 446system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 447system.cpu.iew.lsq.thread0.squashedLoads 2271 # Number of loads squashed 448system.cpu.iew.lsq.thread0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed 449system.cpu.iew.lsq.thread0.memOrderViolation 28 # Number of memory ordering violations 450system.cpu.iew.lsq.thread0.squashedStores 1437 # Number of stores squashed 451system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 452system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 453system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled 454system.cpu.iew.lsq.thread0.cacheBlocked 22 # Number of times an access to memory failed due to the cache being blocked 455system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 456system.cpu.iew.iewSquashCycles 1532 # Number of cycles IEW is squashing 457system.cpu.iew.iewBlockCycles 2073 # Number of cycles IEW is blocking 458system.cpu.iew.iewUnblockCycles 16 # Number of cycles IEW is unblocking 459system.cpu.iew.iewDispatchedInsts 30726 # Number of instructions dispatched to IQ 460system.cpu.iew.iewDispSquashedInsts 235 # Number of squashed instructions skipped by dispatch 461system.cpu.iew.iewDispLoadInsts 4496 # Number of dispatched load instructions 462system.cpu.iew.iewDispStoreInsts 2885 # Number of dispatched store instructions 463system.cpu.iew.iewDispNonSpecInsts 744 # Number of dispatched non-speculative instructions 464system.cpu.iew.iewIQFullEvents 7 # Number of times the IQ has become full, causing a stall 465system.cpu.iew.iewLSQFullEvents 4 # Number of times the LSQ has become full, causing a stall 466system.cpu.iew.memOrderViolationEvents 28 # Number of memory order violations 467system.cpu.iew.predictedTakenIncorrect 207 # Number of branches that were predicted taken incorrectly 468system.cpu.iew.predictedNotTakenIncorrect 1575 # Number of branches that were predicted not taken incorrectly 469system.cpu.iew.branchMispredicts 1782 # Number of branch mispredicts detected at execute 470system.cpu.iew.iewExecutedInsts 23436 # Number of executed instructions 471system.cpu.iew.iewExecLoadInsts 3882 # Number of load instructions executed 472system.cpu.iew.iewExecSquashedInsts 1596 # Number of squashed instructions skipped in execute 473system.cpu.iew.exec_swp 0 # number of swp insts executed 474system.cpu.iew.exec_nop 1532 # number of nop insts executed 475system.cpu.iew.exec_refs 6191 # number of memory reference insts executed 476system.cpu.iew.exec_branches 4986 # Number of branches executed 477system.cpu.iew.exec_stores 2309 # Number of stores executed 478system.cpu.iew.exec_rate 0.391788 # Inst execution rate 479system.cpu.iew.wb_sent 22845 # cumulative count of insts sent to commit 480system.cpu.iew.wb_count 22374 # cumulative count of insts written-back 481system.cpu.iew.wb_producers 10411 # num instructions producing a value 482system.cpu.iew.wb_consumers 13650 # num instructions consuming a value 483system.cpu.iew.wb_rate 0.374035 # insts written-back per cycle 484system.cpu.iew.wb_fanout 0.762711 # average fanout of values written-back 485system.cpu.commit.commitSquashedInsts 15475 # The number of squashed insts skipped by commit 486system.cpu.commit.commitNonSpecStalls 475 # The number of times commit has been forced to stall to communicate backwards 487system.cpu.commit.branchMispredicts 1435 # The number of times a branch was mispredicted 488system.cpu.commit.committed_per_cycle::samples 32615 # Number of insts commited each cycle 489system.cpu.commit.committed_per_cycle::mean 0.464878 # Number of insts commited each cycle 490system.cpu.commit.committed_per_cycle::stdev 1.257144 # Number of insts commited each cycle 491system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 492system.cpu.commit.committed_per_cycle::0 25974 79.64% 79.64% # Number of insts commited each cycle 493system.cpu.commit.committed_per_cycle::1 3555 10.90% 90.54% # Number of insts commited each cycle 494system.cpu.commit.committed_per_cycle::2 1191 3.65% 94.19% # Number of insts commited each cycle 495system.cpu.commit.committed_per_cycle::3 577 1.77% 95.96% # Number of insts commited each cycle 496system.cpu.commit.committed_per_cycle::4 319 0.98% 96.94% # Number of insts commited each cycle 497system.cpu.commit.committed_per_cycle::5 311 0.95% 97.89% # Number of insts commited each cycle 498system.cpu.commit.committed_per_cycle::6 392 1.20% 99.09% # Number of insts commited each cycle 499system.cpu.commit.committed_per_cycle::7 57 0.17% 99.27% # Number of insts commited each cycle 500system.cpu.commit.committed_per_cycle::8 239 0.73% 100.00% # Number of insts commited each cycle 501system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 502system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 503system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 504system.cpu.commit.committed_per_cycle::total 32615 # Number of insts commited each cycle 505system.cpu.commit.committedInsts 15162 # Number of instructions committed 506system.cpu.commit.committedOps 15162 # Number of ops (including micro ops) committed 507system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 508system.cpu.commit.refs 3673 # Number of memory references committed 509system.cpu.commit.loads 2225 # Number of loads committed 510system.cpu.commit.membars 0 # Number of memory barriers committed 511system.cpu.commit.branches 3358 # Number of branches committed 512system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. 513system.cpu.commit.int_insts 12174 # Number of committed integer instructions. 514system.cpu.commit.function_calls 187 # Number of function calls committed. 515system.cpu.commit.op_class_0::No_OpClass 726 4.79% 4.79% # Class of committed instruction 516system.cpu.commit.op_class_0::IntAlu 10763 70.99% 75.77% # Class of committed instruction 517system.cpu.commit.op_class_0::IntMult 0 0.00% 75.77% # Class of committed instruction 518system.cpu.commit.op_class_0::IntDiv 0 0.00% 75.77% # Class of committed instruction 519system.cpu.commit.op_class_0::FloatAdd 0 0.00% 75.77% # Class of committed instruction 520system.cpu.commit.op_class_0::FloatCmp 0 0.00% 75.77% # Class of committed instruction 521system.cpu.commit.op_class_0::FloatCvt 0 0.00% 75.77% # Class of committed instruction 522system.cpu.commit.op_class_0::FloatMult 0 0.00% 75.77% # Class of committed instruction 523system.cpu.commit.op_class_0::FloatDiv 0 0.00% 75.77% # Class of committed instruction 524system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 75.77% # Class of committed instruction 525system.cpu.commit.op_class_0::SimdAdd 0 0.00% 75.77% # Class of committed instruction 526system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 75.77% # Class of committed instruction 527system.cpu.commit.op_class_0::SimdAlu 0 0.00% 75.77% # Class of committed instruction 528system.cpu.commit.op_class_0::SimdCmp 0 0.00% 75.77% # Class of committed instruction 529system.cpu.commit.op_class_0::SimdCvt 0 0.00% 75.77% # Class of committed instruction 530system.cpu.commit.op_class_0::SimdMisc 0 0.00% 75.77% # Class of committed instruction 531system.cpu.commit.op_class_0::SimdMult 0 0.00% 75.77% # Class of committed instruction 532system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 75.77% # Class of committed instruction 533system.cpu.commit.op_class_0::SimdShift 0 0.00% 75.77% # Class of committed instruction 534system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 75.77% # Class of committed instruction 535system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 75.77% # Class of committed instruction 536system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 75.77% # Class of committed instruction 537system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 75.77% # Class of committed instruction 538system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 75.77% # Class of committed instruction 539system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 75.77% # Class of committed instruction 540system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 75.77% # Class of committed instruction 541system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 75.77% # Class of committed instruction 542system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 75.77% # Class of committed instruction 543system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 75.77% # Class of committed instruction 544system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 75.77% # Class of committed instruction 545system.cpu.commit.op_class_0::MemRead 2225 14.67% 90.45% # Class of committed instruction 546system.cpu.commit.op_class_0::MemWrite 1448 9.55% 100.00% # Class of committed instruction 547system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 548system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 549system.cpu.commit.op_class_0::total 15162 # Class of committed instruction 550system.cpu.commit.bw_lim_events 239 # number cycles where commit BW limit reached 551system.cpu.rob.rob_reads 62190 # The number of ROB reads 552system.cpu.rob.rob_writes 64431 # The number of ROB writes 553system.cpu.timesIdled 194 # Number of times that the entire CPU went into an idle state and unscheduled itself 554system.cpu.idleCycles 24126 # Total number of cycles that the CPU has spent unscheduled due to idling 555system.cpu.committedInsts 14436 # Number of Instructions Simulated 556system.cpu.committedOps 14436 # Number of Ops (including micro ops) Simulated 557system.cpu.cpi 4.143669 # CPI: Cycles Per Instruction 558system.cpu.cpi_total 4.143669 # CPI: Total CPI of All Threads 559system.cpu.ipc 0.241332 # IPC: Instructions Per Cycle 560system.cpu.ipc_total 0.241332 # IPC: Total IPC of All Threads 561system.cpu.int_regfile_reads 36480 # number of integer regfile reads 562system.cpu.int_regfile_writes 20296 # number of integer regfile writes 563system.cpu.misc_regfile_reads 8094 # number of misc regfile reads 564system.cpu.misc_regfile_writes 569 # number of misc regfile writes 565system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 29908500 # Cumulative time (in ticks) in various power states 566system.cpu.dcache.tags.replacements 0 # number of replacements 567system.cpu.dcache.tags.tagsinuse 99.158435 # Cycle average of tags in use 568system.cpu.dcache.tags.total_refs 4579 # Total number of references to valid blocks. 569system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. 570system.cpu.dcache.tags.avg_refs 31.363014 # Average number of references to valid blocks. 571system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 572system.cpu.dcache.tags.occ_blocks::cpu.data 99.158435 # Average occupied blocks per requestor 573system.cpu.dcache.tags.occ_percent::cpu.data 0.024209 # Average percentage of cache occupancy 574system.cpu.dcache.tags.occ_percent::total 0.024209 # Average percentage of cache occupancy 575system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id 576system.cpu.dcache.tags.age_task_id_blocks_1024::0 21 # Occupied blocks per task id 577system.cpu.dcache.tags.age_task_id_blocks_1024::1 125 # Occupied blocks per task id 578system.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id 579system.cpu.dcache.tags.tag_accesses 10412 # Number of tag accesses 580system.cpu.dcache.tags.data_accesses 10412 # Number of data accesses 581system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 29908500 # Cumulative time (in ticks) in various power states 582system.cpu.dcache.ReadReq_hits::cpu.data 3540 # number of ReadReq hits 583system.cpu.dcache.ReadReq_hits::total 3540 # number of ReadReq hits 584system.cpu.dcache.WriteReq_hits::cpu.data 1033 # number of WriteReq hits 585system.cpu.dcache.WriteReq_hits::total 1033 # number of WriteReq hits 586system.cpu.dcache.SwapReq_hits::cpu.data 6 # number of SwapReq hits 587system.cpu.dcache.SwapReq_hits::total 6 # number of SwapReq hits 588system.cpu.dcache.demand_hits::cpu.data 4573 # number of demand (read+write) hits 589system.cpu.dcache.demand_hits::total 4573 # number of demand (read+write) hits 590system.cpu.dcache.overall_hits::cpu.data 4573 # number of overall hits 591system.cpu.dcache.overall_hits::total 4573 # number of overall hits 592system.cpu.dcache.ReadReq_misses::cpu.data 145 # number of ReadReq misses 593system.cpu.dcache.ReadReq_misses::total 145 # number of ReadReq misses 594system.cpu.dcache.WriteReq_misses::cpu.data 409 # number of WriteReq misses 595system.cpu.dcache.WriteReq_misses::total 409 # number of WriteReq misses 596system.cpu.dcache.demand_misses::cpu.data 554 # number of demand (read+write) misses 597system.cpu.dcache.demand_misses::total 554 # number of demand (read+write) misses 598system.cpu.dcache.overall_misses::cpu.data 554 # number of overall misses 599system.cpu.dcache.overall_misses::total 554 # number of overall misses 600system.cpu.dcache.ReadReq_miss_latency::cpu.data 11443500 # number of ReadReq miss cycles 601system.cpu.dcache.ReadReq_miss_latency::total 11443500 # number of ReadReq miss cycles 602system.cpu.dcache.WriteReq_miss_latency::cpu.data 29003985 # number of WriteReq miss cycles 603system.cpu.dcache.WriteReq_miss_latency::total 29003985 # number of WriteReq miss cycles 604system.cpu.dcache.demand_miss_latency::cpu.data 40447485 # number of demand (read+write) miss cycles 605system.cpu.dcache.demand_miss_latency::total 40447485 # number of demand (read+write) miss cycles 606system.cpu.dcache.overall_miss_latency::cpu.data 40447485 # number of overall miss cycles 607system.cpu.dcache.overall_miss_latency::total 40447485 # number of overall miss cycles 608system.cpu.dcache.ReadReq_accesses::cpu.data 3685 # number of ReadReq accesses(hits+misses) 609system.cpu.dcache.ReadReq_accesses::total 3685 # number of ReadReq accesses(hits+misses) 610system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses) 611system.cpu.dcache.WriteReq_accesses::total 1442 # number of WriteReq accesses(hits+misses) 612system.cpu.dcache.SwapReq_accesses::cpu.data 6 # number of SwapReq accesses(hits+misses) 613system.cpu.dcache.SwapReq_accesses::total 6 # number of SwapReq accesses(hits+misses) 614system.cpu.dcache.demand_accesses::cpu.data 5127 # number of demand (read+write) accesses 615system.cpu.dcache.demand_accesses::total 5127 # number of demand (read+write) accesses 616system.cpu.dcache.overall_accesses::cpu.data 5127 # number of overall (read+write) accesses 617system.cpu.dcache.overall_accesses::total 5127 # number of overall (read+write) accesses 618system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.039349 # miss rate for ReadReq accesses 619system.cpu.dcache.ReadReq_miss_rate::total 0.039349 # miss rate for ReadReq accesses 620system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.283634 # miss rate for WriteReq accesses 621system.cpu.dcache.WriteReq_miss_rate::total 0.283634 # miss rate for WriteReq accesses 622system.cpu.dcache.demand_miss_rate::cpu.data 0.108055 # miss rate for demand accesses 623system.cpu.dcache.demand_miss_rate::total 0.108055 # miss rate for demand accesses 624system.cpu.dcache.overall_miss_rate::cpu.data 0.108055 # miss rate for overall accesses 625system.cpu.dcache.overall_miss_rate::total 0.108055 # miss rate for overall accesses 626system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 78920.689655 # average ReadReq miss latency 627system.cpu.dcache.ReadReq_avg_miss_latency::total 78920.689655 # average ReadReq miss latency 628system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70914.388753 # average WriteReq miss latency 629system.cpu.dcache.WriteReq_avg_miss_latency::total 70914.388753 # average WriteReq miss latency 630system.cpu.dcache.demand_avg_miss_latency::cpu.data 73009.900722 # average overall miss latency 631system.cpu.dcache.demand_avg_miss_latency::total 73009.900722 # average overall miss latency 632system.cpu.dcache.overall_avg_miss_latency::cpu.data 73009.900722 # average overall miss latency 633system.cpu.dcache.overall_avg_miss_latency::total 73009.900722 # average overall miss latency 634system.cpu.dcache.blocked_cycles::no_mshrs 1437 # number of cycles access was blocked 635system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 636system.cpu.dcache.blocked::no_mshrs 19 # number of cycles access was blocked 637system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 638system.cpu.dcache.avg_blocked_cycles::no_mshrs 75.631579 # average number of cycles each access was blocked 639system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 640system.cpu.dcache.ReadReq_mshr_hits::cpu.data 80 # number of ReadReq MSHR hits 641system.cpu.dcache.ReadReq_mshr_hits::total 80 # number of ReadReq MSHR hits 642system.cpu.dcache.WriteReq_mshr_hits::cpu.data 326 # number of WriteReq MSHR hits 643system.cpu.dcache.WriteReq_mshr_hits::total 326 # number of WriteReq MSHR hits 644system.cpu.dcache.demand_mshr_hits::cpu.data 406 # number of demand (read+write) MSHR hits 645system.cpu.dcache.demand_mshr_hits::total 406 # number of demand (read+write) MSHR hits 646system.cpu.dcache.overall_mshr_hits::cpu.data 406 # number of overall MSHR hits 647system.cpu.dcache.overall_mshr_hits::total 406 # number of overall MSHR hits 648system.cpu.dcache.ReadReq_mshr_misses::cpu.data 65 # number of ReadReq MSHR misses 649system.cpu.dcache.ReadReq_mshr_misses::total 65 # number of ReadReq MSHR misses 650system.cpu.dcache.WriteReq_mshr_misses::cpu.data 83 # number of WriteReq MSHR misses 651system.cpu.dcache.WriteReq_mshr_misses::total 83 # number of WriteReq MSHR misses 652system.cpu.dcache.demand_mshr_misses::cpu.data 148 # number of demand (read+write) MSHR misses 653system.cpu.dcache.demand_mshr_misses::total 148 # number of demand (read+write) MSHR misses 654system.cpu.dcache.overall_mshr_misses::cpu.data 148 # number of overall MSHR misses 655system.cpu.dcache.overall_mshr_misses::total 148 # number of overall MSHR misses 656system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6078000 # number of ReadReq MSHR miss cycles 657system.cpu.dcache.ReadReq_mshr_miss_latency::total 6078000 # number of ReadReq MSHR miss cycles 658system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6888000 # number of WriteReq MSHR miss cycles 659system.cpu.dcache.WriteReq_mshr_miss_latency::total 6888000 # number of WriteReq MSHR miss cycles 660system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12966000 # number of demand (read+write) MSHR miss cycles 661system.cpu.dcache.demand_mshr_miss_latency::total 12966000 # number of demand (read+write) MSHR miss cycles 662system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12966000 # number of overall MSHR miss cycles 663system.cpu.dcache.overall_mshr_miss_latency::total 12966000 # number of overall MSHR miss cycles 664system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017639 # mshr miss rate for ReadReq accesses 665system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017639 # mshr miss rate for ReadReq accesses 666system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.057559 # mshr miss rate for WriteReq accesses 667system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.057559 # mshr miss rate for WriteReq accesses 668system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.028867 # mshr miss rate for demand accesses 669system.cpu.dcache.demand_mshr_miss_rate::total 0.028867 # mshr miss rate for demand accesses 670system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028867 # mshr miss rate for overall accesses 671system.cpu.dcache.overall_mshr_miss_rate::total 0.028867 # mshr miss rate for overall accesses 672system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 93507.692308 # average ReadReq mshr miss latency 673system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 93507.692308 # average ReadReq mshr miss latency 674system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 82987.951807 # average WriteReq mshr miss latency 675system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 82987.951807 # average WriteReq mshr miss latency 676system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 87608.108108 # average overall mshr miss latency 677system.cpu.dcache.demand_avg_mshr_miss_latency::total 87608.108108 # average overall mshr miss latency 678system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 87608.108108 # average overall mshr miss latency 679system.cpu.dcache.overall_avg_mshr_miss_latency::total 87608.108108 # average overall mshr miss latency 680system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 29908500 # Cumulative time (in ticks) in various power states 681system.cpu.icache.tags.replacements 0 # number of replacements 682system.cpu.icache.tags.tagsinuse 204.747820 # Cycle average of tags in use 683system.cpu.icache.tags.total_refs 6856 # Total number of references to valid blocks. 684system.cpu.icache.tags.sampled_refs 367 # Sample count of references to valid blocks. 685system.cpu.icache.tags.avg_refs 18.681199 # Average number of references to valid blocks. 686system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 687system.cpu.icache.tags.occ_blocks::cpu.inst 204.747820 # Average occupied blocks per requestor 688system.cpu.icache.tags.occ_percent::cpu.inst 0.099975 # Average percentage of cache occupancy 689system.cpu.icache.tags.occ_percent::total 0.099975 # Average percentage of cache occupancy 690system.cpu.icache.tags.occ_task_id_blocks::1024 367 # Occupied blocks per task id 691system.cpu.icache.tags.age_task_id_blocks_1024::0 92 # Occupied blocks per task id 692system.cpu.icache.tags.age_task_id_blocks_1024::1 275 # Occupied blocks per task id 693system.cpu.icache.tags.occ_task_id_percent::1024 0.179199 # Percentage of cache occupancy per task id 694system.cpu.icache.tags.tag_accesses 15259 # Number of tag accesses 695system.cpu.icache.tags.data_accesses 15259 # Number of data accesses 696system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 29908500 # Cumulative time (in ticks) in various power states 697system.cpu.icache.ReadReq_hits::cpu.inst 6856 # number of ReadReq hits 698system.cpu.icache.ReadReq_hits::total 6856 # number of ReadReq hits 699system.cpu.icache.demand_hits::cpu.inst 6856 # number of demand (read+write) hits 700system.cpu.icache.demand_hits::total 6856 # number of demand (read+write) hits 701system.cpu.icache.overall_hits::cpu.inst 6856 # number of overall hits 702system.cpu.icache.overall_hits::total 6856 # number of overall hits 703system.cpu.icache.ReadReq_misses::cpu.inst 590 # number of ReadReq misses 704system.cpu.icache.ReadReq_misses::total 590 # number of ReadReq misses 705system.cpu.icache.demand_misses::cpu.inst 590 # number of demand (read+write) misses 706system.cpu.icache.demand_misses::total 590 # number of demand (read+write) misses 707system.cpu.icache.overall_misses::cpu.inst 590 # number of overall misses 708system.cpu.icache.overall_misses::total 590 # number of overall misses 709system.cpu.icache.ReadReq_miss_latency::cpu.inst 45891500 # number of ReadReq miss cycles 710system.cpu.icache.ReadReq_miss_latency::total 45891500 # number of ReadReq miss cycles 711system.cpu.icache.demand_miss_latency::cpu.inst 45891500 # number of demand (read+write) miss cycles 712system.cpu.icache.demand_miss_latency::total 45891500 # number of demand (read+write) miss cycles 713system.cpu.icache.overall_miss_latency::cpu.inst 45891500 # number of overall miss cycles 714system.cpu.icache.overall_miss_latency::total 45891500 # number of overall miss cycles 715system.cpu.icache.ReadReq_accesses::cpu.inst 7446 # number of ReadReq accesses(hits+misses) 716system.cpu.icache.ReadReq_accesses::total 7446 # number of ReadReq accesses(hits+misses) 717system.cpu.icache.demand_accesses::cpu.inst 7446 # number of demand (read+write) accesses 718system.cpu.icache.demand_accesses::total 7446 # number of demand (read+write) accesses 719system.cpu.icache.overall_accesses::cpu.inst 7446 # number of overall (read+write) accesses 720system.cpu.icache.overall_accesses::total 7446 # number of overall (read+write) accesses 721system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.079237 # miss rate for ReadReq accesses 722system.cpu.icache.ReadReq_miss_rate::total 0.079237 # miss rate for ReadReq accesses 723system.cpu.icache.demand_miss_rate::cpu.inst 0.079237 # miss rate for demand accesses 724system.cpu.icache.demand_miss_rate::total 0.079237 # miss rate for demand accesses 725system.cpu.icache.overall_miss_rate::cpu.inst 0.079237 # miss rate for overall accesses 726system.cpu.icache.overall_miss_rate::total 0.079237 # miss rate for overall accesses 727system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77782.203390 # average ReadReq miss latency 728system.cpu.icache.ReadReq_avg_miss_latency::total 77782.203390 # average ReadReq miss latency 729system.cpu.icache.demand_avg_miss_latency::cpu.inst 77782.203390 # average overall miss latency 730system.cpu.icache.demand_avg_miss_latency::total 77782.203390 # average overall miss latency 731system.cpu.icache.overall_avg_miss_latency::cpu.inst 77782.203390 # average overall miss latency 732system.cpu.icache.overall_avg_miss_latency::total 77782.203390 # average overall miss latency 733system.cpu.icache.blocked_cycles::no_mshrs 123 # number of cycles access was blocked 734system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 735system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked 736system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 737system.cpu.icache.avg_blocked_cycles::no_mshrs 123 # average number of cycles each access was blocked 738system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 739system.cpu.icache.ReadReq_mshr_hits::cpu.inst 223 # number of ReadReq MSHR hits 740system.cpu.icache.ReadReq_mshr_hits::total 223 # number of ReadReq MSHR hits 741system.cpu.icache.demand_mshr_hits::cpu.inst 223 # number of demand (read+write) MSHR hits 742system.cpu.icache.demand_mshr_hits::total 223 # number of demand (read+write) MSHR hits 743system.cpu.icache.overall_mshr_hits::cpu.inst 223 # number of overall MSHR hits 744system.cpu.icache.overall_mshr_hits::total 223 # number of overall MSHR hits 745system.cpu.icache.ReadReq_mshr_misses::cpu.inst 367 # number of ReadReq MSHR misses 746system.cpu.icache.ReadReq_mshr_misses::total 367 # number of ReadReq MSHR misses 747system.cpu.icache.demand_mshr_misses::cpu.inst 367 # number of demand (read+write) MSHR misses 748system.cpu.icache.demand_mshr_misses::total 367 # number of demand (read+write) MSHR misses 749system.cpu.icache.overall_mshr_misses::cpu.inst 367 # number of overall MSHR misses 750system.cpu.icache.overall_mshr_misses::total 367 # number of overall MSHR misses 751system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 30257500 # number of ReadReq MSHR miss cycles 752system.cpu.icache.ReadReq_mshr_miss_latency::total 30257500 # number of ReadReq MSHR miss cycles 753system.cpu.icache.demand_mshr_miss_latency::cpu.inst 30257500 # number of demand (read+write) MSHR miss cycles 754system.cpu.icache.demand_mshr_miss_latency::total 30257500 # number of demand (read+write) MSHR miss cycles 755system.cpu.icache.overall_mshr_miss_latency::cpu.inst 30257500 # number of overall MSHR miss cycles 756system.cpu.icache.overall_mshr_miss_latency::total 30257500 # number of overall MSHR miss cycles 757system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.049288 # mshr miss rate for ReadReq accesses 758system.cpu.icache.ReadReq_mshr_miss_rate::total 0.049288 # mshr miss rate for ReadReq accesses 759system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.049288 # mshr miss rate for demand accesses 760system.cpu.icache.demand_mshr_miss_rate::total 0.049288 # mshr miss rate for demand accesses 761system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.049288 # mshr miss rate for overall accesses 762system.cpu.icache.overall_mshr_miss_rate::total 0.049288 # mshr miss rate for overall accesses 763system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 82445.504087 # average ReadReq mshr miss latency 764system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 82445.504087 # average ReadReq mshr miss latency 765system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 82445.504087 # average overall mshr miss latency 766system.cpu.icache.demand_avg_mshr_miss_latency::total 82445.504087 # average overall mshr miss latency 767system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 82445.504087 # average overall mshr miss latency 768system.cpu.icache.overall_avg_mshr_miss_latency::total 82445.504087 # average overall mshr miss latency 769system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 29908500 # Cumulative time (in ticks) in various power states 770system.cpu.l2cache.tags.replacements 0 # number of replacements 771system.cpu.l2cache.tags.tagsinuse 303.316506 # Cycle average of tags in use 772system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. 773system.cpu.l2cache.tags.sampled_refs 511 # Sample count of references to valid blocks. 774system.cpu.l2cache.tags.avg_refs 0.003914 # Average number of references to valid blocks. 775system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 776system.cpu.l2cache.tags.occ_blocks::cpu.inst 204.106814 # Average occupied blocks per requestor 777system.cpu.l2cache.tags.occ_blocks::cpu.data 99.209691 # Average occupied blocks per requestor 778system.cpu.l2cache.tags.occ_percent::cpu.inst 0.006229 # Average percentage of cache occupancy 779system.cpu.l2cache.tags.occ_percent::cpu.data 0.003028 # Average percentage of cache occupancy 780system.cpu.l2cache.tags.occ_percent::total 0.009256 # Average percentage of cache occupancy 781system.cpu.l2cache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id 782system.cpu.l2cache.tags.age_task_id_blocks_1024::0 112 # Occupied blocks per task id 783system.cpu.l2cache.tags.age_task_id_blocks_1024::1 399 # Occupied blocks per task id 784system.cpu.l2cache.tags.occ_task_id_percent::1024 0.015594 # Percentage of cache occupancy per task id 785system.cpu.l2cache.tags.tag_accesses 4631 # Number of tag accesses 786system.cpu.l2cache.tags.data_accesses 4631 # Number of data accesses 787system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 29908500 # Cumulative time (in ticks) in various power states 788system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2 # number of ReadCleanReq hits 789system.cpu.l2cache.ReadCleanReq_hits::total 2 # number of ReadCleanReq hits 790system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits 791system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits 792system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits 793system.cpu.l2cache.overall_hits::total 2 # number of overall hits 794system.cpu.l2cache.ReadExReq_misses::cpu.data 83 # number of ReadExReq misses 795system.cpu.l2cache.ReadExReq_misses::total 83 # number of ReadExReq misses 796system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 365 # number of ReadCleanReq misses 797system.cpu.l2cache.ReadCleanReq_misses::total 365 # number of ReadCleanReq misses 798system.cpu.l2cache.ReadSharedReq_misses::cpu.data 65 # number of ReadSharedReq misses 799system.cpu.l2cache.ReadSharedReq_misses::total 65 # number of ReadSharedReq misses 800system.cpu.l2cache.demand_misses::cpu.inst 365 # number of demand (read+write) misses 801system.cpu.l2cache.demand_misses::cpu.data 148 # number of demand (read+write) misses 802system.cpu.l2cache.demand_misses::total 513 # number of demand (read+write) misses 803system.cpu.l2cache.overall_misses::cpu.inst 365 # number of overall misses 804system.cpu.l2cache.overall_misses::cpu.data 148 # number of overall misses 805system.cpu.l2cache.overall_misses::total 513 # number of overall misses 806system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6762500 # number of ReadExReq miss cycles 807system.cpu.l2cache.ReadExReq_miss_latency::total 6762500 # number of ReadExReq miss cycles 808system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 29684000 # number of ReadCleanReq miss cycles 809system.cpu.l2cache.ReadCleanReq_miss_latency::total 29684000 # number of ReadCleanReq miss cycles 810system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 5983000 # number of ReadSharedReq miss cycles 811system.cpu.l2cache.ReadSharedReq_miss_latency::total 5983000 # number of ReadSharedReq miss cycles 812system.cpu.l2cache.demand_miss_latency::cpu.inst 29684000 # number of demand (read+write) miss cycles 813system.cpu.l2cache.demand_miss_latency::cpu.data 12745500 # number of demand (read+write) miss cycles 814system.cpu.l2cache.demand_miss_latency::total 42429500 # number of demand (read+write) miss cycles 815system.cpu.l2cache.overall_miss_latency::cpu.inst 29684000 # number of overall miss cycles 816system.cpu.l2cache.overall_miss_latency::cpu.data 12745500 # number of overall miss cycles 817system.cpu.l2cache.overall_miss_latency::total 42429500 # number of overall miss cycles 818system.cpu.l2cache.ReadExReq_accesses::cpu.data 83 # number of ReadExReq accesses(hits+misses) 819system.cpu.l2cache.ReadExReq_accesses::total 83 # number of ReadExReq accesses(hits+misses) 820system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 367 # number of ReadCleanReq accesses(hits+misses) 821system.cpu.l2cache.ReadCleanReq_accesses::total 367 # number of ReadCleanReq accesses(hits+misses) 822system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 65 # number of ReadSharedReq accesses(hits+misses) 823system.cpu.l2cache.ReadSharedReq_accesses::total 65 # number of ReadSharedReq accesses(hits+misses) 824system.cpu.l2cache.demand_accesses::cpu.inst 367 # number of demand (read+write) accesses 825system.cpu.l2cache.demand_accesses::cpu.data 148 # number of demand (read+write) accesses 826system.cpu.l2cache.demand_accesses::total 515 # number of demand (read+write) accesses 827system.cpu.l2cache.overall_accesses::cpu.inst 367 # number of overall (read+write) accesses 828system.cpu.l2cache.overall_accesses::cpu.data 148 # number of overall (read+write) accesses 829system.cpu.l2cache.overall_accesses::total 515 # number of overall (read+write) accesses 830system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 831system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 832system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.994550 # miss rate for ReadCleanReq accesses 833system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.994550 # miss rate for ReadCleanReq accesses 834system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses 835system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses 836system.cpu.l2cache.demand_miss_rate::cpu.inst 0.994550 # miss rate for demand accesses 837system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 838system.cpu.l2cache.demand_miss_rate::total 0.996117 # miss rate for demand accesses 839system.cpu.l2cache.overall_miss_rate::cpu.inst 0.994550 # miss rate for overall accesses 840system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 841system.cpu.l2cache.overall_miss_rate::total 0.996117 # miss rate for overall accesses 842system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81475.903614 # average ReadExReq miss latency 843system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81475.903614 # average ReadExReq miss latency 844system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 81326.027397 # average ReadCleanReq miss latency 845system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 81326.027397 # average ReadCleanReq miss latency 846system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 92046.153846 # average ReadSharedReq miss latency 847system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 92046.153846 # average ReadSharedReq miss latency 848system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81326.027397 # average overall miss latency 849system.cpu.l2cache.demand_avg_miss_latency::cpu.data 86118.243243 # average overall miss latency 850system.cpu.l2cache.demand_avg_miss_latency::total 82708.576998 # average overall miss latency 851system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81326.027397 # average overall miss latency 852system.cpu.l2cache.overall_avg_miss_latency::cpu.data 86118.243243 # average overall miss latency 853system.cpu.l2cache.overall_avg_miss_latency::total 82708.576998 # average overall miss latency 854system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 855system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 856system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 857system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 858system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 859system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 860system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 83 # number of ReadExReq MSHR misses 861system.cpu.l2cache.ReadExReq_mshr_misses::total 83 # number of ReadExReq MSHR misses 862system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 365 # number of ReadCleanReq MSHR misses 863system.cpu.l2cache.ReadCleanReq_mshr_misses::total 365 # number of ReadCleanReq MSHR misses 864system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 65 # number of ReadSharedReq MSHR misses 865system.cpu.l2cache.ReadSharedReq_mshr_misses::total 65 # number of ReadSharedReq MSHR misses 866system.cpu.l2cache.demand_mshr_misses::cpu.inst 365 # number of demand (read+write) MSHR misses 867system.cpu.l2cache.demand_mshr_misses::cpu.data 148 # number of demand (read+write) MSHR misses 868system.cpu.l2cache.demand_mshr_misses::total 513 # number of demand (read+write) MSHR misses 869system.cpu.l2cache.overall_mshr_misses::cpu.inst 365 # number of overall MSHR misses 870system.cpu.l2cache.overall_mshr_misses::cpu.data 148 # number of overall MSHR misses 871system.cpu.l2cache.overall_mshr_misses::total 513 # number of overall MSHR misses 872system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5932500 # number of ReadExReq MSHR miss cycles 873system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5932500 # number of ReadExReq MSHR miss cycles 874system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 26034000 # number of ReadCleanReq MSHR miss cycles 875system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 26034000 # number of ReadCleanReq MSHR miss cycles 876system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5353000 # number of ReadSharedReq MSHR miss cycles 877system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5353000 # number of ReadSharedReq MSHR miss cycles 878system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 26034000 # number of demand (read+write) MSHR miss cycles 879system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11285500 # number of demand (read+write) MSHR miss cycles 880system.cpu.l2cache.demand_mshr_miss_latency::total 37319500 # number of demand (read+write) MSHR miss cycles 881system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 26034000 # number of overall MSHR miss cycles 882system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11285500 # number of overall MSHR miss cycles 883system.cpu.l2cache.overall_mshr_miss_latency::total 37319500 # number of overall MSHR miss cycles 884system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 885system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 886system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.994550 # mshr miss rate for ReadCleanReq accesses 887system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.994550 # mshr miss rate for ReadCleanReq accesses 888system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses 889system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses 890system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.994550 # mshr miss rate for demand accesses 891system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 892system.cpu.l2cache.demand_mshr_miss_rate::total 0.996117 # mshr miss rate for demand accesses 893system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.994550 # mshr miss rate for overall accesses 894system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 895system.cpu.l2cache.overall_mshr_miss_rate::total 0.996117 # mshr miss rate for overall accesses 896system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71475.903614 # average ReadExReq mshr miss latency 897system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71475.903614 # average ReadExReq mshr miss latency 898system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 71326.027397 # average ReadCleanReq mshr miss latency 899system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 71326.027397 # average ReadCleanReq mshr miss latency 900system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 82353.846154 # average ReadSharedReq mshr miss latency 901system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 82353.846154 # average ReadSharedReq mshr miss latency 902system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71326.027397 # average overall mshr miss latency 903system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 76253.378378 # average overall mshr miss latency 904system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72747.563353 # average overall mshr miss latency 905system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71326.027397 # average overall mshr miss latency 906system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 76253.378378 # average overall mshr miss latency 907system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72747.563353 # average overall mshr miss latency 908system.cpu.toL2Bus.snoop_filter.tot_requests 515 # Total number of requests made to the snoop filter. 909system.cpu.toL2Bus.snoop_filter.hit_single_requests 2 # Number of requests hitting in the snoop filter with a single holder of the requested data. 910system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 911system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 912system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 913system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 914system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 29908500 # Cumulative time (in ticks) in various power states 915system.cpu.toL2Bus.trans_dist::ReadResp 430 # Transaction distribution 916system.cpu.toL2Bus.trans_dist::ReadExReq 83 # Transaction distribution 917system.cpu.toL2Bus.trans_dist::ReadExResp 83 # Transaction distribution 918system.cpu.toL2Bus.trans_dist::ReadCleanReq 367 # Transaction distribution 919system.cpu.toL2Bus.trans_dist::ReadSharedReq 65 # Transaction distribution 920system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 734 # Packet count per connected master and slave (bytes) 921system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 294 # Packet count per connected master and slave (bytes) 922system.cpu.toL2Bus.pkt_count::total 1028 # Packet count per connected master and slave (bytes) 923system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23488 # Cumulative packet size per connected master and slave (bytes) 924system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes) 925system.cpu.toL2Bus.pkt_size::total 32832 # Cumulative packet size per connected master and slave (bytes) 926system.cpu.toL2Bus.snoops 0 # Total snoops (count) 927system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) 928system.cpu.toL2Bus.snoop_fanout::samples 515 # Request fanout histogram 929system.cpu.toL2Bus.snoop_fanout::mean 0.003883 # Request fanout histogram 930system.cpu.toL2Bus.snoop_fanout::stdev 0.062257 # Request fanout histogram 931system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 932system.cpu.toL2Bus.snoop_fanout::0 513 99.61% 99.61% # Request fanout histogram 933system.cpu.toL2Bus.snoop_fanout::1 2 0.39% 100.00% # Request fanout histogram 934system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 935system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 936system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 937system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 938system.cpu.toL2Bus.snoop_fanout::total 515 # Request fanout histogram 939system.cpu.toL2Bus.reqLayer0.occupancy 257500 # Layer occupancy (ticks) 940system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) 941system.cpu.toL2Bus.respLayer0.occupancy 550500 # Layer occupancy (ticks) 942system.cpu.toL2Bus.respLayer0.utilization 1.8 # Layer utilization (%) 943system.cpu.toL2Bus.respLayer1.occupancy 219000 # Layer occupancy (ticks) 944system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) 945system.membus.snoop_filter.tot_requests 513 # Total number of requests made to the snoop filter. 946system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. 947system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 948system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 949system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 950system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 951system.membus.pwrStateResidencyTicks::UNDEFINED 29908500 # Cumulative time (in ticks) in various power states 952system.membus.trans_dist::ReadResp 428 # Transaction distribution 953system.membus.trans_dist::ReadExReq 83 # Transaction distribution 954system.membus.trans_dist::ReadExResp 83 # Transaction distribution 955system.membus.trans_dist::ReadSharedReq 430 # Transaction distribution 956system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1024 # Packet count per connected master and slave (bytes) 957system.membus.pkt_count::total 1024 # Packet count per connected master and slave (bytes) 958system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 32704 # Cumulative packet size per connected master and slave (bytes) 959system.membus.pkt_size::total 32704 # Cumulative packet size per connected master and slave (bytes) 960system.membus.snoops 0 # Total snoops (count) 961system.membus.snoopTraffic 0 # Total snoop traffic (bytes) 962system.membus.snoop_fanout::samples 513 # Request fanout histogram 963system.membus.snoop_fanout::mean 0 # Request fanout histogram 964system.membus.snoop_fanout::stdev 0 # Request fanout histogram 965system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 966system.membus.snoop_fanout::0 513 100.00% 100.00% # Request fanout histogram 967system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 968system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 969system.membus.snoop_fanout::min_value 0 # Request fanout histogram 970system.membus.snoop_fanout::max_value 0 # Request fanout histogram 971system.membus.snoop_fanout::total 513 # Request fanout histogram 972system.membus.reqLayer0.occupancy 627500 # Layer occupancy (ticks) 973system.membus.reqLayer0.utilization 2.1 # Layer utilization (%) 974system.membus.respLayer1.occupancy 2707250 # Layer occupancy (ticks) 975system.membus.respLayer1.utilization 9.1 # Layer utilization (%) 976 977---------- End Simulation Statistics ---------- 978