simout revision 9481:b0fa6b872f40 
1Redirecting stdout to build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing/simout
2Redirecting stderr to build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing/simerr
3gem5 Simulator System.  http://gem5.org
4gem5 is copyrighted software; use the --copyright option for details.
5
6gem5 compiled Jan 23 2013 15:49:24
7gem5 started Jan 23 2013 16:08:16
8gem5 executing on ribera.cs.wisc.edu
9command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing -re tests/run.py build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing
10Global frequency set at 1000000000000 ticks per second
11info: Entering event queue @ 0.  Starting simulation...
12Begining test of difficult SPARC instructions...
13LDSTUB:		Passed
14SWAP:		Passed
15CAS FAIL:	Passed
16CAS WORK:	Passed
17CASX FAIL:	Passed
18CASX WORK:	Passed
19LDTX:		Passed
20LDTW:		Passed
21STTW:		Passed
22Done
23Exiting @ tick 23180500 because target called exit()
24