config.ini revision 11440:76b5639162af
1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain 17eventq_index=0 18exit_on_work_items=false 19init_param=0 20kernel= 21kernel_addr_check=true 22load_addr_mask=1099511627775 23load_offset=0 24mem_mode=timing 25mem_ranges= 26memories=system.physmem 27mmap_using_noreserve=false 28multi_thread=false 29num_work_ids=16 30readfile= 31symbolfile= 32thermal_components= 33thermal_model=Null 34work_begin_ckpt_count=0 35work_begin_cpu_id_exit=-1 36work_begin_exit_count=0 37work_cpus_ckpt_count=0 38work_end_ckpt_count=0 39work_end_exit_count=0 40work_item_id=-1 41system_port=system.membus.slave[0] 42 43[system.clk_domain] 44type=SrcClockDomain 45clock=1000 46domain_id=-1 47eventq_index=0 48init_perf_level=0 49voltage_domain=system.voltage_domain 50 51[system.cpu] 52type=DerivO3CPU 53children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload 54LFSTSize=1024 55LQEntries=32 56LSQCheckLoads=true 57LSQDepCheckShift=4 58SQEntries=32 59SSITSize=1024 60activity=0 61backComSize=5 62branchPred=system.cpu.branchPred 63cachePorts=200 64checker=Null 65clk_domain=system.cpu_clk_domain 66commitToDecodeDelay=1 67commitToFetchDelay=1 68commitToIEWDelay=1 69commitToRenameDelay=1 70commitWidth=8 71cpu_id=0 72decodeToFetchDelay=1 73decodeToRenameDelay=1 74decodeWidth=8 75dispatchWidth=8 76do_checkpoint_insts=true 77do_quiesce=true 78do_statistics_insts=true 79dtb=system.cpu.dtb 80eventq_index=0 81fetchBufferSize=64 82fetchQueueSize=32 83fetchToDecodeDelay=1 84fetchTrapLatency=1 85fetchWidth=8 86forwardComSize=5 87fuPool=system.cpu.fuPool 88function_trace=false 89function_trace_start=0 90iewToCommitDelay=1 91iewToDecodeDelay=1 92iewToFetchDelay=1 93iewToRenameDelay=1 94interrupts=system.cpu.interrupts 95isa=system.cpu.isa 96issueToExecuteDelay=1 97issueWidth=8 98itb=system.cpu.itb 99max_insts_all_threads=0 100max_insts_any_thread=0 101max_loads_all_threads=0 102max_loads_any_thread=0 103needsTSO=false 104numIQEntries=64 105numPhysCCRegs=0 106numPhysFloatRegs=256 107numPhysIntRegs=256 108numROBEntries=192 109numRobs=1 110numThreads=1 111profile=0 112progress_interval=0 113renameToDecodeDelay=1 114renameToFetchDelay=1 115renameToIEWDelay=2 116renameToROBDelay=1 117renameWidth=8 118simpoint_start_insts= 119smtCommitPolicy=RoundRobin 120smtFetchPolicy=SingleThread 121smtIQPolicy=Partitioned 122smtIQThreshold=100 123smtLSQPolicy=Partitioned 124smtLSQThreshold=100 125smtNumFetchingThreads=1 126smtROBPolicy=Partitioned 127smtROBThreshold=100 128socket_id=0 129squashWidth=8 130store_set_clear_period=250000 131switched_out=false 132system=system 133tracer=system.cpu.tracer 134trapLatency=13 135wbWidth=8 136workload=system.cpu.workload 137dcache_port=system.cpu.dcache.cpu_side 138icache_port=system.cpu.icache.cpu_side 139 140[system.cpu.branchPred] 141type=TournamentBP 142BTBEntries=4096 143BTBTagSize=16 144RASSize=16 145choiceCtrBits=2 146choicePredictorSize=8192 147eventq_index=0 148globalCtrBits=2 149globalPredictorSize=8192 150indirectHashGHR=true 151indirectHashTargets=true 152indirectPathLength=3 153indirectSets=256 154indirectTagSize=16 155indirectWays=2 156instShiftAmt=2 157localCtrBits=2 158localHistoryTableSize=2048 159localPredictorSize=2048 160numThreads=1 161useIndirect=true 162 163[system.cpu.dcache] 164type=Cache 165children=tags 166addr_ranges=0:18446744073709551615 167assoc=2 168clk_domain=system.cpu_clk_domain 169clusivity=mostly_incl 170demand_mshr_reserve=1 171eventq_index=0 172hit_latency=2 173is_read_only=false 174max_miss_count=0 175mshrs=4 176prefetch_on_access=false 177prefetcher=Null 178response_latency=2 179sequential_access=false 180size=262144 181system=system 182tags=system.cpu.dcache.tags 183tgts_per_mshr=20 184write_buffers=8 185writeback_clean=false 186cpu_side=system.cpu.dcache_port 187mem_side=system.cpu.toL2Bus.slave[1] 188 189[system.cpu.dcache.tags] 190type=LRU 191assoc=2 192block_size=64 193clk_domain=system.cpu_clk_domain 194eventq_index=0 195hit_latency=2 196sequential_access=false 197size=262144 198 199[system.cpu.dtb] 200type=SparcTLB 201eventq_index=0 202size=64 203 204[system.cpu.fuPool] 205type=FUPool 206children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 207FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 208eventq_index=0 209 210[system.cpu.fuPool.FUList0] 211type=FUDesc 212children=opList 213count=6 214eventq_index=0 215opList=system.cpu.fuPool.FUList0.opList 216 217[system.cpu.fuPool.FUList0.opList] 218type=OpDesc 219eventq_index=0 220opClass=IntAlu 221opLat=1 222pipelined=true 223 224[system.cpu.fuPool.FUList1] 225type=FUDesc 226children=opList0 opList1 227count=2 228eventq_index=0 229opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 230 231[system.cpu.fuPool.FUList1.opList0] 232type=OpDesc 233eventq_index=0 234opClass=IntMult 235opLat=3 236pipelined=true 237 238[system.cpu.fuPool.FUList1.opList1] 239type=OpDesc 240eventq_index=0 241opClass=IntDiv 242opLat=20 243pipelined=false 244 245[system.cpu.fuPool.FUList2] 246type=FUDesc 247children=opList0 opList1 opList2 248count=4 249eventq_index=0 250opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 251 252[system.cpu.fuPool.FUList2.opList0] 253type=OpDesc 254eventq_index=0 255opClass=FloatAdd 256opLat=2 257pipelined=true 258 259[system.cpu.fuPool.FUList2.opList1] 260type=OpDesc 261eventq_index=0 262opClass=FloatCmp 263opLat=2 264pipelined=true 265 266[system.cpu.fuPool.FUList2.opList2] 267type=OpDesc 268eventq_index=0 269opClass=FloatCvt 270opLat=2 271pipelined=true 272 273[system.cpu.fuPool.FUList3] 274type=FUDesc 275children=opList0 opList1 opList2 276count=2 277eventq_index=0 278opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 279 280[system.cpu.fuPool.FUList3.opList0] 281type=OpDesc 282eventq_index=0 283opClass=FloatMult 284opLat=4 285pipelined=true 286 287[system.cpu.fuPool.FUList3.opList1] 288type=OpDesc 289eventq_index=0 290opClass=FloatDiv 291opLat=12 292pipelined=false 293 294[system.cpu.fuPool.FUList3.opList2] 295type=OpDesc 296eventq_index=0 297opClass=FloatSqrt 298opLat=24 299pipelined=false 300 301[system.cpu.fuPool.FUList4] 302type=FUDesc 303children=opList 304count=0 305eventq_index=0 306opList=system.cpu.fuPool.FUList4.opList 307 308[system.cpu.fuPool.FUList4.opList] 309type=OpDesc 310eventq_index=0 311opClass=MemRead 312opLat=1 313pipelined=true 314 315[system.cpu.fuPool.FUList5] 316type=FUDesc 317children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 318count=4 319eventq_index=0 320opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 321 322[system.cpu.fuPool.FUList5.opList00] 323type=OpDesc 324eventq_index=0 325opClass=SimdAdd 326opLat=1 327pipelined=true 328 329[system.cpu.fuPool.FUList5.opList01] 330type=OpDesc 331eventq_index=0 332opClass=SimdAddAcc 333opLat=1 334pipelined=true 335 336[system.cpu.fuPool.FUList5.opList02] 337type=OpDesc 338eventq_index=0 339opClass=SimdAlu 340opLat=1 341pipelined=true 342 343[system.cpu.fuPool.FUList5.opList03] 344type=OpDesc 345eventq_index=0 346opClass=SimdCmp 347opLat=1 348pipelined=true 349 350[system.cpu.fuPool.FUList5.opList04] 351type=OpDesc 352eventq_index=0 353opClass=SimdCvt 354opLat=1 355pipelined=true 356 357[system.cpu.fuPool.FUList5.opList05] 358type=OpDesc 359eventq_index=0 360opClass=SimdMisc 361opLat=1 362pipelined=true 363 364[system.cpu.fuPool.FUList5.opList06] 365type=OpDesc 366eventq_index=0 367opClass=SimdMult 368opLat=1 369pipelined=true 370 371[system.cpu.fuPool.FUList5.opList07] 372type=OpDesc 373eventq_index=0 374opClass=SimdMultAcc 375opLat=1 376pipelined=true 377 378[system.cpu.fuPool.FUList5.opList08] 379type=OpDesc 380eventq_index=0 381opClass=SimdShift 382opLat=1 383pipelined=true 384 385[system.cpu.fuPool.FUList5.opList09] 386type=OpDesc 387eventq_index=0 388opClass=SimdShiftAcc 389opLat=1 390pipelined=true 391 392[system.cpu.fuPool.FUList5.opList10] 393type=OpDesc 394eventq_index=0 395opClass=SimdSqrt 396opLat=1 397pipelined=true 398 399[system.cpu.fuPool.FUList5.opList11] 400type=OpDesc 401eventq_index=0 402opClass=SimdFloatAdd 403opLat=1 404pipelined=true 405 406[system.cpu.fuPool.FUList5.opList12] 407type=OpDesc 408eventq_index=0 409opClass=SimdFloatAlu 410opLat=1 411pipelined=true 412 413[system.cpu.fuPool.FUList5.opList13] 414type=OpDesc 415eventq_index=0 416opClass=SimdFloatCmp 417opLat=1 418pipelined=true 419 420[system.cpu.fuPool.FUList5.opList14] 421type=OpDesc 422eventq_index=0 423opClass=SimdFloatCvt 424opLat=1 425pipelined=true 426 427[system.cpu.fuPool.FUList5.opList15] 428type=OpDesc 429eventq_index=0 430opClass=SimdFloatDiv 431opLat=1 432pipelined=true 433 434[system.cpu.fuPool.FUList5.opList16] 435type=OpDesc 436eventq_index=0 437opClass=SimdFloatMisc 438opLat=1 439pipelined=true 440 441[system.cpu.fuPool.FUList5.opList17] 442type=OpDesc 443eventq_index=0 444opClass=SimdFloatMult 445opLat=1 446pipelined=true 447 448[system.cpu.fuPool.FUList5.opList18] 449type=OpDesc 450eventq_index=0 451opClass=SimdFloatMultAcc 452opLat=1 453pipelined=true 454 455[system.cpu.fuPool.FUList5.opList19] 456type=OpDesc 457eventq_index=0 458opClass=SimdFloatSqrt 459opLat=1 460pipelined=true 461 462[system.cpu.fuPool.FUList6] 463type=FUDesc 464children=opList 465count=0 466eventq_index=0 467opList=system.cpu.fuPool.FUList6.opList 468 469[system.cpu.fuPool.FUList6.opList] 470type=OpDesc 471eventq_index=0 472opClass=MemWrite 473opLat=1 474pipelined=true 475 476[system.cpu.fuPool.FUList7] 477type=FUDesc 478children=opList0 opList1 479count=4 480eventq_index=0 481opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 482 483[system.cpu.fuPool.FUList7.opList0] 484type=OpDesc 485eventq_index=0 486opClass=MemRead 487opLat=1 488pipelined=true 489 490[system.cpu.fuPool.FUList7.opList1] 491type=OpDesc 492eventq_index=0 493opClass=MemWrite 494opLat=1 495pipelined=true 496 497[system.cpu.fuPool.FUList8] 498type=FUDesc 499children=opList 500count=1 501eventq_index=0 502opList=system.cpu.fuPool.FUList8.opList 503 504[system.cpu.fuPool.FUList8.opList] 505type=OpDesc 506eventq_index=0 507opClass=IprAccess 508opLat=3 509pipelined=false 510 511[system.cpu.icache] 512type=Cache 513children=tags 514addr_ranges=0:18446744073709551615 515assoc=2 516clk_domain=system.cpu_clk_domain 517clusivity=mostly_incl 518demand_mshr_reserve=1 519eventq_index=0 520hit_latency=2 521is_read_only=true 522max_miss_count=0 523mshrs=4 524prefetch_on_access=false 525prefetcher=Null 526response_latency=2 527sequential_access=false 528size=131072 529system=system 530tags=system.cpu.icache.tags 531tgts_per_mshr=20 532write_buffers=8 533writeback_clean=true 534cpu_side=system.cpu.icache_port 535mem_side=system.cpu.toL2Bus.slave[0] 536 537[system.cpu.icache.tags] 538type=LRU 539assoc=2 540block_size=64 541clk_domain=system.cpu_clk_domain 542eventq_index=0 543hit_latency=2 544sequential_access=false 545size=131072 546 547[system.cpu.interrupts] 548type=SparcInterrupts 549eventq_index=0 550 551[system.cpu.isa] 552type=SparcISA 553eventq_index=0 554 555[system.cpu.itb] 556type=SparcTLB 557eventq_index=0 558size=64 559 560[system.cpu.l2cache] 561type=Cache 562children=tags 563addr_ranges=0:18446744073709551615 564assoc=8 565clk_domain=system.cpu_clk_domain 566clusivity=mostly_incl 567demand_mshr_reserve=1 568eventq_index=0 569hit_latency=20 570is_read_only=false 571max_miss_count=0 572mshrs=20 573prefetch_on_access=false 574prefetcher=Null 575response_latency=20 576sequential_access=false 577size=2097152 578system=system 579tags=system.cpu.l2cache.tags 580tgts_per_mshr=12 581write_buffers=8 582writeback_clean=false 583cpu_side=system.cpu.toL2Bus.master[0] 584mem_side=system.membus.slave[1] 585 586[system.cpu.l2cache.tags] 587type=LRU 588assoc=8 589block_size=64 590clk_domain=system.cpu_clk_domain 591eventq_index=0 592hit_latency=20 593sequential_access=false 594size=2097152 595 596[system.cpu.toL2Bus] 597type=CoherentXBar 598children=snoop_filter 599clk_domain=system.cpu_clk_domain 600eventq_index=0 601forward_latency=0 602frontend_latency=1 603point_of_coherency=false 604response_latency=1 605snoop_filter=system.cpu.toL2Bus.snoop_filter 606snoop_response_latency=1 607system=system 608use_default_range=false 609width=32 610master=system.cpu.l2cache.cpu_side 611slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side 612 613[system.cpu.toL2Bus.snoop_filter] 614type=SnoopFilter 615eventq_index=0 616lookup_latency=0 617max_capacity=8388608 618system=system 619 620[system.cpu.tracer] 621type=ExeTracer 622eventq_index=0 623 624[system.cpu.workload] 625type=LiveProcess 626cmd=insttest 627cwd= 628drivers= 629egid=100 630env= 631errout=cerr 632euid=100 633eventq_index=0 634executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/insttest/bin/sparc/linux/insttest 635gid=100 636input=cin 637kvmInSE=false 638max_stack_size=67108864 639output=cout 640pid=100 641ppid=99 642simpoint=0 643system=system 644uid=100 645useArchPT=false 646 647[system.cpu_clk_domain] 648type=SrcClockDomain 649clock=500 650domain_id=-1 651eventq_index=0 652init_perf_level=0 653voltage_domain=system.voltage_domain 654 655[system.dvfs_handler] 656type=DVFSHandler 657domains= 658enable=false 659eventq_index=0 660sys_clk_domain=system.clk_domain 661transition_latency=100000000 662 663[system.membus] 664type=CoherentXBar 665clk_domain=system.clk_domain 666eventq_index=0 667forward_latency=4 668frontend_latency=3 669point_of_coherency=true 670response_latency=2 671snoop_filter=Null 672snoop_response_latency=4 673system=system 674use_default_range=false 675width=16 676master=system.physmem.port 677slave=system.system_port system.cpu.l2cache.mem_side 678 679[system.physmem] 680type=DRAMCtrl 681IDD0=0.075000 682IDD02=0.000000 683IDD2N=0.050000 684IDD2N2=0.000000 685IDD2P0=0.000000 686IDD2P02=0.000000 687IDD2P1=0.000000 688IDD2P12=0.000000 689IDD3N=0.057000 690IDD3N2=0.000000 691IDD3P0=0.000000 692IDD3P02=0.000000 693IDD3P1=0.000000 694IDD3P12=0.000000 695IDD4R=0.187000 696IDD4R2=0.000000 697IDD4W=0.165000 698IDD4W2=0.000000 699IDD5=0.220000 700IDD52=0.000000 701IDD6=0.000000 702IDD62=0.000000 703VDD=1.500000 704VDD2=0.000000 705activation_limit=4 706addr_mapping=RoRaBaCoCh 707bank_groups_per_rank=0 708banks_per_rank=8 709burst_length=8 710channels=1 711clk_domain=system.clk_domain 712conf_table_reported=true 713device_bus_width=8 714device_rowbuffer_size=1024 715device_size=536870912 716devices_per_rank=8 717dll=true 718eventq_index=0 719in_addr_map=true 720max_accesses_per_row=16 721mem_sched_policy=frfcfs 722min_writes_per_switch=16 723null=false 724page_policy=open_adaptive 725range=0:134217727 726ranks_per_channel=2 727read_buffer_size=32 728static_backend_latency=10000 729static_frontend_latency=10000 730tBURST=5000 731tCCD_L=0 732tCK=1250 733tCL=13750 734tCS=2500 735tRAS=35000 736tRCD=13750 737tREFI=7800000 738tRFC=260000 739tRP=13750 740tRRD=6000 741tRRD_L=0 742tRTP=7500 743tRTW=2500 744tWR=15000 745tWTR=7500 746tXAW=30000 747tXP=0 748tXPDLL=0 749tXS=0 750tXSDLL=0 751write_buffer_size=64 752write_high_thresh_perc=85 753write_low_thresh_perc=50 754port=system.membus.master[0] 755 756[system.voltage_domain] 757type=VoltageDomain 758eventq_index=0 759voltage=1.000000 760 761