config.ini revision 11312:3d7a85d71bd1
1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain 17eventq_index=0 18exit_on_work_items=false 19init_param=0 20kernel= 21kernel_addr_check=true 22load_addr_mask=1099511627775 23load_offset=0 24mem_mode=timing 25mem_ranges= 26memories=system.physmem 27mmap_using_noreserve=false 28multi_thread=false 29num_work_ids=16 30readfile= 31symbolfile= 32work_begin_ckpt_count=0 33work_begin_cpu_id_exit=-1 34work_begin_exit_count=0 35work_cpus_ckpt_count=0 36work_end_ckpt_count=0 37work_end_exit_count=0 38work_item_id=-1 39system_port=system.membus.slave[0] 40 41[system.clk_domain] 42type=SrcClockDomain 43clock=1000 44domain_id=-1 45eventq_index=0 46init_perf_level=0 47voltage_domain=system.voltage_domain 48 49[system.cpu] 50type=DerivO3CPU 51children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload 52LFSTSize=1024 53LQEntries=32 54LSQCheckLoads=true 55LSQDepCheckShift=4 56SQEntries=32 57SSITSize=1024 58activity=0 59backComSize=5 60branchPred=system.cpu.branchPred 61cachePorts=200 62checker=Null 63clk_domain=system.cpu_clk_domain 64commitToDecodeDelay=1 65commitToFetchDelay=1 66commitToIEWDelay=1 67commitToRenameDelay=1 68commitWidth=8 69cpu_id=0 70decodeToFetchDelay=1 71decodeToRenameDelay=1 72decodeWidth=8 73dispatchWidth=8 74do_checkpoint_insts=true 75do_quiesce=true 76do_statistics_insts=true 77dtb=system.cpu.dtb 78eventq_index=0 79fetchBufferSize=64 80fetchQueueSize=32 81fetchToDecodeDelay=1 82fetchTrapLatency=1 83fetchWidth=8 84forwardComSize=5 85fuPool=system.cpu.fuPool 86function_trace=false 87function_trace_start=0 88iewToCommitDelay=1 89iewToDecodeDelay=1 90iewToFetchDelay=1 91iewToRenameDelay=1 92interrupts=system.cpu.interrupts 93isa=system.cpu.isa 94issueToExecuteDelay=1 95issueWidth=8 96itb=system.cpu.itb 97max_insts_all_threads=0 98max_insts_any_thread=0 99max_loads_all_threads=0 100max_loads_any_thread=0 101needsTSO=false 102numIQEntries=64 103numPhysCCRegs=0 104numPhysFloatRegs=256 105numPhysIntRegs=256 106numROBEntries=192 107numRobs=1 108numThreads=1 109profile=0 110progress_interval=0 111renameToDecodeDelay=1 112renameToFetchDelay=1 113renameToIEWDelay=2 114renameToROBDelay=1 115renameWidth=8 116simpoint_start_insts= 117smtCommitPolicy=RoundRobin 118smtFetchPolicy=SingleThread 119smtIQPolicy=Partitioned 120smtIQThreshold=100 121smtLSQPolicy=Partitioned 122smtLSQThreshold=100 123smtNumFetchingThreads=1 124smtROBPolicy=Partitioned 125smtROBThreshold=100 126socket_id=0 127squashWidth=8 128store_set_clear_period=250000 129switched_out=false 130system=system 131tracer=system.cpu.tracer 132trapLatency=13 133wbWidth=8 134workload=system.cpu.workload 135dcache_port=system.cpu.dcache.cpu_side 136icache_port=system.cpu.icache.cpu_side 137 138[system.cpu.branchPred] 139type=TournamentBP 140BTBEntries=4096 141BTBTagSize=16 142RASSize=16 143choiceCtrBits=2 144choicePredictorSize=8192 145eventq_index=0 146globalCtrBits=2 147globalPredictorSize=8192 148instShiftAmt=2 149localCtrBits=2 150localHistoryTableSize=2048 151localPredictorSize=2048 152numThreads=1 153 154[system.cpu.dcache] 155type=Cache 156children=tags 157addr_ranges=0:18446744073709551615 158assoc=2 159clk_domain=system.cpu_clk_domain 160clusivity=mostly_incl 161demand_mshr_reserve=1 162eventq_index=0 163forward_snoops=true 164hit_latency=2 165is_read_only=false 166max_miss_count=0 167mshrs=4 168prefetch_on_access=false 169prefetcher=Null 170response_latency=2 171sequential_access=false 172size=262144 173system=system 174tags=system.cpu.dcache.tags 175tgts_per_mshr=20 176write_buffers=8 177writeback_clean=false 178cpu_side=system.cpu.dcache_port 179mem_side=system.cpu.toL2Bus.slave[1] 180 181[system.cpu.dcache.tags] 182type=LRU 183assoc=2 184block_size=64 185clk_domain=system.cpu_clk_domain 186eventq_index=0 187hit_latency=2 188sequential_access=false 189size=262144 190 191[system.cpu.dtb] 192type=SparcTLB 193eventq_index=0 194size=64 195 196[system.cpu.fuPool] 197type=FUPool 198children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 199FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 200eventq_index=0 201 202[system.cpu.fuPool.FUList0] 203type=FUDesc 204children=opList 205count=6 206eventq_index=0 207opList=system.cpu.fuPool.FUList0.opList 208 209[system.cpu.fuPool.FUList0.opList] 210type=OpDesc 211eventq_index=0 212opClass=IntAlu 213opLat=1 214pipelined=true 215 216[system.cpu.fuPool.FUList1] 217type=FUDesc 218children=opList0 opList1 219count=2 220eventq_index=0 221opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 222 223[system.cpu.fuPool.FUList1.opList0] 224type=OpDesc 225eventq_index=0 226opClass=IntMult 227opLat=3 228pipelined=true 229 230[system.cpu.fuPool.FUList1.opList1] 231type=OpDesc 232eventq_index=0 233opClass=IntDiv 234opLat=20 235pipelined=false 236 237[system.cpu.fuPool.FUList2] 238type=FUDesc 239children=opList0 opList1 opList2 240count=4 241eventq_index=0 242opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 243 244[system.cpu.fuPool.FUList2.opList0] 245type=OpDesc 246eventq_index=0 247opClass=FloatAdd 248opLat=2 249pipelined=true 250 251[system.cpu.fuPool.FUList2.opList1] 252type=OpDesc 253eventq_index=0 254opClass=FloatCmp 255opLat=2 256pipelined=true 257 258[system.cpu.fuPool.FUList2.opList2] 259type=OpDesc 260eventq_index=0 261opClass=FloatCvt 262opLat=2 263pipelined=true 264 265[system.cpu.fuPool.FUList3] 266type=FUDesc 267children=opList0 opList1 opList2 268count=2 269eventq_index=0 270opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 271 272[system.cpu.fuPool.FUList3.opList0] 273type=OpDesc 274eventq_index=0 275opClass=FloatMult 276opLat=4 277pipelined=true 278 279[system.cpu.fuPool.FUList3.opList1] 280type=OpDesc 281eventq_index=0 282opClass=FloatDiv 283opLat=12 284pipelined=false 285 286[system.cpu.fuPool.FUList3.opList2] 287type=OpDesc 288eventq_index=0 289opClass=FloatSqrt 290opLat=24 291pipelined=false 292 293[system.cpu.fuPool.FUList4] 294type=FUDesc 295children=opList 296count=0 297eventq_index=0 298opList=system.cpu.fuPool.FUList4.opList 299 300[system.cpu.fuPool.FUList4.opList] 301type=OpDesc 302eventq_index=0 303opClass=MemRead 304opLat=1 305pipelined=true 306 307[system.cpu.fuPool.FUList5] 308type=FUDesc 309children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 310count=4 311eventq_index=0 312opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 313 314[system.cpu.fuPool.FUList5.opList00] 315type=OpDesc 316eventq_index=0 317opClass=SimdAdd 318opLat=1 319pipelined=true 320 321[system.cpu.fuPool.FUList5.opList01] 322type=OpDesc 323eventq_index=0 324opClass=SimdAddAcc 325opLat=1 326pipelined=true 327 328[system.cpu.fuPool.FUList5.opList02] 329type=OpDesc 330eventq_index=0 331opClass=SimdAlu 332opLat=1 333pipelined=true 334 335[system.cpu.fuPool.FUList5.opList03] 336type=OpDesc 337eventq_index=0 338opClass=SimdCmp 339opLat=1 340pipelined=true 341 342[system.cpu.fuPool.FUList5.opList04] 343type=OpDesc 344eventq_index=0 345opClass=SimdCvt 346opLat=1 347pipelined=true 348 349[system.cpu.fuPool.FUList5.opList05] 350type=OpDesc 351eventq_index=0 352opClass=SimdMisc 353opLat=1 354pipelined=true 355 356[system.cpu.fuPool.FUList5.opList06] 357type=OpDesc 358eventq_index=0 359opClass=SimdMult 360opLat=1 361pipelined=true 362 363[system.cpu.fuPool.FUList5.opList07] 364type=OpDesc 365eventq_index=0 366opClass=SimdMultAcc 367opLat=1 368pipelined=true 369 370[system.cpu.fuPool.FUList5.opList08] 371type=OpDesc 372eventq_index=0 373opClass=SimdShift 374opLat=1 375pipelined=true 376 377[system.cpu.fuPool.FUList5.opList09] 378type=OpDesc 379eventq_index=0 380opClass=SimdShiftAcc 381opLat=1 382pipelined=true 383 384[system.cpu.fuPool.FUList5.opList10] 385type=OpDesc 386eventq_index=0 387opClass=SimdSqrt 388opLat=1 389pipelined=true 390 391[system.cpu.fuPool.FUList5.opList11] 392type=OpDesc 393eventq_index=0 394opClass=SimdFloatAdd 395opLat=1 396pipelined=true 397 398[system.cpu.fuPool.FUList5.opList12] 399type=OpDesc 400eventq_index=0 401opClass=SimdFloatAlu 402opLat=1 403pipelined=true 404 405[system.cpu.fuPool.FUList5.opList13] 406type=OpDesc 407eventq_index=0 408opClass=SimdFloatCmp 409opLat=1 410pipelined=true 411 412[system.cpu.fuPool.FUList5.opList14] 413type=OpDesc 414eventq_index=0 415opClass=SimdFloatCvt 416opLat=1 417pipelined=true 418 419[system.cpu.fuPool.FUList5.opList15] 420type=OpDesc 421eventq_index=0 422opClass=SimdFloatDiv 423opLat=1 424pipelined=true 425 426[system.cpu.fuPool.FUList5.opList16] 427type=OpDesc 428eventq_index=0 429opClass=SimdFloatMisc 430opLat=1 431pipelined=true 432 433[system.cpu.fuPool.FUList5.opList17] 434type=OpDesc 435eventq_index=0 436opClass=SimdFloatMult 437opLat=1 438pipelined=true 439 440[system.cpu.fuPool.FUList5.opList18] 441type=OpDesc 442eventq_index=0 443opClass=SimdFloatMultAcc 444opLat=1 445pipelined=true 446 447[system.cpu.fuPool.FUList5.opList19] 448type=OpDesc 449eventq_index=0 450opClass=SimdFloatSqrt 451opLat=1 452pipelined=true 453 454[system.cpu.fuPool.FUList6] 455type=FUDesc 456children=opList 457count=0 458eventq_index=0 459opList=system.cpu.fuPool.FUList6.opList 460 461[system.cpu.fuPool.FUList6.opList] 462type=OpDesc 463eventq_index=0 464opClass=MemWrite 465opLat=1 466pipelined=true 467 468[system.cpu.fuPool.FUList7] 469type=FUDesc 470children=opList0 opList1 471count=4 472eventq_index=0 473opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 474 475[system.cpu.fuPool.FUList7.opList0] 476type=OpDesc 477eventq_index=0 478opClass=MemRead 479opLat=1 480pipelined=true 481 482[system.cpu.fuPool.FUList7.opList1] 483type=OpDesc 484eventq_index=0 485opClass=MemWrite 486opLat=1 487pipelined=true 488 489[system.cpu.fuPool.FUList8] 490type=FUDesc 491children=opList 492count=1 493eventq_index=0 494opList=system.cpu.fuPool.FUList8.opList 495 496[system.cpu.fuPool.FUList8.opList] 497type=OpDesc 498eventq_index=0 499opClass=IprAccess 500opLat=3 501pipelined=false 502 503[system.cpu.icache] 504type=Cache 505children=tags 506addr_ranges=0:18446744073709551615 507assoc=2 508clk_domain=system.cpu_clk_domain 509clusivity=mostly_incl 510demand_mshr_reserve=1 511eventq_index=0 512forward_snoops=true 513hit_latency=2 514is_read_only=true 515max_miss_count=0 516mshrs=4 517prefetch_on_access=false 518prefetcher=Null 519response_latency=2 520sequential_access=false 521size=131072 522system=system 523tags=system.cpu.icache.tags 524tgts_per_mshr=20 525write_buffers=8 526writeback_clean=true 527cpu_side=system.cpu.icache_port 528mem_side=system.cpu.toL2Bus.slave[0] 529 530[system.cpu.icache.tags] 531type=LRU 532assoc=2 533block_size=64 534clk_domain=system.cpu_clk_domain 535eventq_index=0 536hit_latency=2 537sequential_access=false 538size=131072 539 540[system.cpu.interrupts] 541type=SparcInterrupts 542eventq_index=0 543 544[system.cpu.isa] 545type=SparcISA 546eventq_index=0 547 548[system.cpu.itb] 549type=SparcTLB 550eventq_index=0 551size=64 552 553[system.cpu.l2cache] 554type=Cache 555children=tags 556addr_ranges=0:18446744073709551615 557assoc=8 558clk_domain=system.cpu_clk_domain 559clusivity=mostly_incl 560demand_mshr_reserve=1 561eventq_index=0 562forward_snoops=true 563hit_latency=20 564is_read_only=false 565max_miss_count=0 566mshrs=20 567prefetch_on_access=false 568prefetcher=Null 569response_latency=20 570sequential_access=false 571size=2097152 572system=system 573tags=system.cpu.l2cache.tags 574tgts_per_mshr=12 575write_buffers=8 576writeback_clean=false 577cpu_side=system.cpu.toL2Bus.master[0] 578mem_side=system.membus.slave[1] 579 580[system.cpu.l2cache.tags] 581type=LRU 582assoc=8 583block_size=64 584clk_domain=system.cpu_clk_domain 585eventq_index=0 586hit_latency=20 587sequential_access=false 588size=2097152 589 590[system.cpu.toL2Bus] 591type=CoherentXBar 592children=snoop_filter 593clk_domain=system.cpu_clk_domain 594eventq_index=0 595forward_latency=0 596frontend_latency=1 597response_latency=1 598snoop_filter=system.cpu.toL2Bus.snoop_filter 599snoop_response_latency=1 600system=system 601use_default_range=false 602width=32 603master=system.cpu.l2cache.cpu_side 604slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side 605 606[system.cpu.toL2Bus.snoop_filter] 607type=SnoopFilter 608eventq_index=0 609lookup_latency=0 610max_capacity=8388608 611system=system 612 613[system.cpu.tracer] 614type=ExeTracer 615eventq_index=0 616 617[system.cpu.workload] 618type=LiveProcess 619cmd=insttest 620cwd= 621drivers= 622egid=100 623env= 624errout=cerr 625euid=100 626eventq_index=0 627executable=/dist/m5/regression/test-progs/insttest/bin/sparc/linux/insttest 628gid=100 629input=cin 630kvmInSE=false 631max_stack_size=67108864 632output=cout 633pid=100 634ppid=99 635simpoint=0 636system=system 637uid=100 638useArchPT=false 639 640[system.cpu_clk_domain] 641type=SrcClockDomain 642clock=500 643domain_id=-1 644eventq_index=0 645init_perf_level=0 646voltage_domain=system.voltage_domain 647 648[system.dvfs_handler] 649type=DVFSHandler 650domains= 651enable=false 652eventq_index=0 653sys_clk_domain=system.clk_domain 654transition_latency=100000000 655 656[system.membus] 657type=CoherentXBar 658clk_domain=system.clk_domain 659eventq_index=0 660forward_latency=4 661frontend_latency=3 662response_latency=2 663snoop_filter=Null 664snoop_response_latency=4 665system=system 666use_default_range=false 667width=16 668master=system.physmem.port 669slave=system.system_port system.cpu.l2cache.mem_side 670 671[system.physmem] 672type=DRAMCtrl 673IDD0=0.075000 674IDD02=0.000000 675IDD2N=0.050000 676IDD2N2=0.000000 677IDD2P0=0.000000 678IDD2P02=0.000000 679IDD2P1=0.000000 680IDD2P12=0.000000 681IDD3N=0.057000 682IDD3N2=0.000000 683IDD3P0=0.000000 684IDD3P02=0.000000 685IDD3P1=0.000000 686IDD3P12=0.000000 687IDD4R=0.187000 688IDD4R2=0.000000 689IDD4W=0.165000 690IDD4W2=0.000000 691IDD5=0.220000 692IDD52=0.000000 693IDD6=0.000000 694IDD62=0.000000 695VDD=1.500000 696VDD2=0.000000 697activation_limit=4 698addr_mapping=RoRaBaCoCh 699bank_groups_per_rank=0 700banks_per_rank=8 701burst_length=8 702channels=1 703clk_domain=system.clk_domain 704conf_table_reported=true 705device_bus_width=8 706device_rowbuffer_size=1024 707device_size=536870912 708devices_per_rank=8 709dll=true 710eventq_index=0 711in_addr_map=true 712max_accesses_per_row=16 713mem_sched_policy=frfcfs 714min_writes_per_switch=16 715null=false 716page_policy=open_adaptive 717range=0:134217727 718ranks_per_channel=2 719read_buffer_size=32 720static_backend_latency=10000 721static_frontend_latency=10000 722tBURST=5000 723tCCD_L=0 724tCK=1250 725tCL=13750 726tCS=2500 727tRAS=35000 728tRCD=13750 729tREFI=7800000 730tRFC=260000 731tRP=13750 732tRRD=6000 733tRRD_L=0 734tRTP=7500 735tRTW=2500 736tWR=15000 737tWTR=7500 738tXAW=30000 739tXP=0 740tXPDLL=0 741tXS=0 742tXSDLL=0 743write_buffer_size=64 744write_high_thresh_perc=85 745write_low_thresh_perc=50 746port=system.membus.master[0] 747 748[system.voltage_domain] 749type=VoltageDomain 750eventq_index=0 751voltage=1.000000 752 753