config.ini revision 10798:74e3c7359393
1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain 17eventq_index=0 18init_param=0 19kernel= 20kernel_addr_check=true 21load_addr_mask=1099511627775 22load_offset=0 23mem_mode=timing 24mem_ranges= 25memories=system.physmem 26mmap_using_noreserve=false 27num_work_ids=16 28readfile= 29symbolfile= 30work_begin_ckpt_count=0 31work_begin_cpu_id_exit=-1 32work_begin_exit_count=0 33work_cpus_ckpt_count=0 34work_end_ckpt_count=0 35work_end_exit_count=0 36work_item_id=-1 37system_port=system.membus.slave[0] 38 39[system.clk_domain] 40type=SrcClockDomain 41clock=1000 42domain_id=-1 43eventq_index=0 44init_perf_level=0 45voltage_domain=system.voltage_domain 46 47[system.cpu] 48type=DerivO3CPU 49children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload 50LFSTSize=1024 51LQEntries=32 52LSQCheckLoads=true 53LSQDepCheckShift=4 54SQEntries=32 55SSITSize=1024 56activity=0 57backComSize=5 58branchPred=system.cpu.branchPred 59cachePorts=200 60checker=Null 61clk_domain=system.cpu_clk_domain 62commitToDecodeDelay=1 63commitToFetchDelay=1 64commitToIEWDelay=1 65commitToRenameDelay=1 66commitWidth=8 67cpu_id=0 68decodeToFetchDelay=1 69decodeToRenameDelay=1 70decodeWidth=8 71dispatchWidth=8 72do_checkpoint_insts=true 73do_quiesce=true 74do_statistics_insts=true 75dtb=system.cpu.dtb 76eventq_index=0 77fetchBufferSize=64 78fetchQueueSize=32 79fetchToDecodeDelay=1 80fetchTrapLatency=1 81fetchWidth=8 82forwardComSize=5 83fuPool=system.cpu.fuPool 84function_trace=false 85function_trace_start=0 86iewToCommitDelay=1 87iewToDecodeDelay=1 88iewToFetchDelay=1 89iewToRenameDelay=1 90interrupts=system.cpu.interrupts 91isa=system.cpu.isa 92issueToExecuteDelay=1 93issueWidth=8 94itb=system.cpu.itb 95max_insts_all_threads=0 96max_insts_any_thread=0 97max_loads_all_threads=0 98max_loads_any_thread=0 99needsTSO=false 100numIQEntries=64 101numPhysCCRegs=0 102numPhysFloatRegs=256 103numPhysIntRegs=256 104numROBEntries=192 105numRobs=1 106numThreads=1 107profile=0 108progress_interval=0 109renameToDecodeDelay=1 110renameToFetchDelay=1 111renameToIEWDelay=2 112renameToROBDelay=1 113renameWidth=8 114simpoint_start_insts= 115smtCommitPolicy=RoundRobin 116smtFetchPolicy=SingleThread 117smtIQPolicy=Partitioned 118smtIQThreshold=100 119smtLSQPolicy=Partitioned 120smtLSQThreshold=100 121smtNumFetchingThreads=1 122smtROBPolicy=Partitioned 123smtROBThreshold=100 124socket_id=0 125squashWidth=8 126store_set_clear_period=250000 127switched_out=false 128system=system 129tracer=system.cpu.tracer 130trapLatency=13 131wbWidth=8 132workload=system.cpu.workload 133dcache_port=system.cpu.dcache.cpu_side 134icache_port=system.cpu.icache.cpu_side 135 136[system.cpu.branchPred] 137type=TournamentBP 138BTBEntries=4096 139BTBTagSize=16 140RASSize=16 141choiceCtrBits=2 142choicePredictorSize=8192 143eventq_index=0 144globalCtrBits=2 145globalPredictorSize=8192 146instShiftAmt=2 147localCtrBits=2 148localHistoryTableSize=2048 149localPredictorSize=2048 150numThreads=1 151 152[system.cpu.dcache] 153type=BaseCache 154children=tags 155addr_ranges=0:18446744073709551615 156assoc=2 157clk_domain=system.cpu_clk_domain 158demand_mshr_reserve=1 159eventq_index=0 160forward_snoops=true 161hit_latency=2 162is_top_level=true 163max_miss_count=0 164mshrs=4 165prefetch_on_access=false 166prefetcher=Null 167response_latency=2 168sequential_access=false 169size=262144 170system=system 171tags=system.cpu.dcache.tags 172tgts_per_mshr=20 173two_queue=false 174write_buffers=8 175cpu_side=system.cpu.dcache_port 176mem_side=system.cpu.toL2Bus.slave[1] 177 178[system.cpu.dcache.tags] 179type=LRU 180assoc=2 181block_size=64 182clk_domain=system.cpu_clk_domain 183eventq_index=0 184hit_latency=2 185sequential_access=false 186size=262144 187 188[system.cpu.dtb] 189type=SparcTLB 190eventq_index=0 191size=64 192 193[system.cpu.fuPool] 194type=FUPool 195children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 196FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 197eventq_index=0 198 199[system.cpu.fuPool.FUList0] 200type=FUDesc 201children=opList 202count=6 203eventq_index=0 204opList=system.cpu.fuPool.FUList0.opList 205 206[system.cpu.fuPool.FUList0.opList] 207type=OpDesc 208eventq_index=0 209issueLat=1 210opClass=IntAlu 211opLat=1 212 213[system.cpu.fuPool.FUList1] 214type=FUDesc 215children=opList0 opList1 216count=2 217eventq_index=0 218opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 219 220[system.cpu.fuPool.FUList1.opList0] 221type=OpDesc 222eventq_index=0 223issueLat=1 224opClass=IntMult 225opLat=3 226 227[system.cpu.fuPool.FUList1.opList1] 228type=OpDesc 229eventq_index=0 230issueLat=19 231opClass=IntDiv 232opLat=20 233 234[system.cpu.fuPool.FUList2] 235type=FUDesc 236children=opList0 opList1 opList2 237count=4 238eventq_index=0 239opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 240 241[system.cpu.fuPool.FUList2.opList0] 242type=OpDesc 243eventq_index=0 244issueLat=1 245opClass=FloatAdd 246opLat=2 247 248[system.cpu.fuPool.FUList2.opList1] 249type=OpDesc 250eventq_index=0 251issueLat=1 252opClass=FloatCmp 253opLat=2 254 255[system.cpu.fuPool.FUList2.opList2] 256type=OpDesc 257eventq_index=0 258issueLat=1 259opClass=FloatCvt 260opLat=2 261 262[system.cpu.fuPool.FUList3] 263type=FUDesc 264children=opList0 opList1 opList2 265count=2 266eventq_index=0 267opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 268 269[system.cpu.fuPool.FUList3.opList0] 270type=OpDesc 271eventq_index=0 272issueLat=1 273opClass=FloatMult 274opLat=4 275 276[system.cpu.fuPool.FUList3.opList1] 277type=OpDesc 278eventq_index=0 279issueLat=12 280opClass=FloatDiv 281opLat=12 282 283[system.cpu.fuPool.FUList3.opList2] 284type=OpDesc 285eventq_index=0 286issueLat=24 287opClass=FloatSqrt 288opLat=24 289 290[system.cpu.fuPool.FUList4] 291type=FUDesc 292children=opList 293count=0 294eventq_index=0 295opList=system.cpu.fuPool.FUList4.opList 296 297[system.cpu.fuPool.FUList4.opList] 298type=OpDesc 299eventq_index=0 300issueLat=1 301opClass=MemRead 302opLat=1 303 304[system.cpu.fuPool.FUList5] 305type=FUDesc 306children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 307count=4 308eventq_index=0 309opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 310 311[system.cpu.fuPool.FUList5.opList00] 312type=OpDesc 313eventq_index=0 314issueLat=1 315opClass=SimdAdd 316opLat=1 317 318[system.cpu.fuPool.FUList5.opList01] 319type=OpDesc 320eventq_index=0 321issueLat=1 322opClass=SimdAddAcc 323opLat=1 324 325[system.cpu.fuPool.FUList5.opList02] 326type=OpDesc 327eventq_index=0 328issueLat=1 329opClass=SimdAlu 330opLat=1 331 332[system.cpu.fuPool.FUList5.opList03] 333type=OpDesc 334eventq_index=0 335issueLat=1 336opClass=SimdCmp 337opLat=1 338 339[system.cpu.fuPool.FUList5.opList04] 340type=OpDesc 341eventq_index=0 342issueLat=1 343opClass=SimdCvt 344opLat=1 345 346[system.cpu.fuPool.FUList5.opList05] 347type=OpDesc 348eventq_index=0 349issueLat=1 350opClass=SimdMisc 351opLat=1 352 353[system.cpu.fuPool.FUList5.opList06] 354type=OpDesc 355eventq_index=0 356issueLat=1 357opClass=SimdMult 358opLat=1 359 360[system.cpu.fuPool.FUList5.opList07] 361type=OpDesc 362eventq_index=0 363issueLat=1 364opClass=SimdMultAcc 365opLat=1 366 367[system.cpu.fuPool.FUList5.opList08] 368type=OpDesc 369eventq_index=0 370issueLat=1 371opClass=SimdShift 372opLat=1 373 374[system.cpu.fuPool.FUList5.opList09] 375type=OpDesc 376eventq_index=0 377issueLat=1 378opClass=SimdShiftAcc 379opLat=1 380 381[system.cpu.fuPool.FUList5.opList10] 382type=OpDesc 383eventq_index=0 384issueLat=1 385opClass=SimdSqrt 386opLat=1 387 388[system.cpu.fuPool.FUList5.opList11] 389type=OpDesc 390eventq_index=0 391issueLat=1 392opClass=SimdFloatAdd 393opLat=1 394 395[system.cpu.fuPool.FUList5.opList12] 396type=OpDesc 397eventq_index=0 398issueLat=1 399opClass=SimdFloatAlu 400opLat=1 401 402[system.cpu.fuPool.FUList5.opList13] 403type=OpDesc 404eventq_index=0 405issueLat=1 406opClass=SimdFloatCmp 407opLat=1 408 409[system.cpu.fuPool.FUList5.opList14] 410type=OpDesc 411eventq_index=0 412issueLat=1 413opClass=SimdFloatCvt 414opLat=1 415 416[system.cpu.fuPool.FUList5.opList15] 417type=OpDesc 418eventq_index=0 419issueLat=1 420opClass=SimdFloatDiv 421opLat=1 422 423[system.cpu.fuPool.FUList5.opList16] 424type=OpDesc 425eventq_index=0 426issueLat=1 427opClass=SimdFloatMisc 428opLat=1 429 430[system.cpu.fuPool.FUList5.opList17] 431type=OpDesc 432eventq_index=0 433issueLat=1 434opClass=SimdFloatMult 435opLat=1 436 437[system.cpu.fuPool.FUList5.opList18] 438type=OpDesc 439eventq_index=0 440issueLat=1 441opClass=SimdFloatMultAcc 442opLat=1 443 444[system.cpu.fuPool.FUList5.opList19] 445type=OpDesc 446eventq_index=0 447issueLat=1 448opClass=SimdFloatSqrt 449opLat=1 450 451[system.cpu.fuPool.FUList6] 452type=FUDesc 453children=opList 454count=0 455eventq_index=0 456opList=system.cpu.fuPool.FUList6.opList 457 458[system.cpu.fuPool.FUList6.opList] 459type=OpDesc 460eventq_index=0 461issueLat=1 462opClass=MemWrite 463opLat=1 464 465[system.cpu.fuPool.FUList7] 466type=FUDesc 467children=opList0 opList1 468count=4 469eventq_index=0 470opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 471 472[system.cpu.fuPool.FUList7.opList0] 473type=OpDesc 474eventq_index=0 475issueLat=1 476opClass=MemRead 477opLat=1 478 479[system.cpu.fuPool.FUList7.opList1] 480type=OpDesc 481eventq_index=0 482issueLat=1 483opClass=MemWrite 484opLat=1 485 486[system.cpu.fuPool.FUList8] 487type=FUDesc 488children=opList 489count=1 490eventq_index=0 491opList=system.cpu.fuPool.FUList8.opList 492 493[system.cpu.fuPool.FUList8.opList] 494type=OpDesc 495eventq_index=0 496issueLat=3 497opClass=IprAccess 498opLat=3 499 500[system.cpu.icache] 501type=BaseCache 502children=tags 503addr_ranges=0:18446744073709551615 504assoc=2 505clk_domain=system.cpu_clk_domain 506demand_mshr_reserve=1 507eventq_index=0 508forward_snoops=true 509hit_latency=2 510is_top_level=true 511max_miss_count=0 512mshrs=4 513prefetch_on_access=false 514prefetcher=Null 515response_latency=2 516sequential_access=false 517size=131072 518system=system 519tags=system.cpu.icache.tags 520tgts_per_mshr=20 521two_queue=false 522write_buffers=8 523cpu_side=system.cpu.icache_port 524mem_side=system.cpu.toL2Bus.slave[0] 525 526[system.cpu.icache.tags] 527type=LRU 528assoc=2 529block_size=64 530clk_domain=system.cpu_clk_domain 531eventq_index=0 532hit_latency=2 533sequential_access=false 534size=131072 535 536[system.cpu.interrupts] 537type=SparcInterrupts 538eventq_index=0 539 540[system.cpu.isa] 541type=SparcISA 542eventq_index=0 543 544[system.cpu.itb] 545type=SparcTLB 546eventq_index=0 547size=64 548 549[system.cpu.l2cache] 550type=BaseCache 551children=tags 552addr_ranges=0:18446744073709551615 553assoc=8 554clk_domain=system.cpu_clk_domain 555demand_mshr_reserve=1 556eventq_index=0 557forward_snoops=true 558hit_latency=20 559is_top_level=false 560max_miss_count=0 561mshrs=20 562prefetch_on_access=false 563prefetcher=Null 564response_latency=20 565sequential_access=false 566size=2097152 567system=system 568tags=system.cpu.l2cache.tags 569tgts_per_mshr=12 570two_queue=false 571write_buffers=8 572cpu_side=system.cpu.toL2Bus.master[0] 573mem_side=system.membus.slave[1] 574 575[system.cpu.l2cache.tags] 576type=LRU 577assoc=8 578block_size=64 579clk_domain=system.cpu_clk_domain 580eventq_index=0 581hit_latency=20 582sequential_access=false 583size=2097152 584 585[system.cpu.toL2Bus] 586type=CoherentXBar 587clk_domain=system.cpu_clk_domain 588eventq_index=0 589forward_latency=0 590frontend_latency=1 591response_latency=1 592snoop_filter=Null 593snoop_response_latency=1 594system=system 595use_default_range=false 596width=32 597master=system.cpu.l2cache.cpu_side 598slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side 599 600[system.cpu.tracer] 601type=ExeTracer 602eventq_index=0 603 604[system.cpu.workload] 605type=LiveProcess 606cmd=insttest 607cwd= 608drivers= 609egid=100 610env= 611errout=cerr 612euid=100 613eventq_index=0 614executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/insttest/bin/sparc/linux/insttest 615gid=100 616input=cin 617kvmInSE=false 618max_stack_size=67108864 619output=cout 620pid=100 621ppid=99 622simpoint=0 623system=system 624uid=100 625useArchPT=false 626 627[system.cpu_clk_domain] 628type=SrcClockDomain 629clock=500 630domain_id=-1 631eventq_index=0 632init_perf_level=0 633voltage_domain=system.voltage_domain 634 635[system.dvfs_handler] 636type=DVFSHandler 637domains= 638enable=false 639eventq_index=0 640sys_clk_domain=system.clk_domain 641transition_latency=100000000 642 643[system.membus] 644type=CoherentXBar 645clk_domain=system.clk_domain 646eventq_index=0 647forward_latency=4 648frontend_latency=3 649response_latency=2 650snoop_filter=Null 651snoop_response_latency=4 652system=system 653use_default_range=false 654width=16 655master=system.physmem.port 656slave=system.system_port system.cpu.l2cache.mem_side 657 658[system.physmem] 659type=DRAMCtrl 660IDD0=0.075000 661IDD02=0.000000 662IDD2N=0.050000 663IDD2N2=0.000000 664IDD2P0=0.000000 665IDD2P02=0.000000 666IDD2P1=0.000000 667IDD2P12=0.000000 668IDD3N=0.057000 669IDD3N2=0.000000 670IDD3P0=0.000000 671IDD3P02=0.000000 672IDD3P1=0.000000 673IDD3P12=0.000000 674IDD4R=0.187000 675IDD4R2=0.000000 676IDD4W=0.165000 677IDD4W2=0.000000 678IDD5=0.220000 679IDD52=0.000000 680IDD6=0.000000 681IDD62=0.000000 682VDD=1.500000 683VDD2=0.000000 684activation_limit=4 685addr_mapping=RoRaBaCoCh 686bank_groups_per_rank=0 687banks_per_rank=8 688burst_length=8 689channels=1 690clk_domain=system.clk_domain 691conf_table_reported=true 692device_bus_width=8 693device_rowbuffer_size=1024 694device_size=536870912 695devices_per_rank=8 696dll=true 697eventq_index=0 698in_addr_map=true 699max_accesses_per_row=16 700mem_sched_policy=frfcfs 701min_writes_per_switch=16 702null=false 703page_policy=open_adaptive 704range=0:134217727 705ranks_per_channel=2 706read_buffer_size=32 707static_backend_latency=10000 708static_frontend_latency=10000 709tBURST=5000 710tCCD_L=0 711tCK=1250 712tCL=13750 713tCS=2500 714tRAS=35000 715tRCD=13750 716tREFI=7800000 717tRFC=260000 718tRP=13750 719tRRD=6000 720tRRD_L=0 721tRTP=7500 722tRTW=2500 723tWR=15000 724tWTR=7500 725tXAW=30000 726tXP=0 727tXPDLL=0 728tXS=0 729tXSDLL=0 730write_buffer_size=64 731write_high_thresh_perc=85 732write_low_thresh_perc=50 733port=system.membus.master[0] 734 735[system.voltage_domain] 736type=VoltageDomain 737eventq_index=0 738voltage=1.000000 739 740