111731Sjason@lowepower.comRedirecting stdout to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64m/simple-timing/simout 211731Sjason@lowepower.comRedirecting stderr to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64m/simple-timing/simerr 311731Sjason@lowepower.comgem5 Simulator System. http://gem5.org 411731Sjason@lowepower.comgem5 is copyrighted software; use the --copyright option for details. 511731Sjason@lowepower.com 612137Sar4jc@virginia.edugem5 compiled Jul 13 2017 17:09:45 712137Sar4jc@virginia.edugem5 started Jul 13 2017 17:12:17 812137Sar4jc@virginia.edugem5 executing on boldrock, pid 2077 912137Sar4jc@virginia.educommand line: /home/ar4jc/gem5/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64m/simple-timing --stats-file 'text://stats.txt?desc=False' -re /home/ar4jc/gem5/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64m/simple-timing 1011731Sjason@lowepower.com 1111731Sjason@lowepower.comGlobal frequency set at 1000000000000 ticks per second 1211731Sjason@lowepower.commul: PASS 1311731Sjason@lowepower.commul, overflow: PASS 1411731Sjason@lowepower.commulh: PASS 1511731Sjason@lowepower.commulh, negative: PASS 1611731Sjason@lowepower.commulh, all bits set: PASS 1711731Sjason@lowepower.commulhsu, all bits set: PASS 1811731Sjason@lowepower.commulhsu: PASS 1911731Sjason@lowepower.commulhu: PASS 2011731Sjason@lowepower.commulhu, all bits set: PASS 2111731Sjason@lowepower.comdiv: PASS 2211731Sjason@lowepower.comdiv/0: PASS 2311731Sjason@lowepower.comdiv, overflow: PASS 2411731Sjason@lowepower.comdivu: PASS 2511731Sjason@lowepower.comdivu/0: PASS 2611731Sjason@lowepower.comdivu, "overflow": PASS 2711731Sjason@lowepower.comrem: PASS 2811731Sjason@lowepower.comrem/0: PASS 2911731Sjason@lowepower.comrem, overflow: PASS 3011731Sjason@lowepower.comremu: PASS 3111731Sjason@lowepower.comremu/0: PASS 3211731Sjason@lowepower.comremu, "overflow": PASS 3311731Sjason@lowepower.commulw, truncate: PASS 3411731Sjason@lowepower.commulw, overflow: PASS 3511731Sjason@lowepower.comdivw, truncate: PASS 3611731Sjason@lowepower.comdivw/0: PASS 3711731Sjason@lowepower.comdivw, overflow: PASS 3811731Sjason@lowepower.comdivuw, truncate: PASS 3911731Sjason@lowepower.comdivuw/0: PASS 4011731Sjason@lowepower.comdivuw, "overflow": PASS 4111731Sjason@lowepower.comdivuw, sign extend: PASS 4211731Sjason@lowepower.comremw, truncate: PASS 4311731Sjason@lowepower.comremw/0: PASS 4411731Sjason@lowepower.comremw, overflow: PASS 4511731Sjason@lowepower.comremuw, truncate: PASS 4611731Sjason@lowepower.comremuw/0: PASS 4711731Sjason@lowepower.comremuw, "overflow": PASS 4811731Sjason@lowepower.comremuw, sign extend: PASS 4912137Sar4jc@virginia.eduExiting @ tick 246972500 because exiting with last active thread context 50