111731Sjason@lowepower.com{ 211731Sjason@lowepower.com "name": null, 311731Sjason@lowepower.com "sim_quantum": 0, 411731Sjason@lowepower.com "system": { 511731Sjason@lowepower.com "kernel": "", 611731Sjason@lowepower.com "mmap_using_noreserve": false, 711731Sjason@lowepower.com "kernel_addr_check": true, 811731Sjason@lowepower.com "membus": { 911731Sjason@lowepower.com "point_of_coherency": true, 1011731Sjason@lowepower.com "system": "system", 1111731Sjason@lowepower.com "response_latency": 2, 1211731Sjason@lowepower.com "cxx_class": "CoherentXBar", 1311731Sjason@lowepower.com "forward_latency": 4, 1411731Sjason@lowepower.com "clk_domain": "system.clk_domain", 1511731Sjason@lowepower.com "width": 16, 1611731Sjason@lowepower.com "eventq_index": 0, 1711731Sjason@lowepower.com "default_p_state": "UNDEFINED", 1811731Sjason@lowepower.com "p_state_clk_gate_max": 1000000000000, 1911731Sjason@lowepower.com "master": { 2011731Sjason@lowepower.com "peer": [ 2111731Sjason@lowepower.com "system.physmem.port" 2211731Sjason@lowepower.com ], 2311731Sjason@lowepower.com "role": "MASTER" 2411731Sjason@lowepower.com }, 2511731Sjason@lowepower.com "type": "CoherentXBar", 2611731Sjason@lowepower.com "frontend_latency": 3, 2711731Sjason@lowepower.com "slave": { 2811731Sjason@lowepower.com "peer": [ 2911731Sjason@lowepower.com "system.system_port", 3011731Sjason@lowepower.com "system.cpu.l2cache.mem_side" 3111731Sjason@lowepower.com ], 3211731Sjason@lowepower.com "role": "SLAVE" 3311731Sjason@lowepower.com }, 3411731Sjason@lowepower.com "p_state_clk_gate_min": 1000, 3511731Sjason@lowepower.com "snoop_filter": { 3611731Sjason@lowepower.com "name": "snoop_filter", 3711731Sjason@lowepower.com "system": "system", 3811731Sjason@lowepower.com "max_capacity": 8388608, 3911731Sjason@lowepower.com "eventq_index": 0, 4011731Sjason@lowepower.com "cxx_class": "SnoopFilter", 4111731Sjason@lowepower.com "path": "system.membus.snoop_filter", 4211731Sjason@lowepower.com "type": "SnoopFilter", 4311731Sjason@lowepower.com "lookup_latency": 1 4411731Sjason@lowepower.com }, 4511731Sjason@lowepower.com "power_model": null, 4611731Sjason@lowepower.com "path": "system.membus", 4711731Sjason@lowepower.com "snoop_response_latency": 4, 4811731Sjason@lowepower.com "name": "membus", 4911731Sjason@lowepower.com "p_state_clk_gate_bins": 20, 5011731Sjason@lowepower.com "use_default_range": false 5111731Sjason@lowepower.com }, 5211731Sjason@lowepower.com "symbolfile": "", 5311731Sjason@lowepower.com "readfile": "", 5411731Sjason@lowepower.com "thermal_model": null, 5511731Sjason@lowepower.com "cxx_class": "System", 5611731Sjason@lowepower.com "work_begin_cpu_id_exit": -1, 5711731Sjason@lowepower.com "load_offset": 0, 5811731Sjason@lowepower.com "work_begin_exit_count": 0, 5911731Sjason@lowepower.com "p_state_clk_gate_min": 1000, 6011731Sjason@lowepower.com "memories": [ 6111731Sjason@lowepower.com "system.physmem" 6211731Sjason@lowepower.com ], 6311731Sjason@lowepower.com "work_begin_ckpt_count": 0, 6411731Sjason@lowepower.com "clk_domain": { 6511731Sjason@lowepower.com "name": "clk_domain", 6611731Sjason@lowepower.com "clock": [ 6711731Sjason@lowepower.com 1000 6811731Sjason@lowepower.com ], 6911731Sjason@lowepower.com "init_perf_level": 0, 7011731Sjason@lowepower.com "voltage_domain": "system.voltage_domain", 7111731Sjason@lowepower.com "eventq_index": 0, 7211731Sjason@lowepower.com "cxx_class": "SrcClockDomain", 7311731Sjason@lowepower.com "path": "system.clk_domain", 7411731Sjason@lowepower.com "type": "SrcClockDomain", 7511731Sjason@lowepower.com "domain_id": -1 7611731Sjason@lowepower.com }, 7711731Sjason@lowepower.com "mem_ranges": [], 7811731Sjason@lowepower.com "eventq_index": 0, 7911731Sjason@lowepower.com "default_p_state": "UNDEFINED", 8011731Sjason@lowepower.com "p_state_clk_gate_max": 1000000000000, 8111731Sjason@lowepower.com "dvfs_handler": { 8211731Sjason@lowepower.com "enable": false, 8311731Sjason@lowepower.com "name": "dvfs_handler", 8411731Sjason@lowepower.com "sys_clk_domain": "system.clk_domain", 8511731Sjason@lowepower.com "transition_latency": 100000000, 8611731Sjason@lowepower.com "eventq_index": 0, 8711731Sjason@lowepower.com "cxx_class": "DVFSHandler", 8811731Sjason@lowepower.com "domains": [], 8911731Sjason@lowepower.com "path": "system.dvfs_handler", 9011731Sjason@lowepower.com "type": "DVFSHandler" 9111731Sjason@lowepower.com }, 9211731Sjason@lowepower.com "work_end_exit_count": 0, 9311731Sjason@lowepower.com "type": "System", 9411731Sjason@lowepower.com "voltage_domain": { 9511731Sjason@lowepower.com "name": "voltage_domain", 9611731Sjason@lowepower.com "eventq_index": 0, 9711731Sjason@lowepower.com "voltage": [ 9811731Sjason@lowepower.com "1.0" 9911731Sjason@lowepower.com ], 10011731Sjason@lowepower.com "cxx_class": "VoltageDomain", 10111731Sjason@lowepower.com "path": "system.voltage_domain", 10211731Sjason@lowepower.com "type": "VoltageDomain" 10311731Sjason@lowepower.com }, 10411731Sjason@lowepower.com "cache_line_size": 64, 10511731Sjason@lowepower.com "boot_osflags": "a", 10611731Sjason@lowepower.com "system_port": { 10711731Sjason@lowepower.com "peer": "system.membus.slave[0]", 10811731Sjason@lowepower.com "role": "MASTER" 10911731Sjason@lowepower.com }, 11011731Sjason@lowepower.com "physmem": { 11111731Sjason@lowepower.com "range": "0:134217727:0:0:0:0", 11211731Sjason@lowepower.com "latency": 30000, 11311731Sjason@lowepower.com "name": "physmem", 11411731Sjason@lowepower.com "p_state_clk_gate_min": 1000, 11511731Sjason@lowepower.com "eventq_index": 0, 11611731Sjason@lowepower.com "p_state_clk_gate_bins": 20, 11711731Sjason@lowepower.com "default_p_state": "UNDEFINED", 11811731Sjason@lowepower.com "kvm_map": true, 11911731Sjason@lowepower.com "clk_domain": "system.clk_domain", 12011731Sjason@lowepower.com "power_model": null, 12111731Sjason@lowepower.com "latency_var": 0, 12211731Sjason@lowepower.com "bandwidth": "73.000000", 12311731Sjason@lowepower.com "conf_table_reported": true, 12411731Sjason@lowepower.com "cxx_class": "SimpleMemory", 12511731Sjason@lowepower.com "p_state_clk_gate_max": 1000000000000, 12611731Sjason@lowepower.com "path": "system.physmem", 12711731Sjason@lowepower.com "null": false, 12811731Sjason@lowepower.com "type": "SimpleMemory", 12911731Sjason@lowepower.com "port": { 13011731Sjason@lowepower.com "peer": "system.membus.master[0]", 13111731Sjason@lowepower.com "role": "SLAVE" 13211731Sjason@lowepower.com }, 13311731Sjason@lowepower.com "in_addr_map": true 13411731Sjason@lowepower.com }, 13511731Sjason@lowepower.com "power_model": null, 13611731Sjason@lowepower.com "work_cpus_ckpt_count": 0, 13711731Sjason@lowepower.com "thermal_components": [], 13811731Sjason@lowepower.com "path": "system", 13911731Sjason@lowepower.com "cpu_clk_domain": { 14011731Sjason@lowepower.com "name": "cpu_clk_domain", 14111731Sjason@lowepower.com "clock": [ 14211731Sjason@lowepower.com 500 14311731Sjason@lowepower.com ], 14411731Sjason@lowepower.com "init_perf_level": 0, 14511731Sjason@lowepower.com "voltage_domain": "system.voltage_domain", 14611731Sjason@lowepower.com "eventq_index": 0, 14711731Sjason@lowepower.com "cxx_class": "SrcClockDomain", 14811731Sjason@lowepower.com "path": "system.cpu_clk_domain", 14911731Sjason@lowepower.com "type": "SrcClockDomain", 15011731Sjason@lowepower.com "domain_id": -1 15111731Sjason@lowepower.com }, 15211731Sjason@lowepower.com "work_end_ckpt_count": 0, 15311731Sjason@lowepower.com "mem_mode": "timing", 15411731Sjason@lowepower.com "name": "system", 15511731Sjason@lowepower.com "init_param": 0, 15611731Sjason@lowepower.com "p_state_clk_gate_bins": 20, 15711731Sjason@lowepower.com "load_addr_mask": 1099511627775, 15811731Sjason@lowepower.com "cpu": [ 15911731Sjason@lowepower.com { 16011731Sjason@lowepower.com "do_statistics_insts": true, 16111731Sjason@lowepower.com "numThreads": 1, 16211731Sjason@lowepower.com "itb": { 16311731Sjason@lowepower.com "name": "itb", 16411731Sjason@lowepower.com "eventq_index": 0, 16511731Sjason@lowepower.com "cxx_class": "RiscvISA::TLB", 16611731Sjason@lowepower.com "path": "system.cpu.itb", 16711731Sjason@lowepower.com "type": "RiscvTLB", 16811731Sjason@lowepower.com "size": 64 16911731Sjason@lowepower.com }, 17011731Sjason@lowepower.com "system": "system", 17111731Sjason@lowepower.com "icache": { 17211731Sjason@lowepower.com "cpu_side": { 17311731Sjason@lowepower.com "peer": "system.cpu.icache_port", 17411731Sjason@lowepower.com "role": "SLAVE" 17511731Sjason@lowepower.com }, 17611731Sjason@lowepower.com "clusivity": "mostly_incl", 17711731Sjason@lowepower.com "prefetcher": null, 17811731Sjason@lowepower.com "system": "system", 17911731Sjason@lowepower.com "write_buffers": 8, 18011731Sjason@lowepower.com "response_latency": 2, 18111731Sjason@lowepower.com "cxx_class": "Cache", 18211731Sjason@lowepower.com "size": 131072, 18311731Sjason@lowepower.com "type": "Cache", 18411731Sjason@lowepower.com "clk_domain": "system.cpu_clk_domain", 18511731Sjason@lowepower.com "max_miss_count": 0, 18611731Sjason@lowepower.com "eventq_index": 0, 18711731Sjason@lowepower.com "default_p_state": "UNDEFINED", 18811731Sjason@lowepower.com "p_state_clk_gate_max": 1000000000000, 18911731Sjason@lowepower.com "mem_side": { 19011731Sjason@lowepower.com "peer": "system.cpu.toL2Bus.slave[0]", 19111731Sjason@lowepower.com "role": "MASTER" 19211731Sjason@lowepower.com }, 19311731Sjason@lowepower.com "mshrs": 4, 19411731Sjason@lowepower.com "writeback_clean": true, 19511731Sjason@lowepower.com "p_state_clk_gate_min": 1000, 19611731Sjason@lowepower.com "tags": { 19711731Sjason@lowepower.com "size": 131072, 19811731Sjason@lowepower.com "tag_latency": 2, 19911731Sjason@lowepower.com "name": "tags", 20011731Sjason@lowepower.com "p_state_clk_gate_min": 1000, 20111731Sjason@lowepower.com "eventq_index": 0, 20211731Sjason@lowepower.com "p_state_clk_gate_bins": 20, 20311731Sjason@lowepower.com "default_p_state": "UNDEFINED", 20411731Sjason@lowepower.com "clk_domain": "system.cpu_clk_domain", 20511731Sjason@lowepower.com "power_model": null, 20611731Sjason@lowepower.com "sequential_access": false, 20711731Sjason@lowepower.com "assoc": 2, 20811731Sjason@lowepower.com "cxx_class": "LRU", 20911731Sjason@lowepower.com "p_state_clk_gate_max": 1000000000000, 21011731Sjason@lowepower.com "path": "system.cpu.icache.tags", 21111731Sjason@lowepower.com "block_size": 64, 21211731Sjason@lowepower.com "type": "LRU", 21311731Sjason@lowepower.com "data_latency": 2 21411731Sjason@lowepower.com }, 21511731Sjason@lowepower.com "tgts_per_mshr": 20, 21611731Sjason@lowepower.com "demand_mshr_reserve": 1, 21711731Sjason@lowepower.com "power_model": null, 21811731Sjason@lowepower.com "addr_ranges": [ 21911731Sjason@lowepower.com "0:18446744073709551615:0:0:0:0" 22011731Sjason@lowepower.com ], 22111731Sjason@lowepower.com "is_read_only": true, 22211731Sjason@lowepower.com "prefetch_on_access": false, 22311731Sjason@lowepower.com "path": "system.cpu.icache", 22411731Sjason@lowepower.com "data_latency": 2, 22511731Sjason@lowepower.com "tag_latency": 2, 22611731Sjason@lowepower.com "name": "icache", 22711731Sjason@lowepower.com "p_state_clk_gate_bins": 20, 22811731Sjason@lowepower.com "sequential_access": false, 22911731Sjason@lowepower.com "assoc": 2 23011731Sjason@lowepower.com }, 23111731Sjason@lowepower.com "function_trace": false, 23211731Sjason@lowepower.com "do_checkpoint_insts": true, 23311731Sjason@lowepower.com "cxx_class": "TimingSimpleCPU", 23411731Sjason@lowepower.com "max_loads_all_threads": 0, 23511731Sjason@lowepower.com "clk_domain": "system.cpu_clk_domain", 23611731Sjason@lowepower.com "function_trace_start": 0, 23711731Sjason@lowepower.com "cpu_id": 0, 23811731Sjason@lowepower.com "checker": null, 23911731Sjason@lowepower.com "eventq_index": 0, 24011731Sjason@lowepower.com "default_p_state": "UNDEFINED", 24111731Sjason@lowepower.com "p_state_clk_gate_max": 1000000000000, 24211731Sjason@lowepower.com "toL2Bus": { 24311731Sjason@lowepower.com "point_of_coherency": false, 24411731Sjason@lowepower.com "system": "system", 24511731Sjason@lowepower.com "response_latency": 1, 24611731Sjason@lowepower.com "cxx_class": "CoherentXBar", 24711731Sjason@lowepower.com "forward_latency": 0, 24811731Sjason@lowepower.com "clk_domain": "system.cpu_clk_domain", 24911731Sjason@lowepower.com "width": 32, 25011731Sjason@lowepower.com "eventq_index": 0, 25111731Sjason@lowepower.com "default_p_state": "UNDEFINED", 25211731Sjason@lowepower.com "p_state_clk_gate_max": 1000000000000, 25311731Sjason@lowepower.com "master": { 25411731Sjason@lowepower.com "peer": [ 25511731Sjason@lowepower.com "system.cpu.l2cache.cpu_side" 25611731Sjason@lowepower.com ], 25711731Sjason@lowepower.com "role": "MASTER" 25811731Sjason@lowepower.com }, 25911731Sjason@lowepower.com "type": "CoherentXBar", 26011731Sjason@lowepower.com "frontend_latency": 1, 26111731Sjason@lowepower.com "slave": { 26211731Sjason@lowepower.com "peer": [ 26311731Sjason@lowepower.com "system.cpu.icache.mem_side", 26411731Sjason@lowepower.com "system.cpu.dcache.mem_side" 26511731Sjason@lowepower.com ], 26611731Sjason@lowepower.com "role": "SLAVE" 26711731Sjason@lowepower.com }, 26811731Sjason@lowepower.com "p_state_clk_gate_min": 1000, 26911731Sjason@lowepower.com "snoop_filter": { 27011731Sjason@lowepower.com "name": "snoop_filter", 27111731Sjason@lowepower.com "system": "system", 27211731Sjason@lowepower.com "max_capacity": 8388608, 27311731Sjason@lowepower.com "eventq_index": 0, 27411731Sjason@lowepower.com "cxx_class": "SnoopFilter", 27511731Sjason@lowepower.com "path": "system.cpu.toL2Bus.snoop_filter", 27611731Sjason@lowepower.com "type": "SnoopFilter", 27711731Sjason@lowepower.com "lookup_latency": 0 27811731Sjason@lowepower.com }, 27911731Sjason@lowepower.com "power_model": null, 28011731Sjason@lowepower.com "path": "system.cpu.toL2Bus", 28111731Sjason@lowepower.com "snoop_response_latency": 1, 28211731Sjason@lowepower.com "name": "toL2Bus", 28311731Sjason@lowepower.com "p_state_clk_gate_bins": 20, 28411731Sjason@lowepower.com "use_default_range": false 28511731Sjason@lowepower.com }, 28611731Sjason@lowepower.com "do_quiesce": true, 28711731Sjason@lowepower.com "type": "TimingSimpleCPU", 28811731Sjason@lowepower.com "profile": 0, 28911731Sjason@lowepower.com "icache_port": { 29011731Sjason@lowepower.com "peer": "system.cpu.icache.cpu_side", 29111731Sjason@lowepower.com "role": "MASTER" 29211731Sjason@lowepower.com }, 29311731Sjason@lowepower.com "p_state_clk_gate_bins": 20, 29411731Sjason@lowepower.com "p_state_clk_gate_min": 1000, 29512137Sar4jc@virginia.edu "syscallRetryLatency": 10000, 29611731Sjason@lowepower.com "interrupts": [ 29711731Sjason@lowepower.com { 29811731Sjason@lowepower.com "eventq_index": 0, 29911731Sjason@lowepower.com "path": "system.cpu.interrupts", 30011731Sjason@lowepower.com "type": "RiscvInterrupts", 30111731Sjason@lowepower.com "name": "interrupts", 30211731Sjason@lowepower.com "cxx_class": "RiscvISA::Interrupts" 30311731Sjason@lowepower.com } 30411731Sjason@lowepower.com ], 30511731Sjason@lowepower.com "dcache_port": { 30611731Sjason@lowepower.com "peer": "system.cpu.dcache.cpu_side", 30711731Sjason@lowepower.com "role": "MASTER" 30811731Sjason@lowepower.com }, 30911731Sjason@lowepower.com "socket_id": 0, 31011731Sjason@lowepower.com "power_model": null, 31111731Sjason@lowepower.com "max_insts_all_threads": 0, 31211731Sjason@lowepower.com "l2cache": { 31311731Sjason@lowepower.com "cpu_side": { 31411731Sjason@lowepower.com "peer": "system.cpu.toL2Bus.master[0]", 31511731Sjason@lowepower.com "role": "SLAVE" 31611731Sjason@lowepower.com }, 31711731Sjason@lowepower.com "clusivity": "mostly_incl", 31811731Sjason@lowepower.com "prefetcher": null, 31911731Sjason@lowepower.com "system": "system", 32011731Sjason@lowepower.com "write_buffers": 8, 32111731Sjason@lowepower.com "response_latency": 20, 32211731Sjason@lowepower.com "cxx_class": "Cache", 32311731Sjason@lowepower.com "size": 2097152, 32411731Sjason@lowepower.com "type": "Cache", 32511731Sjason@lowepower.com "clk_domain": "system.cpu_clk_domain", 32611731Sjason@lowepower.com "max_miss_count": 0, 32711731Sjason@lowepower.com "eventq_index": 0, 32811731Sjason@lowepower.com "default_p_state": "UNDEFINED", 32911731Sjason@lowepower.com "p_state_clk_gate_max": 1000000000000, 33011731Sjason@lowepower.com "mem_side": { 33111731Sjason@lowepower.com "peer": "system.membus.slave[1]", 33211731Sjason@lowepower.com "role": "MASTER" 33311731Sjason@lowepower.com }, 33411731Sjason@lowepower.com "mshrs": 20, 33511731Sjason@lowepower.com "writeback_clean": false, 33611731Sjason@lowepower.com "p_state_clk_gate_min": 1000, 33711731Sjason@lowepower.com "tags": { 33811731Sjason@lowepower.com "size": 2097152, 33911731Sjason@lowepower.com "tag_latency": 20, 34011731Sjason@lowepower.com "name": "tags", 34111731Sjason@lowepower.com "p_state_clk_gate_min": 1000, 34211731Sjason@lowepower.com "eventq_index": 0, 34311731Sjason@lowepower.com "p_state_clk_gate_bins": 20, 34411731Sjason@lowepower.com "default_p_state": "UNDEFINED", 34511731Sjason@lowepower.com "clk_domain": "system.cpu_clk_domain", 34611731Sjason@lowepower.com "power_model": null, 34711731Sjason@lowepower.com "sequential_access": false, 34811731Sjason@lowepower.com "assoc": 8, 34911731Sjason@lowepower.com "cxx_class": "LRU", 35011731Sjason@lowepower.com "p_state_clk_gate_max": 1000000000000, 35111731Sjason@lowepower.com "path": "system.cpu.l2cache.tags", 35211731Sjason@lowepower.com "block_size": 64, 35311731Sjason@lowepower.com "type": "LRU", 35411731Sjason@lowepower.com "data_latency": 20 35511731Sjason@lowepower.com }, 35611731Sjason@lowepower.com "tgts_per_mshr": 12, 35711731Sjason@lowepower.com "demand_mshr_reserve": 1, 35811731Sjason@lowepower.com "power_model": null, 35911731Sjason@lowepower.com "addr_ranges": [ 36011731Sjason@lowepower.com "0:18446744073709551615:0:0:0:0" 36111731Sjason@lowepower.com ], 36211731Sjason@lowepower.com "is_read_only": false, 36311731Sjason@lowepower.com "prefetch_on_access": false, 36411731Sjason@lowepower.com "path": "system.cpu.l2cache", 36511731Sjason@lowepower.com "data_latency": 20, 36611731Sjason@lowepower.com "tag_latency": 20, 36711731Sjason@lowepower.com "name": "l2cache", 36811731Sjason@lowepower.com "p_state_clk_gate_bins": 20, 36911731Sjason@lowepower.com "sequential_access": false, 37011731Sjason@lowepower.com "assoc": 8 37111731Sjason@lowepower.com }, 37211731Sjason@lowepower.com "path": "system.cpu", 37311731Sjason@lowepower.com "max_loads_any_thread": 0, 37411731Sjason@lowepower.com "switched_out": false, 37511731Sjason@lowepower.com "workload": [ 37611731Sjason@lowepower.com { 37711731Sjason@lowepower.com "uid": 100, 37811731Sjason@lowepower.com "pid": 100, 37911731Sjason@lowepower.com "kvmInSE": false, 38012137Sar4jc@virginia.edu "cxx_class": "Process", 38112137Sar4jc@virginia.edu "executable": "/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64m/insttest", 38211731Sjason@lowepower.com "drivers": [], 38311731Sjason@lowepower.com "system": "system", 38411731Sjason@lowepower.com "gid": 100, 38511731Sjason@lowepower.com "eventq_index": 0, 38611731Sjason@lowepower.com "env": [], 38712137Sar4jc@virginia.edu "maxStackSize": 67108864, 38812137Sar4jc@virginia.edu "ppid": 0, 38912137Sar4jc@virginia.edu "type": "Process", 39011731Sjason@lowepower.com "cwd": "", 39112137Sar4jc@virginia.edu "pgid": 100, 39211731Sjason@lowepower.com "simpoint": 0, 39311731Sjason@lowepower.com "euid": 100, 39412137Sar4jc@virginia.edu "input": "cin", 39511731Sjason@lowepower.com "path": "system.cpu.workload", 39611731Sjason@lowepower.com "name": "workload", 39711731Sjason@lowepower.com "cmd": [ 39811731Sjason@lowepower.com "insttest" 39911731Sjason@lowepower.com ], 40011731Sjason@lowepower.com "errout": "cerr", 40111731Sjason@lowepower.com "useArchPT": false, 40211731Sjason@lowepower.com "egid": 100, 40311731Sjason@lowepower.com "output": "cout" 40411731Sjason@lowepower.com } 40511731Sjason@lowepower.com ], 40611731Sjason@lowepower.com "name": "cpu", 40712137Sar4jc@virginia.edu "wait_for_remote_gdb": false, 40811731Sjason@lowepower.com "dtb": { 40911731Sjason@lowepower.com "name": "dtb", 41011731Sjason@lowepower.com "eventq_index": 0, 41111731Sjason@lowepower.com "cxx_class": "RiscvISA::TLB", 41211731Sjason@lowepower.com "path": "system.cpu.dtb", 41311731Sjason@lowepower.com "type": "RiscvTLB", 41411731Sjason@lowepower.com "size": 64 41511731Sjason@lowepower.com }, 41611731Sjason@lowepower.com "simpoint_start_insts": [], 41711731Sjason@lowepower.com "max_insts_any_thread": 0, 41811731Sjason@lowepower.com "progress_interval": 0, 41911731Sjason@lowepower.com "branchPred": null, 42011731Sjason@lowepower.com "dcache": { 42111731Sjason@lowepower.com "cpu_side": { 42211731Sjason@lowepower.com "peer": "system.cpu.dcache_port", 42311731Sjason@lowepower.com "role": "SLAVE" 42411731Sjason@lowepower.com }, 42511731Sjason@lowepower.com "clusivity": "mostly_incl", 42611731Sjason@lowepower.com "prefetcher": null, 42711731Sjason@lowepower.com "system": "system", 42811731Sjason@lowepower.com "write_buffers": 8, 42911731Sjason@lowepower.com "response_latency": 2, 43011731Sjason@lowepower.com "cxx_class": "Cache", 43111731Sjason@lowepower.com "size": 262144, 43211731Sjason@lowepower.com "type": "Cache", 43311731Sjason@lowepower.com "clk_domain": "system.cpu_clk_domain", 43411731Sjason@lowepower.com "max_miss_count": 0, 43511731Sjason@lowepower.com "eventq_index": 0, 43611731Sjason@lowepower.com "default_p_state": "UNDEFINED", 43711731Sjason@lowepower.com "p_state_clk_gate_max": 1000000000000, 43811731Sjason@lowepower.com "mem_side": { 43911731Sjason@lowepower.com "peer": "system.cpu.toL2Bus.slave[1]", 44011731Sjason@lowepower.com "role": "MASTER" 44111731Sjason@lowepower.com }, 44211731Sjason@lowepower.com "mshrs": 4, 44311731Sjason@lowepower.com "writeback_clean": false, 44411731Sjason@lowepower.com "p_state_clk_gate_min": 1000, 44511731Sjason@lowepower.com "tags": { 44611731Sjason@lowepower.com "size": 262144, 44711731Sjason@lowepower.com "tag_latency": 2, 44811731Sjason@lowepower.com "name": "tags", 44911731Sjason@lowepower.com "p_state_clk_gate_min": 1000, 45011731Sjason@lowepower.com "eventq_index": 0, 45111731Sjason@lowepower.com "p_state_clk_gate_bins": 20, 45211731Sjason@lowepower.com "default_p_state": "UNDEFINED", 45311731Sjason@lowepower.com "clk_domain": "system.cpu_clk_domain", 45411731Sjason@lowepower.com "power_model": null, 45511731Sjason@lowepower.com "sequential_access": false, 45611731Sjason@lowepower.com "assoc": 2, 45711731Sjason@lowepower.com "cxx_class": "LRU", 45811731Sjason@lowepower.com "p_state_clk_gate_max": 1000000000000, 45911731Sjason@lowepower.com "path": "system.cpu.dcache.tags", 46011731Sjason@lowepower.com "block_size": 64, 46111731Sjason@lowepower.com "type": "LRU", 46211731Sjason@lowepower.com "data_latency": 2 46311731Sjason@lowepower.com }, 46411731Sjason@lowepower.com "tgts_per_mshr": 20, 46511731Sjason@lowepower.com "demand_mshr_reserve": 1, 46611731Sjason@lowepower.com "power_model": null, 46711731Sjason@lowepower.com "addr_ranges": [ 46811731Sjason@lowepower.com "0:18446744073709551615:0:0:0:0" 46911731Sjason@lowepower.com ], 47011731Sjason@lowepower.com "is_read_only": false, 47111731Sjason@lowepower.com "prefetch_on_access": false, 47211731Sjason@lowepower.com "path": "system.cpu.dcache", 47311731Sjason@lowepower.com "data_latency": 2, 47411731Sjason@lowepower.com "tag_latency": 2, 47511731Sjason@lowepower.com "name": "dcache", 47611731Sjason@lowepower.com "p_state_clk_gate_bins": 20, 47711731Sjason@lowepower.com "sequential_access": false, 47811731Sjason@lowepower.com "assoc": 2 47911731Sjason@lowepower.com }, 48011731Sjason@lowepower.com "isa": [ 48111731Sjason@lowepower.com { 48211731Sjason@lowepower.com "eventq_index": 0, 48311731Sjason@lowepower.com "path": "system.cpu.isa", 48411731Sjason@lowepower.com "type": "RiscvISA", 48511731Sjason@lowepower.com "name": "isa", 48611731Sjason@lowepower.com "cxx_class": "RiscvISA::ISA" 48711731Sjason@lowepower.com } 48811731Sjason@lowepower.com ], 48911731Sjason@lowepower.com "tracer": { 49011731Sjason@lowepower.com "eventq_index": 0, 49111731Sjason@lowepower.com "path": "system.cpu.tracer", 49211731Sjason@lowepower.com "type": "ExeTracer", 49311731Sjason@lowepower.com "name": "tracer", 49411731Sjason@lowepower.com "cxx_class": "Trace::ExeTracer" 49511731Sjason@lowepower.com } 49611731Sjason@lowepower.com } 49711731Sjason@lowepower.com ], 49811731Sjason@lowepower.com "multi_thread": false, 49911731Sjason@lowepower.com "exit_on_work_items": false, 50011731Sjason@lowepower.com "work_item_id": -1, 50111731Sjason@lowepower.com "num_work_ids": 16 50211731Sjason@lowepower.com }, 50311731Sjason@lowepower.com "time_sync_period": 100000000000, 50411731Sjason@lowepower.com "eventq_index": 0, 50511731Sjason@lowepower.com "time_sync_spin_threshold": 100000000, 50611731Sjason@lowepower.com "cxx_class": "Root", 50711731Sjason@lowepower.com "path": "root", 50811731Sjason@lowepower.com "time_sync_enable": false, 50911731Sjason@lowepower.com "type": "Root", 51011731Sjason@lowepower.com "full_system": false 51111731Sjason@lowepower.com}