simout revision 12137:d877205ec1bc
1Redirecting stdout to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64m/minor-timing/simout 2Redirecting stderr to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64m/minor-timing/simerr 3gem5 Simulator System. http://gem5.org 4gem5 is copyrighted software; use the --copyright option for details. 5 6gem5 compiled Jul 13 2017 17:09:45 7gem5 started Jul 13 2017 17:12:00 8gem5 executing on boldrock, pid 2002 9command line: /home/ar4jc/gem5/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64m/minor-timing --stats-file 'text://stats.txt?desc=False' -re /home/ar4jc/gem5/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64m/minor-timing 10 11Global frequency set at 1000000000000 ticks per second 12mul: PASS 13mul, overflow: PASS 14mulh: PASS 15mulh, negative: PASS 16mulh, all bits set: PASS 17mulhsu, all bits set: PASS 18mulhsu: PASS 19mulhu: PASS 20mulhu, all bits set: PASS 21div: PASS 22div/0: PASS 23div, overflow: PASS 24divu: PASS 25divu/0: PASS 26divu, "overflow": PASS 27rem: PASS 28rem/0: PASS 29rem, overflow: PASS 30remu: PASS 31remu/0: PASS 32remu, "overflow": PASS 33mulw, truncate: PASS 34mulw, overflow: PASS 35divw, truncate: PASS 36divw/0: PASS 37divw, overflow: PASS 38divuw, truncate: PASS 39divuw/0: PASS 40divuw, "overflow": PASS 41divuw, sign extend: PASS 42remw, truncate: PASS 43remw/0: PASS 44remw, overflow: PASS 45remuw, truncate: PASS 46remuw/0: PASS 47remuw, "overflow": PASS 48remuw, sign extend: PASS 49Exiting @ tick 177558500 because exiting with last active thread context 50