config.json revision 12137:d877205ec1bc
1{ 2 "name": null, 3 "sim_quantum": 0, 4 "system": { 5 "kernel": "", 6 "mmap_using_noreserve": false, 7 "kernel_addr_check": true, 8 "membus": { 9 "point_of_coherency": true, 10 "system": "system", 11 "response_latency": 2, 12 "cxx_class": "CoherentXBar", 13 "forward_latency": 4, 14 "clk_domain": "system.clk_domain", 15 "width": 16, 16 "eventq_index": 0, 17 "default_p_state": "UNDEFINED", 18 "p_state_clk_gate_max": 1000000000000, 19 "master": { 20 "peer": [ 21 "system.physmem.port" 22 ], 23 "role": "MASTER" 24 }, 25 "type": "CoherentXBar", 26 "frontend_latency": 3, 27 "slave": { 28 "peer": [ 29 "system.system_port", 30 "system.cpu.l2cache.mem_side" 31 ], 32 "role": "SLAVE" 33 }, 34 "p_state_clk_gate_min": 1000, 35 "snoop_filter": { 36 "name": "snoop_filter", 37 "system": "system", 38 "max_capacity": 8388608, 39 "eventq_index": 0, 40 "cxx_class": "SnoopFilter", 41 "path": "system.membus.snoop_filter", 42 "type": "SnoopFilter", 43 "lookup_latency": 1 44 }, 45 "power_model": null, 46 "path": "system.membus", 47 "snoop_response_latency": 4, 48 "name": "membus", 49 "p_state_clk_gate_bins": 20, 50 "use_default_range": false 51 }, 52 "symbolfile": "", 53 "readfile": "", 54 "thermal_model": null, 55 "cxx_class": "System", 56 "work_begin_cpu_id_exit": -1, 57 "load_offset": 0, 58 "work_begin_exit_count": 0, 59 "p_state_clk_gate_min": 1000, 60 "memories": [ 61 "system.physmem" 62 ], 63 "work_begin_ckpt_count": 0, 64 "clk_domain": { 65 "name": "clk_domain", 66 "clock": [ 67 1000 68 ], 69 "init_perf_level": 0, 70 "voltage_domain": "system.voltage_domain", 71 "eventq_index": 0, 72 "cxx_class": "SrcClockDomain", 73 "path": "system.clk_domain", 74 "type": "SrcClockDomain", 75 "domain_id": -1 76 }, 77 "mem_ranges": [], 78 "eventq_index": 0, 79 "default_p_state": "UNDEFINED", 80 "p_state_clk_gate_max": 1000000000000, 81 "dvfs_handler": { 82 "enable": false, 83 "name": "dvfs_handler", 84 "sys_clk_domain": "system.clk_domain", 85 "transition_latency": 100000000, 86 "eventq_index": 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"system.physmem", 127 "null": false, 128 "type": "SimpleMemory", 129 "port": { 130 "peer": "system.membus.master[0]", 131 "role": "SLAVE" 132 }, 133 "in_addr_map": true 134 }, 135 "power_model": null, 136 "work_cpus_ckpt_count": 0, 137 "thermal_components": [], 138 "path": "system", 139 "cpu_clk_domain": { 140 "name": "cpu_clk_domain", 141 "clock": [ 142 500 143 ], 144 "init_perf_level": 0, 145 "voltage_domain": "system.voltage_domain", 146 "eventq_index": 0, 147 "cxx_class": "SrcClockDomain", 148 "path": "system.cpu_clk_domain", 149 "type": "SrcClockDomain", 150 "domain_id": -1 151 }, 152 "work_end_ckpt_count": 0, 153 "mem_mode": "timing", 154 "name": "system", 155 "init_param": 0, 156 "p_state_clk_gate_bins": 20, 157 "load_addr_mask": 1099511627775, 158 "cpu": [ 159 { 160 "do_statistics_insts": true, 161 "numThreads": 1, 162 "itb": { 163 "name": "itb", 164 "eventq_index": 0, 165 "cxx_class": "RiscvISA::TLB", 166 "path": "system.cpu.itb", 167 "type": "RiscvTLB", 168 "size": 64 169 }, 170 "system": "system", 171 "icache": { 172 "cpu_side": { 173 "peer": "system.cpu.icache_port", 174 "role": "SLAVE" 175 }, 176 "clusivity": "mostly_incl", 177 "prefetcher": null, 178 "system": "system", 179 "write_buffers": 8, 180 "response_latency": 2, 181 "cxx_class": "Cache", 182 "size": 131072, 183 "type": "Cache", 184 "clk_domain": "system.cpu_clk_domain", 185 "max_miss_count": 0, 186 "eventq_index": 0, 187 "default_p_state": "UNDEFINED", 188 "p_state_clk_gate_max": 1000000000000, 189 "mem_side": { 190 "peer": "system.cpu.toL2Bus.slave[0]", 191 "role": "MASTER" 192 }, 193 "mshrs": 4, 194 "writeback_clean": true, 195 "p_state_clk_gate_min": 1000, 196 "tags": { 197 "size": 131072, 198 "tag_latency": 2, 199 "name": "tags", 200 "p_state_clk_gate_min": 1000, 201 "eventq_index": 0, 202 "p_state_clk_gate_bins": 20, 203 "default_p_state": "UNDEFINED", 204 "clk_domain": "system.cpu_clk_domain", 205 "power_model": null, 206 "sequential_access": false, 207 "assoc": 2, 208 "cxx_class": "LRU", 209 "p_state_clk_gate_max": 1000000000000, 210 "path": "system.cpu.icache.tags", 211 "block_size": 64, 212 "type": "LRU", 213 "data_latency": 2 214 }, 215 "tgts_per_mshr": 20, 216 "demand_mshr_reserve": 1, 217 "power_model": null, 218 "addr_ranges": [ 219 "0:18446744073709551615:0:0:0:0" 220 ], 221 "is_read_only": true, 222 "prefetch_on_access": false, 223 "path": "system.cpu.icache", 224 "data_latency": 2, 225 "tag_latency": 2, 226 "name": "icache", 227 "p_state_clk_gate_bins": 20, 228 "sequential_access": false, 229 "assoc": 2 230 }, 231 "function_trace": false, 232 "do_checkpoint_insts": true, 233 "cxx_class": "TimingSimpleCPU", 234 "max_loads_all_threads": 0, 235 "clk_domain": "system.cpu_clk_domain", 236 "function_trace_start": 0, 237 "cpu_id": 0, 238 "checker": null, 239 "eventq_index": 0, 240 "default_p_state": "UNDEFINED", 241 "p_state_clk_gate_max": 1000000000000, 242 "toL2Bus": { 243 "point_of_coherency": false, 244 "system": "system", 245 "response_latency": 1, 246 "cxx_class": "CoherentXBar", 247 "forward_latency": 0, 248 "clk_domain": "system.cpu_clk_domain", 249 "width": 32, 250 "eventq_index": 0, 251 "default_p_state": "UNDEFINED", 252 "p_state_clk_gate_max": 1000000000000, 253 "master": { 254 "peer": [ 255 "system.cpu.l2cache.cpu_side" 256 ], 257 "role": "MASTER" 258 }, 259 "type": "CoherentXBar", 260 "frontend_latency": 1, 261 "slave": { 262 "peer": [ 263 "system.cpu.icache.mem_side", 264 "system.cpu.dcache.mem_side" 265 ], 266 "role": "SLAVE" 267 }, 268 "p_state_clk_gate_min": 1000, 269 "snoop_filter": { 270 "name": "snoop_filter", 271 "system": "system", 272 "max_capacity": 8388608, 273 "eventq_index": 0, 274 "cxx_class": "SnoopFilter", 275 "path": "system.cpu.toL2Bus.snoop_filter", 276 "type": "SnoopFilter", 277 "lookup_latency": 0 278 }, 279 "power_model": null, 280 "path": "system.cpu.toL2Bus", 281 "snoop_response_latency": 1, 282 "name": "toL2Bus", 283 "p_state_clk_gate_bins": 20, 284 "use_default_range": false 285 }, 286 "do_quiesce": true, 287 "type": "TimingSimpleCPU", 288 "profile": 0, 289 "icache_port": { 290 "peer": "system.cpu.icache.cpu_side", 291 "role": "MASTER" 292 }, 293 "p_state_clk_gate_bins": 20, 294 "p_state_clk_gate_min": 1000, 295 "syscallRetryLatency": 10000, 296 "interrupts": [ 297 { 298 "eventq_index": 0, 299 "path": "system.cpu.interrupts", 300 "type": "RiscvInterrupts", 301 "name": "interrupts", 302 "cxx_class": "RiscvISA::Interrupts" 303 } 304 ], 305 "dcache_port": { 306 "peer": "system.cpu.dcache.cpu_side", 307 "role": "MASTER" 308 }, 309 "socket_id": 0, 310 "power_model": null, 311 "max_insts_all_threads": 0, 312 "l2cache": { 313 "cpu_side": { 314 "peer": "system.cpu.toL2Bus.master[0]", 315 "role": "SLAVE" 316 }, 317 "clusivity": "mostly_incl", 318 "prefetcher": null, 319 "system": "system", 320 "write_buffers": 8, 321 "response_latency": 20, 322 "cxx_class": "Cache", 323 "size": 2097152, 324 "type": "Cache", 325 "clk_domain": "system.cpu_clk_domain", 326 "max_miss_count": 0, 327 "eventq_index": 0, 328 "default_p_state": "UNDEFINED", 329 "p_state_clk_gate_max": 1000000000000, 330 "mem_side": { 331 "peer": "system.membus.slave[1]", 332 "role": "MASTER" 333 }, 334 "mshrs": 20, 335 "writeback_clean": false, 336 "p_state_clk_gate_min": 1000, 337 "tags": { 338 "size": 2097152, 339 "tag_latency": 20, 340 "name": "tags", 341 "p_state_clk_gate_min": 1000, 342 "eventq_index": 0, 343 "p_state_clk_gate_bins": 20, 344 "default_p_state": "UNDEFINED", 345 "clk_domain": "system.cpu_clk_domain", 346 "power_model": null, 347 "sequential_access": false, 348 "assoc": 8, 349 "cxx_class": "LRU", 350 "p_state_clk_gate_max": 1000000000000, 351 "path": "system.cpu.l2cache.tags", 352 "block_size": 64, 353 "type": "LRU", 354 "data_latency": 20 355 }, 356 "tgts_per_mshr": 12, 357 "demand_mshr_reserve": 1, 358 "power_model": null, 359 "addr_ranges": [ 360 "0:18446744073709551615:0:0:0:0" 361 ], 362 "is_read_only": false, 363 "prefetch_on_access": false, 364 "path": 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"dtb", 410 "eventq_index": 0, 411 "cxx_class": "RiscvISA::TLB", 412 "path": "system.cpu.dtb", 413 "type": "RiscvTLB", 414 "size": 64 415 }, 416 "simpoint_start_insts": [], 417 "max_insts_any_thread": 0, 418 "progress_interval": 0, 419 "branchPred": null, 420 "dcache": { 421 "cpu_side": { 422 "peer": "system.cpu.dcache_port", 423 "role": "SLAVE" 424 }, 425 "clusivity": "mostly_incl", 426 "prefetcher": null, 427 "system": "system", 428 "write_buffers": 8, 429 "response_latency": 2, 430 "cxx_class": "Cache", 431 "size": 262144, 432 "type": "Cache", 433 "clk_domain": "system.cpu_clk_domain", 434 "max_miss_count": 0, 435 "eventq_index": 0, 436 "default_p_state": "UNDEFINED", 437 "p_state_clk_gate_max": 1000000000000, 438 "mem_side": { 439 "peer": "system.cpu.toL2Bus.slave[1]", 440 "role": "MASTER" 441 }, 442 "mshrs": 4, 443 "writeback_clean": false, 444 "p_state_clk_gate_min": 1000, 445 "tags": { 446 "size": 262144, 447 "tag_latency": 2, 448 "name": "tags", 449 "p_state_clk_gate_min": 1000, 450 "eventq_index": 0, 451 "p_state_clk_gate_bins": 20, 452 "default_p_state": "UNDEFINED", 453 "clk_domain": "system.cpu_clk_domain", 454 "power_model": null, 455 "sequential_access": false, 456 "assoc": 2, 457 "cxx_class": "LRU", 458 "p_state_clk_gate_max": 1000000000000, 459 "path": "system.cpu.dcache.tags", 460 "block_size": 64, 461 "type": "LRU", 462 "data_latency": 2 463 }, 464 "tgts_per_mshr": 20, 465 "demand_mshr_reserve": 1, 466 "power_model": null, 467 "addr_ranges": [ 468 "0:18446744073709551615:0:0:0:0" 469 ], 470 "is_read_only": false, 471 "prefetch_on_access": false, 472 "path": "system.cpu.dcache", 473 "data_latency": 2, 474 "tag_latency": 2, 475 "name": "dcache", 476 "p_state_clk_gate_bins": 20, 477 "sequential_access": false, 478 "assoc": 2 479 }, 480 "isa": [ 481 { 482 "eventq_index": 0, 483 "path": "system.cpu.isa", 484 "type": "RiscvISA", 485 "name": "isa", 486 "cxx_class": "RiscvISA::ISA" 487 } 488 ], 489 "tracer": { 490 "eventq_index": 0, 491 "path": "system.cpu.tracer", 492 "type": "ExeTracer", 493 "name": "tracer", 494 "cxx_class": "Trace::ExeTracer" 495 } 496 } 497 ], 498 "multi_thread": false, 499 "exit_on_work_items": false, 500 "work_item_id": -1, 501 "num_work_ids": 16 502 }, 503 "time_sync_period": 100000000000, 504 "eventq_index": 0, 505 "time_sync_spin_threshold": 100000000, 506 "cxx_class": "Root", 507 "path": "root", 508 "time_sync_enable": false, 509 "type": "Root", 510 "full_system": false 511}