config.json revision 11731:c473ca7cc650
1{ 2 "name": null, 3 "sim_quantum": 0, 4 "system": { 5 "kernel": "", 6 "mmap_using_noreserve": false, 7 "kernel_addr_check": true, 8 "symbolfile": "", 9 "readfile": "", 10 "thermal_model": null, 11 "cxx_class": "System", 12 "work_begin_cpu_id_exit": -1, 13 "load_offset": 0, 14 "work_begin_exit_count": 0, 15 "p_state_clk_gate_min": 1, 16 "memories": [ 17 "system.mem_ctrls" 18 ], 19 "work_begin_ckpt_count": 0, 20 "clk_domain": { 21 "name": "clk_domain", 22 "clock": [ 23 1 24 ], 25 "init_perf_level": 0, 26 "voltage_domain": "system.voltage_domain", 27 "eventq_index": 0, 28 "cxx_class": "SrcClockDomain", 29 "path": "system.clk_domain", 30 "type": "SrcClockDomain", 31 "domain_id": -1 32 }, 33 "mem_ranges": [ 34 "0:268435455:0:0:0:0" 35 ], 36 "eventq_index": 0, 37 "default_p_state": "UNDEFINED", 38 "p_state_clk_gate_max": 1000000000, 39 "dvfs_handler": { 40 "enable": false, 41 "name": "dvfs_handler", 42 "sys_clk_domain": "system.clk_domain", 43 "transition_latency": 100000, 44 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16 1725 }, 1726 "time_sync_period": 100000000, 1727 "eventq_index": 0, 1728 "time_sync_spin_threshold": 100000, 1729 "cxx_class": "Root", 1730 "path": "root", 1731 "time_sync_enable": false, 1732 "type": "Root", 1733 "full_system": false 1734}