stats.txt revision 11731
13048SN/A
23048SN/A---------- Begin Simulation Statistics ----------
311201Sandreas.hansson@arm.comsim_seconds                                  0.004665                       # Number of seconds simulated
411390Ssteve.reinhardt@amd.comsim_ticks                                     4665394                       # Number of ticks simulated
511390Ssteve.reinhardt@amd.comfinal_tick                                    4665394                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
68428SN/Asim_freq                                   1000000000                       # Frequency of simulated ticks
711570SCurtis.Dunham@arm.comhost_inst_rate                                  17585                       # Simulator instruction rate (inst/s)
811570SCurtis.Dunham@arm.comhost_op_rate                                    17585                       # Simulator op (including micro ops) rate (op/s)
911570SCurtis.Dunham@arm.comhost_tick_rate                                 362753                       # Simulator tick rate (ticks/s)
1011570SCurtis.Dunham@arm.comhost_mem_usage                                 412420                       # Number of bytes of host memory used
1111570SCurtis.Dunham@arm.comhost_seconds                                    12.86                       # Real time elapsed on the host
1211390Ssteve.reinhardt@amd.comsim_insts                                      226159                       # Number of instructions simulated
1311390Ssteve.reinhardt@amd.comsim_ops                                        226159                       # Number of ops (including micro ops) simulated
1410036SAli.Saidi@ARM.comsystem.voltage_domain.voltage                       1                       # Voltage in Volts
1510036SAli.Saidi@ARM.comsystem.clk_domain.clock                             1                       # Clock period in ticks
1611530Sandreas.sandberg@arm.comsystem.mem_ctrls.pwrStateResidencyTicks::UNDEFINED      4665394                       # Cumulative time (in ticks) in various power states
179055Ssaidi@eecs.umich.edusystem.mem_ctrls.bytes_read::ruby.dir_cntrl0      4623808                       # Number of bytes read from this memory
189055Ssaidi@eecs.umich.edusystem.mem_ctrls.bytes_read::total            4623808                       # Number of bytes read from this memory
199055Ssaidi@eecs.umich.edusystem.mem_ctrls.bytes_written::ruby.dir_cntrl0      4623552                       # Number of bytes written to this memory
209055Ssaidi@eecs.umich.edusystem.mem_ctrls.bytes_written::total         4623552                       # Number of bytes written to this memory
219055Ssaidi@eecs.umich.edusystem.mem_ctrls.num_reads::ruby.dir_cntrl0        72247                       # Number of read requests responded to by this memory
229055Ssaidi@eecs.umich.edusystem.mem_ctrls.num_reads::total               72247                       # Number of read requests responded to by this memory
239055Ssaidi@eecs.umich.edusystem.mem_ctrls.num_writes::ruby.dir_cntrl0        72243                       # Number of write requests responded to by this memory
249055Ssaidi@eecs.umich.edusystem.mem_ctrls.num_writes::total              72243                       # Number of write requests responded to by this memory
2511390Ssteve.reinhardt@amd.comsystem.mem_ctrls.bw_read::ruby.dir_cntrl0    991086283                       # Total read bandwidth from this memory (bytes/s)
2611390Ssteve.reinhardt@amd.comsystem.mem_ctrls.bw_read::total             991086283                       # Total read bandwidth from this memory (bytes/s)
2711390Ssteve.reinhardt@amd.comsystem.mem_ctrls.bw_write::ruby.dir_cntrl0    991031411                       # Write bandwidth from this memory (bytes/s)
2811390Ssteve.reinhardt@amd.comsystem.mem_ctrls.bw_write::total            991031411                       # Write bandwidth from this memory (bytes/s)
2911390Ssteve.reinhardt@amd.comsystem.mem_ctrls.bw_total::ruby.dir_cntrl0   1982117695                       # Total bandwidth to/from this memory (bytes/s)
3011390Ssteve.reinhardt@amd.comsystem.mem_ctrls.bw_total::total           1982117695                       # Total bandwidth to/from this memory (bytes/s)
3111390Ssteve.reinhardt@amd.comsystem.mem_ctrls.readReqs                       72247                       # Number of read requests accepted
3211390Ssteve.reinhardt@amd.comsystem.mem_ctrls.writeReqs                      72243                       # Number of write requests accepted
3311530Sandreas.sandberg@arm.comsystem.mem_ctrls.readBursts                     72247                       # Number of DRAM read bursts, including those serviced by the write queue
3410036SAli.Saidi@ARM.comsystem.mem_ctrls.writeBursts                    72243                       # Number of DRAM write bursts, including those merged in the write queue
358428SN/Asystem.mem_ctrls.bytesReadDRAM                2375168                       # Total number of bytes read from DRAM
368428SN/Asystem.mem_ctrls.bytesReadWrQ                 2248640                       # Total number of bytes read from write queue
378428SN/Asystem.mem_ctrls.bytesWritten                 2474112                       # Total number of bytes written to DRAM
388428SN/Asystem.mem_ctrls.bytesReadSys                 4623808                       # Total read bytes from the system interface side
3911390Ssteve.reinhardt@amd.comsystem.mem_ctrls.bytesWrittenSys              4623552                       # Total written bytes from the system interface side
408428SN/Asystem.mem_ctrls.servicedByWrQ                  35135                       # Number of DRAM read bursts serviced by the write queue
418428SN/Asystem.mem_ctrls.mergedWrBursts                 33568                       # Number of DRAM write bursts merged with an existing one
4211390Ssteve.reinhardt@amd.comsystem.mem_ctrls.neitherReadNorWriteReqs            0                       # Number of requests that are neither read nor write
438428SN/Asystem.mem_ctrls.perBankRdBursts::0               360                       # Per bank write bursts
448428SN/Asystem.mem_ctrls.perBankRdBursts::1               641                       # Per bank write bursts
458428SN/Asystem.mem_ctrls.perBankRdBursts::2                33                       # Per bank write bursts
468428SN/Asystem.mem_ctrls.perBankRdBursts::3              2702                       # Per bank write bursts
4711390Ssteve.reinhardt@amd.comsystem.mem_ctrls.perBankRdBursts::4              5567                       # Per bank write bursts
488428SN/Asystem.mem_ctrls.perBankRdBursts::5              5413                       # Per bank write bursts
498428SN/Asystem.mem_ctrls.perBankRdBursts::6              5211                       # Per bank write bursts
5011390Ssteve.reinhardt@amd.comsystem.mem_ctrls.perBankRdBursts::7              1018                       # Per bank write bursts
5111390Ssteve.reinhardt@amd.comsystem.mem_ctrls.perBankRdBursts::8               201                       # Per bank write bursts
528428SN/Asystem.mem_ctrls.perBankRdBursts::9               679                       # Per bank write bursts
538428SN/Asystem.mem_ctrls.perBankRdBursts::10             1777                       # Per bank write bursts
5411390Ssteve.reinhardt@amd.comsystem.mem_ctrls.perBankRdBursts::11            10251                       # Per bank write bursts
558428SN/Asystem.mem_ctrls.perBankRdBursts::12             1439                       # Per bank write bursts
568428SN/Asystem.mem_ctrls.perBankRdBursts::13             1161                       # Per bank write bursts
578428SN/Asystem.mem_ctrls.perBankRdBursts::14               39                       # Per bank write bursts
588428SN/Asystem.mem_ctrls.perBankRdBursts::15              620                       # Per bank write bursts
598428SN/Asystem.mem_ctrls.perBankWrBursts::0               374                       # Per bank write bursts
608428SN/Asystem.mem_ctrls.perBankWrBursts::1               689                       # Per bank write bursts
618428SN/Asystem.mem_ctrls.perBankWrBursts::2                35                       # Per bank write bursts
628428SN/Asystem.mem_ctrls.perBankWrBursts::3              2847                       # Per bank write bursts
638428SN/Asystem.mem_ctrls.perBankWrBursts::4              5733                       # Per bank write bursts
648428SN/Asystem.mem_ctrls.perBankWrBursts::5              5572                       # Per bank write bursts
658428SN/Asystem.mem_ctrls.perBankWrBursts::6              5809                       # Per bank write bursts
668428SN/Asystem.mem_ctrls.perBankWrBursts::7              1085                       # Per bank write bursts
678428SN/Asystem.mem_ctrls.perBankWrBursts::8               201                       # Per bank write bursts
6811530Sandreas.sandberg@arm.comsystem.mem_ctrls.perBankWrBursts::9               742                       # Per bank write bursts
6911390Ssteve.reinhardt@amd.comsystem.mem_ctrls.perBankWrBursts::10             1831                       # Per bank write bursts
708428SN/Asystem.mem_ctrls.perBankWrBursts::11            10392                       # Per bank write bursts
718428SN/Asystem.mem_ctrls.perBankWrBursts::12             1454                       # Per bank write bursts
7211390Ssteve.reinhardt@amd.comsystem.mem_ctrls.perBankWrBursts::13             1229                       # Per bank write bursts
7311390Ssteve.reinhardt@amd.comsystem.mem_ctrls.perBankWrBursts::14               39                       # Per bank write bursts
7411390Ssteve.reinhardt@amd.comsystem.mem_ctrls.perBankWrBursts::15              626                       # Per bank write bursts
758428SN/Asystem.mem_ctrls.numRdRetry                         0                       # Number of times read queue was full causing retry
768428SN/Asystem.mem_ctrls.numWrRetry                         0                       # Number of times write queue was full causing retry
7711390Ssteve.reinhardt@amd.comsystem.mem_ctrls.totGap                       4665243                       # Total gap between requests
7811390Ssteve.reinhardt@amd.comsystem.mem_ctrls.readPktSize::0                     0                       # Read request sizes (log2)
798428SN/Asystem.mem_ctrls.readPktSize::1                     0                       # Read request sizes (log2)
8011390Ssteve.reinhardt@amd.comsystem.mem_ctrls.readPktSize::2                     0                       # Read request sizes (log2)
8111390Ssteve.reinhardt@amd.comsystem.mem_ctrls.readPktSize::3                     0                       # Read request sizes (log2)
828428SN/Asystem.mem_ctrls.readPktSize::4                     0                       # Read request sizes (log2)
838428SN/Asystem.mem_ctrls.readPktSize::5                     0                       # Read request sizes (log2)
8411390Ssteve.reinhardt@amd.comsystem.mem_ctrls.readPktSize::6                 72247                       # Read request sizes (log2)
8511390Ssteve.reinhardt@amd.comsystem.mem_ctrls.writePktSize::0                    0                       # Write request sizes (log2)
868428SN/Asystem.mem_ctrls.writePktSize::1                    0                       # Write request sizes (log2)
878428SN/Asystem.mem_ctrls.writePktSize::2                    0                       # Write request sizes (log2)
8811390Ssteve.reinhardt@amd.comsystem.mem_ctrls.writePktSize::3                    0                       # Write request sizes (log2)
898428SN/Asystem.mem_ctrls.writePktSize::4                    0                       # Write request sizes (log2)
908428SN/Asystem.mem_ctrls.writePktSize::5                    0                       # Write request sizes (log2)
9111390Ssteve.reinhardt@amd.comsystem.mem_ctrls.writePktSize::6                72243                       # Write request sizes (log2)
9210220Sandreas.hansson@arm.comsystem.mem_ctrls.rdQLenPdf::0                   37112                       # What read queue length does an incoming req see
9311390Ssteve.reinhardt@amd.comsystem.mem_ctrls.rdQLenPdf::1                       0                       # What read queue length does an incoming req see
9411390Ssteve.reinhardt@amd.comsystem.mem_ctrls.rdQLenPdf::2                       0                       # What read queue length does an incoming req see
9511390Ssteve.reinhardt@amd.comsystem.mem_ctrls.rdQLenPdf::3                       0                       # What read queue length does an incoming req see
9611390Ssteve.reinhardt@amd.comsystem.mem_ctrls.rdQLenPdf::4                       0                       # What read queue length does an incoming req see
9711390Ssteve.reinhardt@amd.comsystem.mem_ctrls.rdQLenPdf::5                       0                       # What read queue length does an incoming req see
9811390Ssteve.reinhardt@amd.comsystem.mem_ctrls.rdQLenPdf::6                       0                       # What read queue length does an incoming req see
9911390Ssteve.reinhardt@amd.comsystem.mem_ctrls.rdQLenPdf::7                       0                       # What read queue length does an incoming req see
10011390Ssteve.reinhardt@amd.comsystem.mem_ctrls.rdQLenPdf::8                       0                       # What read queue length does an incoming req see
10111390Ssteve.reinhardt@amd.comsystem.mem_ctrls.rdQLenPdf::9                       0                       # What read queue length does an incoming req see
10211390Ssteve.reinhardt@amd.comsystem.mem_ctrls.rdQLenPdf::10                      0                       # What read queue length does an incoming req see
10311390Ssteve.reinhardt@amd.comsystem.mem_ctrls.rdQLenPdf::11                      0                       # What read queue length does an incoming req see
10411390Ssteve.reinhardt@amd.comsystem.mem_ctrls.rdQLenPdf::12                      0                       # What read queue length does an incoming req see
10511390Ssteve.reinhardt@amd.comsystem.mem_ctrls.rdQLenPdf::13                      0                       # What read queue length does an incoming req see
10611390Ssteve.reinhardt@amd.comsystem.mem_ctrls.rdQLenPdf::14                      0                       # What read queue length does an incoming req see
10711390Ssteve.reinhardt@amd.comsystem.mem_ctrls.rdQLenPdf::15                      0                       # What read queue length does an incoming req see
10811390Ssteve.reinhardt@amd.comsystem.mem_ctrls.rdQLenPdf::16                      0                       # What read queue length does an incoming req see
10911390Ssteve.reinhardt@amd.comsystem.mem_ctrls.rdQLenPdf::17                      0                       # What read queue length does an incoming req see
11011390Ssteve.reinhardt@amd.comsystem.mem_ctrls.rdQLenPdf::18                      0                       # What read queue length does an incoming req see
11111390Ssteve.reinhardt@amd.comsystem.mem_ctrls.rdQLenPdf::19                      0                       # What read queue length does an incoming req see
11211390Ssteve.reinhardt@amd.comsystem.mem_ctrls.rdQLenPdf::20                      0                       # What read queue length does an incoming req see
11311390Ssteve.reinhardt@amd.comsystem.mem_ctrls.rdQLenPdf::21                      0                       # What read queue length does an incoming req see
11411390Ssteve.reinhardt@amd.comsystem.mem_ctrls.rdQLenPdf::22                      0                       # What read queue length does an incoming req see
11511390Ssteve.reinhardt@amd.comsystem.mem_ctrls.rdQLenPdf::23                      0                       # What read queue length does an incoming req see
11611390Ssteve.reinhardt@amd.comsystem.mem_ctrls.rdQLenPdf::24                      0                       # What read queue length does an incoming req see
11711390Ssteve.reinhardt@amd.comsystem.mem_ctrls.rdQLenPdf::25                      0                       # What read queue length does an incoming req see
11811390Ssteve.reinhardt@amd.comsystem.mem_ctrls.rdQLenPdf::26                      0                       # What read queue length does an incoming req see
11911390Ssteve.reinhardt@amd.comsystem.mem_ctrls.rdQLenPdf::27                      0                       # What read queue length does an incoming req see
12011390Ssteve.reinhardt@amd.comsystem.mem_ctrls.rdQLenPdf::28                      0                       # What read queue length does an incoming req see
12111390Ssteve.reinhardt@amd.comsystem.mem_ctrls.rdQLenPdf::29                      0                       # What read queue length does an incoming req see
12211390Ssteve.reinhardt@amd.comsystem.mem_ctrls.rdQLenPdf::30                      0                       # What read queue length does an incoming req see
12311390Ssteve.reinhardt@amd.comsystem.mem_ctrls.rdQLenPdf::31                      0                       # What read queue length does an incoming req see
12410220Sandreas.hansson@arm.comsystem.mem_ctrls.wrQLenPdf::0                       1                       # What write queue length does an incoming req see
12510220Sandreas.hansson@arm.comsystem.mem_ctrls.wrQLenPdf::1                       1                       # What write queue length does an incoming req see
12611390Ssteve.reinhardt@amd.comsystem.mem_ctrls.wrQLenPdf::2                       1                       # What write queue length does an incoming req see
12711530Sandreas.sandberg@arm.comsystem.mem_ctrls.wrQLenPdf::3                       1                       # What write queue length does an incoming req see
1289838Sandreas.hansson@arm.comsystem.mem_ctrls.wrQLenPdf::4                       1                       # What write queue length does an incoming req see
12911390Ssteve.reinhardt@amd.comsystem.mem_ctrls.wrQLenPdf::5                       1                       # What write queue length does an incoming req see
13011390Ssteve.reinhardt@amd.comsystem.mem_ctrls.wrQLenPdf::6                       1                       # What write queue length does an incoming req see
1319838Sandreas.hansson@arm.comsystem.mem_ctrls.wrQLenPdf::7                       1                       # What write queue length does an incoming req see
13211390Ssteve.reinhardt@amd.comsystem.mem_ctrls.wrQLenPdf::8                       1                       # What write queue length does an incoming req see
1339838Sandreas.hansson@arm.comsystem.mem_ctrls.wrQLenPdf::9                       1                       # What write queue length does an incoming req see
13411390Ssteve.reinhardt@amd.comsystem.mem_ctrls.wrQLenPdf::10                      1                       # What write queue length does an incoming req see
13511390Ssteve.reinhardt@amd.comsystem.mem_ctrls.wrQLenPdf::11                      1                       # What write queue length does an incoming req see
13611390Ssteve.reinhardt@amd.comsystem.mem_ctrls.wrQLenPdf::12                      1                       # What write queue length does an incoming req see
13710036SAli.Saidi@ARM.comsystem.mem_ctrls.wrQLenPdf::13                      1                       # What write queue length does an incoming req see
13811201Sandreas.hansson@arm.comsystem.mem_ctrls.wrQLenPdf::14                      1                       # What write queue length does an incoming req see
13911201Sandreas.hansson@arm.comsystem.mem_ctrls.wrQLenPdf::15                    208                       # What write queue length does an incoming req see
14010036SAli.Saidi@ARM.comsystem.mem_ctrls.wrQLenPdf::16                    255                       # What write queue length does an incoming req see
14111390Ssteve.reinhardt@amd.comsystem.mem_ctrls.wrQLenPdf::17                   2030                       # What write queue length does an incoming req see
14211390Ssteve.reinhardt@amd.comsystem.mem_ctrls.wrQLenPdf::18                   2392                       # What write queue length does an incoming req see
14311530Sandreas.sandberg@arm.comsystem.mem_ctrls.wrQLenPdf::19                   2414                       # What write queue length does an incoming req see
14411390Ssteve.reinhardt@amd.comsystem.mem_ctrls.wrQLenPdf::20                   2512                       # What write queue length does an incoming req see
14511390Ssteve.reinhardt@amd.comsystem.mem_ctrls.wrQLenPdf::21                   2548                       # What write queue length does an incoming req see
1469481Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::22                   2499                       # What write queue length does an incoming req see
1479481Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::23                   2385                       # What write queue length does an incoming req see
14811390Ssteve.reinhardt@amd.comsystem.mem_ctrls.wrQLenPdf::24                   2380                       # What write queue length does an incoming req see
14911390Ssteve.reinhardt@amd.comsystem.mem_ctrls.wrQLenPdf::25                   2383                       # What write queue length does an incoming req see
15011390Ssteve.reinhardt@amd.comsystem.mem_ctrls.wrQLenPdf::26                   2379                       # What write queue length does an incoming req see
15111390Ssteve.reinhardt@amd.comsystem.mem_ctrls.wrQLenPdf::27                   2380                       # What write queue length does an incoming req see
1529481Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::28                   2379                       # What write queue length does an incoming req see
1539481Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::29                   2379                       # What write queue length does an incoming req see
1549481Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::30                   2379                       # What write queue length does an incoming req see
1559481Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::31                   2379                       # What write queue length does an incoming req see
1569481Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::32                   2379                       # What write queue length does an incoming req see
1579481Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::33                      0                       # What write queue length does an incoming req see
1589481Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::34                      0                       # What write queue length does an incoming req see
1599481Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::35                      0                       # What write queue length does an incoming req see
16011201Sandreas.hansson@arm.comsystem.mem_ctrls.wrQLenPdf::36                      0                       # What write queue length does an incoming req see
16111201Sandreas.hansson@arm.comsystem.mem_ctrls.wrQLenPdf::37                      0                       # What write queue length does an incoming req see
16211201Sandreas.hansson@arm.comsystem.mem_ctrls.wrQLenPdf::38                      0                       # What write queue length does an incoming req see
16311201Sandreas.hansson@arm.comsystem.mem_ctrls.wrQLenPdf::39                      0                       # What write queue length does an incoming req see
16411201Sandreas.hansson@arm.comsystem.mem_ctrls.wrQLenPdf::40                      0                       # What write queue length does an incoming req see
16511201Sandreas.hansson@arm.comsystem.mem_ctrls.wrQLenPdf::41                      0                       # What write queue length does an incoming req see
16611201Sandreas.hansson@arm.comsystem.mem_ctrls.wrQLenPdf::42                      0                       # What write queue length does an incoming req see
16711201Sandreas.hansson@arm.comsystem.mem_ctrls.wrQLenPdf::43                      0                       # What write queue length does an incoming req see
16811390Ssteve.reinhardt@amd.comsystem.mem_ctrls.wrQLenPdf::44                      0                       # What write queue length does an incoming req see
16911390Ssteve.reinhardt@amd.comsystem.mem_ctrls.wrQLenPdf::45                      0                       # What write queue length does an incoming req see
1709481Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::46                      0                       # What write queue length does an incoming req see
1719481Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::47                      0                       # What write queue length does an incoming req see
17211390Ssteve.reinhardt@amd.comsystem.mem_ctrls.wrQLenPdf::48                      0                       # What write queue length does an incoming req see
17311390Ssteve.reinhardt@amd.comsystem.mem_ctrls.wrQLenPdf::49                      0                       # What write queue length does an incoming req see
17411390Ssteve.reinhardt@amd.comsystem.mem_ctrls.wrQLenPdf::50                      0                       # What write queue length does an incoming req see
17511390Ssteve.reinhardt@amd.comsystem.mem_ctrls.wrQLenPdf::51                      0                       # What write queue length does an incoming req see
17611390Ssteve.reinhardt@amd.comsystem.mem_ctrls.wrQLenPdf::52                      0                       # What write queue length does an incoming req see
17711390Ssteve.reinhardt@amd.comsystem.mem_ctrls.wrQLenPdf::53                      0                       # What write queue length does an incoming req see
1789481Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::54                      0                       # What write queue length does an incoming req see
1799481Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::55                      0                       # What write queue length does an incoming req see
18011390Ssteve.reinhardt@amd.comsystem.mem_ctrls.wrQLenPdf::56                      0                       # What write queue length does an incoming req see
18111390Ssteve.reinhardt@amd.comsystem.mem_ctrls.wrQLenPdf::57                      0                       # What write queue length does an incoming req see
18211390Ssteve.reinhardt@amd.comsystem.mem_ctrls.wrQLenPdf::58                      0                       # What write queue length does an incoming req see
18311390Ssteve.reinhardt@amd.comsystem.mem_ctrls.wrQLenPdf::59                      0                       # What write queue length does an incoming req see
18411201Sandreas.hansson@arm.comsystem.mem_ctrls.wrQLenPdf::60                      0                       # What write queue length does an incoming req see
18511201Sandreas.hansson@arm.comsystem.mem_ctrls.wrQLenPdf::61                      0                       # What write queue length does an incoming req see
18611201Sandreas.hansson@arm.comsystem.mem_ctrls.wrQLenPdf::62                      0                       # What write queue length does an incoming req see
18711201Sandreas.hansson@arm.comsystem.mem_ctrls.wrQLenPdf::63                      0                       # What write queue length does an incoming req see
18811201Sandreas.hansson@arm.comsystem.mem_ctrls.bytesPerActivate::samples        13232                       # Bytes accessed per row activation
18911201Sandreas.hansson@arm.comsystem.mem_ctrls.bytesPerActivate::mean    366.340992                       # Bytes accessed per row activation
19011201Sandreas.hansson@arm.comsystem.mem_ctrls.bytesPerActivate::gmean   230.810737                       # Bytes accessed per row activation
19111201Sandreas.hansson@arm.comsystem.mem_ctrls.bytesPerActivate::stdev   342.245951                       # Bytes accessed per row activation
1929481Snilay@cs.wisc.edusystem.mem_ctrls.bytesPerActivate::0-127         3082     23.29%     23.29% # Bytes accessed per row activation
1939481Snilay@cs.wisc.edusystem.mem_ctrls.bytesPerActivate::128-255         3681     27.82%     51.11% # Bytes accessed per row activation
1949481Snilay@cs.wisc.edusystem.mem_ctrls.bytesPerActivate::256-383         1764     13.33%     64.44% # Bytes accessed per row activation
1959481Snilay@cs.wisc.edusystem.mem_ctrls.bytesPerActivate::384-511          976      7.38%     71.82% # Bytes accessed per row activation
1969481Snilay@cs.wisc.edusystem.mem_ctrls.bytesPerActivate::512-639          696      5.26%     77.08% # Bytes accessed per row activation
1979481Snilay@cs.wisc.edusystem.mem_ctrls.bytesPerActivate::640-767          455      3.44%     80.52% # Bytes accessed per row activation
1989481Snilay@cs.wisc.edusystem.mem_ctrls.bytesPerActivate::768-895          307      2.32%     82.84% # Bytes accessed per row activation
1999481Snilay@cs.wisc.edusystem.mem_ctrls.bytesPerActivate::896-1023          275      2.08%     84.92% # Bytes accessed per row activation
2009481Snilay@cs.wisc.edusystem.mem_ctrls.bytesPerActivate::1024-1151         1996     15.08%    100.00% # Bytes accessed per row activation
2019481Snilay@cs.wisc.edusystem.mem_ctrls.bytesPerActivate::total        13232                       # Bytes accessed per row activation
2029481Snilay@cs.wisc.edusystem.mem_ctrls.rdPerTurnAround::samples         2379                       # Reads before turning the bus around for writes
2039481Snilay@cs.wisc.edusystem.mem_ctrls.rdPerTurnAround::mean      15.599412                       # Reads before turning the bus around for writes
2049481Snilay@cs.wisc.edusystem.mem_ctrls.rdPerTurnAround::gmean     15.547106                       # Reads before turning the bus around for writes
2059481Snilay@cs.wisc.edusystem.mem_ctrls.rdPerTurnAround::stdev      1.309736                       # Reads before turning the bus around for writes
20611201Sandreas.hansson@arm.comsystem.mem_ctrls.rdPerTurnAround::12-13            94      3.95%      3.95% # Reads before turning the bus around for writes
20711201Sandreas.hansson@arm.comsystem.mem_ctrls.rdPerTurnAround::14-15          1021     42.92%     46.87% # Reads before turning the bus around for writes
20811201Sandreas.hansson@arm.comsystem.mem_ctrls.rdPerTurnAround::16-17          1131     47.54%     94.41% # Reads before turning the bus around for writes
20911201Sandreas.hansson@arm.comsystem.mem_ctrls.rdPerTurnAround::18-19           122      5.13%     99.54% # Reads before turning the bus around for writes
21011201Sandreas.hansson@arm.comsystem.mem_ctrls.rdPerTurnAround::20-21            10      0.42%     99.96% # Reads before turning the bus around for writes
21111201Sandreas.hansson@arm.comsystem.mem_ctrls.rdPerTurnAround::36-37             1      0.04%    100.00% # Reads before turning the bus around for writes
21211201Sandreas.hansson@arm.comsystem.mem_ctrls.rdPerTurnAround::total          2379                       # Reads before turning the bus around for writes
21311201Sandreas.hansson@arm.comsystem.mem_ctrls.wrPerTurnAround::samples         2379                       # Writes before turning the bus around for reads
21411390Ssteve.reinhardt@amd.comsystem.mem_ctrls.wrPerTurnAround::mean      16.249685                       # Writes before turning the bus around for reads
21511390Ssteve.reinhardt@amd.comsystem.mem_ctrls.wrPerTurnAround::gmean     16.232515                       # Writes before turning the bus around for reads
2169481Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::stdev      0.782399                       # Writes before turning the bus around for reads
2179481Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::16             2139     89.91%     89.91% # Writes before turning the bus around for reads
21811390Ssteve.reinhardt@amd.comsystem.mem_ctrls.wrPerTurnAround::17               18      0.76%     90.67% # Writes before turning the bus around for reads
21911390Ssteve.reinhardt@amd.comsystem.mem_ctrls.wrPerTurnAround::18              109      4.58%     95.25% # Writes before turning the bus around for reads
22011390Ssteve.reinhardt@amd.comsystem.mem_ctrls.wrPerTurnAround::19               94      3.95%     99.20% # Writes before turning the bus around for reads
22111390Ssteve.reinhardt@amd.comsystem.mem_ctrls.wrPerTurnAround::20               19      0.80%    100.00% # Writes before turning the bus around for reads
22211201Sandreas.hansson@arm.comsystem.mem_ctrls.wrPerTurnAround::total          2379                       # Writes before turning the bus around for reads
22311201Sandreas.hansson@arm.comsystem.mem_ctrls.totQLat                       719075                       # Total ticks spent queuing
22411201Sandreas.hansson@arm.comsystem.mem_ctrls.totMemAccLat                 1424203                       # Total ticks spent from burst creation until serviced by the DRAM
22511201Sandreas.hansson@arm.comsystem.mem_ctrls.totBusLat                     185560                       # Total ticks spent in databus transfers
22611201Sandreas.hansson@arm.comsystem.mem_ctrls.avgQLat                        19.38                       # Average queueing delay per DRAM burst
22711201Sandreas.hansson@arm.comsystem.mem_ctrls.avgBusLat                       5.00                       # Average bus latency per DRAM burst
22811201Sandreas.hansson@arm.comsystem.mem_ctrls.avgMemAccLat                   38.38                       # Average memory access latency per DRAM burst
22911201Sandreas.hansson@arm.comsystem.mem_ctrls.avgRdBW                       509.10                       # Average DRAM read bandwidth in MiByte/s
23011530Sandreas.sandberg@arm.comsystem.mem_ctrls.avgWrBW                       530.31                       # Average achieved write bandwidth in MiByte/s
23110726Sandreas.hansson@arm.comsystem.mem_ctrls.avgRdBWSys                    991.09                       # Average system read bandwidth in MiByte/s
23211390Ssteve.reinhardt@amd.comsystem.mem_ctrls.avgWrBWSys                    991.03                       # Average system write bandwidth in MiByte/s
23311390Ssteve.reinhardt@amd.comsystem.mem_ctrls.peakBW                      12800.00                       # Theoretical peak bandwidth in MiByte/s
23410726Sandreas.hansson@arm.comsystem.mem_ctrls.busUtil                         8.12                       # Data bus utilization in percentage
23511390Ssteve.reinhardt@amd.comsystem.mem_ctrls.busUtilRead                     3.98                       # Data bus utilization in percentage for reads
23610726Sandreas.hansson@arm.comsystem.mem_ctrls.busUtilWrite                    4.14                       # Data bus utilization in percentage for writes
23711390Ssteve.reinhardt@amd.comsystem.mem_ctrls.avgRdQLen                       1.00                       # Average read queue length when enqueuing
23811390Ssteve.reinhardt@amd.comsystem.mem_ctrls.avgWrQLen                      25.97                       # Average write queue length when enqueuing
23911390Ssteve.reinhardt@amd.comsystem.mem_ctrls.readRowHits                    27462                       # Number of row buffer hits during reads
24010726Sandreas.hansson@arm.comsystem.mem_ctrls.writeRowHits                   35070                       # Number of row buffer hits during writes
24111201Sandreas.hansson@arm.comsystem.mem_ctrls.readRowHitRate                 74.00                       # Row buffer hit rate for reads
24211201Sandreas.hansson@arm.comsystem.mem_ctrls.writeRowHitRate                90.68                       # Row buffer hit rate for writes
24310726Sandreas.hansson@arm.comsystem.mem_ctrls.avgGap                         32.29                       # Average gap between requests
24411390Ssteve.reinhardt@amd.comsystem.mem_ctrls.pageHitRate                    82.51                       # Row buffer hit rate, read and write combined
24511390Ssteve.reinhardt@amd.comsystem.mem_ctrls_0.actEnergy                 60632880                       # Energy for activate commands per rank (pJ)
24611530Sandreas.sandberg@arm.comsystem.mem_ctrls_0.preEnergy                 32801496                       # Energy for precharge commands per rank (pJ)
24711390Ssteve.reinhardt@amd.comsystem.mem_ctrls_0.readEnergy               239275680                       # Energy for read commands per rank (pJ)
24811390Ssteve.reinhardt@amd.comsystem.mem_ctrls_0.writeEnergy              184946688                       # Energy for write commands per rank (pJ)
24911390Ssteve.reinhardt@amd.comsystem.mem_ctrls_0.refreshEnergy         366325440.000000                       # Energy for refresh commands per rank (pJ)
25011390Ssteve.reinhardt@amd.comsystem.mem_ctrls_0.actBackEnergy            608748144                       # Energy for active background per rank (pJ)
25111390Ssteve.reinhardt@amd.comsystem.mem_ctrls_0.preBackEnergy              8669568                       # Energy for precharge background per rank (pJ)
25211390Ssteve.reinhardt@amd.comsystem.mem_ctrls_0.actPowerDownEnergy      1381360344                       # Energy for active power-down per rank (pJ)
25310726Sandreas.hansson@arm.comsystem.mem_ctrls_0.prePowerDownEnergy        69824640                       # Energy for precharge power-down per rank (pJ)
25410726Sandreas.hansson@arm.comsystem.mem_ctrls_0.selfRefreshEnergy         28732560                       # Energy for self refresh per rank (pJ)
25510726Sandreas.hansson@arm.comsystem.mem_ctrls_0.totalEnergy             2981317440                       # Total energy per rank (pJ)
25610726Sandreas.hansson@arm.comsystem.mem_ctrls_0.averagePower            639.028009                       # Core power per rank (mW)
25710726Sandreas.hansson@arm.comsystem.mem_ctrls_0.totalIdleTime              3307806                       # Total Idle time Per DRAM Rank
25810726Sandreas.hansson@arm.comsystem.mem_ctrls_0.memoryStateTime::IDLE         5774                       # Time in different power states
25911201Sandreas.hansson@arm.comsystem.mem_ctrls_0.memoryStateTime::REF        155020                       # Time in different power states
26011201Sandreas.hansson@arm.comsystem.mem_ctrls_0.memoryStateTime::SREF        96709                       # Time in different power states
26111201Sandreas.hansson@arm.comsystem.mem_ctrls_0.memoryStateTime::PRE_PDN       181835                       # Time in different power states
26211201Sandreas.hansson@arm.comsystem.mem_ctrls_0.memoryStateTime::ACT       1196757                       # Time in different power states
26311201Sandreas.hansson@arm.comsystem.mem_ctrls_0.memoryStateTime::ACT_PDN      3029299                       # Time in different power states
26411201Sandreas.hansson@arm.comsystem.mem_ctrls_1.actEnergy                 33886440                       # Energy for activate commands per rank (pJ)
26511390Ssteve.reinhardt@amd.comsystem.mem_ctrls_1.preEnergy                 18326952                       # Energy for precharge commands per rank (pJ)
26611390Ssteve.reinhardt@amd.comsystem.mem_ctrls_1.readEnergy               184691808                       # Energy for read commands per rank (pJ)
26711390Ssteve.reinhardt@amd.comsystem.mem_ctrls_1.writeEnergy              137924928                       # Energy for write commands per rank (pJ)
26811390Ssteve.reinhardt@amd.comsystem.mem_ctrls_1.refreshEnergy         348500880.000000                       # Energy for refresh commands per rank (pJ)
26911390Ssteve.reinhardt@amd.comsystem.mem_ctrls_1.actBackEnergy            590211744                       # Energy for active background per rank (pJ)
27011390Ssteve.reinhardt@amd.comsystem.mem_ctrls_1.preBackEnergy             11048832                       # Energy for precharge background per rank (pJ)
27111390Ssteve.reinhardt@amd.comsystem.mem_ctrls_1.actPowerDownEnergy      1320078504                       # Energy for active power-down per rank (pJ)
27211390Ssteve.reinhardt@amd.comsystem.mem_ctrls_1.prePowerDownEnergy        60484992                       # Energy for precharge power-down per rank (pJ)
27311390Ssteve.reinhardt@amd.comsystem.mem_ctrls_1.selfRefreshEnergy         72883440                       # Energy for self refresh per rank (pJ)
27411390Ssteve.reinhardt@amd.comsystem.mem_ctrls_1.totalEnergy             2778038520                       # Total energy per rank (pJ)
27511390Ssteve.reinhardt@amd.comsystem.mem_ctrls_1.averagePower            595.456358                       # Core power per rank (mW)
27611390Ssteve.reinhardt@amd.comsystem.mem_ctrls_1.totalIdleTime              3342297                       # Total Idle time Per DRAM Rank
27711201Sandreas.hansson@arm.comsystem.mem_ctrls_1.memoryStateTime::IDLE        12341                       # Time in different power states
27811201Sandreas.hansson@arm.comsystem.mem_ctrls_1.memoryStateTime::REF        147456                       # Time in different power states
27911201Sandreas.hansson@arm.comsystem.mem_ctrls_1.memoryStateTime::SREF       289875                       # Time in different power states
28011201Sandreas.hansson@arm.comsystem.mem_ctrls_1.memoryStateTime::PRE_PDN       157513                       # Time in different power states
28111201Sandreas.hansson@arm.comsystem.mem_ctrls_1.memoryStateTime::ACT       1163300                       # Time in different power states
28211201Sandreas.hansson@arm.comsystem.mem_ctrls_1.memoryStateTime::ACT_PDN      2894909                       # Time in different power states
28310726Sandreas.hansson@arm.comsystem.pwrStateResidencyTicks::UNDEFINED      4665394                       # Cumulative time (in ticks) in various power states
28410726Sandreas.hansson@arm.comsystem.cpu.clk_domain.clock                         1                       # Clock period in ticks
28510726Sandreas.hansson@arm.comsystem.cpu.dtb.read_hits                            0                       # DTB read hits
28610726Sandreas.hansson@arm.comsystem.cpu.dtb.read_misses                          0                       # DTB read misses
28710726Sandreas.hansson@arm.comsystem.cpu.dtb.read_accesses                        0                       # DTB read accesses
28810726Sandreas.hansson@arm.comsystem.cpu.dtb.write_hits                           0                       # DTB write hits
28910726Sandreas.hansson@arm.comsystem.cpu.dtb.write_misses                         0                       # DTB write misses
29010726Sandreas.hansson@arm.comsystem.cpu.dtb.write_accesses                       0                       # DTB write accesses
29110726Sandreas.hansson@arm.comsystem.cpu.dtb.hits                                 0                       # DTB hits
29210726Sandreas.hansson@arm.comsystem.cpu.dtb.misses                               0                       # DTB misses
29310726Sandreas.hansson@arm.comsystem.cpu.dtb.accesses                             0                       # DTB accesses
29410726Sandreas.hansson@arm.comsystem.cpu.itb.read_hits                            0                       # DTB read hits
29511201Sandreas.hansson@arm.comsystem.cpu.itb.read_misses                          0                       # DTB read misses
29611201Sandreas.hansson@arm.comsystem.cpu.itb.read_accesses                        0                       # DTB read accesses
29711201Sandreas.hansson@arm.comsystem.cpu.itb.write_hits                           0                       # DTB write hits
29811201Sandreas.hansson@arm.comsystem.cpu.itb.write_misses                         0                       # DTB write misses
29911201Sandreas.hansson@arm.comsystem.cpu.itb.write_accesses                       0                       # DTB write accesses
30011201Sandreas.hansson@arm.comsystem.cpu.itb.hits                                 0                       # DTB hits
30111390Ssteve.reinhardt@amd.comsystem.cpu.itb.misses                               0                       # DTB misses
30211390Ssteve.reinhardt@amd.comsystem.cpu.itb.accesses                             0                       # DTB accesses
30311390Ssteve.reinhardt@amd.comsystem.cpu.workload.num_syscalls                  115                       # Number of system calls
30411390Ssteve.reinhardt@amd.comsystem.cpu.pwrStateResidencyTicks::ON         4665394                       # Cumulative time (in ticks) in various power states
30511390Ssteve.reinhardt@amd.comsystem.cpu.numCycles                          4665394                       # number of cpu cycles simulated
30611390Ssteve.reinhardt@amd.comsystem.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
30711201Sandreas.hansson@arm.comsystem.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
30811201Sandreas.hansson@arm.comsystem.cpu.committedInsts                      226159                       # Number of instructions committed
30911201Sandreas.hansson@arm.comsystem.cpu.committedOps                        226159                       # Number of ops (including micro ops) committed
31011201Sandreas.hansson@arm.comsystem.cpu.num_int_alu_accesses                225992                       # Number of integer alu accesses
31111201Sandreas.hansson@arm.comsystem.cpu.num_fp_alu_accesses                    862                       # Number of float alu accesses
31211201Sandreas.hansson@arm.comsystem.cpu.num_func_calls                       16616                       # number of times a function call or return occured
31311530Sandreas.sandberg@arm.comsystem.cpu.num_conditional_control_insts        33789                       # number of instructions that are conditional controls
31410726Sandreas.hansson@arm.comsystem.cpu.num_int_insts                       225992                       # number of integer instructions
31511390Ssteve.reinhardt@amd.comsystem.cpu.num_fp_insts                           862                       # number of float instructions
31610726Sandreas.hansson@arm.comsystem.cpu.num_int_register_reads              298589                       # number of times the integer registers were read
31710726Sandreas.hansson@arm.comsystem.cpu.num_int_register_writes             154866                       # number of times the integer registers were written
31810726Sandreas.hansson@arm.comsystem.cpu.num_fp_register_reads                  733                       # number of times the floating registers were read
31910726Sandreas.hansson@arm.comsystem.cpu.num_fp_register_writes                 588                       # number of times the floating registers were written
32011390Ssteve.reinhardt@amd.comsystem.cpu.num_mem_refs                         88941                       # number of memory refs
32111390Ssteve.reinhardt@amd.comsystem.cpu.num_load_insts                       51711                       # Number of load instructions
32211390Ssteve.reinhardt@amd.comsystem.cpu.num_store_insts                      37230                       # Number of store instructions
32311390Ssteve.reinhardt@amd.comsystem.cpu.num_idle_cycles                          0                       # Number of idle cycles
32411390Ssteve.reinhardt@amd.comsystem.cpu.num_busy_cycles                    4665394                       # Number of busy cycles
32510726Sandreas.hansson@arm.comsystem.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
32611201Sandreas.hansson@arm.comsystem.cpu.idle_fraction                            0                       # Percentage of idle cycles
32711201Sandreas.hansson@arm.comsystem.cpu.Branches                             50405                       # Number of branches fetched
32810726Sandreas.hansson@arm.comsystem.cpu.op_class::No_OpClass                   117      0.05%      0.05% # Class of executed instruction
32910726Sandreas.hansson@arm.comsystem.cpu.op_class::IntAlu                    136540     60.34%     60.39% # Class of executed instruction
33010726Sandreas.hansson@arm.comsystem.cpu.op_class::IntMult                      325      0.14%     60.54% # Class of executed instruction
33111530Sandreas.sandberg@arm.comsystem.cpu.op_class::IntDiv                        40      0.02%     60.56% # Class of executed instruction
33210892Sandreas.hansson@arm.comsystem.cpu.op_class::FloatAdd                     104      0.05%     60.60% # Class of executed instruction
33310892Sandreas.hansson@arm.comsystem.cpu.op_class::FloatCmp                     119      0.05%     60.65% # Class of executed instruction
33410726Sandreas.hansson@arm.comsystem.cpu.op_class::FloatCvt                      43      0.02%     60.67% # Class of executed instruction
33510726Sandreas.hansson@arm.comsystem.cpu.op_class::FloatMult                     30      0.01%     60.69% # Class of executed instruction
33610726Sandreas.hansson@arm.comsystem.cpu.op_class::FloatMultAcc                   0      0.00%     60.69% # Class of executed instruction
33710726Sandreas.hansson@arm.comsystem.cpu.op_class::FloatDiv                      11      0.00%     60.69% # Class of executed instruction
33810726Sandreas.hansson@arm.comsystem.cpu.op_class::FloatMisc                      0      0.00%     60.69% # Class of executed instruction
33910726Sandreas.hansson@arm.comsystem.cpu.op_class::FloatSqrt                      5      0.00%     60.69% # Class of executed instruction
34010892Sandreas.hansson@arm.comsystem.cpu.op_class::SimdAdd                        0      0.00%     60.69% # Class of executed instruction
34110892Sandreas.hansson@arm.comsystem.cpu.op_class::SimdAddAcc                     0      0.00%     60.69% # Class of executed instruction
34210892Sandreas.hansson@arm.comsystem.cpu.op_class::SimdAlu                        0      0.00%     60.69% # Class of executed instruction
34310892Sandreas.hansson@arm.comsystem.cpu.op_class::SimdCmp                        0      0.00%     60.69% # Class of executed instruction
34410726Sandreas.hansson@arm.comsystem.cpu.op_class::SimdCvt                        0      0.00%     60.69% # Class of executed instruction
34510726Sandreas.hansson@arm.comsystem.cpu.op_class::SimdMisc                       0      0.00%     60.69% # Class of executed instruction
34610726Sandreas.hansson@arm.comsystem.cpu.op_class::SimdMult                       0      0.00%     60.69% # Class of executed instruction
34710726Sandreas.hansson@arm.comsystem.cpu.op_class::SimdMultAcc                    0      0.00%     60.69% # Class of executed instruction
34810726Sandreas.hansson@arm.comsystem.cpu.op_class::SimdShift                      0      0.00%     60.69% # Class of executed instruction
34910726Sandreas.hansson@arm.comsystem.cpu.op_class::SimdShiftAcc                   0      0.00%     60.69% # Class of executed instruction
35011201Sandreas.hansson@arm.comsystem.cpu.op_class::SimdSqrt                       0      0.00%     60.69% # Class of executed instruction
35111201Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatAdd                   0      0.00%     60.69% # Class of executed instruction
35211201Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatAlu                   0      0.00%     60.69% # Class of executed instruction
35311201Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatCmp                   0      0.00%     60.69% # Class of executed instruction
35411201Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatCvt                   0      0.00%     60.69% # Class of executed instruction
35511201Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatDiv                   0      0.00%     60.69% # Class of executed instruction
35611201Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatMisc                  0      0.00%     60.69% # Class of executed instruction
35711201Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatMult                  0      0.00%     60.69% # Class of executed instruction
35811201Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatMultAcc               0      0.00%     60.69% # Class of executed instruction
35911201Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatSqrt                  0      0.00%     60.69% # Class of executed instruction
36011201Sandreas.hansson@arm.comsystem.cpu.op_class::MemRead                    51297     22.67%     83.36% # Class of executed instruction
36111201Sandreas.hansson@arm.comsystem.cpu.op_class::MemWrite                   37094     16.39%     99.76% # Class of executed instruction
36210726Sandreas.hansson@arm.comsystem.cpu.op_class::FloatMemRead                 414      0.18%     99.94% # Class of executed instruction
36310726Sandreas.hansson@arm.comsystem.cpu.op_class::FloatMemWrite                136      0.06%    100.00% # Class of executed instruction
36410892Sandreas.hansson@arm.comsystem.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
36510892Sandreas.hansson@arm.comsystem.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
36610892Sandreas.hansson@arm.comsystem.cpu.op_class::total                     226275                       # Class of executed instruction
36710892Sandreas.hansson@arm.comsystem.ruby.clk_domain.clock                        1                       # Clock period in ticks
36810726Sandreas.hansson@arm.comsystem.ruby.pwrStateResidencyTicks::UNDEFINED      4665394                       # Cumulative time (in ticks) in various power states
36910726Sandreas.hansson@arm.comsystem.ruby.delayHist::bucket_size                  1                       # delay histogram for all message
37010726Sandreas.hansson@arm.comsystem.ruby.delayHist::max_bucket                   9                       # delay histogram for all message
37110726Sandreas.hansson@arm.comsystem.ruby.delayHist::samples                 144490                       # delay histogram for all message
37210726Sandreas.hansson@arm.comsystem.ruby.delayHist                    |      144490    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% # delay histogram for all message
37310726Sandreas.hansson@arm.comsystem.ruby.delayHist::total                   144490                       # delay histogram for all message
37410726Sandreas.hansson@arm.comsystem.ruby.outstanding_req_hist_seqr::bucket_size            1                      
37510726Sandreas.hansson@arm.comsystem.ruby.outstanding_req_hist_seqr::max_bucket            9                      
37610892Sandreas.hansson@arm.comsystem.ruby.outstanding_req_hist_seqr::samples       315216                      
37710892Sandreas.hansson@arm.comsystem.ruby.outstanding_req_hist_seqr::mean            1                      
37810892Sandreas.hansson@arm.comsystem.ruby.outstanding_req_hist_seqr::gmean            1                      
37910892Sandreas.hansson@arm.comsystem.ruby.outstanding_req_hist_seqr    |           0      0.00%      0.00% |      315216    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
38010726Sandreas.hansson@arm.comsystem.ruby.outstanding_req_hist_seqr::total       315216                      
38110726Sandreas.hansson@arm.comsystem.ruby.latency_hist_seqr::bucket_size           64                      
38210726Sandreas.hansson@arm.comsystem.ruby.latency_hist_seqr::max_bucket          639                      
38310726Sandreas.hansson@arm.comsystem.ruby.latency_hist_seqr::samples         315215                      
38410726Sandreas.hansson@arm.comsystem.ruby.latency_hist_seqr::mean         13.800673                      
38510726Sandreas.hansson@arm.comsystem.ruby.latency_hist_seqr::gmean         2.449814                      
38611201Sandreas.hansson@arm.comsystem.ruby.latency_hist_seqr::stdev        29.448647                      
38711201Sandreas.hansson@arm.comsystem.ruby.latency_hist_seqr            |      279385     88.63%     88.63% |       33252     10.55%     99.18% |        1716      0.54%     99.73% |         307      0.10%     99.82% |         278      0.09%     99.91% |         236      0.07%     99.99% |          20      0.01%     99.99% |           8      0.00%    100.00% |           0      0.00%    100.00% |          13      0.00%    100.00%
38811201Sandreas.hansson@arm.comsystem.ruby.latency_hist_seqr::total           315215                      
38911201Sandreas.hansson@arm.comsystem.ruby.hit_latency_hist_seqr::bucket_size            1                      
39011201Sandreas.hansson@arm.comsystem.ruby.hit_latency_hist_seqr::max_bucket            9                      
39111201Sandreas.hansson@arm.comsystem.ruby.hit_latency_hist_seqr::samples       242968                      
39211201Sandreas.hansson@arm.comsystem.ruby.hit_latency_hist_seqr::mean             1                      
39311201Sandreas.hansson@arm.comsystem.ruby.hit_latency_hist_seqr::gmean            1                      
39411201Sandreas.hansson@arm.comsystem.ruby.hit_latency_hist_seqr        |           0      0.00%      0.00% |      242968    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
39511201Sandreas.hansson@arm.comsystem.ruby.hit_latency_hist_seqr::total       242968                      
39611201Sandreas.hansson@arm.comsystem.ruby.miss_latency_hist_seqr::bucket_size           64                      
39711201Sandreas.hansson@arm.comsystem.ruby.miss_latency_hist_seqr::max_bucket          639                      
39810726Sandreas.hansson@arm.comsystem.ruby.miss_latency_hist_seqr::samples        72247                      
39910726Sandreas.hansson@arm.comsystem.ruby.miss_latency_hist_seqr::mean    56.849572                      
40010726Sandreas.hansson@arm.comsystem.ruby.miss_latency_hist_seqr::gmean    49.864909                      
40110726Sandreas.hansson@arm.comsystem.ruby.miss_latency_hist_seqr::stdev    37.140999                      
40210726Sandreas.hansson@arm.comsystem.ruby.miss_latency_hist_seqr       |       36417     50.41%     50.41% |       33252     46.03%     96.43% |        1716      2.38%     98.81% |         307      0.42%     99.23% |         278      0.38%     99.62% |         236      0.33%     99.94% |          20      0.03%     99.97% |           8      0.01%     99.98% |           0      0.00%     99.98% |          13      0.02%    100.00%
40310726Sandreas.hansson@arm.comsystem.ruby.miss_latency_hist_seqr::total        72247                      
40410726Sandreas.hansson@arm.comsystem.ruby.Directory.incomplete_times_seqr        72246                      
40510726Sandreas.hansson@arm.comsystem.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED      4665394                       # Cumulative time (in ticks) in various power states
40610892Sandreas.hansson@arm.comsystem.ruby.l1_cntrl0.cacheMemory.demand_hits       242968                       # Number of cache demand hits
40710892Sandreas.hansson@arm.comsystem.ruby.l1_cntrl0.cacheMemory.demand_misses        72247                       # Number of cache demand misses
40810892Sandreas.hansson@arm.comsystem.ruby.l1_cntrl0.cacheMemory.demand_accesses       315215                       # Number of cache demand accesses
40910892Sandreas.hansson@arm.comsystem.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED      4665394                       # Cumulative time (in ticks) in various power states
41010726Sandreas.hansson@arm.comsystem.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED      4665394                       # Cumulative time (in ticks) in various power states
41110726Sandreas.hansson@arm.comsystem.ruby.memctrl_clk_domain.clock                3                       # Clock period in ticks
41210726Sandreas.hansson@arm.comsystem.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED      4665394                       # Cumulative time (in ticks) in various power states
41310726Sandreas.hansson@arm.comsystem.ruby.network.routers0.percent_links_utilized     7.742647                      
41410726Sandreas.hansson@arm.comsystem.ruby.network.routers0.msg_count.Control::2        72247                      
41510726Sandreas.hansson@arm.comsystem.ruby.network.routers0.msg_count.Data::2        72243                      
41611201Sandreas.hansson@arm.comsystem.ruby.network.routers0.msg_count.Response_Data::4        72247                      
41711201Sandreas.hansson@arm.comsystem.ruby.network.routers0.msg_count.Writeback_Control::3        72243                      
41811201Sandreas.hansson@arm.comsystem.ruby.network.routers0.msg_bytes.Control::2       577976                      
41911201Sandreas.hansson@arm.comsystem.ruby.network.routers0.msg_bytes.Data::2      5201496                      
42011201Sandreas.hansson@arm.comsystem.ruby.network.routers0.msg_bytes.Response_Data::4      5201784                      
42111201Sandreas.hansson@arm.comsystem.ruby.network.routers0.msg_bytes.Writeback_Control::3       577944                      
42211201Sandreas.hansson@arm.comsystem.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED      4665394                       # Cumulative time (in ticks) in various power states
42311201Sandreas.hansson@arm.comsystem.ruby.network.routers1.percent_links_utilized     7.742647                      
42411201Sandreas.hansson@arm.comsystem.ruby.network.routers1.msg_count.Control::2        72247                      
42511201Sandreas.hansson@arm.comsystem.ruby.network.routers1.msg_count.Data::2        72243                      
42611201Sandreas.hansson@arm.comsystem.ruby.network.routers1.msg_count.Response_Data::4        72247                      
42711201Sandreas.hansson@arm.comsystem.ruby.network.routers1.msg_count.Writeback_Control::3        72243                      
42810726Sandreas.hansson@arm.comsystem.ruby.network.routers1.msg_bytes.Control::2       577976                      
42910726Sandreas.hansson@arm.comsystem.ruby.network.routers1.msg_bytes.Data::2      5201496                      
43010892Sandreas.hansson@arm.comsystem.ruby.network.routers1.msg_bytes.Response_Data::4      5201784                      
43110892Sandreas.hansson@arm.comsystem.ruby.network.routers1.msg_bytes.Writeback_Control::3       577944                      
43210892Sandreas.hansson@arm.comsystem.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED      4665394                       # Cumulative time (in ticks) in various power states
43310892Sandreas.hansson@arm.comsystem.ruby.network.routers2.percent_links_utilized     7.742647                      
43410726Sandreas.hansson@arm.comsystem.ruby.network.routers2.msg_count.Control::2        72247                      
43510726Sandreas.hansson@arm.comsystem.ruby.network.routers2.msg_count.Data::2        72243                      
43610726Sandreas.hansson@arm.comsystem.ruby.network.routers2.msg_count.Response_Data::4        72247                      
43710726Sandreas.hansson@arm.comsystem.ruby.network.routers2.msg_count.Writeback_Control::3        72243                      
43810726Sandreas.hansson@arm.comsystem.ruby.network.routers2.msg_bytes.Control::2       577976                      
43910726Sandreas.hansson@arm.comsystem.ruby.network.routers2.msg_bytes.Data::2      5201496                      
44011201Sandreas.hansson@arm.comsystem.ruby.network.routers2.msg_bytes.Response_Data::4      5201784                      
44111201Sandreas.hansson@arm.comsystem.ruby.network.routers2.msg_bytes.Writeback_Control::3       577944                      
44211201Sandreas.hansson@arm.comsystem.ruby.network.pwrStateResidencyTicks::UNDEFINED      4665394                       # Cumulative time (in ticks) in various power states
44311201Sandreas.hansson@arm.comsystem.ruby.network.msg_count.Control          216741                      
44411201Sandreas.hansson@arm.comsystem.ruby.network.msg_count.Data             216729                      
44511201Sandreas.hansson@arm.comsystem.ruby.network.msg_count.Response_Data       216741                      
44611201Sandreas.hansson@arm.comsystem.ruby.network.msg_count.Writeback_Control       216729                      
44711201Sandreas.hansson@arm.comsystem.ruby.network.msg_byte.Control          1733928                      
44811201Sandreas.hansson@arm.comsystem.ruby.network.msg_byte.Data            15604488                      
44911201Sandreas.hansson@arm.comsystem.ruby.network.msg_byte.Response_Data     15605352                      
45011201Sandreas.hansson@arm.comsystem.ruby.network.msg_byte.Writeback_Control      1733832                      
45111201Sandreas.hansson@arm.comsystem.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED      4665394                       # Cumulative time (in ticks) in various power states
45211138Sandreas.hansson@arm.comsystem.ruby.network.routers0.throttle0.link_utilization     7.742819                      
45311138Sandreas.hansson@arm.comsystem.ruby.network.routers0.throttle0.msg_count.Response_Data::4        72247                      
45411138Sandreas.hansson@arm.comsystem.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3        72243                      
45511138Sandreas.hansson@arm.comsystem.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4      5201784                      
45611138Sandreas.hansson@arm.comsystem.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3       577944                      
45711138Sandreas.hansson@arm.comsystem.ruby.network.routers0.throttle1.link_utilization     7.742476                      
45811530Sandreas.sandberg@arm.comsystem.ruby.network.routers0.throttle1.msg_count.Control::2        72247                      
4599729Sandreas.hansson@arm.comsystem.ruby.network.routers0.throttle1.msg_count.Data::2        72243                      
4609729Sandreas.hansson@arm.comsystem.ruby.network.routers0.throttle1.msg_bytes.Control::2       577976                      
4619729Sandreas.hansson@arm.comsystem.ruby.network.routers0.throttle1.msg_bytes.Data::2      5201496                      
46210892Sandreas.hansson@arm.comsystem.ruby.network.routers1.throttle0.link_utilization     7.742476                      
46310892Sandreas.hansson@arm.comsystem.ruby.network.routers1.throttle0.msg_count.Control::2        72247                      
4649838Sandreas.hansson@arm.comsystem.ruby.network.routers1.throttle0.msg_count.Data::2        72243                      
4659838Sandreas.hansson@arm.comsystem.ruby.network.routers1.throttle0.msg_bytes.Control::2       577976                      
4669838Sandreas.hansson@arm.comsystem.ruby.network.routers1.throttle0.msg_bytes.Data::2      5201496                      
46710409Sandreas.hansson@arm.comsystem.ruby.network.routers1.throttle1.link_utilization     7.742819                      
46810409Sandreas.hansson@arm.comsystem.ruby.network.routers1.throttle1.msg_count.Response_Data::4        72247                      
46910409Sandreas.hansson@arm.comsystem.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3        72243                      
47010409Sandreas.hansson@arm.comsystem.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4      5201784                      
47111570SCurtis.Dunham@arm.comsystem.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3       577944                      
47210409Sandreas.hansson@arm.comsystem.ruby.network.routers2.throttle0.link_utilization     7.742819                      
47311138Sandreas.hansson@arm.comsystem.ruby.network.routers2.throttle0.msg_count.Response_Data::4        72247                      
47411138Sandreas.hansson@arm.comsystem.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3        72243                      
47510409Sandreas.hansson@arm.comsystem.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4      5201784                      
47611138Sandreas.hansson@arm.comsystem.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3       577944                      
47711138Sandreas.hansson@arm.comsystem.ruby.network.routers2.throttle1.link_utilization     7.742476                      
47810409Sandreas.hansson@arm.comsystem.ruby.network.routers2.throttle1.msg_count.Control::2        72247                      
47910409Sandreas.hansson@arm.comsystem.ruby.network.routers2.throttle1.msg_count.Data::2        72243                      
48011138Sandreas.hansson@arm.comsystem.ruby.network.routers2.throttle1.msg_bytes.Control::2       577976                      
48110409Sandreas.hansson@arm.comsystem.ruby.network.routers2.throttle1.msg_bytes.Data::2      5201496                      
48210409Sandreas.hansson@arm.comsystem.ruby.delayVCHist.vnet_1::bucket_size            1                       # delay histogram for vnet_1
4839729Sandreas.hansson@arm.comsystem.ruby.delayVCHist.vnet_1::max_bucket            9                       # delay histogram for vnet_1
48411201Sandreas.hansson@arm.comsystem.ruby.delayVCHist.vnet_1::samples         72247                       # delay histogram for vnet_1
4859729Sandreas.hansson@arm.comsystem.ruby.delayVCHist.vnet_1           |       72247    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% # delay histogram for vnet_1
48611201Sandreas.hansson@arm.comsystem.ruby.delayVCHist.vnet_1::total           72247                       # delay histogram for vnet_1
4879729Sandreas.hansson@arm.comsystem.ruby.delayVCHist.vnet_2::bucket_size            1                       # delay histogram for vnet_2
48811201Sandreas.hansson@arm.comsystem.ruby.delayVCHist.vnet_2::max_bucket            9                       # delay histogram for vnet_2
48911530Sandreas.sandberg@arm.comsystem.ruby.delayVCHist.vnet_2::samples         72243                       # delay histogram for vnet_2
49010726Sandreas.hansson@arm.comsystem.ruby.delayVCHist.vnet_2           |       72243    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% # delay histogram for vnet_2
49110726Sandreas.hansson@arm.comsystem.ruby.delayVCHist.vnet_2::total           72243                       # delay histogram for vnet_2
49210726Sandreas.hansson@arm.comsystem.ruby.LD.latency_hist_seqr::bucket_size           64                      
49310892Sandreas.hansson@arm.comsystem.ruby.LD.latency_hist_seqr::max_bucket          639                      
49410726Sandreas.hansson@arm.comsystem.ruby.LD.latency_hist_seqr::samples        51711                      
49510726Sandreas.hansson@arm.comsystem.ruby.LD.latency_hist_seqr::mean      28.269208                      
49610726Sandreas.hansson@arm.comsystem.ruby.LD.latency_hist_seqr::gmean      7.619512                      
49710726Sandreas.hansson@arm.comsystem.ruby.LD.latency_hist_seqr::stdev     36.060908                      
49810726Sandreas.hansson@arm.comsystem.ruby.LD.latency_hist_seqr         |       41177     79.63%     79.63% |        9735     18.83%     98.45% |         541      1.05%     99.50% |          99      0.19%     99.69% |          79      0.15%     99.85% |          70      0.14%     99.98% |           7      0.01%     99.99% |           2      0.00%    100.00% |           0      0.00%    100.00% |           1      0.00%    100.00%
49911570SCurtis.Dunham@arm.comsystem.ruby.LD.latency_hist_seqr::total         51711                      
50010726Sandreas.hansson@arm.comsystem.ruby.LD.hit_latency_hist_seqr::bucket_size            1                      
50110726Sandreas.hansson@arm.comsystem.ruby.LD.hit_latency_hist_seqr::max_bucket            9                      
50210726Sandreas.hansson@arm.comsystem.ruby.LD.hit_latency_hist_seqr::samples        24257                      
50310726Sandreas.hansson@arm.comsystem.ruby.LD.hit_latency_hist_seqr::mean            1                      
50410726Sandreas.hansson@arm.comsystem.ruby.LD.hit_latency_hist_seqr::gmean            1                      
50510726Sandreas.hansson@arm.comsystem.ruby.LD.hit_latency_hist_seqr     |           0      0.00%      0.00% |       24257    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
50610726Sandreas.hansson@arm.comsystem.ruby.LD.hit_latency_hist_seqr::total        24257                      
50710726Sandreas.hansson@arm.comsystem.ruby.LD.miss_latency_hist_seqr::bucket_size           64                      
50810726Sandreas.hansson@arm.comsystem.ruby.LD.miss_latency_hist_seqr::max_bucket          639                      
50910726Sandreas.hansson@arm.comsystem.ruby.LD.miss_latency_hist_seqr::samples        27454                      
51010726Sandreas.hansson@arm.comsystem.ruby.LD.miss_latency_hist_seqr::mean    52.362934                      
51111201Sandreas.hansson@arm.comsystem.ruby.LD.miss_latency_hist_seqr::gmean    45.830488                      
51211201Sandreas.hansson@arm.comsystem.ruby.LD.miss_latency_hist_seqr::stdev    34.811219                      
51311390Ssteve.reinhardt@amd.comsystem.ruby.LD.miss_latency_hist_seqr    |       16920     61.63%     61.63% |        9735     35.46%     97.09% |         541      1.97%     99.06% |          99      0.36%     99.42% |          79      0.29%     99.71% |          70      0.25%     99.96% |           7      0.03%     99.99% |           2      0.01%    100.00% |           0      0.00%    100.00% |           1      0.00%    100.00%
5143048SN/Asystem.ruby.LD.miss_latency_hist_seqr::total        27454                      
5153048SN/Asystem.ruby.ST.latency_hist_seqr::bucket_size           64                      
516system.ruby.ST.latency_hist_seqr::max_bucket          639                      
517system.ruby.ST.latency_hist_seqr::samples        37229                      
518system.ruby.ST.latency_hist_seqr::mean      15.219587                      
519system.ruby.ST.latency_hist_seqr::gmean      3.175846                      
520system.ruby.ST.latency_hist_seqr::stdev     28.311515                      
521system.ruby.ST.latency_hist_seqr         |       33814     90.83%     90.83% |        3147      8.45%     99.28% |         181      0.49%     99.77% |          30      0.08%     99.85% |          22      0.06%     99.91% |          24      0.06%     99.97% |           1      0.00%     99.97% |           1      0.00%     99.98% |           0      0.00%     99.98% |           9      0.02%    100.00%
522system.ruby.ST.latency_hist_seqr::total         37229                      
523system.ruby.ST.hit_latency_hist_seqr::bucket_size            1                      
524system.ruby.ST.hit_latency_hist_seqr::max_bucket            9                      
525system.ruby.ST.hit_latency_hist_seqr::samples        25699                      
526system.ruby.ST.hit_latency_hist_seqr::mean            1                      
527system.ruby.ST.hit_latency_hist_seqr::gmean            1                      
528system.ruby.ST.hit_latency_hist_seqr     |           0      0.00%      0.00% |       25699    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
529system.ruby.ST.hit_latency_hist_seqr::total        25699                      
530system.ruby.ST.miss_latency_hist_seqr::bucket_size           64                      
531system.ruby.ST.miss_latency_hist_seqr::max_bucket          639                      
532system.ruby.ST.miss_latency_hist_seqr::samples        11530                      
533system.ruby.ST.miss_latency_hist_seqr::mean    46.913356                      
534system.ruby.ST.miss_latency_hist_seqr::gmean    41.729617                      
535system.ruby.ST.miss_latency_hist_seqr::stdev    33.659248                      
536system.ruby.ST.miss_latency_hist_seqr    |        8115     70.38%     70.38% |        3147     27.29%     97.68% |         181      1.57%     99.25% |          30      0.26%     99.51% |          22      0.19%     99.70% |          24      0.21%     99.90% |           1      0.01%     99.91% |           1      0.01%     99.92% |           0      0.00%     99.92% |           9      0.08%    100.00%
537system.ruby.ST.miss_latency_hist_seqr::total        11530                      
538system.ruby.IFETCH.latency_hist_seqr::bucket_size           64                      
539system.ruby.IFETCH.latency_hist_seqr::max_bucket          639                      
540system.ruby.IFETCH.latency_hist_seqr::samples       226275                      
541system.ruby.IFETCH.latency_hist_seqr::mean    10.260700                      
542system.ruby.IFETCH.latency_hist_seqr::gmean     1.811203                      
543system.ruby.IFETCH.latency_hist_seqr::stdev    26.801914                      
544system.ruby.IFETCH.latency_hist_seqr     |      204394     90.33%     90.33% |       20370      9.00%     99.33% |         994      0.44%     99.77% |         178      0.08%     99.85% |         177      0.08%     99.93% |         142      0.06%     99.99% |          12      0.01%    100.00% |           5      0.00%    100.00% |           0      0.00%    100.00% |           3      0.00%    100.00%
545system.ruby.IFETCH.latency_hist_seqr::total       226275                      
546system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size            1                      
547system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket            9                      
548system.ruby.IFETCH.hit_latency_hist_seqr::samples       193012                      
549system.ruby.IFETCH.hit_latency_hist_seqr::mean            1                      
550system.ruby.IFETCH.hit_latency_hist_seqr::gmean            1                      
551system.ruby.IFETCH.hit_latency_hist_seqr |           0      0.00%      0.00% |      193012    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
552system.ruby.IFETCH.hit_latency_hist_seqr::total       193012                      
553system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size           64                      
554system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket          639                      
555system.ruby.IFETCH.miss_latency_hist_seqr::samples        33263                      
556system.ruby.IFETCH.miss_latency_hist_seqr::mean    63.996873                      
557system.ruby.IFETCH.miss_latency_hist_seqr::gmean    56.865504                      
558system.ruby.IFETCH.miss_latency_hist_seqr::stdev    38.748066                      
559system.ruby.IFETCH.miss_latency_hist_seqr |       11382     34.22%     34.22% |       20370     61.24%     95.46% |         994      2.99%     98.45% |         178      0.54%     98.98% |         177      0.53%     99.51% |         142      0.43%     99.94% |          12      0.04%     99.98% |           5      0.02%     99.99% |           0      0.00%     99.99% |           3      0.01%    100.00%
560system.ruby.IFETCH.miss_latency_hist_seqr::total        33263                      
561system.ruby.Directory.miss_mach_latency_hist_seqr::bucket_size           64                      
562system.ruby.Directory.miss_mach_latency_hist_seqr::max_bucket          639                      
563system.ruby.Directory.miss_mach_latency_hist_seqr::samples        72247                      
564system.ruby.Directory.miss_mach_latency_hist_seqr::mean    56.849572                      
565system.ruby.Directory.miss_mach_latency_hist_seqr::gmean    49.864909                      
566system.ruby.Directory.miss_mach_latency_hist_seqr::stdev    37.140999                      
567system.ruby.Directory.miss_mach_latency_hist_seqr |       36417     50.41%     50.41% |       33252     46.03%     96.43% |        1716      2.38%     98.81% |         307      0.42%     99.23% |         278      0.38%     99.62% |         236      0.33%     99.94% |          20      0.03%     99.97% |           8      0.01%     99.98% |           0      0.00%     99.98% |          13      0.02%    100.00%
568system.ruby.Directory.miss_mach_latency_hist_seqr::total        72247                      
569system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::bucket_size            1                      
570system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::max_bucket            9                      
571system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::samples            1                      
572system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::stdev          nan                      
573system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request |           1    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
574system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::total            1                      
575system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::bucket_size            1                      
576system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::max_bucket            9                      
577system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::samples            1                      
578system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::stdev          nan                      
579system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward |           1    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
580system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::total            1                      
581system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::bucket_size            1                      
582system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::max_bucket            9                      
583system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::samples            1                      
584system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::stdev          nan                      
585system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response |           1    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
586system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::total            1                      
587system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::bucket_size            8                      
588system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::max_bucket           79                      
589system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::samples            1                      
590system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::mean           75                      
591system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::gmean    75.000000                      
592system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::stdev          nan                      
593system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           1    100.00%    100.00%
594system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::total            1                      
595system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size           64                      
596system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket          639                      
597system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples        27454                      
598system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean    52.362934                      
599system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean    45.830488                      
600system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev    34.811219                      
601system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr |       16920     61.63%     61.63% |        9735     35.46%     97.09% |         541      1.97%     99.06% |          99      0.36%     99.42% |          79      0.29%     99.71% |          70      0.25%     99.96% |           7      0.03%     99.99% |           2      0.01%    100.00% |           0      0.00%    100.00% |           1      0.00%    100.00%
602system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total        27454                      
603system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size           64                      
604system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket          639                      
605system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::samples        11530                      
606system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean    46.913356                      
607system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean    41.729617                      
608system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev    33.659248                      
609system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr |        8115     70.38%     70.38% |        3147     27.29%     97.68% |         181      1.57%     99.25% |          30      0.26%     99.51% |          22      0.19%     99.70% |          24      0.21%     99.90% |           1      0.01%     99.91% |           1      0.01%     99.92% |           0      0.00%     99.92% |           9      0.08%    100.00%
610system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total        11530                      
611system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::bucket_size           64                      
612system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::max_bucket          639                      
613system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::samples        33263                      
614system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean    63.996873                      
615system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean    56.865504                      
616system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev    38.748066                      
617system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr |       11382     34.22%     34.22% |       20370     61.24%     95.46% |         994      2.99%     98.45% |         178      0.54%     98.98% |         177      0.53%     99.51% |         142      0.43%     99.94% |          12      0.04%     99.98% |           5      0.02%     99.99% |           0      0.00%     99.99% |           3      0.01%    100.00%
618system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::total        33263                      
619system.ruby.Directory_Controller.GETX           72247      0.00%      0.00%
620system.ruby.Directory_Controller.PUTX           72243      0.00%      0.00%
621system.ruby.Directory_Controller.Memory_Data        72247      0.00%      0.00%
622system.ruby.Directory_Controller.Memory_Ack        72243      0.00%      0.00%
623system.ruby.Directory_Controller.I.GETX         72247      0.00%      0.00%
624system.ruby.Directory_Controller.M.PUTX         72243      0.00%      0.00%
625system.ruby.Directory_Controller.IM.Memory_Data        72247      0.00%      0.00%
626system.ruby.Directory_Controller.MI.Memory_Ack        72243      0.00%      0.00%
627system.ruby.L1Cache_Controller.Load             51711      0.00%      0.00%
628system.ruby.L1Cache_Controller.Ifetch          226275      0.00%      0.00%
629system.ruby.L1Cache_Controller.Store            37229      0.00%      0.00%
630system.ruby.L1Cache_Controller.Data             72247      0.00%      0.00%
631system.ruby.L1Cache_Controller.Replacement        72243      0.00%      0.00%
632system.ruby.L1Cache_Controller.Writeback_Ack        72243      0.00%      0.00%
633system.ruby.L1Cache_Controller.I.Load           27454      0.00%      0.00%
634system.ruby.L1Cache_Controller.I.Ifetch         33263      0.00%      0.00%
635system.ruby.L1Cache_Controller.I.Store          11530      0.00%      0.00%
636system.ruby.L1Cache_Controller.M.Load           24257      0.00%      0.00%
637system.ruby.L1Cache_Controller.M.Ifetch        193012      0.00%      0.00%
638system.ruby.L1Cache_Controller.M.Store          25699      0.00%      0.00%
639system.ruby.L1Cache_Controller.M.Replacement        72243      0.00%      0.00%
640system.ruby.L1Cache_Controller.MI.Writeback_Ack        72243      0.00%      0.00%
641system.ruby.L1Cache_Controller.IS.Data          60717      0.00%      0.00%
642system.ruby.L1Cache_Controller.IM.Data          11530      0.00%      0.00%
643
644---------- End Simulation Statistics   ----------
645