config.json revision 12137:d877205ec1bc
14038Sbinkertn@umich.edu{
24038Sbinkertn@umich.edu    "name": null, 
34038Sbinkertn@umich.edu    "sim_quantum": 0, 
44038Sbinkertn@umich.edu    "system": {
54038Sbinkertn@umich.edu        "kernel": "", 
64038Sbinkertn@umich.edu        "mmap_using_noreserve": false, 
74038Sbinkertn@umich.edu        "kernel_addr_check": true, 
84038Sbinkertn@umich.edu        "membus": {
94038Sbinkertn@umich.edu            "point_of_coherency": true, 
104038Sbinkertn@umich.edu            "system": "system", 
114038Sbinkertn@umich.edu            "response_latency": 2, 
124038Sbinkertn@umich.edu            "cxx_class": "CoherentXBar", 
134038Sbinkertn@umich.edu            "forward_latency": 4, 
144038Sbinkertn@umich.edu            "clk_domain": "system.clk_domain", 
154038Sbinkertn@umich.edu            "width": 16, 
164038Sbinkertn@umich.edu            "eventq_index": 0, 
174038Sbinkertn@umich.edu            "default_p_state": "UNDEFINED", 
184038Sbinkertn@umich.edu            "p_state_clk_gate_max": 1000000000000, 
194038Sbinkertn@umich.edu            "master": {
204038Sbinkertn@umich.edu                "peer": [
214038Sbinkertn@umich.edu                    "system.physmem.port"
224038Sbinkertn@umich.edu                ], 
234038Sbinkertn@umich.edu                "role": "MASTER"
244038Sbinkertn@umich.edu            }, 
254038Sbinkertn@umich.edu            "type": "CoherentXBar", 
264038Sbinkertn@umich.edu            "frontend_latency": 3, 
274038Sbinkertn@umich.edu            "slave": {
284038Sbinkertn@umich.edu                "peer": [
294038Sbinkertn@umich.edu                    "system.system_port", 
304038Sbinkertn@umich.edu                    "system.cpu.l2cache.mem_side"
314038Sbinkertn@umich.edu                ], 
324038Sbinkertn@umich.edu                "role": "SLAVE"
338229Snate@binkert.org            }, 
344038Sbinkertn@umich.edu            "p_state_clk_gate_min": 1000, 
354038Sbinkertn@umich.edu            "snoop_filter": {
364038Sbinkertn@umich.edu                "name": "snoop_filter", 
374038Sbinkertn@umich.edu                "system": "system", 
384038Sbinkertn@umich.edu                "max_capacity": 8388608, 
394038Sbinkertn@umich.edu                "eventq_index": 0, 
404038Sbinkertn@umich.edu                "cxx_class": "SnoopFilter", 
414038Sbinkertn@umich.edu                "path": "system.membus.snoop_filter", 
424038Sbinkertn@umich.edu                "type": "SnoopFilter", 
434038Sbinkertn@umich.edu                "lookup_latency": 1
444038Sbinkertn@umich.edu            }, 
454038Sbinkertn@umich.edu            "power_model": null, 
464038Sbinkertn@umich.edu            "path": "system.membus", 
474038Sbinkertn@umich.edu            "snoop_response_latency": 4, 
484038Sbinkertn@umich.edu            "name": "membus", 
494038Sbinkertn@umich.edu            "p_state_clk_gate_bins": 20, 
504038Sbinkertn@umich.edu            "use_default_range": false
514038Sbinkertn@umich.edu        }, 
524038Sbinkertn@umich.edu        "symbolfile": "", 
534038Sbinkertn@umich.edu        "readfile": "", 
544038Sbinkertn@umich.edu        "thermal_model": null, 
554038Sbinkertn@umich.edu        "cxx_class": "System", 
564038Sbinkertn@umich.edu        "work_begin_cpu_id_exit": -1, 
574038Sbinkertn@umich.edu        "load_offset": 0, 
584038Sbinkertn@umich.edu        "work_begin_exit_count": 0, 
594038Sbinkertn@umich.edu        "p_state_clk_gate_min": 1000, 
604038Sbinkertn@umich.edu        "memories": [
614038Sbinkertn@umich.edu            "system.physmem"
624038Sbinkertn@umich.edu        ], 
634038Sbinkertn@umich.edu        "work_begin_ckpt_count": 0, 
644038Sbinkertn@umich.edu        "clk_domain": {
654038Sbinkertn@umich.edu            "name": "clk_domain", 
664038Sbinkertn@umich.edu            "clock": [
674038Sbinkertn@umich.edu                1000
684038Sbinkertn@umich.edu            ], 
694038Sbinkertn@umich.edu            "init_perf_level": 0, 
704038Sbinkertn@umich.edu            "voltage_domain": "system.voltage_domain", 
714038Sbinkertn@umich.edu            "eventq_index": 0, 
724038Sbinkertn@umich.edu            "cxx_class": "SrcClockDomain", 
734038Sbinkertn@umich.edu            "path": "system.clk_domain", 
744038Sbinkertn@umich.edu            "type": "SrcClockDomain", 
754038Sbinkertn@umich.edu            "domain_id": -1
764038Sbinkertn@umich.edu        }, 
774038Sbinkertn@umich.edu        "mem_ranges": [], 
784038Sbinkertn@umich.edu        "eventq_index": 0, 
794038Sbinkertn@umich.edu        "default_p_state": "UNDEFINED", 
804038Sbinkertn@umich.edu        "p_state_clk_gate_max": 1000000000000, 
814038Sbinkertn@umich.edu        "dvfs_handler": {
824038Sbinkertn@umich.edu            "enable": false, 
834038Sbinkertn@umich.edu            "name": "dvfs_handler", 
844038Sbinkertn@umich.edu            "sys_clk_domain": "system.clk_domain", 
854038Sbinkertn@umich.edu            "transition_latency": 100000000, 
864038Sbinkertn@umich.edu            "eventq_index": 0, 
874038Sbinkertn@umich.edu            "cxx_class": "DVFSHandler", 
884038Sbinkertn@umich.edu            "domains": [], 
894038Sbinkertn@umich.edu            "path": "system.dvfs_handler", 
904038Sbinkertn@umich.edu            "type": "DVFSHandler"
91        }, 
92        "work_end_exit_count": 0, 
93        "type": "System", 
94        "voltage_domain": {
95            "name": "voltage_domain", 
96            "eventq_index": 0, 
97            "voltage": [
98                "1.0"
99            ], 
100            "cxx_class": "VoltageDomain", 
101            "path": "system.voltage_domain", 
102            "type": "VoltageDomain"
103        }, 
104        "cache_line_size": 64, 
105        "boot_osflags": "a", 
106        "system_port": {
107            "peer": "system.membus.slave[0]", 
108            "role": "MASTER"
109        }, 
110        "physmem": {
111            "static_frontend_latency": 10000, 
112            "tRFC": 260000, 
113            "activation_limit": 4, 
114            "in_addr_map": true, 
115            "IDD3N2": "0.0", 
116            "tWTR": 7500, 
117            "IDD52": "0.0", 
118            "clk_domain": "system.clk_domain", 
119            "channels": 1, 
120            "write_buffer_size": 64, 
121            "device_bus_width": 8, 
122            "VDD": "1.5", 
123            "write_high_thresh_perc": 85, 
124            "cxx_class": "DRAMCtrl", 
125            "bank_groups_per_rank": 0, 
126            "IDD2N2": "0.0", 
127            "port": {
128                "peer": "system.membus.master[0]", 
129                "role": "SLAVE"
130            }, 
131            "tCCD_L": 0, 
132            "IDD2N": "0.032", 
133            "p_state_clk_gate_min": 1000, 
134            "null": false, 
135            "IDD2P1": "0.032", 
136            "eventq_index": 0, 
137            "tRRD": 6000, 
138            "tRTW": 2500, 
139            "IDD4R": "0.157", 
140            "burst_length": 8, 
141            "tRTP": 7500, 
142            "IDD4W": "0.125", 
143            "tWR": 15000, 
144            "banks_per_rank": 8, 
145            "devices_per_rank": 8, 
146            "IDD2P02": "0.0", 
147            "default_p_state": "UNDEFINED", 
148            "p_state_clk_gate_max": 1000000000000, 
149            "IDD6": "0.02", 
150            "IDD5": "0.235", 
151            "tRCD": 13750, 
152            "type": "DRAMCtrl", 
153            "IDD3P02": "0.0", 
154            "tRRD_L": 0, 
155            "IDD0": "0.055", 
156            "IDD62": "0.0", 
157            "min_writes_per_switch": 16, 
158            "mem_sched_policy": "frfcfs", 
159            "IDD02": "0.0", 
160            "IDD2P0": "0.0", 
161            "ranks_per_channel": 2, 
162            "page_policy": "open_adaptive", 
163            "IDD4W2": "0.0", 
164            "tCS": 2500, 
165            "power_model": null, 
166            "tCL": 13750, 
167            "read_buffer_size": 32, 
168            "conf_table_reported": true, 
169            "tCK": 1250, 
170            "tRAS": 35000, 
171            "tRP": 13750, 
172            "tBURST": 5000, 
173            "path": "system.physmem", 
174            "tXP": 6000, 
175            "tXS": 270000, 
176            "addr_mapping": "RoRaBaCoCh", 
177            "IDD3P0": "0.0", 
178            "IDD3P1": "0.038", 
179            "IDD3N": "0.038", 
180            "name": "physmem", 
181            "tXSDLL": 0, 
182            "device_size": 536870912, 
183            "kvm_map": true, 
184            "dll": true, 
185            "tXAW": 30000, 
186            "write_low_thresh_perc": 50, 
187            "range": "0:134217727:0:0:0:0", 
188            "VDD2": "0.0", 
189            "IDD2P12": "0.0", 
190            "p_state_clk_gate_bins": 20, 
191            "tXPDLL": 0, 
192            "IDD4R2": "0.0", 
193            "device_rowbuffer_size": 1024, 
194            "static_backend_latency": 10000, 
195            "max_accesses_per_row": 16, 
196            "IDD3P12": "0.0", 
197            "tREFI": 7800000
198        }, 
199        "power_model": null, 
200        "work_cpus_ckpt_count": 0, 
201        "thermal_components": [], 
202        "path": "system", 
203        "cpu_clk_domain": {
204            "name": "cpu_clk_domain", 
205            "clock": [
206                500
207            ], 
208            "init_perf_level": 0, 
209            "voltage_domain": "system.voltage_domain", 
210            "eventq_index": 0, 
211            "cxx_class": "SrcClockDomain", 
212            "path": "system.cpu_clk_domain", 
213            "type": "SrcClockDomain", 
214            "domain_id": -1
215        }, 
216        "work_end_ckpt_count": 0, 
217        "mem_mode": "timing", 
218        "name": "system", 
219        "init_param": 0, 
220        "p_state_clk_gate_bins": 20, 
221        "load_addr_mask": 1099511627775, 
222        "cpu": [
223            {
224                "SQEntries": 32, 
225                "smtLSQThreshold": 100, 
226                "fetchTrapLatency": 1, 
227                "iewToRenameDelay": 1, 
228                "l2cache": {
229                    "cpu_side": {
230                        "peer": "system.cpu.toL2Bus.master[0]", 
231                        "role": "SLAVE"
232                    }, 
233                    "clusivity": "mostly_incl", 
234                    "prefetcher": null, 
235                    "system": "system", 
236                    "write_buffers": 8, 
237                    "response_latency": 20, 
238                    "cxx_class": "Cache", 
239                    "size": 2097152, 
240                    "type": "Cache", 
241                    "clk_domain": "system.cpu_clk_domain", 
242                    "max_miss_count": 0, 
243                    "eventq_index": 0, 
244                    "default_p_state": "UNDEFINED", 
245                    "p_state_clk_gate_max": 1000000000000, 
246                    "mem_side": {
247                        "peer": "system.membus.slave[1]", 
248                        "role": "MASTER"
249                    }, 
250                    "mshrs": 20, 
251                    "writeback_clean": false, 
252                    "p_state_clk_gate_min": 1000, 
253                    "tags": {
254                        "size": 2097152, 
255                        "tag_latency": 20, 
256                        "name": "tags", 
257                        "p_state_clk_gate_min": 1000, 
258                        "eventq_index": 0, 
259                        "p_state_clk_gate_bins": 20, 
260                        "default_p_state": "UNDEFINED", 
261                        "clk_domain": "system.cpu_clk_domain", 
262                        "power_model": null, 
263                        "sequential_access": false, 
264                        "assoc": 8, 
265                        "cxx_class": "LRU", 
266                        "p_state_clk_gate_max": 1000000000000, 
267                        "path": "system.cpu.l2cache.tags", 
268                        "block_size": 64, 
269                        "type": "LRU", 
270                        "data_latency": 20
271                    }, 
272                    "tgts_per_mshr": 12, 
273                    "demand_mshr_reserve": 1, 
274                    "power_model": null, 
275                    "addr_ranges": [
276                        "0:18446744073709551615:0:0:0:0"
277                    ], 
278                    "is_read_only": false, 
279                    "prefetch_on_access": false, 
280                    "path": "system.cpu.l2cache", 
281                    "data_latency": 20, 
282                    "tag_latency": 20, 
283                    "name": "l2cache", 
284                    "p_state_clk_gate_bins": 20, 
285                    "sequential_access": false, 
286                    "assoc": 8
287                }, 
288                "itb": {
289                    "name": "itb", 
290                    "eventq_index": 0, 
291                    "cxx_class": "RiscvISA::TLB", 
292                    "path": "system.cpu.itb", 
293                    "type": "RiscvTLB", 
294                    "size": 64
295                }, 
296                "fetchWidth": 8, 
297                "max_loads_all_threads": 0, 
298                "cpu_id": 0, 
299                "fetchToDecodeDelay": 1, 
300                "renameToDecodeDelay": 1, 
301                "do_quiesce": true, 
302                "renameToROBDelay": 1, 
303                "power_model": null, 
304                "max_insts_all_threads": 0, 
305                "decodeWidth": 8, 
306                "commitToFetchDelay": 1, 
307                "needsTSO": false, 
308                "smtIQThreshold": 100, 
309                "workload": [
310                    {
311                        "uid": 100, 
312                        "pid": 100, 
313                        "kvmInSE": false, 
314                        "cxx_class": "Process", 
315                        "executable": "/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64f/insttest", 
316                        "drivers": [], 
317                        "system": "system", 
318                        "gid": 100, 
319                        "eventq_index": 0, 
320                        "env": [], 
321                        "maxStackSize": 67108864, 
322                        "ppid": 0, 
323                        "type": "Process", 
324                        "cwd": "", 
325                        "pgid": 100, 
326                        "simpoint": 0, 
327                        "euid": 100, 
328                        "input": "cin", 
329                        "path": "system.cpu.workload", 
330                        "name": "workload", 
331                        "cmd": [
332                            "insttest"
333                        ], 
334                        "errout": "cerr", 
335                        "useArchPT": false, 
336                        "egid": 100, 
337                        "output": "cout"
338                    }
339                ], 
340                "name": "cpu", 
341                "SSITSize": 1024, 
342                "activity": 0, 
343                "max_loads_any_thread": 0, 
344                "tracer": {
345                    "eventq_index": 0, 
346                    "path": "system.cpu.tracer", 
347                    "type": "ExeTracer", 
348                    "name": "tracer", 
349                    "cxx_class": "Trace::ExeTracer"
350                }, 
351                "decodeToFetchDelay": 1, 
352                "renameWidth": 8, 
353                "numThreads": 1, 
354                "syscallRetryLatency": 10000, 
355                "squashWidth": 8, 
356                "function_trace": false, 
357                "backComSize": 5, 
358                "decodeToRenameDelay": 1, 
359                "store_set_clear_period": 250000, 
360                "numPhysIntRegs": 256, 
361                "p_state_clk_gate_max": 1000000000000, 
362                "toL2Bus": {
363                    "point_of_coherency": false, 
364                    "system": "system", 
365                    "response_latency": 1, 
366                    "cxx_class": "CoherentXBar", 
367                    "forward_latency": 0, 
368                    "clk_domain": "system.cpu_clk_domain", 
369                    "width": 32, 
370                    "eventq_index": 0, 
371                    "default_p_state": "UNDEFINED", 
372                    "p_state_clk_gate_max": 1000000000000, 
373                    "master": {
374                        "peer": [
375                            "system.cpu.l2cache.cpu_side"
376                        ], 
377                        "role": "MASTER"
378                    }, 
379                    "type": "CoherentXBar", 
380                    "frontend_latency": 1, 
381                    "slave": {
382                        "peer": [
383                            "system.cpu.icache.mem_side", 
384                            "system.cpu.dcache.mem_side"
385                        ], 
386                        "role": "SLAVE"
387                    }, 
388                    "p_state_clk_gate_min": 1000, 
389                    "snoop_filter": {
390                        "name": "snoop_filter", 
391                        "system": "system", 
392                        "max_capacity": 8388608, 
393                        "eventq_index": 0, 
394                        "cxx_class": "SnoopFilter", 
395                        "path": "system.cpu.toL2Bus.snoop_filter", 
396                        "type": "SnoopFilter", 
397                        "lookup_latency": 0
398                    }, 
399                    "power_model": null, 
400                    "path": "system.cpu.toL2Bus", 
401                    "snoop_response_latency": 1, 
402                    "name": "toL2Bus", 
403                    "p_state_clk_gate_bins": 20, 
404                    "use_default_range": false
405                }, 
406                "p_state_clk_gate_min": 1000, 
407                "fuPool": {
408                    "name": "fuPool", 
409                    "FUList": [
410                        {
411                            "count": 6, 
412                            "opList": [
413                                {
414                                    "opClass": "IntAlu", 
415                                    "opLat": 1, 
416                                    "name": "opList", 
417                                    "pipelined": true, 
418                                    "eventq_index": 0, 
419                                    "cxx_class": "OpDesc", 
420                                    "path": "system.cpu.fuPool.FUList0.opList", 
421                                    "type": "OpDesc"
422                                }
423                            ], 
424                            "name": "FUList0", 
425                            "eventq_index": 0, 
426                            "cxx_class": "FUDesc", 
427                            "path": "system.cpu.fuPool.FUList0", 
428                            "type": "FUDesc"
429                        }, 
430                        {
431                            "count": 2, 
432                            "opList": [
433                                {
434                                    "opClass": "IntMult", 
435                                    "opLat": 3, 
436                                    "name": "opList0", 
437                                    "pipelined": true, 
438                                    "eventq_index": 0, 
439                                    "cxx_class": "OpDesc", 
440                                    "path": "system.cpu.fuPool.FUList1.opList0", 
441                                    "type": "OpDesc"
442                                }, 
443                                {
444                                    "opClass": "IntDiv", 
445                                    "opLat": 20, 
446                                    "name": "opList1", 
447                                    "pipelined": false, 
448                                    "eventq_index": 0, 
449                                    "cxx_class": "OpDesc", 
450                                    "path": "system.cpu.fuPool.FUList1.opList1", 
451                                    "type": "OpDesc"
452                                }
453                            ], 
454                            "name": "FUList1", 
455                            "eventq_index": 0, 
456                            "cxx_class": "FUDesc", 
457                            "path": "system.cpu.fuPool.FUList1", 
458                            "type": "FUDesc"
459                        }, 
460                        {
461                            "count": 4, 
462                            "opList": [
463                                {
464                                    "opClass": "FloatAdd", 
465                                    "opLat": 2, 
466                                    "name": "opList0", 
467                                    "pipelined": true, 
468                                    "eventq_index": 0, 
469                                    "cxx_class": "OpDesc", 
470                                    "path": "system.cpu.fuPool.FUList2.opList0", 
471                                    "type": "OpDesc"
472                                }, 
473                                {
474                                    "opClass": "FloatCmp", 
475                                    "opLat": 2, 
476                                    "name": "opList1", 
477                                    "pipelined": true, 
478                                    "eventq_index": 0, 
479                                    "cxx_class": "OpDesc", 
480                                    "path": "system.cpu.fuPool.FUList2.opList1", 
481                                    "type": "OpDesc"
482                                }, 
483                                {
484                                    "opClass": "FloatCvt", 
485                                    "opLat": 2, 
486                                    "name": "opList2", 
487                                    "pipelined": true, 
488                                    "eventq_index": 0, 
489                                    "cxx_class": "OpDesc", 
490                                    "path": "system.cpu.fuPool.FUList2.opList2", 
491                                    "type": "OpDesc"
492                                }
493                            ], 
494                            "name": "FUList2", 
495                            "eventq_index": 0, 
496                            "cxx_class": "FUDesc", 
497                            "path": "system.cpu.fuPool.FUList2", 
498                            "type": "FUDesc"
499                        }, 
500                        {
501                            "count": 2, 
502                            "opList": [
503                                {
504                                    "opClass": "FloatMult", 
505                                    "opLat": 4, 
506                                    "name": "opList0", 
507                                    "pipelined": true, 
508                                    "eventq_index": 0, 
509                                    "cxx_class": "OpDesc", 
510                                    "path": "system.cpu.fuPool.FUList3.opList0", 
511                                    "type": "OpDesc"
512                                }, 
513                                {
514                                    "opClass": "FloatMultAcc", 
515                                    "opLat": 5, 
516                                    "name": "opList1", 
517                                    "pipelined": true, 
518                                    "eventq_index": 0, 
519                                    "cxx_class": "OpDesc", 
520                                    "path": "system.cpu.fuPool.FUList3.opList1", 
521                                    "type": "OpDesc"
522                                }, 
523                                {
524                                    "opClass": "FloatMisc", 
525                                    "opLat": 3, 
526                                    "name": "opList2", 
527                                    "pipelined": true, 
528                                    "eventq_index": 0, 
529                                    "cxx_class": "OpDesc", 
530                                    "path": "system.cpu.fuPool.FUList3.opList2", 
531                                    "type": "OpDesc"
532                                }, 
533                                {
534                                    "opClass": "FloatDiv", 
535                                    "opLat": 12, 
536                                    "name": "opList3", 
537                                    "pipelined": false, 
538                                    "eventq_index": 0, 
539                                    "cxx_class": "OpDesc", 
540                                    "path": "system.cpu.fuPool.FUList3.opList3", 
541                                    "type": "OpDesc"
542                                }, 
543                                {
544                                    "opClass": "FloatSqrt", 
545                                    "opLat": 24, 
546                                    "name": "opList4", 
547                                    "pipelined": false, 
548                                    "eventq_index": 0, 
549                                    "cxx_class": "OpDesc", 
550                                    "path": "system.cpu.fuPool.FUList3.opList4", 
551                                    "type": "OpDesc"
552                                }
553                            ], 
554                            "name": "FUList3", 
555                            "eventq_index": 0, 
556                            "cxx_class": "FUDesc", 
557                            "path": "system.cpu.fuPool.FUList3", 
558                            "type": "FUDesc"
559                        }, 
560                        {
561                            "count": 0, 
562                            "opList": [
563                                {
564                                    "opClass": "MemRead", 
565                                    "opLat": 1, 
566                                    "name": "opList0", 
567                                    "pipelined": true, 
568                                    "eventq_index": 0, 
569                                    "cxx_class": "OpDesc", 
570                                    "path": "system.cpu.fuPool.FUList4.opList0", 
571                                    "type": "OpDesc"
572                                }, 
573                                {
574                                    "opClass": "FloatMemRead", 
575                                    "opLat": 1, 
576                                    "name": "opList1", 
577                                    "pipelined": true, 
578                                    "eventq_index": 0, 
579                                    "cxx_class": "OpDesc", 
580                                    "path": "system.cpu.fuPool.FUList4.opList1", 
581                                    "type": "OpDesc"
582                                }
583                            ], 
584                            "name": "FUList4", 
585                            "eventq_index": 0, 
586                            "cxx_class": "FUDesc", 
587                            "path": "system.cpu.fuPool.FUList4", 
588                            "type": "FUDesc"
589                        }, 
590                        {
591                            "count": 4, 
592                            "opList": [
593                                {
594                                    "opClass": "SimdAdd", 
595                                    "opLat": 1, 
596                                    "name": "opList00", 
597                                    "pipelined": true, 
598                                    "eventq_index": 0, 
599                                    "cxx_class": "OpDesc", 
600                                    "path": "system.cpu.fuPool.FUList5.opList00", 
601                                    "type": "OpDesc"
602                                }, 
603                                {
604                                    "opClass": "SimdAddAcc", 
605                                    "opLat": 1, 
606                                    "name": "opList01", 
607                                    "pipelined": true, 
608                                    "eventq_index": 0, 
609                                    "cxx_class": "OpDesc", 
610                                    "path": "system.cpu.fuPool.FUList5.opList01", 
611                                    "type": "OpDesc"
612                                }, 
613                                {
614                                    "opClass": "SimdAlu", 
615                                    "opLat": 1, 
616                                    "name": "opList02", 
617                                    "pipelined": true, 
618                                    "eventq_index": 0, 
619                                    "cxx_class": "OpDesc", 
620                                    "path": "system.cpu.fuPool.FUList5.opList02", 
621                                    "type": "OpDesc"
622                                }, 
623                                {
624                                    "opClass": "SimdCmp", 
625                                    "opLat": 1, 
626                                    "name": "opList03", 
627                                    "pipelined": true, 
628                                    "eventq_index": 0, 
629                                    "cxx_class": "OpDesc", 
630                                    "path": "system.cpu.fuPool.FUList5.opList03", 
631                                    "type": "OpDesc"
632                                }, 
633                                {
634                                    "opClass": "SimdCvt", 
635                                    "opLat": 1, 
636                                    "name": "opList04", 
637                                    "pipelined": true, 
638                                    "eventq_index": 0, 
639                                    "cxx_class": "OpDesc", 
640                                    "path": "system.cpu.fuPool.FUList5.opList04", 
641                                    "type": "OpDesc"
642                                }, 
643                                {
644                                    "opClass": "SimdMisc", 
645                                    "opLat": 1, 
646                                    "name": "opList05", 
647                                    "pipelined": true, 
648                                    "eventq_index": 0, 
649                                    "cxx_class": "OpDesc", 
650                                    "path": "system.cpu.fuPool.FUList5.opList05", 
651                                    "type": "OpDesc"
652                                }, 
653                                {
654                                    "opClass": "SimdMult", 
655                                    "opLat": 1, 
656                                    "name": "opList06", 
657                                    "pipelined": true, 
658                                    "eventq_index": 0, 
659                                    "cxx_class": "OpDesc", 
660                                    "path": "system.cpu.fuPool.FUList5.opList06", 
661                                    "type": "OpDesc"
662                                }, 
663                                {
664                                    "opClass": "SimdMultAcc", 
665                                    "opLat": 1, 
666                                    "name": "opList07", 
667                                    "pipelined": true, 
668                                    "eventq_index": 0, 
669                                    "cxx_class": "OpDesc", 
670                                    "path": "system.cpu.fuPool.FUList5.opList07", 
671                                    "type": "OpDesc"
672                                }, 
673                                {
674                                    "opClass": "SimdShift", 
675                                    "opLat": 1, 
676                                    "name": "opList08", 
677                                    "pipelined": true, 
678                                    "eventq_index": 0, 
679                                    "cxx_class": "OpDesc", 
680                                    "path": "system.cpu.fuPool.FUList5.opList08", 
681                                    "type": "OpDesc"
682                                }, 
683                                {
684                                    "opClass": "SimdShiftAcc", 
685                                    "opLat": 1, 
686                                    "name": "opList09", 
687                                    "pipelined": true, 
688                                    "eventq_index": 0, 
689                                    "cxx_class": "OpDesc", 
690                                    "path": "system.cpu.fuPool.FUList5.opList09", 
691                                    "type": "OpDesc"
692                                }, 
693                                {
694                                    "opClass": "SimdSqrt", 
695                                    "opLat": 1, 
696                                    "name": "opList10", 
697                                    "pipelined": true, 
698                                    "eventq_index": 0, 
699                                    "cxx_class": "OpDesc", 
700                                    "path": "system.cpu.fuPool.FUList5.opList10", 
701                                    "type": "OpDesc"
702                                }, 
703                                {
704                                    "opClass": "SimdFloatAdd", 
705                                    "opLat": 1, 
706                                    "name": "opList11", 
707                                    "pipelined": true, 
708                                    "eventq_index": 0, 
709                                    "cxx_class": "OpDesc", 
710                                    "path": "system.cpu.fuPool.FUList5.opList11", 
711                                    "type": "OpDesc"
712                                }, 
713                                {
714                                    "opClass": "SimdFloatAlu", 
715                                    "opLat": 1, 
716                                    "name": "opList12", 
717                                    "pipelined": true, 
718                                    "eventq_index": 0, 
719                                    "cxx_class": "OpDesc", 
720                                    "path": "system.cpu.fuPool.FUList5.opList12", 
721                                    "type": "OpDesc"
722                                }, 
723                                {
724                                    "opClass": "SimdFloatCmp", 
725                                    "opLat": 1, 
726                                    "name": "opList13", 
727                                    "pipelined": true, 
728                                    "eventq_index": 0, 
729                                    "cxx_class": "OpDesc", 
730                                    "path": "system.cpu.fuPool.FUList5.opList13", 
731                                    "type": "OpDesc"
732                                }, 
733                                {
734                                    "opClass": "SimdFloatCvt", 
735                                    "opLat": 1, 
736                                    "name": "opList14", 
737                                    "pipelined": true, 
738                                    "eventq_index": 0, 
739                                    "cxx_class": "OpDesc", 
740                                    "path": "system.cpu.fuPool.FUList5.opList14", 
741                                    "type": "OpDesc"
742                                }, 
743                                {
744                                    "opClass": "SimdFloatDiv", 
745                                    "opLat": 1, 
746                                    "name": "opList15", 
747                                    "pipelined": true, 
748                                    "eventq_index": 0, 
749                                    "cxx_class": "OpDesc", 
750                                    "path": "system.cpu.fuPool.FUList5.opList15", 
751                                    "type": "OpDesc"
752                                }, 
753                                {
754                                    "opClass": "SimdFloatMisc", 
755                                    "opLat": 1, 
756                                    "name": "opList16", 
757                                    "pipelined": true, 
758                                    "eventq_index": 0, 
759                                    "cxx_class": "OpDesc", 
760                                    "path": "system.cpu.fuPool.FUList5.opList16", 
761                                    "type": "OpDesc"
762                                }, 
763                                {
764                                    "opClass": "SimdFloatMult", 
765                                    "opLat": 1, 
766                                    "name": "opList17", 
767                                    "pipelined": true, 
768                                    "eventq_index": 0, 
769                                    "cxx_class": "OpDesc", 
770                                    "path": "system.cpu.fuPool.FUList5.opList17", 
771                                    "type": "OpDesc"
772                                }, 
773                                {
774                                    "opClass": "SimdFloatMultAcc", 
775                                    "opLat": 1, 
776                                    "name": "opList18", 
777                                    "pipelined": true, 
778                                    "eventq_index": 0, 
779                                    "cxx_class": "OpDesc", 
780                                    "path": "system.cpu.fuPool.FUList5.opList18", 
781                                    "type": "OpDesc"
782                                }, 
783                                {
784                                    "opClass": "SimdFloatSqrt", 
785                                    "opLat": 1, 
786                                    "name": "opList19", 
787                                    "pipelined": true, 
788                                    "eventq_index": 0, 
789                                    "cxx_class": "OpDesc", 
790                                    "path": "system.cpu.fuPool.FUList5.opList19", 
791                                    "type": "OpDesc"
792                                }
793                            ], 
794                            "name": "FUList5", 
795                            "eventq_index": 0, 
796                            "cxx_class": "FUDesc", 
797                            "path": "system.cpu.fuPool.FUList5", 
798                            "type": "FUDesc"
799                        }, 
800                        {
801                            "count": 0, 
802                            "opList": [
803                                {
804                                    "opClass": "MemWrite", 
805                                    "opLat": 1, 
806                                    "name": "opList0", 
807                                    "pipelined": true, 
808                                    "eventq_index": 0, 
809                                    "cxx_class": "OpDesc", 
810                                    "path": "system.cpu.fuPool.FUList6.opList0", 
811                                    "type": "OpDesc"
812                                }, 
813                                {
814                                    "opClass": "FloatMemWrite", 
815                                    "opLat": 1, 
816                                    "name": "opList1", 
817                                    "pipelined": true, 
818                                    "eventq_index": 0, 
819                                    "cxx_class": "OpDesc", 
820                                    "path": "system.cpu.fuPool.FUList6.opList1", 
821                                    "type": "OpDesc"
822                                }
823                            ], 
824                            "name": "FUList6", 
825                            "eventq_index": 0, 
826                            "cxx_class": "FUDesc", 
827                            "path": "system.cpu.fuPool.FUList6", 
828                            "type": "FUDesc"
829                        }, 
830                        {
831                            "count": 4, 
832                            "opList": [
833                                {
834                                    "opClass": "MemRead", 
835                                    "opLat": 1, 
836                                    "name": "opList0", 
837                                    "pipelined": true, 
838                                    "eventq_index": 0, 
839                                    "cxx_class": "OpDesc", 
840                                    "path": "system.cpu.fuPool.FUList7.opList0", 
841                                    "type": "OpDesc"
842                                }, 
843                                {
844                                    "opClass": "MemWrite", 
845                                    "opLat": 1, 
846                                    "name": "opList1", 
847                                    "pipelined": true, 
848                                    "eventq_index": 0, 
849                                    "cxx_class": "OpDesc", 
850                                    "path": "system.cpu.fuPool.FUList7.opList1", 
851                                    "type": "OpDesc"
852                                }, 
853                                {
854                                    "opClass": "FloatMemRead", 
855                                    "opLat": 1, 
856                                    "name": "opList2", 
857                                    "pipelined": true, 
858                                    "eventq_index": 0, 
859                                    "cxx_class": "OpDesc", 
860                                    "path": "system.cpu.fuPool.FUList7.opList2", 
861                                    "type": "OpDesc"
862                                }, 
863                                {
864                                    "opClass": "FloatMemWrite", 
865                                    "opLat": 1, 
866                                    "name": "opList3", 
867                                    "pipelined": true, 
868                                    "eventq_index": 0, 
869                                    "cxx_class": "OpDesc", 
870                                    "path": "system.cpu.fuPool.FUList7.opList3", 
871                                    "type": "OpDesc"
872                                }
873                            ], 
874                            "name": "FUList7", 
875                            "eventq_index": 0, 
876                            "cxx_class": "FUDesc", 
877                            "path": "system.cpu.fuPool.FUList7", 
878                            "type": "FUDesc"
879                        }, 
880                        {
881                            "count": 1, 
882                            "opList": [
883                                {
884                                    "opClass": "IprAccess", 
885                                    "opLat": 3, 
886                                    "name": "opList", 
887                                    "pipelined": false, 
888                                    "eventq_index": 0, 
889                                    "cxx_class": "OpDesc", 
890                                    "path": "system.cpu.fuPool.FUList8.opList", 
891                                    "type": "OpDesc"
892                                }
893                            ], 
894                            "name": "FUList8", 
895                            "eventq_index": 0, 
896                            "cxx_class": "FUDesc", 
897                            "path": "system.cpu.fuPool.FUList8", 
898                            "type": "FUDesc"
899                        }
900                    ], 
901                    "eventq_index": 0, 
902                    "cxx_class": "FUPool", 
903                    "path": "system.cpu.fuPool", 
904                    "type": "FUPool"
905                }, 
906                "socket_id": 0, 
907                "renameToFetchDelay": 1, 
908                "icache": {
909                    "cpu_side": {
910                        "peer": "system.cpu.icache_port", 
911                        "role": "SLAVE"
912                    }, 
913                    "clusivity": "mostly_incl", 
914                    "prefetcher": null, 
915                    "system": "system", 
916                    "write_buffers": 8, 
917                    "response_latency": 2, 
918                    "cxx_class": "Cache", 
919                    "size": 131072, 
920                    "type": "Cache", 
921                    "clk_domain": "system.cpu_clk_domain", 
922                    "max_miss_count": 0, 
923                    "eventq_index": 0, 
924                    "default_p_state": "UNDEFINED", 
925                    "p_state_clk_gate_max": 1000000000000, 
926                    "mem_side": {
927                        "peer": "system.cpu.toL2Bus.slave[0]", 
928                        "role": "MASTER"
929                    }, 
930                    "mshrs": 4, 
931                    "writeback_clean": true, 
932                    "p_state_clk_gate_min": 1000, 
933                    "tags": {
934                        "size": 131072, 
935                        "tag_latency": 2, 
936                        "name": "tags", 
937                        "p_state_clk_gate_min": 1000, 
938                        "eventq_index": 0, 
939                        "p_state_clk_gate_bins": 20, 
940                        "default_p_state": "UNDEFINED", 
941                        "clk_domain": "system.cpu_clk_domain", 
942                        "power_model": null, 
943                        "sequential_access": false, 
944                        "assoc": 2, 
945                        "cxx_class": "LRU", 
946                        "p_state_clk_gate_max": 1000000000000, 
947                        "path": "system.cpu.icache.tags", 
948                        "block_size": 64, 
949                        "type": "LRU", 
950                        "data_latency": 2
951                    }, 
952                    "tgts_per_mshr": 20, 
953                    "demand_mshr_reserve": 1, 
954                    "power_model": null, 
955                    "addr_ranges": [
956                        "0:18446744073709551615:0:0:0:0"
957                    ], 
958                    "is_read_only": true, 
959                    "prefetch_on_access": false, 
960                    "path": "system.cpu.icache", 
961                    "data_latency": 2, 
962                    "tag_latency": 2, 
963                    "name": "icache", 
964                    "p_state_clk_gate_bins": 20, 
965                    "sequential_access": false, 
966                    "assoc": 2
967                }, 
968                "path": "system.cpu", 
969                "numRobs": 1, 
970                "switched_out": false, 
971                "smtLSQPolicy": "Partitioned", 
972                "fetchBufferSize": 64, 
973                "wait_for_remote_gdb": false, 
974                "cacheStorePorts": 200, 
975                "simpoint_start_insts": [], 
976                "max_insts_any_thread": 0, 
977                "smtROBThreshold": 100, 
978                "numIQEntries": 64, 
979                "branchPred": {
980                    "numThreads": 1, 
981                    "BTBEntries": 4096, 
982                    "cxx_class": "TournamentBP", 
983                    "indirectPathLength": 3, 
984                    "globalCtrBits": 2, 
985                    "choicePredictorSize": 8192, 
986                    "indirectHashGHR": true, 
987                    "eventq_index": 0, 
988                    "localHistoryTableSize": 2048, 
989                    "type": "TournamentBP", 
990                    "indirectSets": 256, 
991                    "indirectWays": 2, 
992                    "choiceCtrBits": 2, 
993                    "useIndirect": true, 
994                    "localCtrBits": 2, 
995                    "path": "system.cpu.branchPred", 
996                    "localPredictorSize": 2048, 
997                    "RASSize": 16, 
998                    "globalPredictorSize": 8192, 
999                    "name": "branchPred", 
1000                    "indirectHashTargets": true, 
1001                    "instShiftAmt": 2, 
1002                    "indirectTagSize": 16, 
1003                    "BTBTagSize": 16
1004                }, 
1005                "LFSTSize": 1024, 
1006                "isa": [
1007                    {
1008                        "eventq_index": 0, 
1009                        "path": "system.cpu.isa", 
1010                        "type": "RiscvISA", 
1011                        "name": "isa", 
1012                        "cxx_class": "RiscvISA::ISA"
1013                    }
1014                ], 
1015                "smtROBPolicy": "Partitioned", 
1016                "iewToFetchDelay": 1, 
1017                "do_statistics_insts": true, 
1018                "dispatchWidth": 8, 
1019                "dcache": {
1020                    "cpu_side": {
1021                        "peer": "system.cpu.dcache_port", 
1022                        "role": "SLAVE"
1023                    }, 
1024                    "clusivity": "mostly_incl", 
1025                    "prefetcher": null, 
1026                    "system": "system", 
1027                    "write_buffers": 8, 
1028                    "response_latency": 2, 
1029                    "cxx_class": "Cache", 
1030                    "size": 262144, 
1031                    "type": "Cache", 
1032                    "clk_domain": "system.cpu_clk_domain", 
1033                    "max_miss_count": 0, 
1034                    "eventq_index": 0, 
1035                    "default_p_state": "UNDEFINED", 
1036                    "p_state_clk_gate_max": 1000000000000, 
1037                    "mem_side": {
1038                        "peer": "system.cpu.toL2Bus.slave[1]", 
1039                        "role": "MASTER"
1040                    }, 
1041                    "mshrs": 4, 
1042                    "writeback_clean": false, 
1043                    "p_state_clk_gate_min": 1000, 
1044                    "tags": {
1045                        "size": 262144, 
1046                        "tag_latency": 2, 
1047                        "name": "tags", 
1048                        "p_state_clk_gate_min": 1000, 
1049                        "eventq_index": 0, 
1050                        "p_state_clk_gate_bins": 20, 
1051                        "default_p_state": "UNDEFINED", 
1052                        "clk_domain": "system.cpu_clk_domain", 
1053                        "power_model": null, 
1054                        "sequential_access": false, 
1055                        "assoc": 2, 
1056                        "cxx_class": "LRU", 
1057                        "p_state_clk_gate_max": 1000000000000, 
1058                        "path": "system.cpu.dcache.tags", 
1059                        "block_size": 64, 
1060                        "type": "LRU", 
1061                        "data_latency": 2
1062                    }, 
1063                    "tgts_per_mshr": 20, 
1064                    "demand_mshr_reserve": 1, 
1065                    "power_model": null, 
1066                    "addr_ranges": [
1067                        "0:18446744073709551615:0:0:0:0"
1068                    ], 
1069                    "is_read_only": false, 
1070                    "prefetch_on_access": false, 
1071                    "path": "system.cpu.dcache", 
1072                    "data_latency": 2, 
1073                    "tag_latency": 2, 
1074                    "name": "dcache", 
1075                    "p_state_clk_gate_bins": 20, 
1076                    "sequential_access": false, 
1077                    "assoc": 2
1078                }, 
1079                "commitToDecodeDelay": 1, 
1080                "smtIQPolicy": "Partitioned", 
1081                "issueWidth": 8, 
1082                "LSQCheckLoads": true, 
1083                "commitToRenameDelay": 1, 
1084                "system": "system", 
1085                "checker": null, 
1086                "numPhysFloatRegs": 256, 
1087                "eventq_index": 0, 
1088                "default_p_state": "UNDEFINED", 
1089                "type": "DerivO3CPU", 
1090                "wbWidth": 8, 
1091                "numPhysVecRegs": 256, 
1092                "interrupts": [
1093                    {
1094                        "eventq_index": 0, 
1095                        "path": "system.cpu.interrupts", 
1096                        "type": "RiscvInterrupts", 
1097                        "name": "interrupts", 
1098                        "cxx_class": "RiscvISA::Interrupts"
1099                    }
1100                ], 
1101                "smtCommitPolicy": "RoundRobin", 
1102                "issueToExecuteDelay": 1, 
1103                "dtb": {
1104                    "name": "dtb", 
1105                    "eventq_index": 0, 
1106                    "cxx_class": "RiscvISA::TLB", 
1107                    "path": "system.cpu.dtb", 
1108                    "type": "RiscvTLB", 
1109                    "size": 64
1110                }, 
1111                "numROBEntries": 192, 
1112                "fetchQueueSize": 32, 
1113                "iewToCommitDelay": 1, 
1114                "smtNumFetchingThreads": 1, 
1115                "forwardComSize": 5, 
1116                "do_checkpoint_insts": true, 
1117                "cxx_class": "DerivO3CPU", 
1118                "commitToIEWDelay": 1, 
1119                "commitWidth": 8, 
1120                "clk_domain": "system.cpu_clk_domain", 
1121                "function_trace_start": 0, 
1122                "smtFetchPolicy": "SingleThread", 
1123                "profile": 0, 
1124                "icache_port": {
1125                    "peer": "system.cpu.icache.cpu_side", 
1126                    "role": "MASTER"
1127                }, 
1128                "dcache_port": {
1129                    "peer": "system.cpu.dcache.cpu_side", 
1130                    "role": "MASTER"
1131                }, 
1132                "LSQDepCheckShift": 4, 
1133                "trapLatency": 13, 
1134                "iewToDecodeDelay": 1, 
1135                "numPhysCCRegs": 0, 
1136                "renameToIEWDelay": 2, 
1137                "p_state_clk_gate_bins": 20, 
1138                "progress_interval": 0, 
1139                "LQEntries": 32
1140            }
1141        ], 
1142        "multi_thread": false, 
1143        "exit_on_work_items": false, 
1144        "work_item_id": -1, 
1145        "num_work_ids": 16
1146    }, 
1147    "time_sync_period": 100000000000, 
1148    "eventq_index": 0, 
1149    "time_sync_spin_threshold": 100000000, 
1150    "cxx_class": "Root", 
1151    "path": "root", 
1152    "time_sync_enable": false, 
1153    "type": "Root", 
1154    "full_system": false
1155}