stats.txt revision 11731
111731Sjason@lowepower.com 211731Sjason@lowepower.com---------- Begin Simulation Statistics ---------- 311731Sjason@lowepower.comsim_seconds 0.000339 # Number of seconds simulated 411731Sjason@lowepower.comsim_ticks 339160000 # Number of ticks simulated 511731Sjason@lowepower.comfinal_tick 339160000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 611731Sjason@lowepower.comsim_freq 1000000000000 # Frequency of simulated ticks 711731Sjason@lowepower.comhost_inst_rate 25032 # Simulator instruction rate (inst/s) 811731Sjason@lowepower.comhost_op_rate 25032 # Simulator op (including micro ops) rate (op/s) 911731Sjason@lowepower.comhost_tick_rate 28360795 # Simulator tick rate (ticks/s) 1011731Sjason@lowepower.comhost_mem_usage 244952 # Number of bytes of host memory used 1111731Sjason@lowepower.comhost_seconds 11.96 # Real time elapsed on the host 1211731Sjason@lowepower.comsim_insts 299354 # Number of instructions simulated 1311731Sjason@lowepower.comsim_ops 299354 # Number of ops (including micro ops) simulated 1411731Sjason@lowepower.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1511731Sjason@lowepower.comsystem.clk_domain.clock 1000 # Clock period in ticks 1611731Sjason@lowepower.comsystem.physmem.pwrStateResidencyTicks::UNDEFINED 339160000 # Cumulative time (in ticks) in various power states 1711731Sjason@lowepower.comsystem.physmem.bytes_read::cpu.inst 74688 # Number of bytes read from this memory 1811731Sjason@lowepower.comsystem.physmem.bytes_read::cpu.data 20352 # Number of bytes read from this memory 1911731Sjason@lowepower.comsystem.physmem.bytes_read::total 95040 # Number of bytes read from this memory 2011731Sjason@lowepower.comsystem.physmem.bytes_inst_read::cpu.inst 74688 # Number of instructions bytes read from this memory 2111731Sjason@lowepower.comsystem.physmem.bytes_inst_read::total 74688 # Number of instructions bytes read from this memory 2211731Sjason@lowepower.comsystem.physmem.num_reads::cpu.inst 1167 # Number of read requests responded to by this memory 2311731Sjason@lowepower.comsystem.physmem.num_reads::cpu.data 318 # Number of read requests responded to by this memory 2411731Sjason@lowepower.comsystem.physmem.num_reads::total 1485 # Number of read requests responded to by this memory 2511731Sjason@lowepower.comsystem.physmem.bw_read::cpu.inst 220214648 # Total read bandwidth from this memory (bytes/s) 2611731Sjason@lowepower.comsystem.physmem.bw_read::cpu.data 60007076 # Total read bandwidth from this memory (bytes/s) 2711731Sjason@lowepower.comsystem.physmem.bw_read::total 280221724 # Total read bandwidth from this memory (bytes/s) 2811731Sjason@lowepower.comsystem.physmem.bw_inst_read::cpu.inst 220214648 # Instruction read bandwidth from this memory (bytes/s) 2911731Sjason@lowepower.comsystem.physmem.bw_inst_read::total 220214648 # Instruction read bandwidth from this memory (bytes/s) 3011731Sjason@lowepower.comsystem.physmem.bw_total::cpu.inst 220214648 # Total bandwidth to/from this memory (bytes/s) 3111731Sjason@lowepower.comsystem.physmem.bw_total::cpu.data 60007076 # Total bandwidth to/from this memory (bytes/s) 3211731Sjason@lowepower.comsystem.physmem.bw_total::total 280221724 # Total bandwidth to/from this memory (bytes/s) 3311731Sjason@lowepower.comsystem.physmem.readReqs 1485 # Number of read requests accepted 3411731Sjason@lowepower.comsystem.physmem.writeReqs 0 # Number of write requests accepted 3511731Sjason@lowepower.comsystem.physmem.readBursts 1485 # Number of DRAM read bursts, including those serviced by the write queue 3611731Sjason@lowepower.comsystem.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 3711731Sjason@lowepower.comsystem.physmem.bytesReadDRAM 95040 # Total number of bytes read from DRAM 3811731Sjason@lowepower.comsystem.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 3911731Sjason@lowepower.comsystem.physmem.bytesWritten 0 # Total number of bytes written to DRAM 4011731Sjason@lowepower.comsystem.physmem.bytesReadSys 95040 # Total read bytes from the system interface side 4111731Sjason@lowepower.comsystem.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 4211731Sjason@lowepower.comsystem.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 4311731Sjason@lowepower.comsystem.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 4411731Sjason@lowepower.comsystem.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 4511731Sjason@lowepower.comsystem.physmem.perBankRdBursts::0 175 # Per bank write bursts 4611731Sjason@lowepower.comsystem.physmem.perBankRdBursts::1 68 # Per bank write bursts 4711731Sjason@lowepower.comsystem.physmem.perBankRdBursts::2 18 # Per bank write bursts 4811731Sjason@lowepower.comsystem.physmem.perBankRdBursts::3 72 # Per bank write bursts 4911731Sjason@lowepower.comsystem.physmem.perBankRdBursts::4 169 # Per bank write bursts 5011731Sjason@lowepower.comsystem.physmem.perBankRdBursts::5 291 # Per bank write bursts 5111731Sjason@lowepower.comsystem.physmem.perBankRdBursts::6 95 # Per bank write bursts 5211731Sjason@lowepower.comsystem.physmem.perBankRdBursts::7 4 # Per bank write bursts 5311731Sjason@lowepower.comsystem.physmem.perBankRdBursts::8 9 # Per bank write bursts 5411731Sjason@lowepower.comsystem.physmem.perBankRdBursts::9 115 # Per bank write bursts 5511731Sjason@lowepower.comsystem.physmem.perBankRdBursts::10 155 # Per bank write bursts 5611731Sjason@lowepower.comsystem.physmem.perBankRdBursts::11 169 # Per bank write bursts 5711731Sjason@lowepower.comsystem.physmem.perBankRdBursts::12 48 # Per bank write bursts 5811731Sjason@lowepower.comsystem.physmem.perBankRdBursts::13 55 # Per bank write bursts 5911731Sjason@lowepower.comsystem.physmem.perBankRdBursts::14 15 # Per bank write bursts 6011731Sjason@lowepower.comsystem.physmem.perBankRdBursts::15 27 # Per bank write bursts 6111731Sjason@lowepower.comsystem.physmem.perBankWrBursts::0 0 # Per bank write bursts 6211731Sjason@lowepower.comsystem.physmem.perBankWrBursts::1 0 # Per bank write bursts 6311731Sjason@lowepower.comsystem.physmem.perBankWrBursts::2 0 # Per bank write bursts 6411731Sjason@lowepower.comsystem.physmem.perBankWrBursts::3 0 # Per bank write bursts 6511731Sjason@lowepower.comsystem.physmem.perBankWrBursts::4 0 # Per bank write bursts 6611731Sjason@lowepower.comsystem.physmem.perBankWrBursts::5 0 # Per bank write bursts 6711731Sjason@lowepower.comsystem.physmem.perBankWrBursts::6 0 # Per bank write bursts 6811731Sjason@lowepower.comsystem.physmem.perBankWrBursts::7 0 # Per bank write bursts 6911731Sjason@lowepower.comsystem.physmem.perBankWrBursts::8 0 # Per bank write bursts 7011731Sjason@lowepower.comsystem.physmem.perBankWrBursts::9 0 # Per bank write bursts 7111731Sjason@lowepower.comsystem.physmem.perBankWrBursts::10 0 # Per bank write bursts 7211731Sjason@lowepower.comsystem.physmem.perBankWrBursts::11 0 # Per bank write bursts 7311731Sjason@lowepower.comsystem.physmem.perBankWrBursts::12 0 # Per bank write bursts 7411731Sjason@lowepower.comsystem.physmem.perBankWrBursts::13 0 # Per bank write bursts 7511731Sjason@lowepower.comsystem.physmem.perBankWrBursts::14 0 # Per bank write bursts 7611731Sjason@lowepower.comsystem.physmem.perBankWrBursts::15 0 # Per bank write bursts 7711731Sjason@lowepower.comsystem.physmem.numRdRetry 0 # Number of times read queue was full causing retry 7811731Sjason@lowepower.comsystem.physmem.numWrRetry 0 # Number of times write queue was full causing retry 7911731Sjason@lowepower.comsystem.physmem.totGap 338943500 # Total gap between requests 8011731Sjason@lowepower.comsystem.physmem.readPktSize::0 0 # Read request sizes (log2) 8111731Sjason@lowepower.comsystem.physmem.readPktSize::1 0 # Read request sizes (log2) 8211731Sjason@lowepower.comsystem.physmem.readPktSize::2 0 # Read request sizes (log2) 8311731Sjason@lowepower.comsystem.physmem.readPktSize::3 0 # Read request sizes (log2) 8411731Sjason@lowepower.comsystem.physmem.readPktSize::4 0 # Read request sizes (log2) 8511731Sjason@lowepower.comsystem.physmem.readPktSize::5 0 # Read request sizes (log2) 8611731Sjason@lowepower.comsystem.physmem.readPktSize::6 1485 # Read request sizes (log2) 8711731Sjason@lowepower.comsystem.physmem.writePktSize::0 0 # Write request sizes (log2) 8811731Sjason@lowepower.comsystem.physmem.writePktSize::1 0 # Write request sizes (log2) 8911731Sjason@lowepower.comsystem.physmem.writePktSize::2 0 # Write request sizes (log2) 9011731Sjason@lowepower.comsystem.physmem.writePktSize::3 0 # Write request sizes (log2) 9111731Sjason@lowepower.comsystem.physmem.writePktSize::4 0 # Write request sizes (log2) 9211731Sjason@lowepower.comsystem.physmem.writePktSize::5 0 # Write request sizes (log2) 9311731Sjason@lowepower.comsystem.physmem.writePktSize::6 0 # Write request sizes (log2) 9411731Sjason@lowepower.comsystem.physmem.rdQLenPdf::0 1419 # What read queue length does an incoming req see 9511731Sjason@lowepower.comsystem.physmem.rdQLenPdf::1 63 # What read queue length does an incoming req see 9611731Sjason@lowepower.comsystem.physmem.rdQLenPdf::2 3 # What read queue length does an incoming req see 9711731Sjason@lowepower.comsystem.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see 9811731Sjason@lowepower.comsystem.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see 9911731Sjason@lowepower.comsystem.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 10011731Sjason@lowepower.comsystem.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 10111731Sjason@lowepower.comsystem.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 10211731Sjason@lowepower.comsystem.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 10311731Sjason@lowepower.comsystem.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 10411731Sjason@lowepower.comsystem.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 10511731Sjason@lowepower.comsystem.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 10611731Sjason@lowepower.comsystem.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 10711731Sjason@lowepower.comsystem.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 10811731Sjason@lowepower.comsystem.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 10911731Sjason@lowepower.comsystem.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 11011731Sjason@lowepower.comsystem.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 11111731Sjason@lowepower.comsystem.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 11211731Sjason@lowepower.comsystem.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 11311731Sjason@lowepower.comsystem.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 11411731Sjason@lowepower.comsystem.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 11511731Sjason@lowepower.comsystem.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 11611731Sjason@lowepower.comsystem.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 11711731Sjason@lowepower.comsystem.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 11811731Sjason@lowepower.comsystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 11911731Sjason@lowepower.comsystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 12011731Sjason@lowepower.comsystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 12111731Sjason@lowepower.comsystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 12211731Sjason@lowepower.comsystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 12311731Sjason@lowepower.comsystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 12411731Sjason@lowepower.comsystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 12511731Sjason@lowepower.comsystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 12611731Sjason@lowepower.comsystem.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 12711731Sjason@lowepower.comsystem.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 12811731Sjason@lowepower.comsystem.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 12911731Sjason@lowepower.comsystem.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 13011731Sjason@lowepower.comsystem.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 13111731Sjason@lowepower.comsystem.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 13211731Sjason@lowepower.comsystem.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 13311731Sjason@lowepower.comsystem.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 13411731Sjason@lowepower.comsystem.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 13511731Sjason@lowepower.comsystem.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 13611731Sjason@lowepower.comsystem.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 13711731Sjason@lowepower.comsystem.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 13811731Sjason@lowepower.comsystem.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 13911731Sjason@lowepower.comsystem.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 14011731Sjason@lowepower.comsystem.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 14111731Sjason@lowepower.comsystem.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 14211731Sjason@lowepower.comsystem.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 14311731Sjason@lowepower.comsystem.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 14411731Sjason@lowepower.comsystem.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 14511731Sjason@lowepower.comsystem.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 14611731Sjason@lowepower.comsystem.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 14711731Sjason@lowepower.comsystem.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 14811731Sjason@lowepower.comsystem.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 14911731Sjason@lowepower.comsystem.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 15011731Sjason@lowepower.comsystem.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 15111731Sjason@lowepower.comsystem.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 15211731Sjason@lowepower.comsystem.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 15311731Sjason@lowepower.comsystem.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 15411731Sjason@lowepower.comsystem.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 15511731Sjason@lowepower.comsystem.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 15611731Sjason@lowepower.comsystem.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 15711731Sjason@lowepower.comsystem.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 15811731Sjason@lowepower.comsystem.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 15911731Sjason@lowepower.comsystem.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 16011731Sjason@lowepower.comsystem.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 16111731Sjason@lowepower.comsystem.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 16211731Sjason@lowepower.comsystem.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 16311731Sjason@lowepower.comsystem.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 16411731Sjason@lowepower.comsystem.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 16511731Sjason@lowepower.comsystem.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 16611731Sjason@lowepower.comsystem.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 16711731Sjason@lowepower.comsystem.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 16811731Sjason@lowepower.comsystem.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 16911731Sjason@lowepower.comsystem.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 17011731Sjason@lowepower.comsystem.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 17111731Sjason@lowepower.comsystem.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 17211731Sjason@lowepower.comsystem.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 17311731Sjason@lowepower.comsystem.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 17411731Sjason@lowepower.comsystem.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 17511731Sjason@lowepower.comsystem.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 17611731Sjason@lowepower.comsystem.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 17711731Sjason@lowepower.comsystem.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 17811731Sjason@lowepower.comsystem.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 17911731Sjason@lowepower.comsystem.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 18011731Sjason@lowepower.comsystem.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 18111731Sjason@lowepower.comsystem.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 18211731Sjason@lowepower.comsystem.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 18311731Sjason@lowepower.comsystem.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 18411731Sjason@lowepower.comsystem.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 18511731Sjason@lowepower.comsystem.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 18611731Sjason@lowepower.comsystem.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 18711731Sjason@lowepower.comsystem.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 18811731Sjason@lowepower.comsystem.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 18911731Sjason@lowepower.comsystem.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 19011731Sjason@lowepower.comsystem.physmem.bytesPerActivate::samples 285 # Bytes accessed per row activation 19111731Sjason@lowepower.comsystem.physmem.bytesPerActivate::mean 327.859649 # Bytes accessed per row activation 19211731Sjason@lowepower.comsystem.physmem.bytesPerActivate::gmean 221.469651 # Bytes accessed per row activation 19311731Sjason@lowepower.comsystem.physmem.bytesPerActivate::stdev 283.652997 # Bytes accessed per row activation 19411731Sjason@lowepower.comsystem.physmem.bytesPerActivate::0-127 67 23.51% 23.51% # Bytes accessed per row activation 19511731Sjason@lowepower.comsystem.physmem.bytesPerActivate::128-255 73 25.61% 49.12% # Bytes accessed per row activation 19611731Sjason@lowepower.comsystem.physmem.bytesPerActivate::256-383 39 13.68% 62.81% # Bytes accessed per row activation 19711731Sjason@lowepower.comsystem.physmem.bytesPerActivate::384-511 33 11.58% 74.39% # Bytes accessed per row activation 19811731Sjason@lowepower.comsystem.physmem.bytesPerActivate::512-639 28 9.82% 84.21% # Bytes accessed per row activation 19911731Sjason@lowepower.comsystem.physmem.bytesPerActivate::640-767 15 5.26% 89.47% # Bytes accessed per row activation 20011731Sjason@lowepower.comsystem.physmem.bytesPerActivate::768-895 7 2.46% 91.93% # Bytes accessed per row activation 20111731Sjason@lowepower.comsystem.physmem.bytesPerActivate::896-1023 2 0.70% 92.63% # Bytes accessed per row activation 20211731Sjason@lowepower.comsystem.physmem.bytesPerActivate::1024-1151 21 7.37% 100.00% # Bytes accessed per row activation 20311731Sjason@lowepower.comsystem.physmem.bytesPerActivate::total 285 # Bytes accessed per row activation 20411731Sjason@lowepower.comsystem.physmem.totQLat 19805250 # Total ticks spent queuing 20511731Sjason@lowepower.comsystem.physmem.totMemAccLat 47649000 # Total ticks spent from burst creation until serviced by the DRAM 20611731Sjason@lowepower.comsystem.physmem.totBusLat 7425000 # Total ticks spent in databus transfers 20711731Sjason@lowepower.comsystem.physmem.avgQLat 13336.87 # Average queueing delay per DRAM burst 20811731Sjason@lowepower.comsystem.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 20911731Sjason@lowepower.comsystem.physmem.avgMemAccLat 32086.87 # Average memory access latency per DRAM burst 21011731Sjason@lowepower.comsystem.physmem.avgRdBW 280.22 # Average DRAM read bandwidth in MiByte/s 21111731Sjason@lowepower.comsystem.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 21211731Sjason@lowepower.comsystem.physmem.avgRdBWSys 280.22 # Average system read bandwidth in MiByte/s 21311731Sjason@lowepower.comsystem.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 21411731Sjason@lowepower.comsystem.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 21511731Sjason@lowepower.comsystem.physmem.busUtil 2.19 # Data bus utilization in percentage 21611731Sjason@lowepower.comsystem.physmem.busUtilRead 2.19 # Data bus utilization in percentage for reads 21711731Sjason@lowepower.comsystem.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 21811731Sjason@lowepower.comsystem.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing 21911731Sjason@lowepower.comsystem.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 22011731Sjason@lowepower.comsystem.physmem.readRowHits 1195 # Number of row buffer hits during reads 22111731Sjason@lowepower.comsystem.physmem.writeRowHits 0 # Number of row buffer hits during writes 22211731Sjason@lowepower.comsystem.physmem.readRowHitRate 80.47 # Row buffer hit rate for reads 22311731Sjason@lowepower.comsystem.physmem.writeRowHitRate nan # Row buffer hit rate for writes 22411731Sjason@lowepower.comsystem.physmem.avgGap 228244.78 # Average gap between requests 22511731Sjason@lowepower.comsystem.physmem.pageHitRate 80.47 # Row buffer hit rate, read and write combined 22611731Sjason@lowepower.comsystem.physmem_0.actEnergy 1106700 # Energy for activate commands per rank (pJ) 22711731Sjason@lowepower.comsystem.physmem_0.preEnergy 576840 # Energy for precharge commands per rank (pJ) 22811731Sjason@lowepower.comsystem.physmem_0.readEnergy 6368880 # Energy for read commands per rank (pJ) 22911731Sjason@lowepower.comsystem.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 23011731Sjason@lowepower.comsystem.physmem_0.refreshEnergy 27044160.000000 # Energy for refresh commands per rank (pJ) 23111731Sjason@lowepower.comsystem.physmem_0.actBackEnergy 16006740 # Energy for active background per rank (pJ) 23211731Sjason@lowepower.comsystem.physmem_0.preBackEnergy 700320 # Energy for precharge background per rank (pJ) 23311731Sjason@lowepower.comsystem.physmem_0.actPowerDownEnergy 122840700 # Energy for active power-down per rank (pJ) 23411731Sjason@lowepower.comsystem.physmem_0.prePowerDownEnergy 12504960 # Energy for precharge power-down per rank (pJ) 23511731Sjason@lowepower.comsystem.physmem_0.selfRefreshEnergy 619740.000000 # Energy for self refresh per rank (pJ) 23611731Sjason@lowepower.comsystem.physmem_0.totalEnergy 187769040 # Total energy per rank (pJ) 23711731Sjason@lowepower.comsystem.physmem_0.averagePower 553.629673 # Core power per rank (mW) 23811731Sjason@lowepower.comsystem.physmem_0.totalIdleTime 301401000 # Total Idle time Per DRAM Rank 23911731Sjason@lowepower.comsystem.physmem_0.memoryStateTime::IDLE 546000 # Time in different power states 24011731Sjason@lowepower.comsystem.physmem_0.memoryStateTime::REF 11446000 # Time in different power states 24111731Sjason@lowepower.comsystem.physmem_0.memoryStateTime::SREF 280750 # Time in different power states 24211731Sjason@lowepower.comsystem.physmem_0.memoryStateTime::PRE_PDN 32576500 # Time in different power states 24311731Sjason@lowepower.comsystem.physmem_0.memoryStateTime::ACT 24926250 # Time in different power states 24411731Sjason@lowepower.comsystem.physmem_0.memoryStateTime::ACT_PDN 269384500 # Time in different power states 24511731Sjason@lowepower.comsystem.physmem_1.actEnergy 963900 # Energy for activate commands per rank (pJ) 24611731Sjason@lowepower.comsystem.physmem_1.preEnergy 504735 # Energy for precharge commands per rank (pJ) 24711731Sjason@lowepower.comsystem.physmem_1.readEnergy 4234020 # Energy for read commands per rank (pJ) 24811731Sjason@lowepower.comsystem.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 24911731Sjason@lowepower.comsystem.physmem_1.refreshEnergy 27044160.000000 # Energy for refresh commands per rank (pJ) 25011731Sjason@lowepower.comsystem.physmem_1.actBackEnergy 12901950 # Energy for active background per rank (pJ) 25111731Sjason@lowepower.comsystem.physmem_1.preBackEnergy 3644640 # Energy for precharge background per rank (pJ) 25211731Sjason@lowepower.comsystem.physmem_1.actPowerDownEnergy 106370550 # Energy for active power-down per rank (pJ) 25311731Sjason@lowepower.comsystem.physmem_1.prePowerDownEnergy 25587360 # Energy for precharge power-down per rank (pJ) 25411731Sjason@lowepower.comsystem.physmem_1.selfRefreshEnergy 905640.000000 # Energy for self refresh per rank (pJ) 25511731Sjason@lowepower.comsystem.physmem_1.totalEnergy 182156955 # Total energy per rank (pJ) 25611731Sjason@lowepower.comsystem.physmem_1.averagePower 537.082660 # Core power per rank (mW) 25711731Sjason@lowepower.comsystem.physmem_1.totalIdleTime 301148500 # Total Idle time Per DRAM Rank 25811731Sjason@lowepower.comsystem.physmem_1.memoryStateTime::IDLE 8278250 # Time in different power states 25911731Sjason@lowepower.comsystem.physmem_1.memoryStateTime::REF 11446000 # Time in different power states 26011731Sjason@lowepower.comsystem.physmem_1.memoryStateTime::SREF 1471750 # Time in different power states 26111731Sjason@lowepower.comsystem.physmem_1.memoryStateTime::PRE_PDN 66617000 # Time in different power states 26211731Sjason@lowepower.comsystem.physmem_1.memoryStateTime::ACT 18107500 # Time in different power states 26311731Sjason@lowepower.comsystem.physmem_1.memoryStateTime::ACT_PDN 233239500 # Time in different power states 26411731Sjason@lowepower.comsystem.pwrStateResidencyTicks::UNDEFINED 339160000 # Cumulative time (in ticks) in various power states 26511731Sjason@lowepower.comsystem.cpu.branchPred.lookups 80709 # Number of BP lookups 26611731Sjason@lowepower.comsystem.cpu.branchPred.condPredicted 51944 # Number of conditional branches predicted 26711731Sjason@lowepower.comsystem.cpu.branchPred.condIncorrect 5835 # Number of conditional branches incorrect 26811731Sjason@lowepower.comsystem.cpu.branchPred.BTBLookups 64346 # Number of BTB lookups 26911731Sjason@lowepower.comsystem.cpu.branchPred.BTBHits 38294 # Number of BTB hits 27011731Sjason@lowepower.comsystem.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 27111731Sjason@lowepower.comsystem.cpu.branchPred.BTBHitPct 59.512635 # BTB Hit Percentage 27211731Sjason@lowepower.comsystem.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target. 27311731Sjason@lowepower.comsystem.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. 27411731Sjason@lowepower.comsystem.cpu.branchPred.indirectLookups 13164 # Number of indirect predictor lookups. 27511731Sjason@lowepower.comsystem.cpu.branchPred.indirectHits 7506 # Number of indirect target hits. 27611731Sjason@lowepower.comsystem.cpu.branchPred.indirectMisses 5658 # Number of indirect misses. 27711731Sjason@lowepower.comsystem.cpu.branchPredindirectMispredicted 3210 # Number of mispredicted indirect branches. 27811731Sjason@lowepower.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 27911731Sjason@lowepower.comsystem.cpu.dtb.read_hits 0 # DTB read hits 28011731Sjason@lowepower.comsystem.cpu.dtb.read_misses 0 # DTB read misses 28111731Sjason@lowepower.comsystem.cpu.dtb.read_accesses 0 # DTB read accesses 28211731Sjason@lowepower.comsystem.cpu.dtb.write_hits 0 # DTB write hits 28311731Sjason@lowepower.comsystem.cpu.dtb.write_misses 0 # DTB write misses 28411731Sjason@lowepower.comsystem.cpu.dtb.write_accesses 0 # DTB write accesses 28511731Sjason@lowepower.comsystem.cpu.dtb.hits 0 # DTB hits 28611731Sjason@lowepower.comsystem.cpu.dtb.misses 0 # DTB misses 28711731Sjason@lowepower.comsystem.cpu.dtb.accesses 0 # DTB accesses 28811731Sjason@lowepower.comsystem.cpu.itb.read_hits 0 # DTB read hits 28911731Sjason@lowepower.comsystem.cpu.itb.read_misses 0 # DTB read misses 29011731Sjason@lowepower.comsystem.cpu.itb.read_accesses 0 # DTB read accesses 29111731Sjason@lowepower.comsystem.cpu.itb.write_hits 0 # DTB write hits 29211731Sjason@lowepower.comsystem.cpu.itb.write_misses 0 # DTB write misses 29311731Sjason@lowepower.comsystem.cpu.itb.write_accesses 0 # DTB write accesses 29411731Sjason@lowepower.comsystem.cpu.itb.hits 0 # DTB hits 29511731Sjason@lowepower.comsystem.cpu.itb.misses 0 # DTB misses 29611731Sjason@lowepower.comsystem.cpu.itb.accesses 0 # DTB accesses 29711731Sjason@lowepower.comsystem.cpu.workload.num_syscalls 162 # Number of system calls 29811731Sjason@lowepower.comsystem.cpu.pwrStateResidencyTicks::ON 339160000 # Cumulative time (in ticks) in various power states 29911731Sjason@lowepower.comsystem.cpu.numCycles 678320 # number of cpu cycles simulated 30011731Sjason@lowepower.comsystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 30111731Sjason@lowepower.comsystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 30211731Sjason@lowepower.comsystem.cpu.committedInsts 299354 # Number of instructions committed 30311731Sjason@lowepower.comsystem.cpu.committedOps 299354 # Number of ops (including micro ops) committed 30411731Sjason@lowepower.comsystem.cpu.discardedOps 13959 # Number of ops (including micro ops) which were discarded before commit 30511731Sjason@lowepower.comsystem.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching 30611731Sjason@lowepower.comsystem.cpu.cpi 2.265946 # CPI: cycles per instruction 30711731Sjason@lowepower.comsystem.cpu.ipc 0.441317 # IPC: instructions per cycle 30811731Sjason@lowepower.comsystem.cpu.op_class_0::No_OpClass 162 0.05% 0.05% # Class of committed instruction 30911731Sjason@lowepower.comsystem.cpu.op_class_0::IntAlu 179913 60.10% 60.15% # Class of committed instruction 31011731Sjason@lowepower.comsystem.cpu.op_class_0::IntMult 466 0.16% 60.31% # Class of committed instruction 31111731Sjason@lowepower.comsystem.cpu.op_class_0::IntDiv 40 0.01% 60.32% # Class of committed instruction 31211731Sjason@lowepower.comsystem.cpu.op_class_0::FloatAdd 120 0.04% 60.36% # Class of committed instruction 31311731Sjason@lowepower.comsystem.cpu.op_class_0::FloatCmp 157 0.05% 60.42% # Class of committed instruction 31411731Sjason@lowepower.comsystem.cpu.op_class_0::FloatCvt 60 0.02% 60.44% # Class of committed instruction 31511731Sjason@lowepower.comsystem.cpu.op_class_0::FloatMult 30 0.01% 60.45% # Class of committed instruction 31611731Sjason@lowepower.comsystem.cpu.op_class_0::FloatMultAcc 0 0.00% 60.45% # Class of committed instruction 31711731Sjason@lowepower.comsystem.cpu.op_class_0::FloatDiv 11 0.00% 60.45% # Class of committed instruction 31811731Sjason@lowepower.comsystem.cpu.op_class_0::FloatMisc 0 0.00% 60.45% # Class of committed instruction 31911731Sjason@lowepower.comsystem.cpu.op_class_0::FloatSqrt 5 0.00% 60.45% # Class of committed instruction 32011731Sjason@lowepower.comsystem.cpu.op_class_0::SimdAdd 0 0.00% 60.45% # Class of committed instruction 32111731Sjason@lowepower.comsystem.cpu.op_class_0::SimdAddAcc 0 0.00% 60.45% # Class of committed instruction 32211731Sjason@lowepower.comsystem.cpu.op_class_0::SimdAlu 0 0.00% 60.45% # Class of committed instruction 32311731Sjason@lowepower.comsystem.cpu.op_class_0::SimdCmp 0 0.00% 60.45% # Class of committed instruction 32411731Sjason@lowepower.comsystem.cpu.op_class_0::SimdCvt 0 0.00% 60.45% # Class of committed instruction 32511731Sjason@lowepower.comsystem.cpu.op_class_0::SimdMisc 0 0.00% 60.45% # Class of committed instruction 32611731Sjason@lowepower.comsystem.cpu.op_class_0::SimdMult 0 0.00% 60.45% # Class of committed instruction 32711731Sjason@lowepower.comsystem.cpu.op_class_0::SimdMultAcc 0 0.00% 60.45% # Class of committed instruction 32811731Sjason@lowepower.comsystem.cpu.op_class_0::SimdShift 0 0.00% 60.45% # Class of committed instruction 32911731Sjason@lowepower.comsystem.cpu.op_class_0::SimdShiftAcc 0 0.00% 60.45% # Class of committed instruction 33011731Sjason@lowepower.comsystem.cpu.op_class_0::SimdSqrt 0 0.00% 60.45% # Class of committed instruction 33111731Sjason@lowepower.comsystem.cpu.op_class_0::SimdFloatAdd 0 0.00% 60.45% # Class of committed instruction 33211731Sjason@lowepower.comsystem.cpu.op_class_0::SimdFloatAlu 0 0.00% 60.45% # Class of committed instruction 33311731Sjason@lowepower.comsystem.cpu.op_class_0::SimdFloatCmp 0 0.00% 60.45% # Class of committed instruction 33411731Sjason@lowepower.comsystem.cpu.op_class_0::SimdFloatCvt 0 0.00% 60.45% # Class of committed instruction 33511731Sjason@lowepower.comsystem.cpu.op_class_0::SimdFloatDiv 0 0.00% 60.45% # Class of committed instruction 33611731Sjason@lowepower.comsystem.cpu.op_class_0::SimdFloatMisc 0 0.00% 60.45% # Class of committed instruction 33711731Sjason@lowepower.comsystem.cpu.op_class_0::SimdFloatMult 0 0.00% 60.45% # Class of committed instruction 33811731Sjason@lowepower.comsystem.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 60.45% # Class of committed instruction 33911731Sjason@lowepower.comsystem.cpu.op_class_0::SimdFloatSqrt 0 0.00% 60.45% # Class of committed instruction 34011731Sjason@lowepower.comsystem.cpu.op_class_0::MemRead 69348 23.17% 83.62% # Class of committed instruction 34111731Sjason@lowepower.comsystem.cpu.op_class_0::MemWrite 48400 16.17% 99.79% # Class of committed instruction 34211731Sjason@lowepower.comsystem.cpu.op_class_0::FloatMemRead 495 0.17% 99.95% # Class of committed instruction 34311731Sjason@lowepower.comsystem.cpu.op_class_0::FloatMemWrite 147 0.05% 100.00% # Class of committed instruction 34411731Sjason@lowepower.comsystem.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 34511731Sjason@lowepower.comsystem.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 34611731Sjason@lowepower.comsystem.cpu.op_class_0::total 299354 # Class of committed instruction 34711731Sjason@lowepower.comsystem.cpu.tickCycles 449536 # Number of cycles that the object actually ticked 34811731Sjason@lowepower.comsystem.cpu.idleCycles 228784 # Total number of cycles that the object has spent stopped 34911731Sjason@lowepower.comsystem.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 339160000 # Cumulative time (in ticks) in various power states 35011731Sjason@lowepower.comsystem.cpu.dcache.tags.replacements 0 # number of replacements 35111731Sjason@lowepower.comsystem.cpu.dcache.tags.tagsinuse 254.196505 # Cycle average of tags in use 35211731Sjason@lowepower.comsystem.cpu.dcache.tags.total_refs 119907 # Total number of references to valid blocks. 35311731Sjason@lowepower.comsystem.cpu.dcache.tags.sampled_refs 320 # Sample count of references to valid blocks. 35411731Sjason@lowepower.comsystem.cpu.dcache.tags.avg_refs 374.709375 # Average number of references to valid blocks. 35511731Sjason@lowepower.comsystem.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 35611731Sjason@lowepower.comsystem.cpu.dcache.tags.occ_blocks::cpu.data 254.196505 # Average occupied blocks per requestor 35711731Sjason@lowepower.comsystem.cpu.dcache.tags.occ_percent::cpu.data 0.062060 # Average percentage of cache occupancy 35811731Sjason@lowepower.comsystem.cpu.dcache.tags.occ_percent::total 0.062060 # Average percentage of cache occupancy 35911731Sjason@lowepower.comsystem.cpu.dcache.tags.occ_task_id_blocks::1024 320 # Occupied blocks per task id 36011731Sjason@lowepower.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id 36111731Sjason@lowepower.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id 36211731Sjason@lowepower.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::2 288 # Occupied blocks per task id 36311731Sjason@lowepower.comsystem.cpu.dcache.tags.occ_task_id_percent::1024 0.078125 # Percentage of cache occupancy per task id 36411731Sjason@lowepower.comsystem.cpu.dcache.tags.tag_accesses 241156 # Number of tag accesses 36511731Sjason@lowepower.comsystem.cpu.dcache.tags.data_accesses 241156 # Number of data accesses 36611731Sjason@lowepower.comsystem.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 339160000 # Cumulative time (in ticks) in various power states 36711731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_hits::cpu.data 71754 # number of ReadReq hits 36811731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_hits::total 71754 # number of ReadReq hits 36911731Sjason@lowepower.comsystem.cpu.dcache.WriteReq_hits::cpu.data 48153 # number of WriteReq hits 37011731Sjason@lowepower.comsystem.cpu.dcache.WriteReq_hits::total 48153 # number of WriteReq hits 37111731Sjason@lowepower.comsystem.cpu.dcache.demand_hits::cpu.data 119907 # number of demand (read+write) hits 37211731Sjason@lowepower.comsystem.cpu.dcache.demand_hits::total 119907 # number of demand (read+write) hits 37311731Sjason@lowepower.comsystem.cpu.dcache.overall_hits::cpu.data 119907 # number of overall hits 37411731Sjason@lowepower.comsystem.cpu.dcache.overall_hits::total 119907 # number of overall hits 37511731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_misses::cpu.data 118 # number of ReadReq misses 37611731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_misses::total 118 # number of ReadReq misses 37711731Sjason@lowepower.comsystem.cpu.dcache.WriteReq_misses::cpu.data 393 # number of WriteReq misses 37811731Sjason@lowepower.comsystem.cpu.dcache.WriteReq_misses::total 393 # number of WriteReq misses 37911731Sjason@lowepower.comsystem.cpu.dcache.demand_misses::cpu.data 511 # number of demand (read+write) misses 38011731Sjason@lowepower.comsystem.cpu.dcache.demand_misses::total 511 # number of demand (read+write) misses 38111731Sjason@lowepower.comsystem.cpu.dcache.overall_misses::cpu.data 511 # number of overall misses 38211731Sjason@lowepower.comsystem.cpu.dcache.overall_misses::total 511 # number of overall misses 38311731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_miss_latency::cpu.data 10963000 # number of ReadReq miss cycles 38411731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_miss_latency::total 10963000 # number of ReadReq miss cycles 38511731Sjason@lowepower.comsystem.cpu.dcache.WriteReq_miss_latency::cpu.data 31520500 # number of WriteReq miss cycles 38611731Sjason@lowepower.comsystem.cpu.dcache.WriteReq_miss_latency::total 31520500 # number of WriteReq miss cycles 38711731Sjason@lowepower.comsystem.cpu.dcache.demand_miss_latency::cpu.data 42483500 # number of demand (read+write) miss cycles 38811731Sjason@lowepower.comsystem.cpu.dcache.demand_miss_latency::total 42483500 # number of demand (read+write) miss cycles 38911731Sjason@lowepower.comsystem.cpu.dcache.overall_miss_latency::cpu.data 42483500 # number of overall miss cycles 39011731Sjason@lowepower.comsystem.cpu.dcache.overall_miss_latency::total 42483500 # number of overall miss cycles 39111731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_accesses::cpu.data 71872 # number of ReadReq accesses(hits+misses) 39211731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_accesses::total 71872 # number of ReadReq accesses(hits+misses) 39311731Sjason@lowepower.comsystem.cpu.dcache.WriteReq_accesses::cpu.data 48546 # number of WriteReq accesses(hits+misses) 39411731Sjason@lowepower.comsystem.cpu.dcache.WriteReq_accesses::total 48546 # number of WriteReq accesses(hits+misses) 39511731Sjason@lowepower.comsystem.cpu.dcache.demand_accesses::cpu.data 120418 # number of demand (read+write) accesses 39611731Sjason@lowepower.comsystem.cpu.dcache.demand_accesses::total 120418 # number of demand (read+write) accesses 39711731Sjason@lowepower.comsystem.cpu.dcache.overall_accesses::cpu.data 120418 # number of overall (read+write) accesses 39811731Sjason@lowepower.comsystem.cpu.dcache.overall_accesses::total 120418 # number of overall (read+write) accesses 39911731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001642 # miss rate for ReadReq accesses 40011731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_miss_rate::total 0.001642 # miss rate for ReadReq accesses 40111731Sjason@lowepower.comsystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.008095 # miss rate for WriteReq accesses 40211731Sjason@lowepower.comsystem.cpu.dcache.WriteReq_miss_rate::total 0.008095 # miss rate for WriteReq accesses 40311731Sjason@lowepower.comsystem.cpu.dcache.demand_miss_rate::cpu.data 0.004244 # miss rate for demand accesses 40411731Sjason@lowepower.comsystem.cpu.dcache.demand_miss_rate::total 0.004244 # miss rate for demand accesses 40511731Sjason@lowepower.comsystem.cpu.dcache.overall_miss_rate::cpu.data 0.004244 # miss rate for overall accesses 40611731Sjason@lowepower.comsystem.cpu.dcache.overall_miss_rate::total 0.004244 # miss rate for overall accesses 40711731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 92906.779661 # average ReadReq miss latency 40811731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_avg_miss_latency::total 92906.779661 # average ReadReq miss latency 40911731Sjason@lowepower.comsystem.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 80204.834606 # average WriteReq miss latency 41011731Sjason@lowepower.comsystem.cpu.dcache.WriteReq_avg_miss_latency::total 80204.834606 # average WriteReq miss latency 41111731Sjason@lowepower.comsystem.cpu.dcache.demand_avg_miss_latency::cpu.data 83137.964775 # average overall miss latency 41211731Sjason@lowepower.comsystem.cpu.dcache.demand_avg_miss_latency::total 83137.964775 # average overall miss latency 41311731Sjason@lowepower.comsystem.cpu.dcache.overall_avg_miss_latency::cpu.data 83137.964775 # average overall miss latency 41411731Sjason@lowepower.comsystem.cpu.dcache.overall_avg_miss_latency::total 83137.964775 # average overall miss latency 41511731Sjason@lowepower.comsystem.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 41611731Sjason@lowepower.comsystem.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 41711731Sjason@lowepower.comsystem.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 41811731Sjason@lowepower.comsystem.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 41911731Sjason@lowepower.comsystem.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 42011731Sjason@lowepower.comsystem.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 42111731Sjason@lowepower.comsystem.cpu.dcache.WriteReq_mshr_hits::cpu.data 191 # number of WriteReq MSHR hits 42211731Sjason@lowepower.comsystem.cpu.dcache.WriteReq_mshr_hits::total 191 # number of WriteReq MSHR hits 42311731Sjason@lowepower.comsystem.cpu.dcache.demand_mshr_hits::cpu.data 191 # number of demand (read+write) MSHR hits 42411731Sjason@lowepower.comsystem.cpu.dcache.demand_mshr_hits::total 191 # number of demand (read+write) MSHR hits 42511731Sjason@lowepower.comsystem.cpu.dcache.overall_mshr_hits::cpu.data 191 # number of overall MSHR hits 42611731Sjason@lowepower.comsystem.cpu.dcache.overall_mshr_hits::total 191 # number of overall MSHR hits 42711731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_mshr_misses::cpu.data 118 # number of ReadReq MSHR misses 42811731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_mshr_misses::total 118 # number of ReadReq MSHR misses 42911731Sjason@lowepower.comsystem.cpu.dcache.WriteReq_mshr_misses::cpu.data 202 # number of WriteReq MSHR misses 43011731Sjason@lowepower.comsystem.cpu.dcache.WriteReq_mshr_misses::total 202 # number of WriteReq MSHR misses 43111731Sjason@lowepower.comsystem.cpu.dcache.demand_mshr_misses::cpu.data 320 # number of demand (read+write) MSHR misses 43211731Sjason@lowepower.comsystem.cpu.dcache.demand_mshr_misses::total 320 # number of demand (read+write) MSHR misses 43311731Sjason@lowepower.comsystem.cpu.dcache.overall_mshr_misses::cpu.data 320 # number of overall MSHR misses 43411731Sjason@lowepower.comsystem.cpu.dcache.overall_mshr_misses::total 320 # number of overall MSHR misses 43511731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10845000 # number of ReadReq MSHR miss cycles 43611731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::total 10845000 # number of ReadReq MSHR miss cycles 43711731Sjason@lowepower.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 16122000 # number of WriteReq MSHR miss cycles 43811731Sjason@lowepower.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::total 16122000 # number of WriteReq MSHR miss cycles 43911731Sjason@lowepower.comsystem.cpu.dcache.demand_mshr_miss_latency::cpu.data 26967000 # number of demand (read+write) MSHR miss cycles 44011731Sjason@lowepower.comsystem.cpu.dcache.demand_mshr_miss_latency::total 26967000 # number of demand (read+write) MSHR miss cycles 44111731Sjason@lowepower.comsystem.cpu.dcache.overall_mshr_miss_latency::cpu.data 26967000 # number of overall MSHR miss cycles 44211731Sjason@lowepower.comsystem.cpu.dcache.overall_mshr_miss_latency::total 26967000 # number of overall MSHR miss cycles 44311731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001642 # mshr miss rate for ReadReq accesses 44411731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001642 # mshr miss rate for ReadReq accesses 44511731Sjason@lowepower.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.004161 # mshr miss rate for WriteReq accesses 44611731Sjason@lowepower.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::total 0.004161 # mshr miss rate for WriteReq accesses 44711731Sjason@lowepower.comsystem.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002657 # mshr miss rate for demand accesses 44811731Sjason@lowepower.comsystem.cpu.dcache.demand_mshr_miss_rate::total 0.002657 # mshr miss rate for demand accesses 44911731Sjason@lowepower.comsystem.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002657 # mshr miss rate for overall accesses 45011731Sjason@lowepower.comsystem.cpu.dcache.overall_mshr_miss_rate::total 0.002657 # mshr miss rate for overall accesses 45111731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 91906.779661 # average ReadReq mshr miss latency 45211731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 91906.779661 # average ReadReq mshr miss latency 45311731Sjason@lowepower.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79811.881188 # average WriteReq mshr miss latency 45411731Sjason@lowepower.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79811.881188 # average WriteReq mshr miss latency 45511731Sjason@lowepower.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 84271.875000 # average overall mshr miss latency 45611731Sjason@lowepower.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::total 84271.875000 # average overall mshr miss latency 45711731Sjason@lowepower.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 84271.875000 # average overall mshr miss latency 45811731Sjason@lowepower.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::total 84271.875000 # average overall mshr miss latency 45911731Sjason@lowepower.comsystem.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 339160000 # Cumulative time (in ticks) in various power states 46011731Sjason@lowepower.comsystem.cpu.icache.tags.replacements 80 # number of replacements 46111731Sjason@lowepower.comsystem.cpu.icache.tags.tagsinuse 640.869470 # Cycle average of tags in use 46211731Sjason@lowepower.comsystem.cpu.icache.tags.total_refs 135081 # Total number of references to valid blocks. 46311731Sjason@lowepower.comsystem.cpu.icache.tags.sampled_refs 1178 # Sample count of references to valid blocks. 46411731Sjason@lowepower.comsystem.cpu.icache.tags.avg_refs 114.669779 # Average number of references to valid blocks. 46511731Sjason@lowepower.comsystem.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 46611731Sjason@lowepower.comsystem.cpu.icache.tags.occ_blocks::cpu.inst 640.869470 # Average occupied blocks per requestor 46711731Sjason@lowepower.comsystem.cpu.icache.tags.occ_percent::cpu.inst 0.312925 # Average percentage of cache occupancy 46811731Sjason@lowepower.comsystem.cpu.icache.tags.occ_percent::total 0.312925 # Average percentage of cache occupancy 46911731Sjason@lowepower.comsystem.cpu.icache.tags.occ_task_id_blocks::1024 1098 # Occupied blocks per task id 47011731Sjason@lowepower.comsystem.cpu.icache.tags.age_task_id_blocks_1024::0 70 # Occupied blocks per task id 47111731Sjason@lowepower.comsystem.cpu.icache.tags.age_task_id_blocks_1024::1 182 # Occupied blocks per task id 47211731Sjason@lowepower.comsystem.cpu.icache.tags.age_task_id_blocks_1024::2 846 # Occupied blocks per task id 47311731Sjason@lowepower.comsystem.cpu.icache.tags.occ_task_id_percent::1024 0.536133 # Percentage of cache occupancy per task id 47411731Sjason@lowepower.comsystem.cpu.icache.tags.tag_accesses 273696 # Number of tag accesses 47511731Sjason@lowepower.comsystem.cpu.icache.tags.data_accesses 273696 # Number of data accesses 47611731Sjason@lowepower.comsystem.cpu.icache.pwrStateResidencyTicks::UNDEFINED 339160000 # Cumulative time (in ticks) in various power states 47711731Sjason@lowepower.comsystem.cpu.icache.ReadReq_hits::cpu.inst 135081 # number of ReadReq hits 47811731Sjason@lowepower.comsystem.cpu.icache.ReadReq_hits::total 135081 # number of ReadReq hits 47911731Sjason@lowepower.comsystem.cpu.icache.demand_hits::cpu.inst 135081 # number of demand (read+write) hits 48011731Sjason@lowepower.comsystem.cpu.icache.demand_hits::total 135081 # number of demand (read+write) hits 48111731Sjason@lowepower.comsystem.cpu.icache.overall_hits::cpu.inst 135081 # number of overall hits 48211731Sjason@lowepower.comsystem.cpu.icache.overall_hits::total 135081 # number of overall hits 48311731Sjason@lowepower.comsystem.cpu.icache.ReadReq_misses::cpu.inst 1178 # number of ReadReq misses 48411731Sjason@lowepower.comsystem.cpu.icache.ReadReq_misses::total 1178 # number of ReadReq misses 48511731Sjason@lowepower.comsystem.cpu.icache.demand_misses::cpu.inst 1178 # number of demand (read+write) misses 48611731Sjason@lowepower.comsystem.cpu.icache.demand_misses::total 1178 # number of demand (read+write) misses 48711731Sjason@lowepower.comsystem.cpu.icache.overall_misses::cpu.inst 1178 # number of overall misses 48811731Sjason@lowepower.comsystem.cpu.icache.overall_misses::total 1178 # number of overall misses 48911731Sjason@lowepower.comsystem.cpu.icache.ReadReq_miss_latency::cpu.inst 99945500 # number of ReadReq miss cycles 49011731Sjason@lowepower.comsystem.cpu.icache.ReadReq_miss_latency::total 99945500 # number of ReadReq miss cycles 49111731Sjason@lowepower.comsystem.cpu.icache.demand_miss_latency::cpu.inst 99945500 # number of demand (read+write) miss cycles 49211731Sjason@lowepower.comsystem.cpu.icache.demand_miss_latency::total 99945500 # number of demand (read+write) miss cycles 49311731Sjason@lowepower.comsystem.cpu.icache.overall_miss_latency::cpu.inst 99945500 # number of overall miss cycles 49411731Sjason@lowepower.comsystem.cpu.icache.overall_miss_latency::total 99945500 # number of overall miss cycles 49511731Sjason@lowepower.comsystem.cpu.icache.ReadReq_accesses::cpu.inst 136259 # number of ReadReq accesses(hits+misses) 49611731Sjason@lowepower.comsystem.cpu.icache.ReadReq_accesses::total 136259 # number of ReadReq accesses(hits+misses) 49711731Sjason@lowepower.comsystem.cpu.icache.demand_accesses::cpu.inst 136259 # number of demand (read+write) accesses 49811731Sjason@lowepower.comsystem.cpu.icache.demand_accesses::total 136259 # number of demand (read+write) accesses 49911731Sjason@lowepower.comsystem.cpu.icache.overall_accesses::cpu.inst 136259 # number of overall (read+write) accesses 50011731Sjason@lowepower.comsystem.cpu.icache.overall_accesses::total 136259 # number of overall (read+write) accesses 50111731Sjason@lowepower.comsystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.008645 # miss rate for ReadReq accesses 50211731Sjason@lowepower.comsystem.cpu.icache.ReadReq_miss_rate::total 0.008645 # miss rate for ReadReq accesses 50311731Sjason@lowepower.comsystem.cpu.icache.demand_miss_rate::cpu.inst 0.008645 # miss rate for demand accesses 50411731Sjason@lowepower.comsystem.cpu.icache.demand_miss_rate::total 0.008645 # miss rate for demand accesses 50511731Sjason@lowepower.comsystem.cpu.icache.overall_miss_rate::cpu.inst 0.008645 # miss rate for overall accesses 50611731Sjason@lowepower.comsystem.cpu.icache.overall_miss_rate::total 0.008645 # miss rate for overall accesses 50711731Sjason@lowepower.comsystem.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 84843.378608 # average ReadReq miss latency 50811731Sjason@lowepower.comsystem.cpu.icache.ReadReq_avg_miss_latency::total 84843.378608 # average ReadReq miss latency 50911731Sjason@lowepower.comsystem.cpu.icache.demand_avg_miss_latency::cpu.inst 84843.378608 # average overall miss latency 51011731Sjason@lowepower.comsystem.cpu.icache.demand_avg_miss_latency::total 84843.378608 # average overall miss latency 51111731Sjason@lowepower.comsystem.cpu.icache.overall_avg_miss_latency::cpu.inst 84843.378608 # average overall miss latency 51211731Sjason@lowepower.comsystem.cpu.icache.overall_avg_miss_latency::total 84843.378608 # average overall miss latency 51311731Sjason@lowepower.comsystem.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 51411731Sjason@lowepower.comsystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 51511731Sjason@lowepower.comsystem.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 51611731Sjason@lowepower.comsystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 51711731Sjason@lowepower.comsystem.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 51811731Sjason@lowepower.comsystem.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 51911731Sjason@lowepower.comsystem.cpu.icache.writebacks::writebacks 80 # number of writebacks 52011731Sjason@lowepower.comsystem.cpu.icache.writebacks::total 80 # number of writebacks 52111731Sjason@lowepower.comsystem.cpu.icache.ReadReq_mshr_misses::cpu.inst 1178 # number of ReadReq MSHR misses 52211731Sjason@lowepower.comsystem.cpu.icache.ReadReq_mshr_misses::total 1178 # number of ReadReq MSHR misses 52311731Sjason@lowepower.comsystem.cpu.icache.demand_mshr_misses::cpu.inst 1178 # number of demand (read+write) MSHR misses 52411731Sjason@lowepower.comsystem.cpu.icache.demand_mshr_misses::total 1178 # number of demand (read+write) MSHR misses 52511731Sjason@lowepower.comsystem.cpu.icache.overall_mshr_misses::cpu.inst 1178 # number of overall MSHR misses 52611731Sjason@lowepower.comsystem.cpu.icache.overall_mshr_misses::total 1178 # number of overall MSHR misses 52711731Sjason@lowepower.comsystem.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 98767500 # number of ReadReq MSHR miss cycles 52811731Sjason@lowepower.comsystem.cpu.icache.ReadReq_mshr_miss_latency::total 98767500 # number of ReadReq MSHR miss cycles 52911731Sjason@lowepower.comsystem.cpu.icache.demand_mshr_miss_latency::cpu.inst 98767500 # number of demand (read+write) MSHR miss cycles 53011731Sjason@lowepower.comsystem.cpu.icache.demand_mshr_miss_latency::total 98767500 # number of demand (read+write) MSHR miss cycles 53111731Sjason@lowepower.comsystem.cpu.icache.overall_mshr_miss_latency::cpu.inst 98767500 # number of overall MSHR miss cycles 53211731Sjason@lowepower.comsystem.cpu.icache.overall_mshr_miss_latency::total 98767500 # number of overall MSHR miss cycles 53311731Sjason@lowepower.comsystem.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.008645 # mshr miss rate for ReadReq accesses 53411731Sjason@lowepower.comsystem.cpu.icache.ReadReq_mshr_miss_rate::total 0.008645 # mshr miss rate for ReadReq accesses 53511731Sjason@lowepower.comsystem.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.008645 # mshr miss rate for demand accesses 53611731Sjason@lowepower.comsystem.cpu.icache.demand_mshr_miss_rate::total 0.008645 # mshr miss rate for demand accesses 53711731Sjason@lowepower.comsystem.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.008645 # mshr miss rate for overall accesses 53811731Sjason@lowepower.comsystem.cpu.icache.overall_mshr_miss_rate::total 0.008645 # mshr miss rate for overall accesses 53911731Sjason@lowepower.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 83843.378608 # average ReadReq mshr miss latency 54011731Sjason@lowepower.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::total 83843.378608 # average ReadReq mshr miss latency 54111731Sjason@lowepower.comsystem.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 83843.378608 # average overall mshr miss latency 54211731Sjason@lowepower.comsystem.cpu.icache.demand_avg_mshr_miss_latency::total 83843.378608 # average overall mshr miss latency 54311731Sjason@lowepower.comsystem.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 83843.378608 # average overall mshr miss latency 54411731Sjason@lowepower.comsystem.cpu.icache.overall_avg_mshr_miss_latency::total 83843.378608 # average overall mshr miss latency 54511731Sjason@lowepower.comsystem.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 339160000 # Cumulative time (in ticks) in various power states 54611731Sjason@lowepower.comsystem.cpu.l2cache.tags.replacements 0 # number of replacements 54711731Sjason@lowepower.comsystem.cpu.l2cache.tags.tagsinuse 923.863116 # Cycle average of tags in use 54811731Sjason@lowepower.comsystem.cpu.l2cache.tags.total_refs 93 # Total number of references to valid blocks. 54911731Sjason@lowepower.comsystem.cpu.l2cache.tags.sampled_refs 1485 # Sample count of references to valid blocks. 55011731Sjason@lowepower.comsystem.cpu.l2cache.tags.avg_refs 0.062626 # Average number of references to valid blocks. 55111731Sjason@lowepower.comsystem.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 55211731Sjason@lowepower.comsystem.cpu.l2cache.tags.occ_blocks::cpu.inst 671.109849 # Average occupied blocks per requestor 55311731Sjason@lowepower.comsystem.cpu.l2cache.tags.occ_blocks::cpu.data 252.753267 # Average occupied blocks per requestor 55411731Sjason@lowepower.comsystem.cpu.l2cache.tags.occ_percent::cpu.inst 0.020481 # Average percentage of cache occupancy 55511731Sjason@lowepower.comsystem.cpu.l2cache.tags.occ_percent::cpu.data 0.007713 # Average percentage of cache occupancy 55611731Sjason@lowepower.comsystem.cpu.l2cache.tags.occ_percent::total 0.028194 # Average percentage of cache occupancy 55711731Sjason@lowepower.comsystem.cpu.l2cache.tags.occ_task_id_blocks::1024 1485 # Occupied blocks per task id 55811731Sjason@lowepower.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::0 76 # Occupied blocks per task id 55911731Sjason@lowepower.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::1 208 # Occupied blocks per task id 56011731Sjason@lowepower.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::2 1201 # Occupied blocks per task id 56111731Sjason@lowepower.comsystem.cpu.l2cache.tags.occ_task_id_percent::1024 0.045319 # Percentage of cache occupancy per task id 56211731Sjason@lowepower.comsystem.cpu.l2cache.tags.tag_accesses 14109 # Number of tag accesses 56311731Sjason@lowepower.comsystem.cpu.l2cache.tags.data_accesses 14109 # Number of data accesses 56411731Sjason@lowepower.comsystem.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 339160000 # Cumulative time (in ticks) in various power states 56511731Sjason@lowepower.comsystem.cpu.l2cache.WritebackClean_hits::writebacks 80 # number of WritebackClean hits 56611731Sjason@lowepower.comsystem.cpu.l2cache.WritebackClean_hits::total 80 # number of WritebackClean hits 56711731Sjason@lowepower.comsystem.cpu.l2cache.ReadCleanReq_hits::cpu.inst 11 # number of ReadCleanReq hits 56811731Sjason@lowepower.comsystem.cpu.l2cache.ReadCleanReq_hits::total 11 # number of ReadCleanReq hits 56911731Sjason@lowepower.comsystem.cpu.l2cache.ReadSharedReq_hits::cpu.data 2 # number of ReadSharedReq hits 57011731Sjason@lowepower.comsystem.cpu.l2cache.ReadSharedReq_hits::total 2 # number of ReadSharedReq hits 57111731Sjason@lowepower.comsystem.cpu.l2cache.demand_hits::cpu.inst 11 # number of demand (read+write) hits 57211731Sjason@lowepower.comsystem.cpu.l2cache.demand_hits::cpu.data 2 # number of demand (read+write) hits 57311731Sjason@lowepower.comsystem.cpu.l2cache.demand_hits::total 13 # number of demand (read+write) hits 57411731Sjason@lowepower.comsystem.cpu.l2cache.overall_hits::cpu.inst 11 # number of overall hits 57511731Sjason@lowepower.comsystem.cpu.l2cache.overall_hits::cpu.data 2 # number of overall hits 57611731Sjason@lowepower.comsystem.cpu.l2cache.overall_hits::total 13 # number of overall hits 57711731Sjason@lowepower.comsystem.cpu.l2cache.ReadExReq_misses::cpu.data 202 # number of ReadExReq misses 57811731Sjason@lowepower.comsystem.cpu.l2cache.ReadExReq_misses::total 202 # number of ReadExReq misses 57911731Sjason@lowepower.comsystem.cpu.l2cache.ReadCleanReq_misses::cpu.inst 1167 # number of ReadCleanReq misses 58011731Sjason@lowepower.comsystem.cpu.l2cache.ReadCleanReq_misses::total 1167 # number of ReadCleanReq misses 58111731Sjason@lowepower.comsystem.cpu.l2cache.ReadSharedReq_misses::cpu.data 116 # number of ReadSharedReq misses 58211731Sjason@lowepower.comsystem.cpu.l2cache.ReadSharedReq_misses::total 116 # number of ReadSharedReq misses 58311731Sjason@lowepower.comsystem.cpu.l2cache.demand_misses::cpu.inst 1167 # number of demand (read+write) misses 58411731Sjason@lowepower.comsystem.cpu.l2cache.demand_misses::cpu.data 318 # number of demand (read+write) misses 58511731Sjason@lowepower.comsystem.cpu.l2cache.demand_misses::total 1485 # number of demand (read+write) misses 58611731Sjason@lowepower.comsystem.cpu.l2cache.overall_misses::cpu.inst 1167 # number of overall misses 58711731Sjason@lowepower.comsystem.cpu.l2cache.overall_misses::cpu.data 318 # number of overall misses 58811731Sjason@lowepower.comsystem.cpu.l2cache.overall_misses::total 1485 # number of overall misses 58911731Sjason@lowepower.comsystem.cpu.l2cache.ReadExReq_miss_latency::cpu.data 15818500 # number of ReadExReq miss cycles 59011731Sjason@lowepower.comsystem.cpu.l2cache.ReadExReq_miss_latency::total 15818500 # number of ReadExReq miss cycles 59111731Sjason@lowepower.comsystem.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 96885000 # number of ReadCleanReq miss cycles 59211731Sjason@lowepower.comsystem.cpu.l2cache.ReadCleanReq_miss_latency::total 96885000 # number of ReadCleanReq miss cycles 59311731Sjason@lowepower.comsystem.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 10642000 # number of ReadSharedReq miss cycles 59411731Sjason@lowepower.comsystem.cpu.l2cache.ReadSharedReq_miss_latency::total 10642000 # number of ReadSharedReq miss cycles 59511731Sjason@lowepower.comsystem.cpu.l2cache.demand_miss_latency::cpu.inst 96885000 # number of demand (read+write) miss cycles 59611731Sjason@lowepower.comsystem.cpu.l2cache.demand_miss_latency::cpu.data 26460500 # number of demand (read+write) miss cycles 59711731Sjason@lowepower.comsystem.cpu.l2cache.demand_miss_latency::total 123345500 # number of demand (read+write) miss cycles 59811731Sjason@lowepower.comsystem.cpu.l2cache.overall_miss_latency::cpu.inst 96885000 # number of overall miss cycles 59911731Sjason@lowepower.comsystem.cpu.l2cache.overall_miss_latency::cpu.data 26460500 # number of overall miss cycles 60011731Sjason@lowepower.comsystem.cpu.l2cache.overall_miss_latency::total 123345500 # number of overall miss cycles 60111731Sjason@lowepower.comsystem.cpu.l2cache.WritebackClean_accesses::writebacks 80 # number of WritebackClean accesses(hits+misses) 60211731Sjason@lowepower.comsystem.cpu.l2cache.WritebackClean_accesses::total 80 # number of WritebackClean accesses(hits+misses) 60311731Sjason@lowepower.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.data 202 # number of ReadExReq accesses(hits+misses) 60411731Sjason@lowepower.comsystem.cpu.l2cache.ReadExReq_accesses::total 202 # number of ReadExReq accesses(hits+misses) 60511731Sjason@lowepower.comsystem.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1178 # number of ReadCleanReq accesses(hits+misses) 60611731Sjason@lowepower.comsystem.cpu.l2cache.ReadCleanReq_accesses::total 1178 # number of ReadCleanReq accesses(hits+misses) 60711731Sjason@lowepower.comsystem.cpu.l2cache.ReadSharedReq_accesses::cpu.data 118 # number of ReadSharedReq accesses(hits+misses) 60811731Sjason@lowepower.comsystem.cpu.l2cache.ReadSharedReq_accesses::total 118 # number of ReadSharedReq accesses(hits+misses) 60911731Sjason@lowepower.comsystem.cpu.l2cache.demand_accesses::cpu.inst 1178 # number of demand (read+write) accesses 61011731Sjason@lowepower.comsystem.cpu.l2cache.demand_accesses::cpu.data 320 # number of demand (read+write) accesses 61111731Sjason@lowepower.comsystem.cpu.l2cache.demand_accesses::total 1498 # number of demand (read+write) accesses 61211731Sjason@lowepower.comsystem.cpu.l2cache.overall_accesses::cpu.inst 1178 # number of overall (read+write) accesses 61311731Sjason@lowepower.comsystem.cpu.l2cache.overall_accesses::cpu.data 320 # number of overall (read+write) accesses 61411731Sjason@lowepower.comsystem.cpu.l2cache.overall_accesses::total 1498 # number of overall (read+write) accesses 61511731Sjason@lowepower.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 61611731Sjason@lowepower.comsystem.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 61711731Sjason@lowepower.comsystem.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.990662 # miss rate for ReadCleanReq accesses 61811731Sjason@lowepower.comsystem.cpu.l2cache.ReadCleanReq_miss_rate::total 0.990662 # miss rate for ReadCleanReq accesses 61911731Sjason@lowepower.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.983051 # miss rate for ReadSharedReq accesses 62011731Sjason@lowepower.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::total 0.983051 # miss rate for ReadSharedReq accesses 62111731Sjason@lowepower.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.990662 # miss rate for demand accesses 62211731Sjason@lowepower.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 0.993750 # miss rate for demand accesses 62311731Sjason@lowepower.comsystem.cpu.l2cache.demand_miss_rate::total 0.991322 # miss rate for demand accesses 62411731Sjason@lowepower.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.990662 # miss rate for overall accesses 62511731Sjason@lowepower.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 0.993750 # miss rate for overall accesses 62611731Sjason@lowepower.comsystem.cpu.l2cache.overall_miss_rate::total 0.991322 # miss rate for overall accesses 62711731Sjason@lowepower.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78309.405941 # average ReadExReq miss latency 62811731Sjason@lowepower.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::total 78309.405941 # average ReadExReq miss latency 62911731Sjason@lowepower.comsystem.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 83020.565553 # average ReadCleanReq miss latency 63011731Sjason@lowepower.comsystem.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 83020.565553 # average ReadCleanReq miss latency 63111731Sjason@lowepower.comsystem.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 91741.379310 # average ReadSharedReq miss latency 63211731Sjason@lowepower.comsystem.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 91741.379310 # average ReadSharedReq miss latency 63311731Sjason@lowepower.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83020.565553 # average overall miss latency 63411731Sjason@lowepower.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.data 83209.119497 # average overall miss latency 63511731Sjason@lowepower.comsystem.cpu.l2cache.demand_avg_miss_latency::total 83060.942761 # average overall miss latency 63611731Sjason@lowepower.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83020.565553 # average overall miss latency 63711731Sjason@lowepower.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.data 83209.119497 # average overall miss latency 63811731Sjason@lowepower.comsystem.cpu.l2cache.overall_avg_miss_latency::total 83060.942761 # average overall miss latency 63911731Sjason@lowepower.comsystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 64011731Sjason@lowepower.comsystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 64111731Sjason@lowepower.comsystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 64211731Sjason@lowepower.comsystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 64311731Sjason@lowepower.comsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 64411731Sjason@lowepower.comsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 64511731Sjason@lowepower.comsystem.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 202 # number of ReadExReq MSHR misses 64611731Sjason@lowepower.comsystem.cpu.l2cache.ReadExReq_mshr_misses::total 202 # number of ReadExReq MSHR misses 64711731Sjason@lowepower.comsystem.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1167 # number of ReadCleanReq MSHR misses 64811731Sjason@lowepower.comsystem.cpu.l2cache.ReadCleanReq_mshr_misses::total 1167 # number of ReadCleanReq MSHR misses 64911731Sjason@lowepower.comsystem.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 116 # number of ReadSharedReq MSHR misses 65011731Sjason@lowepower.comsystem.cpu.l2cache.ReadSharedReq_mshr_misses::total 116 # number of ReadSharedReq MSHR misses 65111731Sjason@lowepower.comsystem.cpu.l2cache.demand_mshr_misses::cpu.inst 1167 # number of demand (read+write) MSHR misses 65211731Sjason@lowepower.comsystem.cpu.l2cache.demand_mshr_misses::cpu.data 318 # number of demand (read+write) MSHR misses 65311731Sjason@lowepower.comsystem.cpu.l2cache.demand_mshr_misses::total 1485 # number of demand (read+write) MSHR misses 65411731Sjason@lowepower.comsystem.cpu.l2cache.overall_mshr_misses::cpu.inst 1167 # number of overall MSHR misses 65511731Sjason@lowepower.comsystem.cpu.l2cache.overall_mshr_misses::cpu.data 318 # number of overall MSHR misses 65611731Sjason@lowepower.comsystem.cpu.l2cache.overall_mshr_misses::total 1485 # number of overall MSHR misses 65711731Sjason@lowepower.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13798500 # number of ReadExReq MSHR miss cycles 65811731Sjason@lowepower.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13798500 # number of ReadExReq MSHR miss cycles 65911731Sjason@lowepower.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 85215000 # number of ReadCleanReq MSHR miss cycles 66011731Sjason@lowepower.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 85215000 # number of ReadCleanReq MSHR miss cycles 66111731Sjason@lowepower.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 9482000 # number of ReadSharedReq MSHR miss cycles 66211731Sjason@lowepower.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 9482000 # number of ReadSharedReq MSHR miss cycles 66311731Sjason@lowepower.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 85215000 # number of demand (read+write) MSHR miss cycles 66411731Sjason@lowepower.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.data 23280500 # number of demand (read+write) MSHR miss cycles 66511731Sjason@lowepower.comsystem.cpu.l2cache.demand_mshr_miss_latency::total 108495500 # number of demand (read+write) MSHR miss cycles 66611731Sjason@lowepower.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 85215000 # number of overall MSHR miss cycles 66711731Sjason@lowepower.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.data 23280500 # number of overall MSHR miss cycles 66811731Sjason@lowepower.comsystem.cpu.l2cache.overall_mshr_miss_latency::total 108495500 # number of overall MSHR miss cycles 66911731Sjason@lowepower.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 67011731Sjason@lowepower.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 67111731Sjason@lowepower.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.990662 # mshr miss rate for ReadCleanReq accesses 67211731Sjason@lowepower.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.990662 # mshr miss rate for ReadCleanReq accesses 67311731Sjason@lowepower.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.983051 # mshr miss rate for ReadSharedReq accesses 67411731Sjason@lowepower.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.983051 # mshr miss rate for ReadSharedReq accesses 67511731Sjason@lowepower.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.990662 # mshr miss rate for demand accesses 67611731Sjason@lowepower.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.993750 # mshr miss rate for demand accesses 67711731Sjason@lowepower.comsystem.cpu.l2cache.demand_mshr_miss_rate::total 0.991322 # mshr miss rate for demand accesses 67811731Sjason@lowepower.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.990662 # mshr miss rate for overall accesses 67911731Sjason@lowepower.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.993750 # mshr miss rate for overall accesses 68011731Sjason@lowepower.comsystem.cpu.l2cache.overall_mshr_miss_rate::total 0.991322 # mshr miss rate for overall accesses 68111731Sjason@lowepower.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68309.405941 # average ReadExReq mshr miss latency 68211731Sjason@lowepower.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68309.405941 # average ReadExReq mshr miss latency 68311731Sjason@lowepower.comsystem.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 73020.565553 # average ReadCleanReq mshr miss latency 68411731Sjason@lowepower.comsystem.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 73020.565553 # average ReadCleanReq mshr miss latency 68511731Sjason@lowepower.comsystem.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 81741.379310 # average ReadSharedReq mshr miss latency 68611731Sjason@lowepower.comsystem.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 81741.379310 # average ReadSharedReq mshr miss latency 68711731Sjason@lowepower.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73020.565553 # average overall mshr miss latency 68811731Sjason@lowepower.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73209.119497 # average overall mshr miss latency 68911731Sjason@lowepower.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::total 73060.942761 # average overall mshr miss latency 69011731Sjason@lowepower.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73020.565553 # average overall mshr miss latency 69111731Sjason@lowepower.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73209.119497 # average overall mshr miss latency 69211731Sjason@lowepower.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::total 73060.942761 # average overall mshr miss latency 69311731Sjason@lowepower.comsystem.cpu.toL2Bus.snoop_filter.tot_requests 1578 # Total number of requests made to the snoop filter. 69411731Sjason@lowepower.comsystem.cpu.toL2Bus.snoop_filter.hit_single_requests 82 # Number of requests hitting in the snoop filter with a single holder of the requested data. 69511731Sjason@lowepower.comsystem.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 69611731Sjason@lowepower.comsystem.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 69711731Sjason@lowepower.comsystem.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 69811731Sjason@lowepower.comsystem.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 69911731Sjason@lowepower.comsystem.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 339160000 # Cumulative time (in ticks) in various power states 70011731Sjason@lowepower.comsystem.cpu.toL2Bus.trans_dist::ReadResp 1296 # Transaction distribution 70111731Sjason@lowepower.comsystem.cpu.toL2Bus.trans_dist::WritebackClean 80 # Transaction distribution 70211731Sjason@lowepower.comsystem.cpu.toL2Bus.trans_dist::ReadExReq 202 # Transaction distribution 70311731Sjason@lowepower.comsystem.cpu.toL2Bus.trans_dist::ReadExResp 202 # Transaction distribution 70411731Sjason@lowepower.comsystem.cpu.toL2Bus.trans_dist::ReadCleanReq 1178 # Transaction distribution 70511731Sjason@lowepower.comsystem.cpu.toL2Bus.trans_dist::ReadSharedReq 118 # Transaction distribution 70611731Sjason@lowepower.comsystem.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2436 # Packet count per connected master and slave (bytes) 70711731Sjason@lowepower.comsystem.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 640 # Packet count per connected master and slave (bytes) 70811731Sjason@lowepower.comsystem.cpu.toL2Bus.pkt_count::total 3076 # Packet count per connected master and slave (bytes) 70911731Sjason@lowepower.comsystem.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 80512 # Cumulative packet size per connected master and slave (bytes) 71011731Sjason@lowepower.comsystem.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 20480 # Cumulative packet size per connected master and slave (bytes) 71111731Sjason@lowepower.comsystem.cpu.toL2Bus.pkt_size::total 100992 # Cumulative packet size per connected master and slave (bytes) 71211731Sjason@lowepower.comsystem.cpu.toL2Bus.snoops 0 # Total snoops (count) 71311731Sjason@lowepower.comsystem.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) 71411731Sjason@lowepower.comsystem.cpu.toL2Bus.snoop_fanout::samples 1498 # Request fanout histogram 71511731Sjason@lowepower.comsystem.cpu.toL2Bus.snoop_fanout::mean 0.001335 # Request fanout histogram 71611731Sjason@lowepower.comsystem.cpu.toL2Bus.snoop_fanout::stdev 0.036527 # Request fanout histogram 71711731Sjason@lowepower.comsystem.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 71811731Sjason@lowepower.comsystem.cpu.toL2Bus.snoop_fanout::0 1496 99.87% 99.87% # Request fanout histogram 71911731Sjason@lowepower.comsystem.cpu.toL2Bus.snoop_fanout::1 2 0.13% 100.00% # Request fanout histogram 72011731Sjason@lowepower.comsystem.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 72111731Sjason@lowepower.comsystem.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 72211731Sjason@lowepower.comsystem.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 72311731Sjason@lowepower.comsystem.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 72411731Sjason@lowepower.comsystem.cpu.toL2Bus.snoop_fanout::total 1498 # Request fanout histogram 72511731Sjason@lowepower.comsystem.cpu.toL2Bus.reqLayer0.occupancy 869000 # Layer occupancy (ticks) 72611731Sjason@lowepower.comsystem.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) 72711731Sjason@lowepower.comsystem.cpu.toL2Bus.respLayer0.occupancy 1767000 # Layer occupancy (ticks) 72811731Sjason@lowepower.comsystem.cpu.toL2Bus.respLayer0.utilization 0.5 # Layer utilization (%) 72911731Sjason@lowepower.comsystem.cpu.toL2Bus.respLayer1.occupancy 480000 # Layer occupancy (ticks) 73011731Sjason@lowepower.comsystem.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 73111731Sjason@lowepower.comsystem.membus.snoop_filter.tot_requests 1485 # Total number of requests made to the snoop filter. 73211731Sjason@lowepower.comsystem.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. 73311731Sjason@lowepower.comsystem.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 73411731Sjason@lowepower.comsystem.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 73511731Sjason@lowepower.comsystem.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 73611731Sjason@lowepower.comsystem.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 73711731Sjason@lowepower.comsystem.membus.pwrStateResidencyTicks::UNDEFINED 339160000 # Cumulative time (in ticks) in various power states 73811731Sjason@lowepower.comsystem.membus.trans_dist::ReadResp 1283 # Transaction distribution 73911731Sjason@lowepower.comsystem.membus.trans_dist::ReadExReq 202 # Transaction distribution 74011731Sjason@lowepower.comsystem.membus.trans_dist::ReadExResp 202 # Transaction distribution 74111731Sjason@lowepower.comsystem.membus.trans_dist::ReadSharedReq 1283 # Transaction distribution 74211731Sjason@lowepower.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2970 # Packet count per connected master and slave (bytes) 74311731Sjason@lowepower.comsystem.membus.pkt_count::total 2970 # Packet count per connected master and slave (bytes) 74411731Sjason@lowepower.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 95040 # Cumulative packet size per connected master and slave (bytes) 74511731Sjason@lowepower.comsystem.membus.pkt_size::total 95040 # Cumulative packet size per connected master and slave (bytes) 74611731Sjason@lowepower.comsystem.membus.snoops 0 # Total snoops (count) 74711731Sjason@lowepower.comsystem.membus.snoopTraffic 0 # Total snoop traffic (bytes) 74811731Sjason@lowepower.comsystem.membus.snoop_fanout::samples 1485 # Request fanout histogram 74911731Sjason@lowepower.comsystem.membus.snoop_fanout::mean 0 # Request fanout histogram 75011731Sjason@lowepower.comsystem.membus.snoop_fanout::stdev 0 # Request fanout histogram 75111731Sjason@lowepower.comsystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 75211731Sjason@lowepower.comsystem.membus.snoop_fanout::0 1485 100.00% 100.00% # Request fanout histogram 75311731Sjason@lowepower.comsystem.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 75411731Sjason@lowepower.comsystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 75511731Sjason@lowepower.comsystem.membus.snoop_fanout::min_value 0 # Request fanout histogram 75611731Sjason@lowepower.comsystem.membus.snoop_fanout::max_value 0 # Request fanout histogram 75711731Sjason@lowepower.comsystem.membus.snoop_fanout::total 1485 # Request fanout histogram 75811731Sjason@lowepower.comsystem.membus.reqLayer0.occupancy 1720000 # Layer occupancy (ticks) 75911731Sjason@lowepower.comsystem.membus.reqLayer0.utilization 0.5 # Layer utilization (%) 76011731Sjason@lowepower.comsystem.membus.respLayer1.occupancy 7877750 # Layer occupancy (ticks) 76111731Sjason@lowepower.comsystem.membus.respLayer1.utilization 2.3 # Layer utilization (%) 76211731Sjason@lowepower.com 76311731Sjason@lowepower.com---------- End Simulation Statistics ---------- 764